109
109
invalidate_dev_table_entry(iommu, req_id);
110
110
flush_command_buffer(iommu);
112
AMD_IOMMU_DEBUG("Setup I/O page table at DTE:0x%x, root_table:%"PRIx64","
113
"domain_id:%d, paging_mode:%d\n", req_id,
114
page_to_maddr(hd->root_table), hd->domain_id, hd->paging_mode);
112
AMD_IOMMU_DEBUG("Setup I/O page table: device id = 0x%04x, "
113
"root table = 0x%"PRIx64", "
114
"domain = %d, paging mode = %d\n", req_id,
115
page_to_maddr(hd->root_table),
116
hd->domain_id, hd->paging_mode);
117
119
spin_unlock_irqrestore(&iommu->lock, flags);
120
static void amd_iommu_setup_dom0_devices(struct domain *d)
122
static void __init amd_iommu_setup_dom0_devices(struct domain *d)
122
124
struct amd_iommu *iommu;
123
125
struct pci_dev *pdev;
128
128
spin_lock(&pcidevs_lock);
129
129
for ( bus = 0; bus < 256; bus++ )
131
for ( dev = 0; dev < 32; dev++ )
131
for ( devfn = 0; devfn < 256; devfn++ )
133
for ( func = 0; func < 8; func++ )
135
l = pci_conf_read32(bus, dev, func, PCI_VENDOR_ID);
136
/* some broken boards return 0 or ~0 if a slot is empty: */
137
if ( (l == 0xffffffff) || (l == 0x00000000) ||
138
(l == 0x0000ffff) || (l == 0xffff0000) )
141
pdev = alloc_pdev(bus, PCI_DEVFN(dev, func));
143
list_add(&pdev->domain_list, &d->arch.pdev_list);
145
bdf = (bus << 8) | pdev->devfn;
146
iommu = find_iommu_for_device(bdf);
150
AMD_IOMMU_DEBUG("Fail to find iommu for device"
151
"%02x:%02x.%x\n", bus, dev, func);
133
pdev = pci_get_pdev(bus, devfn);
138
list_add(&pdev->domain_list, &d->arch.pdev_list);
140
bdf = (bus << 8) | devfn;
141
iommu = find_iommu_for_device(bdf);
143
if ( likely(iommu != NULL) )
154
144
amd_iommu_setup_domain_device(d, iommu, bdf);
146
AMD_IOMMU_DEBUG("No iommu for device %02x:%02x.%x\n",
147
bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
158
150
spin_unlock(&pcidevs_lock);
161
int amd_iov_detect(void)
153
int __init amd_iov_detect(void)
163
155
INIT_LIST_HEAD(&amd_iommu_head);
217
/* For pv and dom0, stick with get_paging_mode(max_page)
218
* For HVM dom0, use 2 level page table at first */
227
219
hd->paging_mode = is_hvm_domain(d) ?
228
IOMMU_PAGE_TABLE_LEVEL_4 : get_paging_mode(max_page);
220
IOMMU_PAGING_MODE_LEVEL_2 :
221
get_paging_mode(max_page);
230
223
hd->domain_id = d->domain_id;
235
static void amd_iommu_dom0_init(struct domain *d)
228
static void __init amd_iommu_dom0_init(struct domain *d)
239
232
if ( !iommu_passthrough && !need_iommu(d) )
241
234
/* Set up 1:1 page table for dom0 */
242
for ( i = 0; i < max_page; i++ )
243
amd_iommu_map_page(d, i, i, IOMMUF_readable|IOMMUF_writable);
235
for ( i = 0; i < max_pdx; i++ )
237
unsigned long pfn = pdx_to_pfn(i);
240
* XXX Should we really map all non-RAM (above 4G)? Minimally
241
* a pfn_valid() check would seem desirable here.
243
amd_iommu_map_page(d, pfn, pfn, IOMMUF_readable|IOMMUF_writable);
246
247
amd_iommu_setup_dom0_devices(d);
263
264
disable_translation((u32 *)dte);
264
265
invalidate_dev_table_entry(iommu, req_id);
265
266
flush_command_buffer(iommu);
266
AMD_IOMMU_DEBUG("Disable DTE:0x%x,"
267
" domain_id:%d, paging_mode:%d\n",
268
req_id, domain_hvm_iommu(domain)->domain_id,
269
domain_hvm_iommu(domain)->paging_mode);
267
AMD_IOMMU_DEBUG("Disable: device id = 0x%04x, "
268
"domain = %d, paging mode = %d\n",
269
req_id, domain_hvm_iommu(domain)->domain_id,
270
domain_hvm_iommu(domain)->paging_mode);
271
272
spin_unlock_irqrestore(&iommu->lock, flags);
290
292
AMD_IOMMU_DEBUG("Fail to find iommu."
291
" %x:%x.%x cannot be assigned to domain %d\n",
292
bus, PCI_SLOT(devfn), PCI_FUNC(devfn), target->domain_id);
293
" %02x:%x02.%x cannot be assigned to domain %d\n",
294
bus, PCI_SLOT(devfn), PCI_FUNC(devfn),
298
301
list_move(&pdev->domain_list, &target->arch.pdev_list);
299
302
pdev->domain = target;
304
/* IO page tables might be destroyed after pci-detach the last device
305
* In this case, we have to re-allocate root table for next pci-attach.*/
306
if ( t->root_table == NULL )
307
allocate_domain_resources(t);
301
309
amd_iommu_setup_domain_device(target, iommu, bdf);
302
AMD_IOMMU_DEBUG("reassign %x:%x.%x domain %d -> domain %d\n",
303
bus, PCI_SLOT(devfn), PCI_FUNC(devfn),
304
source->domain_id, target->domain_id);
310
AMD_IOMMU_DEBUG("Re-assign %02x:%02x.%x from domain %d to domain %d\n",
311
bus, PCI_SLOT(devfn), PCI_FUNC(devfn),
312
source->domain_id, target->domain_id);
390
398
AMD_IOMMU_DEBUG("Fail to find iommu."
391
" %x:%x.%x cannot be assigned to domain %d\n",
392
pdev->bus, PCI_SLOT(pdev->devfn),
393
PCI_FUNC(pdev->devfn), pdev->domain->domain_id);
399
" %02x:%02x.%x cannot be assigned to domain %d\n",
400
pdev->bus, PCI_SLOT(pdev->devfn),
401
PCI_FUNC(pdev->devfn), pdev->domain->domain_id);
412
420
AMD_IOMMU_DEBUG("Fail to find iommu."
413
" %x:%x.%x cannot be removed from domain %d\n",
414
pdev->bus, PCI_SLOT(pdev->devfn),
415
PCI_FUNC(pdev->devfn), pdev->domain->domain_id);
421
" %02x:%02x.%x cannot be removed from domain %d\n",
422
pdev->bus, PCI_SLOT(pdev->devfn),
423
PCI_FUNC(pdev->devfn), pdev->domain->domain_id);