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;*****************************************************************************
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;* x86inc.asm: x264asm abstraction layer
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;*****************************************************************************
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;* Copyright (C) 2005-2011 x264 project
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;* Authors: Loren Merritt <lorenm@u.washington.edu>
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;* Anton Mitrofanov <BugMaster@narod.ru>
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;* Jason Garrett-Glaser <darkshikari@gmail.com>
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;* Permission to use, copy, modify, and/or distribute this software for any
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;* purpose with or without fee is hereby granted, provided that the above
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;* copyright notice and this permission notice appear in all copies.
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;* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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;*****************************************************************************
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; This is a header file for the x264ASM assembly language, which uses
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; NASM/YASM syntax combined with a large number of macros to provide easy
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; abstraction between different calling conventions (x86_32, win64, linux64).
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; It also has various other useful features to simplify writing the kind of
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; DSP functions that are most often used in x264.
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; Unlike the rest of x264, this file is available under an ISC license, as it
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; has significant usefulness outside of x264 and we want it to be available
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; to the largest audience possible. Of course, if you modify it for your own
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; purposes to add a new feature, we strongly encourage contributing a patch
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; as this feature might be useful for others as well. Send patches or ideas
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; to x264-devel@videolan.org .
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%define program_name ff
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%ifidn __OUTPUT_FORMAT__,win32
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%define mangle(x) _ %+ x
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; FIXME: All of the 64bit asm functions that take a stride as an argument
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; via register, assume that the high dword of that register is filled with 0.
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; This is true in practice (since we never do any 64bit arithmetic on strides,
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; and x264's strides are all positive), but is not guaranteed by the ABI.
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; Name of the .rodata section.
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; Kludge: Something on OS X fails to align .rodata even given an align attribute,
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; so use a different read-only section.
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%macro SECTION_RODATA 0-1 16
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%ifidn __OUTPUT_FORMAT__,macho64
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SECTION .text align=%1
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%elifidn __OUTPUT_FORMAT__,macho
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SECTION .text align=%1
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%elifidn __OUTPUT_FORMAT__,aout
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SECTION .rodata align=%1
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; aout does not support align=
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%macro SECTION_TEXT 0-1 16
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%ifidn __OUTPUT_FORMAT__,aout
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SECTION .text align=%1
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; x86_32 doesn't require PIC.
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; Some distros prefer shared objects to be PIC, but nothing breaks if
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; the code contains a few textrels, so we'll skip that complexity.
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; Macros to eliminate most code duplication between x86_32 and x86_64:
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; Currently this works only for leaf functions which load all their arguments
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; into registers at the start, and make no other use of the stack. Luckily that
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; covers most of x264's asm.
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; %1 = number of arguments. loads them from stack if needed.
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; %2 = number of registers used. pushes callee-saved regs if needed.
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; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.
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; %4 = list of names to define to registers
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; PROLOGUE can also be invoked by adding the same options to cglobal
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; cglobal foo, 2,3,0, dst, src, tmp
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; declares a function (foo), taking two args (dst and src) and one local variable (tmp)
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; TODO Some functions can use some args directly from the stack. If they're the
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; last args then you can just not declare them, but if they're in the middle
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; we need more flexible macro.
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; Pops anything that was pushed by PROLOGUE, and returns.
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; Same, but if it doesn't pop anything it becomes a 2-byte ret, for athlons
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; which are slow when a normal ret follows a branch.
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; rN and rNq are the native-size register holding function argument N
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; rNd, rNw, rNb are dword, word, and byte size
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; rNm is the original location of arg N (a register or on the stack), dword
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; rNmp is native size
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%ifid %6 ; i.e. it's a register
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%elifdef ARCH_X86_64 ; memory
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%define r%1mp qword %6
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%define r%1mp dword %6
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%macro DECLARE_REG_SIZE 2
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DECLARE_REG_SIZE ax, al
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DECLARE_REG_SIZE bx, bl
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DECLARE_REG_SIZE cx, cl
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DECLARE_REG_SIZE dx, dl
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DECLARE_REG_SIZE si, sil
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DECLARE_REG_SIZE di, dil
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DECLARE_REG_SIZE bp, bpl
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; t# defines for when per-arch register allocation is more complex than just function arguments
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%macro DECLARE_REG_TMP 1-*
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CAT_XDEFINE t, %%i, r%1
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%macro DECLARE_REG_TMP_SIZE 0-*
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%define t%1q t%1 %+ q
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%define t%1d t%1 %+ d
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%define t%1w t%1 %+ w
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%define t%1b t%1 %+ b
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DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9
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%assign stack_offset stack_offset+gprsize
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%assign stack_offset stack_offset-gprsize
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%assign stack_offset stack_offset+(%2)
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%assign stack_offset stack_offset-(%2)
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%macro movsxdifnidn 2
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%macro DEFINE_ARGS 0-*
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CAT_UNDEF arg_name %+ %%i, q
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CAT_UNDEF arg_name %+ %%i, d
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CAT_UNDEF arg_name %+ %%i, w
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CAT_UNDEF arg_name %+ %%i, b
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CAT_UNDEF arg_name %+ %%i, m
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CAT_UNDEF arg_name, %%i
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%xdefine %1q r %+ %%i %+ q
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%xdefine %1d r %+ %%i %+ d
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%xdefine %1w r %+ %%i %+ w
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%xdefine %1b r %+ %%i %+ b
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%xdefine %1m r %+ %%i %+ m
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CAT_XDEFINE arg_name, %%i, %1
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%assign n_arg_names %%i
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%ifdef WIN64 ; Windows x64 ;=================================================
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DECLARE_REG 0, rcx, ecx, cx, cl, ecx
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DECLARE_REG 1, rdx, edx, dx, dl, edx
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DECLARE_REG 2, r8, r8d, r8w, r8b, r8d
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DECLARE_REG 3, r9, r9d, r9w, r9b, r9d
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DECLARE_REG 4, rdi, edi, di, dil, [rsp + stack_offset + 40]
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DECLARE_REG 5, rsi, esi, si, sil, [rsp + stack_offset + 48]
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DECLARE_REG 6, rax, eax, ax, al, [rsp + stack_offset + 56]
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%define r7m [rsp + stack_offset + 64]
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%define r8m [rsp + stack_offset + 72]
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%macro LOAD_IF_USED 2 ; reg_id, number_of_args
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mov r%1, [rsp + stack_offset + 8 + %1*8]
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%macro PROLOGUE 2-4+ 0 ; #args, #regs, #xmm_regs, arg_names...
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ASSERT regs_used <= 7
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%assign stack_offset stack_offset+16
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%macro WIN64_SPILL_XMM 1
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%assign xmm_regs_used %1
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%assign xmm_regs_used 0
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ASSERT xmm_regs_used <= 16
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%if xmm_regs_used > 6
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sub rsp, (xmm_regs_used-6)*16+16
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%assign stack_offset stack_offset+(xmm_regs_used-6)*16+16
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%assign %%i xmm_regs_used
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%rep (xmm_regs_used-6)
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movdqa [rsp + (%%i-6)*16+8], xmm %+ %%i
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%macro WIN64_RESTORE_XMM_INTERNAL 1
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%if xmm_regs_used > 6
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%assign %%i xmm_regs_used
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%rep (xmm_regs_used-6)
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movdqa xmm %+ %%i, [%1 + (%%i-6)*16+8]
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add %1, (xmm_regs_used-6)*16+16
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%macro WIN64_RESTORE_XMM 1
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WIN64_RESTORE_XMM_INTERNAL %1
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%assign stack_offset stack_offset-(xmm_regs_used-6)*16+16
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%assign xmm_regs_used 0
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WIN64_RESTORE_XMM_INTERNAL rsp
342
%if regs_used > 4 || xmm_regs_used > 6
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%elifdef ARCH_X86_64 ; *nix x64 ;=============================================
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DECLARE_REG 0, rdi, edi, di, dil, edi
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DECLARE_REG 1, rsi, esi, si, sil, esi
353
DECLARE_REG 2, rdx, edx, dx, dl, edx
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DECLARE_REG 3, rcx, ecx, cx, cl, ecx
355
DECLARE_REG 4, r8, r8d, r8w, r8b, r8d
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DECLARE_REG 5, r9, r9d, r9w, r9b, r9d
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DECLARE_REG 6, rax, eax, ax, al, [rsp + stack_offset + 8]
358
%define r7m [rsp + stack_offset + 16]
359
%define r8m [rsp + stack_offset + 24]
361
%macro LOAD_IF_USED 2 ; reg_id, number_of_args
363
mov r%1, [rsp - 40 + %1*8]
367
%macro PROLOGUE 2-4+ ; #args, #regs, #xmm_regs, arg_names...
382
%else ; X86_32 ;==============================================================
384
DECLARE_REG 0, eax, eax, ax, al, [esp + stack_offset + 4]
385
DECLARE_REG 1, ecx, ecx, cx, cl, [esp + stack_offset + 8]
386
DECLARE_REG 2, edx, edx, dx, dl, [esp + stack_offset + 12]
387
DECLARE_REG 3, ebx, ebx, bx, bl, [esp + stack_offset + 16]
388
DECLARE_REG 4, esi, esi, si, null, [esp + stack_offset + 20]
389
DECLARE_REG 5, edi, edi, di, null, [esp + stack_offset + 24]
390
DECLARE_REG 6, ebp, ebp, bp, null, [esp + stack_offset + 28]
391
%define r7m [esp + stack_offset + 32]
392
%define r8m [esp + stack_offset + 36]
395
%macro PUSH_IF_USED 1 ; reg_id
398
%assign stack_offset stack_offset+4
402
%macro POP_IF_USED 1 ; reg_id
408
%macro LOAD_IF_USED 2 ; reg_id, number_of_args
410
mov r%1, [esp + stack_offset + 4 + %1*4]
414
%macro PROLOGUE 2-4+ ; #args, #regs, #xmm_regs, arg_names...
417
ASSERT regs_used <= 7
448
%endif ;======================================================================
451
%macro WIN64_SPILL_XMM 1
453
%macro WIN64_RESTORE_XMM 1
459
;=============================================================================
460
; arch-independent part
461
;=============================================================================
463
%assign function_align 16
466
; Applies any symbol mangling needed for C linkage, and sets up a define such that
467
; subsequent uses of the function name automatically refer to the mangled version.
468
; Appends cpuflags to the function name if cpuflags has been specified.
469
%macro cglobal 1-2+ ; name, [PROLOGUE args]
471
cglobal_internal %1 %+ SUFFIX
473
cglobal_internal %1 %+ SUFFIX, %2
476
%macro cglobal_internal 1-2+
478
%xdefine %1 mangle(program_name %+ _ %+ %1)
479
%xdefine %1.skip_prologue %1 %+ .skip_prologue
480
CAT_XDEFINE cglobaled_, %1, 1
482
%xdefine current_function %1
483
%ifidn __OUTPUT_FORMAT__,elf
484
global %1:function hidden
490
RESET_MM_PERMUTATION ; not really needed, but makes disassembly somewhat nicer
491
%assign stack_offset 0
498
%xdefine %1 mangle(program_name %+ _ %+ %1)
499
CAT_XDEFINE cglobaled_, %1, 1
503
; like cextern, but without the prefix
504
%macro cextern_naked 1
505
%xdefine %1 mangle(%1)
506
CAT_XDEFINE cglobaled_, %1, 1
511
%xdefine %1 mangle(program_name %+ _ %+ %1)
516
; This is needed for ELF, otherwise the GNU linker assumes the stack is
517
; executable by default.
518
%ifidn __OUTPUT_FORMAT__,elf
519
SECTION .note.GNU-stack noalloc noexec nowrite progbits
524
%assign cpuflags_mmx (1<<0)
525
%assign cpuflags_mmx2 (1<<1) | cpuflags_mmx
526
%assign cpuflags_3dnow (1<<2) | cpuflags_mmx
527
%assign cpuflags_3dnow2 (1<<3) | cpuflags_3dnow
528
%assign cpuflags_sse (1<<4) | cpuflags_mmx2
529
%assign cpuflags_sse2 (1<<5) | cpuflags_sse
530
%assign cpuflags_sse2slow (1<<6) | cpuflags_sse2
531
%assign cpuflags_sse3 (1<<7) | cpuflags_sse2
532
%assign cpuflags_ssse3 (1<<8) | cpuflags_sse3
533
%assign cpuflags_sse4 (1<<9) | cpuflags_ssse3
534
%assign cpuflags_sse42 (1<<10)| cpuflags_sse4
535
%assign cpuflags_avx (1<<11)| cpuflags_sse42
536
%assign cpuflags_xop (1<<12)| cpuflags_avx
537
%assign cpuflags_fma4 (1<<13)| cpuflags_avx
539
%assign cpuflags_cache32 (1<<16)
540
%assign cpuflags_cache64 (1<<17)
541
%assign cpuflags_slowctz (1<<18)
542
%assign cpuflags_lzcnt (1<<19)
543
%assign cpuflags_misalign (1<<20)
544
%assign cpuflags_aligned (1<<21) ; not a cpu feature, but a function variant
545
%assign cpuflags_atom (1<<22)
547
%define cpuflag(x) ((cpuflags & (cpuflags_ %+ x)) == (cpuflags_ %+ x))
548
%define notcpuflag(x) ((cpuflags & (cpuflags_ %+ x)) != (cpuflags_ %+ x))
550
; Takes up to 2 cpuflags from the above list.
551
; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.
552
; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.
553
%macro INIT_CPUFLAGS 0-2
556
%assign cpuflags cpuflags_%1
558
%xdefine cpuname %1_%2
559
%assign cpuflags cpuflags | cpuflags_%2
561
%xdefine SUFFIX _ %+ cpuname
563
%assign avx_enabled 1
565
%if mmsize == 16 && notcpuflag(sse2)
568
%define movnta movntps
593
%assign avx_enabled 0
594
%define RESET_MM_PERMUTATION INIT_MMX %1
600
%define movnta movntq
603
CAT_XDEFINE m, %%i, mm %+ %%i
604
CAT_XDEFINE nmm, %%i, %%i
616
%assign avx_enabled 0
617
%define RESET_MM_PERMUTATION INIT_XMM %1
621
%define num_mmregs 16
626
%define movnta movntdq
629
CAT_XDEFINE m, %%i, xmm %+ %%i
630
CAT_XDEFINE nxmm, %%i, %%i
636
; FIXME: INIT_AVX can be replaced by INIT_XMM avx
639
%assign avx_enabled 1
640
%define PALIGNR PALIGNR_SSSE3
641
%define RESET_MM_PERMUTATION INIT_AVX
645
%assign avx_enabled 1
646
%define RESET_MM_PERMUTATION INIT_YMM %1
650
%define num_mmregs 16
655
%define movnta vmovntps
658
CAT_XDEFINE m, %%i, ymm %+ %%i
659
CAT_XDEFINE nymm, %%i, %%i
667
; I often want to use macros that permute their arguments. e.g. there's no
668
; efficient way to implement butterfly or transpose or dct without swapping some
671
; I would like to not have to manually keep track of the permutations:
672
; If I insert a permutation in the middle of a function, it should automatically
673
; change everything that follows. For more complex macros I may also have multiple
674
; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.
676
; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that
677
; permutes its arguments. It's equivalent to exchanging the contents of the
678
; registers, except that this way you exchange the register names instead, so it
679
; doesn't cost any cycles.
681
%macro PERMUTE 2-* ; takes a list of pairs to swap
696
%macro SWAP 2-* ; swaps a single chain (sometimes more concise than pairs)
702
CAT_XDEFINE n, m%1, %1
703
CAT_XDEFINE n, m%2, %2
705
; If we were called as "SWAP m0,m1" rather than "SWAP 0,1" infer the original numbers here.
706
; Be careful using this mode in nested macros though, as in some cases there may be
707
; other copies of m# that have already been dereferenced and don't get updated correctly.
708
%xdefine %%n1 n %+ %1
709
%xdefine %%n2 n %+ %2
710
%xdefine tmp m %+ %%n1
711
CAT_XDEFINE m, %%n1, m %+ %%n2
712
CAT_XDEFINE m, %%n2, tmp
713
CAT_XDEFINE n, m %+ %%n1, %%n1
714
CAT_XDEFINE n, m %+ %%n2, %%n2
721
; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later
722
; calls to that function will automatically load the permutation, so values can
723
; be returned in mmregs.
724
%macro SAVE_MM_PERMUTATION 0-1
728
%xdefine %%f current_function %+ _m
732
CAT_XDEFINE %%f, %%i, m %+ %%i
737
%macro LOAD_MM_PERMUTATION 1 ; name to load from
741
CAT_XDEFINE m, %%i, %1_m %+ %%i
742
CAT_XDEFINE n, m %+ %%i, %%i
748
; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't
750
call_internal %1, %1 %+ SUFFIX
752
%macro call_internal 2
760
LOAD_MM_PERMUTATION %%i
763
; Substitutions that reduce instruction size but are functionally equivalent
788
;=============================================================================
789
; AVX abstraction layer
790
;=============================================================================
795
CAT_XDEFINE sizeofmm, i, 8
797
CAT_XDEFINE sizeofxmm, i, 16
798
CAT_XDEFINE sizeofymm, i, 32
804
;%2 == 1 if float, 0 if int
805
;%3 == 1 if 4-operand (xmm, xmm, xmm, imm), 0 if 3-operand (xmm, xmm, xmm)
806
;%4 == number of operands given
808
%macro RUN_AVX_INSTR 6-7+
810
%define %%size sizeof%5
812
%define %%size mmsize
818
%define %%regmov movq
820
%define %%regmov movaps
822
%define %%regmov movdqa
827
%if avx_enabled && sizeof%5==16
844
; 3arg AVX ops with a memory arg can only have it in src2,
845
; whereas SSE emulation of 3arg prefers to have it in src1 (i.e. the mov).
846
; So, if the op is symmetric and the wrong one is memory, swap them.
847
%macro RUN_AVX_INSTR1 8
858
%if %%swap && %3 == 0 && %8 == 1
859
RUN_AVX_INSTR %1, %2, %3, %4, %5, %7, %6
861
RUN_AVX_INSTR %1, %2, %3, %4, %5, %6, %7
866
;%2 == 1 if float, 0 if int
867
;%3 == 1 if 4-operand (xmm, xmm, xmm, imm), 0 if 3-operand (xmm, xmm, xmm)
868
;%4 == 1 if symmetric (i.e. doesn't matter which src arg is which), 0 if not
870
%macro %1 2-9 fnord, fnord, fnord, %1, %2, %3, %4
872
RUN_AVX_INSTR %6, %7, %8, 2, %1, %2
874
RUN_AVX_INSTR1 %6, %7, %8, 3, %1, %2, %3, %9
876
RUN_AVX_INSTR %6, %7, %8, 4, %1, %2, %3, %4
878
RUN_AVX_INSTR %6, %7, %8, 5, %1, %2, %3, %4, %5
883
AVX_INSTR addpd, 1, 0, 1
884
AVX_INSTR addps, 1, 0, 1
885
AVX_INSTR addsd, 1, 0, 1
886
AVX_INSTR addss, 1, 0, 1
887
AVX_INSTR addsubpd, 1, 0, 0
888
AVX_INSTR addsubps, 1, 0, 0
889
AVX_INSTR andpd, 1, 0, 1
890
AVX_INSTR andps, 1, 0, 1
891
AVX_INSTR andnpd, 1, 0, 0
892
AVX_INSTR andnps, 1, 0, 0
893
AVX_INSTR blendpd, 1, 0, 0
894
AVX_INSTR blendps, 1, 0, 0
895
AVX_INSTR blendvpd, 1, 0, 0
896
AVX_INSTR blendvps, 1, 0, 0
897
AVX_INSTR cmppd, 1, 0, 0
898
AVX_INSTR cmpps, 1, 0, 0
899
AVX_INSTR cmpsd, 1, 0, 0
900
AVX_INSTR cmpss, 1, 0, 0
901
AVX_INSTR divpd, 1, 0, 0
902
AVX_INSTR divps, 1, 0, 0
903
AVX_INSTR divsd, 1, 0, 0
904
AVX_INSTR divss, 1, 0, 0
905
AVX_INSTR dppd, 1, 1, 0
906
AVX_INSTR dpps, 1, 1, 0
907
AVX_INSTR haddpd, 1, 0, 0
908
AVX_INSTR haddps, 1, 0, 0
909
AVX_INSTR hsubpd, 1, 0, 0
910
AVX_INSTR hsubps, 1, 0, 0
911
AVX_INSTR maxpd, 1, 0, 1
912
AVX_INSTR maxps, 1, 0, 1
913
AVX_INSTR maxsd, 1, 0, 1
914
AVX_INSTR maxss, 1, 0, 1
915
AVX_INSTR minpd, 1, 0, 1
916
AVX_INSTR minps, 1, 0, 1
917
AVX_INSTR minsd, 1, 0, 1
918
AVX_INSTR minss, 1, 0, 1
919
AVX_INSTR movhlps, 1, 0, 0
920
AVX_INSTR movlhps, 1, 0, 0
921
AVX_INSTR movsd, 1, 0, 0
922
AVX_INSTR movss, 1, 0, 0
923
AVX_INSTR mpsadbw, 0, 1, 0
924
AVX_INSTR mulpd, 1, 0, 1
925
AVX_INSTR mulps, 1, 0, 1
926
AVX_INSTR mulsd, 1, 0, 1
927
AVX_INSTR mulss, 1, 0, 1
928
AVX_INSTR orpd, 1, 0, 1
929
AVX_INSTR orps, 1, 0, 1
930
AVX_INSTR packsswb, 0, 0, 0
931
AVX_INSTR packssdw, 0, 0, 0
932
AVX_INSTR packuswb, 0, 0, 0
933
AVX_INSTR packusdw, 0, 0, 0
934
AVX_INSTR paddb, 0, 0, 1
935
AVX_INSTR paddw, 0, 0, 1
936
AVX_INSTR paddd, 0, 0, 1
937
AVX_INSTR paddq, 0, 0, 1
938
AVX_INSTR paddsb, 0, 0, 1
939
AVX_INSTR paddsw, 0, 0, 1
940
AVX_INSTR paddusb, 0, 0, 1
941
AVX_INSTR paddusw, 0, 0, 1
942
AVX_INSTR palignr, 0, 1, 0
943
AVX_INSTR pand, 0, 0, 1
944
AVX_INSTR pandn, 0, 0, 0
945
AVX_INSTR pavgb, 0, 0, 1
946
AVX_INSTR pavgw, 0, 0, 1
947
AVX_INSTR pblendvb, 0, 0, 0
948
AVX_INSTR pblendw, 0, 1, 0
949
AVX_INSTR pcmpestri, 0, 0, 0
950
AVX_INSTR pcmpestrm, 0, 0, 0
951
AVX_INSTR pcmpistri, 0, 0, 0
952
AVX_INSTR pcmpistrm, 0, 0, 0
953
AVX_INSTR pcmpeqb, 0, 0, 1
954
AVX_INSTR pcmpeqw, 0, 0, 1
955
AVX_INSTR pcmpeqd, 0, 0, 1
956
AVX_INSTR pcmpeqq, 0, 0, 1
957
AVX_INSTR pcmpgtb, 0, 0, 0
958
AVX_INSTR pcmpgtw, 0, 0, 0
959
AVX_INSTR pcmpgtd, 0, 0, 0
960
AVX_INSTR pcmpgtq, 0, 0, 0
961
AVX_INSTR phaddw, 0, 0, 0
962
AVX_INSTR phaddd, 0, 0, 0
963
AVX_INSTR phaddsw, 0, 0, 0
964
AVX_INSTR phsubw, 0, 0, 0
965
AVX_INSTR phsubd, 0, 0, 0
966
AVX_INSTR phsubsw, 0, 0, 0
967
AVX_INSTR pmaddwd, 0, 0, 1
968
AVX_INSTR pmaddubsw, 0, 0, 0
969
AVX_INSTR pmaxsb, 0, 0, 1
970
AVX_INSTR pmaxsw, 0, 0, 1
971
AVX_INSTR pmaxsd, 0, 0, 1
972
AVX_INSTR pmaxub, 0, 0, 1
973
AVX_INSTR pmaxuw, 0, 0, 1
974
AVX_INSTR pmaxud, 0, 0, 1
975
AVX_INSTR pminsb, 0, 0, 1
976
AVX_INSTR pminsw, 0, 0, 1
977
AVX_INSTR pminsd, 0, 0, 1
978
AVX_INSTR pminub, 0, 0, 1
979
AVX_INSTR pminuw, 0, 0, 1
980
AVX_INSTR pminud, 0, 0, 1
981
AVX_INSTR pmulhuw, 0, 0, 1
982
AVX_INSTR pmulhrsw, 0, 0, 1
983
AVX_INSTR pmulhw, 0, 0, 1
984
AVX_INSTR pmullw, 0, 0, 1
985
AVX_INSTR pmulld, 0, 0, 1
986
AVX_INSTR pmuludq, 0, 0, 1
987
AVX_INSTR pmuldq, 0, 0, 1
988
AVX_INSTR por, 0, 0, 1
989
AVX_INSTR psadbw, 0, 0, 1
990
AVX_INSTR pshufb, 0, 0, 0
991
AVX_INSTR psignb, 0, 0, 0
992
AVX_INSTR psignw, 0, 0, 0
993
AVX_INSTR psignd, 0, 0, 0
994
AVX_INSTR psllw, 0, 0, 0
995
AVX_INSTR pslld, 0, 0, 0
996
AVX_INSTR psllq, 0, 0, 0
997
AVX_INSTR pslldq, 0, 0, 0
998
AVX_INSTR psraw, 0, 0, 0
999
AVX_INSTR psrad, 0, 0, 0
1000
AVX_INSTR psrlw, 0, 0, 0
1001
AVX_INSTR psrld, 0, 0, 0
1002
AVX_INSTR psrlq, 0, 0, 0
1003
AVX_INSTR psrldq, 0, 0, 0
1004
AVX_INSTR psubb, 0, 0, 0
1005
AVX_INSTR psubw, 0, 0, 0
1006
AVX_INSTR psubd, 0, 0, 0
1007
AVX_INSTR psubq, 0, 0, 0
1008
AVX_INSTR psubsb, 0, 0, 0
1009
AVX_INSTR psubsw, 0, 0, 0
1010
AVX_INSTR psubusb, 0, 0, 0
1011
AVX_INSTR psubusw, 0, 0, 0
1012
AVX_INSTR punpckhbw, 0, 0, 0
1013
AVX_INSTR punpckhwd, 0, 0, 0
1014
AVX_INSTR punpckhdq, 0, 0, 0
1015
AVX_INSTR punpckhqdq, 0, 0, 0
1016
AVX_INSTR punpcklbw, 0, 0, 0
1017
AVX_INSTR punpcklwd, 0, 0, 0
1018
AVX_INSTR punpckldq, 0, 0, 0
1019
AVX_INSTR punpcklqdq, 0, 0, 0
1020
AVX_INSTR pxor, 0, 0, 1
1021
AVX_INSTR shufps, 1, 1, 0
1022
AVX_INSTR subpd, 1, 0, 0
1023
AVX_INSTR subps, 1, 0, 0
1024
AVX_INSTR subsd, 1, 0, 0
1025
AVX_INSTR subss, 1, 0, 0
1026
AVX_INSTR unpckhpd, 1, 0, 0
1027
AVX_INSTR unpckhps, 1, 0, 0
1028
AVX_INSTR unpcklpd, 1, 0, 0
1029
AVX_INSTR unpcklps, 1, 0, 0
1030
AVX_INSTR xorpd, 1, 0, 1
1031
AVX_INSTR xorps, 1, 0, 1
1033
; 3DNow instructions, for sharing code between AVX, SSE and 3DN
1034
AVX_INSTR pfadd, 1, 0, 1
1035
AVX_INSTR pfsub, 1, 0, 0
1036
AVX_INSTR pfmul, 1, 0, 1
1038
; base-4 constants for shuffles
1041
%assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)
1043
CAT_XDEFINE q000, j, i
1045
CAT_XDEFINE q00, j, i
1047
CAT_XDEFINE q0, j, i
1057
%macro %1 4-7 %1, %2, %3
1067
FMA_INSTR pmacsdd, pmulld, paddd
1068
FMA_INSTR pmacsww, pmullw, paddw
1069
FMA_INSTR pmadcswd, pmaddwd, paddd
added
removed
libavutil/x86/x86inc.asm
