4
* Attiny portability header.
5
* This helps abstract away the differences between various attiny MCUs.
7
* Copyright (C) 2015 Selene Scriven
9
* This program is free software: you can redistribute it and/or modify
10
* it under the terms of the GNU General Public License as published by
11
* the Free Software Foundation, either version 3 of the License, or
12
* (at your option) any later version.
14
* This program is distributed in the hope that it will be useful,
15
* but WITHOUT ANY WARRANTY; without even the implied warranty of
16
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17
* GNU General Public License for more details.
19
* You should have received a copy of the GNU General Public License
20
* along with this program. If not, see <http://www.gnu.org/licenses/>.
24
// Choose your MCU here, or in the main .c file, or in the build script
28
/******************** hardware-specific values **************************/
30
#define F_CPU 4800000UL
35
// TODO: Use 6.4 MHz instead of 8 MHz?
36
#define F_CPU 8000000UL
39
#define BOGOMIPS (F_CPU/3200)
41
Hey, you need to define ATTINY.
45
/******************** I/O pin and register layout ************************/
46
#ifdef FET_7135_LAYOUT
50
* OTC -|2 7|- Voltage ADC
51
* Star 3 -|3 6|- PWM (FET)
52
* GND -|4 5|- PWM (1x7135)
56
#define STAR2_PIN PB0 // If this pin isn't used for ALT_PWM
57
#define STAR3_PIN PB4 // pin 3
59
#define CAP_PIN PB3 // pin 2, OTC
60
#define CAP_CHANNEL 0x03 // MUX 03 corresponds with PB3 (Star 4)
61
#define CAP_DIDR ADC3D // Digital input disable bit corresponding with PB3
63
#define PWM_PIN PB1 // pin 6, FET PWM
64
#define PWM_LVL OCR0B // OCR0B is the output compare register for PB1
65
#define ALT_PWM_PIN PB0 // pin 5, 1x7135 PWM
66
#define ALT_PWM_LVL OCR0A // OCR0A is the output compare register for PB0
68
#define VOLTAGE_PIN PB2 // pin 7, voltage ADC
69
#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2
70
#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2
71
#define ADC_PRSCL 0x06 // clk/64
73
//#define TEMP_DIDR ADC4D
74
#define TEMP_CHANNEL 0b00001111
76
#endif // FET_7135_LAYOUT
78
#ifdef TRIPLEDOWN_LAYOUT
82
* OTC -|2 7|- Voltage ADC
83
* PWM (FET) -|3 6|- PWM (6x7135)
84
* GND -|4 5|- PWM (1x7135)
88
#define STAR2_PIN PB0 // If this pin isn't used for ALT_PWM
90
#define CAP_PIN PB3 // pin 2, OTC
91
#define CAP_CHANNEL 0x03 // MUX 03 corresponds with PB3 (Star 4)
92
#define CAP_DIDR ADC3D // Digital input disable bit corresponding with PB3
94
#define PWM_PIN PB1 // pin 6, 6x7135 PWM
95
#define PWM_LVL OCR0B // OCR0B is the output compare register for PB1
96
#define ALT_PWM_PIN PB0 // pin 5, 1x7135 PWM
97
#define ALT_PWM_LVL OCR0A // OCR0A is the output compare register for PB0
98
#define FET_PWM_PIN PB4 // pin 3
99
#define FET_PWM_LVL OCR1B // output compare register for PB4
101
#define VOLTAGE_PIN PB2 // pin 7, voltage ADC
102
#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2
103
#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2
104
#define ADC_PRSCL 0x06 // clk/64
106
//#define TEMP_DIDR ADC4D
107
#define TEMP_CHANNEL 0b00001111
109
#endif // FET_7135_LAYOUT
111
#ifdef FERRERO_ROCHER_LAYOUT
115
* E-switch -|2 7|- Voltage ADC
116
* Red LED -|3 6|- PWM
117
* GND -|4 5|- Green LED
120
// TODO: fill in this section, update Ferrero_Rocher code to use it.
121
#endif // FERRERO_ROCHER_LAYOUT
124
#define STAR2_PIN PB0
125
#define STAR3_PIN PB4
126
#define STAR4_PIN PB3
128
#define VOLTAGE_PIN PB2
129
#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2
130
#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2
131
#define ADC_PRSCL 0x06 // clk/64
133
#define PWM_LVL OCR0B // OCR0B is the output compare register for PB1
134
#endif // NANJG_LAYOUT
137
Hey, you need to define an I/O pin layout.
140
#endif // TK_ATTINY_H