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//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
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// both before and after the DAG is legalized.
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// This pass is not a substitute for the LLVM IR instcombine pass. This pass is
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// primarily intended to handle simplification opportunities that are implicit
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// in the LLVM IR and exposed by the various codegen lowering phases.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "dagcombine"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/LLVMContext.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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STATISTIC(NodesCombined , "Number of dag nodes combined");
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STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
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STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
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STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
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CombinerAA("combiner-alias-analysis", cl::Hidden,
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cl::desc("Turn on alias analysis during testing"));
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CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
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cl::desc("Include global information in alias analysis"));
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//------------------------------ DAGCombiner ---------------------------------//
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const TargetLowering &TLI;
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CodeGenOpt::Level OptLevel;
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// Worklist of all of the nodes that need to be simplified.
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std::vector<SDNode*> WorkList;
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// AA - Used for DAG load/store alias analysis.
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/// AddUsersToWorkList - When an instruction is simplified, add all users of
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/// the instruction to the work lists because they might get more simplified
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void AddUsersToWorkList(SDNode *N) {
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for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
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/// visit - call the node-specific routine that knows how to fold each
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/// particular type of node.
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SDValue visit(SDNode *N);
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/// AddToWorkList - Add to the work list making sure it's instance is at the
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/// the back (next to be processed.)
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void AddToWorkList(SDNode *N) {
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removeFromWorkList(N);
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WorkList.push_back(N);
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/// removeFromWorkList - remove all instances of N from the worklist.
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void removeFromWorkList(SDNode *N) {
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WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
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SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
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SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
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return CombineTo(N, &Res, 1, AddTo);
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SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
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SDValue To[] = { Res0, Res1 };
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return CombineTo(N, To, 2, AddTo);
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void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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/// it can be simplified or if things it uses can be simplified by bit
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/// propagation. If so, return true.
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bool SimplifyDemandedBits(SDValue Op) {
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unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
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APInt Demanded = APInt::getAllOnesValue(BitWidth);
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return SimplifyDemandedBits(Op, Demanded);
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bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
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bool CombineToPreIndexedLoadStore(SDNode *N);
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bool CombineToPostIndexedLoadStore(SDNode *N);
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void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
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SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
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SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
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SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
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SDValue PromoteIntBinOp(SDValue Op);
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SDValue PromoteIntShiftOp(SDValue Op);
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SDValue PromoteExtend(SDValue Op);
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bool PromoteLoad(SDValue Op);
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/// combine - call the node-specific routine that knows how to fold each
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/// particular type of node. If that doesn't do anything, try the
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/// target-specific DAG combines.
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SDValue combine(SDNode *N);
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// Visitation implementation - Implement dag node combining for different
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// node types. The semantics are as follows:
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// SDValue.getNode() == 0 - No change was made
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// SDValue.getNode() == N - N was replaced, is dead and has been handled.
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// otherwise - N should be replaced by the returned Operand.
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SDValue visitTokenFactor(SDNode *N);
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SDValue visitMERGE_VALUES(SDNode *N);
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SDValue visitADD(SDNode *N);
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SDValue visitSUB(SDNode *N);
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SDValue visitADDC(SDNode *N);
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SDValue visitADDE(SDNode *N);
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SDValue visitMUL(SDNode *N);
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SDValue visitSDIV(SDNode *N);
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SDValue visitUDIV(SDNode *N);
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SDValue visitSREM(SDNode *N);
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SDValue visitUREM(SDNode *N);
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SDValue visitMULHU(SDNode *N);
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SDValue visitMULHS(SDNode *N);
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SDValue visitSMUL_LOHI(SDNode *N);
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SDValue visitUMUL_LOHI(SDNode *N);
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SDValue visitSDIVREM(SDNode *N);
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SDValue visitUDIVREM(SDNode *N);
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SDValue visitAND(SDNode *N);
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SDValue visitOR(SDNode *N);
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SDValue visitXOR(SDNode *N);
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SDValue SimplifyVBinOp(SDNode *N);
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SDValue visitSHL(SDNode *N);
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SDValue visitSRA(SDNode *N);
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SDValue visitSRL(SDNode *N);
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SDValue visitCTLZ(SDNode *N);
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SDValue visitCTTZ(SDNode *N);
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SDValue visitCTPOP(SDNode *N);
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SDValue visitSELECT(SDNode *N);
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SDValue visitSELECT_CC(SDNode *N);
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SDValue visitSETCC(SDNode *N);
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SDValue visitSIGN_EXTEND(SDNode *N);
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SDValue visitZERO_EXTEND(SDNode *N);
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SDValue visitANY_EXTEND(SDNode *N);
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SDValue visitSIGN_EXTEND_INREG(SDNode *N);
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SDValue visitTRUNCATE(SDNode *N);
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SDValue visitBIT_CONVERT(SDNode *N);
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SDValue visitBUILD_PAIR(SDNode *N);
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SDValue visitFADD(SDNode *N);
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SDValue visitFSUB(SDNode *N);
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SDValue visitFMUL(SDNode *N);
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SDValue visitFDIV(SDNode *N);
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SDValue visitFREM(SDNode *N);
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SDValue visitFCOPYSIGN(SDNode *N);
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SDValue visitSINT_TO_FP(SDNode *N);
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SDValue visitUINT_TO_FP(SDNode *N);
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SDValue visitFP_TO_SINT(SDNode *N);
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SDValue visitFP_TO_UINT(SDNode *N);
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SDValue visitFP_ROUND(SDNode *N);
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SDValue visitFP_ROUND_INREG(SDNode *N);
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SDValue visitFP_EXTEND(SDNode *N);
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SDValue visitFNEG(SDNode *N);
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SDValue visitFABS(SDNode *N);
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SDValue visitBRCOND(SDNode *N);
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SDValue visitBR_CC(SDNode *N);
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SDValue visitLOAD(SDNode *N);
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SDValue visitSTORE(SDNode *N);
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SDValue visitINSERT_VECTOR_ELT(SDNode *N);
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SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
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SDValue visitBUILD_VECTOR(SDNode *N);
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SDValue visitCONCAT_VECTORS(SDNode *N);
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SDValue visitVECTOR_SHUFFLE(SDNode *N);
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SDValue visitMEMBARRIER(SDNode *N);
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SDValue XformToShuffleWithZero(SDNode *N);
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SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
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SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
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bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
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SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
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SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
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SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
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SDValue N3, ISD::CondCode CC,
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bool NotExtCompare = false);
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SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
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DebugLoc DL, bool foldBooleans = true);
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SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
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SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
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SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT);
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SDValue BuildSDIV(SDNode *N);
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SDValue BuildUDIV(SDNode *N);
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SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
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SDValue ReduceLoadWidth(SDNode *N);
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SDValue ReduceLoadOpStoreWidth(SDNode *N);
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SDValue GetDemandedBits(SDValue V, const APInt &Mask);
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/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
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/// looking for aliasing nodes and adding them to the Aliases vector.
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void GatherAllAliases(SDNode *N, SDValue OriginalChain,
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SmallVector<SDValue, 8> &Aliases);
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/// isAlias - Return true if there is any possibility that the two addresses
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bool isAlias(SDValue Ptr1, int64_t Size1,
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const Value *SrcValue1, int SrcValueOffset1,
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unsigned SrcValueAlign1,
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SDValue Ptr2, int64_t Size2,
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const Value *SrcValue2, int SrcValueOffset2,
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unsigned SrcValueAlign2) const;
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/// FindAliasInfo - Extracts the relevant alias information from the memory
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/// node. Returns true if the operand was a load.
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bool FindAliasInfo(SDNode *N,
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SDValue &Ptr, int64_t &Size,
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const Value *&SrcValue, int &SrcValueOffset,
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unsigned &SrcValueAlignment) const;
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/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
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/// looking for a better chain (aliasing node.)
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SDValue FindBetterChain(SDNode *N, SDValue Chain);
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DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
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: DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
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OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
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/// Run - runs the dag combiner on all nodes in the work list
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void Run(CombineLevel AtLevel);
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SelectionDAG &getDAG() const { return DAG; }
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/// getShiftAmountTy - Returns a type large enough to hold any valid
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/// shift amount - before type legalization these can be huge.
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EVT getShiftAmountTy() {
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return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
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/// isTypeLegal - This method returns true if we are running before type
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/// legalization or if the specified VT is legal.
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bool isTypeLegal(const EVT &VT) {
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if (!LegalTypes) return true;
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return TLI.isTypeLegal(VT);
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/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
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/// nodes from the worklist.
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class WorkListRemover : public SelectionDAG::DAGUpdateListener {
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explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
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virtual void NodeDeleted(SDNode *N, SDNode *E) {
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DC.removeFromWorkList(N);
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virtual void NodeUpdated(SDNode *N) {
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//===----------------------------------------------------------------------===//
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// TargetLowering::DAGCombinerInfo implementation
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//===----------------------------------------------------------------------===//
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void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
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((DAGCombiner*)DC)->AddToWorkList(N);
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SDValue TargetLowering::DAGCombinerInfo::
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CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
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return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
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SDValue TargetLowering::DAGCombinerInfo::
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CombineTo(SDNode *N, SDValue Res, bool AddTo) {
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return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
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SDValue TargetLowering::DAGCombinerInfo::
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CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
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return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
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void TargetLowering::DAGCombinerInfo::
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CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
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return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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/// isNegatibleForFree - Return 1 if we can compute the negated form of the
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/// specified expression for the same cost as the expression itself, or 2 if we
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/// can compute the negated form more cheaply than the expression itself.
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static char isNegatibleForFree(SDValue Op, bool LegalOperations,
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unsigned Depth = 0) {
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// No compile time optimizations on this type.
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if (Op.getValueType() == MVT::ppcf128)
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// fneg is removable even if it has multiple uses.
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if (Op.getOpcode() == ISD::FNEG) return 2;
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// Don't allow anything with multiple uses.
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if (!Op.hasOneUse()) return 0;
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// Don't recurse exponentially.
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if (Depth > 6) return 0;
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switch (Op.getOpcode()) {
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default: return false;
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case ISD::ConstantFP:
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// Don't invert constant FP values after legalize. The negated constant
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// isn't necessarily legal.
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return LegalOperations ? 0 : 1;
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// FIXME: determine better conditions for this xform.
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if (!UnsafeFPMath) return 0;
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// fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
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if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
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// fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
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return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
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// We can't turn -(A-B) into B-A when we honor signed zeros.
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if (!UnsafeFPMath) return 0;
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// fold (fneg (fsub A, B)) -> (fsub B, A)
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if (HonorSignDependentRoundingFPMath()) return 0;
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// fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
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if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
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return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
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return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
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/// GetNegatedExpression - If isNegatibleForFree returns true, this function
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/// returns the newly negated expression.
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static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
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bool LegalOperations, unsigned Depth = 0) {
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// fneg is removable even if it has multiple uses.
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if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
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// Don't allow anything with multiple uses.
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assert(Op.hasOneUse() && "Unknown reuse!");
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assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
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switch (Op.getOpcode()) {
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default: llvm_unreachable("Unknown code");
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case ISD::ConstantFP: {
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APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
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return DAG.getConstantFP(V, Op.getValueType());
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// FIXME: determine better conditions for this xform.
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assert(UnsafeFPMath);
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// fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
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if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
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return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
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GetNegatedExpression(Op.getOperand(0), DAG,
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LegalOperations, Depth+1),
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// fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
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return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
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GetNegatedExpression(Op.getOperand(1), DAG,
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LegalOperations, Depth+1),
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// We can't turn -(A-B) into B-A when we honor signed zeros.
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assert(UnsafeFPMath);
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// fold (fneg (fsub 0, B)) -> B
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if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
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if (N0CFP->getValueAPF().isZero())
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return Op.getOperand(1);
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// fold (fneg (fsub A, B)) -> (fsub B, A)
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return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
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Op.getOperand(1), Op.getOperand(0));
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assert(!HonorSignDependentRoundingFPMath());
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// fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
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if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
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return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
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GetNegatedExpression(Op.getOperand(0), DAG,
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LegalOperations, Depth+1),
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// fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
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return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
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GetNegatedExpression(Op.getOperand(1), DAG,
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LegalOperations, Depth+1));
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return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
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GetNegatedExpression(Op.getOperand(0), DAG,
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LegalOperations, Depth+1));
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return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
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GetNegatedExpression(Op.getOperand(0), DAG,
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LegalOperations, Depth+1),
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// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
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// that selects between the values 1 and 0, making it equivalent to a setcc.
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// Also, set the incoming LHS, RHS, and CC references to the appropriate
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// nodes based on the type of node we are checking. This simplifies life a
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// bit for the callers.
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static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
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if (N.getOpcode() == ISD::SETCC) {
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LHS = N.getOperand(0);
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RHS = N.getOperand(1);
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CC = N.getOperand(2);
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if (N.getOpcode() == ISD::SELECT_CC &&
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N.getOperand(2).getOpcode() == ISD::Constant &&
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N.getOperand(3).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
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cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
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LHS = N.getOperand(0);
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RHS = N.getOperand(1);
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CC = N.getOperand(4);
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// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
504
// one use. If this is true, it allows the users to invert the operation for
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// free when it is profitable to do so.
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static bool isOneUseSetCC(SDValue N) {
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if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
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SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
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SDValue N0, SDValue N1) {
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EVT VT = N0.getValueType();
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if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
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if (isa<ConstantSDNode>(N1)) {
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// reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
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DAG.FoldConstantArithmetic(Opc, VT,
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cast<ConstantSDNode>(N0.getOperand(1)),
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cast<ConstantSDNode>(N1));
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return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
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} else if (N0.hasOneUse()) {
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// reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
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SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
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N0.getOperand(0), N1);
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AddToWorkList(OpNode.getNode());
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return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
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if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
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if (isa<ConstantSDNode>(N0)) {
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// reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
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DAG.FoldConstantArithmetic(Opc, VT,
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cast<ConstantSDNode>(N1.getOperand(1)),
539
cast<ConstantSDNode>(N0));
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return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
541
} else if (N1.hasOneUse()) {
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// reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
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SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
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N1.getOperand(0), N0);
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AddToWorkList(OpNode.getNode());
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return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
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SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
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assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
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DEBUG(dbgs() << "\nReplacing.1 ";
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dbgs() << "\nWith: ";
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To[0].getNode()->dump(&DAG);
561
dbgs() << " and " << NumTo-1 << " other values\n";
562
for (unsigned i = 0, e = NumTo; i != e; ++i)
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assert((!To[i].getNode() ||
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N->getValueType(i) == To[i].getValueType()) &&
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"Cannot combine value to value of different type!"));
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WorkListRemover DeadNodes(*this);
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DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
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// Push the new nodes and any users onto the worklist
571
for (unsigned i = 0, e = NumTo; i != e; ++i) {
572
if (To[i].getNode()) {
573
AddToWorkList(To[i].getNode());
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AddUsersToWorkList(To[i].getNode());
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// Finally, if the node is now dead, remove it from the graph. The node
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// may not be dead if the replacement process recursively simplified to
581
// something else needing this node.
582
if (N->use_empty()) {
583
// Nodes can be reintroduced into the worklist. Make sure we do not
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// process a node that has been replaced.
585
removeFromWorkList(N);
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// Finally, since the node is now dead, remove it from the graph.
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return SDValue(N, 0);
594
CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
595
// Replace all uses. If any nodes become isomorphic to other nodes and
596
// are deleted, make sure to remove them from our worklist.
597
WorkListRemover DeadNodes(*this);
598
DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
600
// Push the new node and any (possibly new) users onto the worklist.
601
AddToWorkList(TLO.New.getNode());
602
AddUsersToWorkList(TLO.New.getNode());
604
// Finally, if the node is now dead, remove it from the graph. The node
605
// may not be dead if the replacement process recursively simplified to
606
// something else needing this node.
607
if (TLO.Old.getNode()->use_empty()) {
608
removeFromWorkList(TLO.Old.getNode());
610
// If the operands of this node are only used by the node, they will now
611
// be dead. Make sure to visit them first to delete dead nodes early.
612
for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
613
if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
614
AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
616
DAG.DeleteNode(TLO.Old.getNode());
620
/// SimplifyDemandedBits - Check the specified integer node value to see if
621
/// it can be simplified or if things it uses can be simplified by bit
622
/// propagation. If so, return true.
623
bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
624
TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
625
APInt KnownZero, KnownOne;
626
if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
630
AddToWorkList(Op.getNode());
632
// Replace the old value with the new one.
634
DEBUG(dbgs() << "\nReplacing.2 ";
635
TLO.Old.getNode()->dump(&DAG);
636
dbgs() << "\nWith: ";
637
TLO.New.getNode()->dump(&DAG);
640
CommitTargetLoweringOpt(TLO);
644
void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
645
DebugLoc dl = Load->getDebugLoc();
646
EVT VT = Load->getValueType(0);
647
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
649
DEBUG(dbgs() << "\nReplacing.9 ";
651
dbgs() << "\nWith: ";
652
Trunc.getNode()->dump(&DAG);
654
WorkListRemover DeadNodes(*this);
655
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
656
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
658
removeFromWorkList(Load);
659
DAG.DeleteNode(Load);
660
AddToWorkList(Trunc.getNode());
663
SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
665
DebugLoc dl = Op.getDebugLoc();
666
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
667
EVT MemVT = LD->getMemoryVT();
668
ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
669
? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
670
: LD->getExtensionType();
672
return DAG.getExtLoad(ExtType, PVT, dl,
673
LD->getChain(), LD->getBasePtr(),
674
LD->getSrcValue(), LD->getSrcValueOffset(),
675
MemVT, LD->isVolatile(),
676
LD->isNonTemporal(), LD->getAlignment());
679
unsigned Opc = Op.getOpcode();
682
case ISD::AssertSext:
683
return DAG.getNode(ISD::AssertSext, dl, PVT,
684
SExtPromoteOperand(Op.getOperand(0), PVT),
686
case ISD::AssertZext:
687
return DAG.getNode(ISD::AssertZext, dl, PVT,
688
ZExtPromoteOperand(Op.getOperand(0), PVT),
690
case ISD::Constant: {
692
Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
693
return DAG.getNode(ExtOpc, dl, PVT, Op);
697
if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
699
return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
702
SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
703
if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
705
EVT OldVT = Op.getValueType();
706
DebugLoc dl = Op.getDebugLoc();
707
bool Replace = false;
708
SDValue NewOp = PromoteOperand(Op, PVT, Replace);
709
if (NewOp.getNode() == 0)
711
AddToWorkList(NewOp.getNode());
714
ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
715
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
716
DAG.getValueType(OldVT));
719
SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
720
EVT OldVT = Op.getValueType();
721
DebugLoc dl = Op.getDebugLoc();
722
bool Replace = false;
723
SDValue NewOp = PromoteOperand(Op, PVT, Replace);
724
if (NewOp.getNode() == 0)
726
AddToWorkList(NewOp.getNode());
729
ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
730
return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
733
/// PromoteIntBinOp - Promote the specified integer binary operation if the
734
/// target indicates it is beneficial. e.g. On x86, it's usually better to
735
/// promote i16 operations to i32 since i16 instructions are longer.
736
SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
737
if (!LegalOperations)
740
EVT VT = Op.getValueType();
741
if (VT.isVector() || !VT.isInteger())
744
// If operation type is 'undesirable', e.g. i16 on x86, consider
746
unsigned Opc = Op.getOpcode();
747
if (TLI.isTypeDesirableForOp(Opc, VT))
751
// Consult target whether it is a good idea to promote this operation and
752
// what's the right type to promote it to.
753
if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
754
assert(PVT != VT && "Don't know what type to promote to!");
756
bool Replace0 = false;
757
SDValue N0 = Op.getOperand(0);
758
SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
759
if (NN0.getNode() == 0)
762
bool Replace1 = false;
763
SDValue N1 = Op.getOperand(1);
768
NN1 = PromoteOperand(N1, PVT, Replace1);
769
if (NN1.getNode() == 0)
773
AddToWorkList(NN0.getNode());
775
AddToWorkList(NN1.getNode());
778
ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
780
ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
782
DEBUG(dbgs() << "\nPromoting ";
783
Op.getNode()->dump(&DAG));
784
DebugLoc dl = Op.getDebugLoc();
785
return DAG.getNode(ISD::TRUNCATE, dl, VT,
786
DAG.getNode(Opc, dl, PVT, NN0, NN1));
791
/// PromoteIntShiftOp - Promote the specified integer shift operation if the
792
/// target indicates it is beneficial. e.g. On x86, it's usually better to
793
/// promote i16 operations to i32 since i16 instructions are longer.
794
SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
795
if (!LegalOperations)
798
EVT VT = Op.getValueType();
799
if (VT.isVector() || !VT.isInteger())
802
// If operation type is 'undesirable', e.g. i16 on x86, consider
804
unsigned Opc = Op.getOpcode();
805
if (TLI.isTypeDesirableForOp(Opc, VT))
809
// Consult target whether it is a good idea to promote this operation and
810
// what's the right type to promote it to.
811
if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
812
assert(PVT != VT && "Don't know what type to promote to!");
814
bool Replace = false;
815
SDValue N0 = Op.getOperand(0);
817
N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
818
else if (Opc == ISD::SRL)
819
N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
821
N0 = PromoteOperand(N0, PVT, Replace);
822
if (N0.getNode() == 0)
825
AddToWorkList(N0.getNode());
827
ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
829
DEBUG(dbgs() << "\nPromoting ";
830
Op.getNode()->dump(&DAG));
831
DebugLoc dl = Op.getDebugLoc();
832
return DAG.getNode(ISD::TRUNCATE, dl, VT,
833
DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
838
SDValue DAGCombiner::PromoteExtend(SDValue Op) {
839
if (!LegalOperations)
842
EVT VT = Op.getValueType();
843
if (VT.isVector() || !VT.isInteger())
846
// If operation type is 'undesirable', e.g. i16 on x86, consider
848
unsigned Opc = Op.getOpcode();
849
if (TLI.isTypeDesirableForOp(Opc, VT))
853
// Consult target whether it is a good idea to promote this operation and
854
// what's the right type to promote it to.
855
if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
856
assert(PVT != VT && "Don't know what type to promote to!");
857
// fold (aext (aext x)) -> (aext x)
858
// fold (aext (zext x)) -> (zext x)
859
// fold (aext (sext x)) -> (sext x)
860
DEBUG(dbgs() << "\nPromoting ";
861
Op.getNode()->dump(&DAG));
862
return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
867
bool DAGCombiner::PromoteLoad(SDValue Op) {
868
if (!LegalOperations)
871
EVT VT = Op.getValueType();
872
if (VT.isVector() || !VT.isInteger())
875
// If operation type is 'undesirable', e.g. i16 on x86, consider
877
unsigned Opc = Op.getOpcode();
878
if (TLI.isTypeDesirableForOp(Opc, VT))
882
// Consult target whether it is a good idea to promote this operation and
883
// what's the right type to promote it to.
884
if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
885
assert(PVT != VT && "Don't know what type to promote to!");
887
DebugLoc dl = Op.getDebugLoc();
888
SDNode *N = Op.getNode();
889
LoadSDNode *LD = cast<LoadSDNode>(N);
890
EVT MemVT = LD->getMemoryVT();
891
ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
892
? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
893
: LD->getExtensionType();
894
SDValue NewLD = DAG.getExtLoad(ExtType, PVT, dl,
895
LD->getChain(), LD->getBasePtr(),
896
LD->getSrcValue(), LD->getSrcValueOffset(),
897
MemVT, LD->isVolatile(),
898
LD->isNonTemporal(), LD->getAlignment());
899
SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
901
DEBUG(dbgs() << "\nPromoting ";
904
Result.getNode()->dump(&DAG);
906
WorkListRemover DeadNodes(*this);
907
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
908
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
909
removeFromWorkList(N);
911
AddToWorkList(Result.getNode());
918
//===----------------------------------------------------------------------===//
919
// Main DAG Combiner implementation
920
//===----------------------------------------------------------------------===//
922
void DAGCombiner::Run(CombineLevel AtLevel) {
923
// set the instance variables, so that the various visit routines may use it.
925
LegalOperations = Level >= NoIllegalOperations;
926
LegalTypes = Level >= NoIllegalTypes;
928
// Add all the dag nodes to the worklist.
929
WorkList.reserve(DAG.allnodes_size());
930
for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
931
E = DAG.allnodes_end(); I != E; ++I)
932
WorkList.push_back(I);
934
// Create a dummy node (which is not added to allnodes), that adds a reference
935
// to the root node, preventing it from being deleted, and tracking any
936
// changes of the root.
937
HandleSDNode Dummy(DAG.getRoot());
939
// The root of the dag may dangle to deleted nodes until the dag combiner is
940
// done. Set it to null to avoid confusion.
941
DAG.setRoot(SDValue());
943
// while the worklist isn't empty, inspect the node on the end of it and
944
// try and combine it.
945
while (!WorkList.empty()) {
946
SDNode *N = WorkList.back();
949
// If N has no uses, it is dead. Make sure to revisit all N's operands once
950
// N is deleted from the DAG, since they too may now be dead or may have a
951
// reduced number of uses, allowing other xforms.
952
if (N->use_empty() && N != &Dummy) {
953
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
954
AddToWorkList(N->getOperand(i).getNode());
960
SDValue RV = combine(N);
962
if (RV.getNode() == 0)
967
// If we get back the same node we passed in, rather than a new node or
968
// zero, we know that the node must have defined multiple values and
969
// CombineTo was used. Since CombineTo takes care of the worklist
970
// mechanics for us, we have no work to do in this case.
971
if (RV.getNode() == N)
974
assert(N->getOpcode() != ISD::DELETED_NODE &&
975
RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
976
"Node was deleted but visit returned new node!");
978
DEBUG(dbgs() << "\nReplacing.3 ";
980
dbgs() << "\nWith: ";
981
RV.getNode()->dump(&DAG);
983
WorkListRemover DeadNodes(*this);
984
if (N->getNumValues() == RV.getNode()->getNumValues())
985
DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
987
assert(N->getValueType(0) == RV.getValueType() &&
988
N->getNumValues() == 1 && "Type mismatch");
990
DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
993
// Push the new node and any users onto the worklist
994
AddToWorkList(RV.getNode());
995
AddUsersToWorkList(RV.getNode());
997
// Add any uses of the old node to the worklist in case this node is the
998
// last one that uses them. They may become dead after this node is
1000
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1001
AddToWorkList(N->getOperand(i).getNode());
1003
// Finally, if the node is now dead, remove it from the graph. The node
1004
// may not be dead if the replacement process recursively simplified to
1005
// something else needing this node.
1006
if (N->use_empty()) {
1007
// Nodes can be reintroduced into the worklist. Make sure we do not
1008
// process a node that has been replaced.
1009
removeFromWorkList(N);
1011
// Finally, since the node is now dead, remove it from the graph.
1016
// If the root changed (e.g. it was a dead load, update the root).
1017
DAG.setRoot(Dummy.getValue());
1020
SDValue DAGCombiner::visit(SDNode *N) {
1021
switch (N->getOpcode()) {
1023
case ISD::TokenFactor: return visitTokenFactor(N);
1024
case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1025
case ISD::ADD: return visitADD(N);
1026
case ISD::SUB: return visitSUB(N);
1027
case ISD::ADDC: return visitADDC(N);
1028
case ISD::ADDE: return visitADDE(N);
1029
case ISD::MUL: return visitMUL(N);
1030
case ISD::SDIV: return visitSDIV(N);
1031
case ISD::UDIV: return visitUDIV(N);
1032
case ISD::SREM: return visitSREM(N);
1033
case ISD::UREM: return visitUREM(N);
1034
case ISD::MULHU: return visitMULHU(N);
1035
case ISD::MULHS: return visitMULHS(N);
1036
case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1037
case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1038
case ISD::SDIVREM: return visitSDIVREM(N);
1039
case ISD::UDIVREM: return visitUDIVREM(N);
1040
case ISD::AND: return visitAND(N);
1041
case ISD::OR: return visitOR(N);
1042
case ISD::XOR: return visitXOR(N);
1043
case ISD::SHL: return visitSHL(N);
1044
case ISD::SRA: return visitSRA(N);
1045
case ISD::SRL: return visitSRL(N);
1046
case ISD::CTLZ: return visitCTLZ(N);
1047
case ISD::CTTZ: return visitCTTZ(N);
1048
case ISD::CTPOP: return visitCTPOP(N);
1049
case ISD::SELECT: return visitSELECT(N);
1050
case ISD::SELECT_CC: return visitSELECT_CC(N);
1051
case ISD::SETCC: return visitSETCC(N);
1052
case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1053
case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1054
case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1055
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1056
case ISD::TRUNCATE: return visitTRUNCATE(N);
1057
case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
1058
case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1059
case ISD::FADD: return visitFADD(N);
1060
case ISD::FSUB: return visitFSUB(N);
1061
case ISD::FMUL: return visitFMUL(N);
1062
case ISD::FDIV: return visitFDIV(N);
1063
case ISD::FREM: return visitFREM(N);
1064
case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1065
case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1066
case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1067
case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1068
case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1069
case ISD::FP_ROUND: return visitFP_ROUND(N);
1070
case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1071
case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1072
case ISD::FNEG: return visitFNEG(N);
1073
case ISD::FABS: return visitFABS(N);
1074
case ISD::BRCOND: return visitBRCOND(N);
1075
case ISD::BR_CC: return visitBR_CC(N);
1076
case ISD::LOAD: return visitLOAD(N);
1077
case ISD::STORE: return visitSTORE(N);
1078
case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1079
case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1080
case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1081
case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1082
case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1083
case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1088
SDValue DAGCombiner::combine(SDNode *N) {
1089
SDValue RV = visit(N);
1091
// If nothing happened, try a target-specific DAG combine.
1092
if (RV.getNode() == 0) {
1093
assert(N->getOpcode() != ISD::DELETED_NODE &&
1094
"Node was deleted but visit returned NULL!");
1096
if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1097
TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1099
// Expose the DAG combiner to the target combiner impls.
1100
TargetLowering::DAGCombinerInfo
1101
DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1103
RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1107
// If nothing happened still, try promoting the operation.
1108
if (RV.getNode() == 0) {
1109
switch (N->getOpcode()) {
1117
RV = PromoteIntBinOp(SDValue(N, 0));
1122
RV = PromoteIntShiftOp(SDValue(N, 0));
1124
case ISD::SIGN_EXTEND:
1125
case ISD::ZERO_EXTEND:
1126
case ISD::ANY_EXTEND:
1127
RV = PromoteExtend(SDValue(N, 0));
1130
if (PromoteLoad(SDValue(N, 0)))
1136
// If N is a commutative binary node, try commuting it to enable more
1138
if (RV.getNode() == 0 &&
1139
SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1140
N->getNumValues() == 1) {
1141
SDValue N0 = N->getOperand(0);
1142
SDValue N1 = N->getOperand(1);
1144
// Constant operands are canonicalized to RHS.
1145
if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1146
SDValue Ops[] = { N1, N0 };
1147
SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1150
return SDValue(CSENode, 0);
1157
/// getInputChainForNode - Given a node, return its input chain if it has one,
1158
/// otherwise return a null sd operand.
1159
static SDValue getInputChainForNode(SDNode *N) {
1160
if (unsigned NumOps = N->getNumOperands()) {
1161
if (N->getOperand(0).getValueType() == MVT::Other)
1162
return N->getOperand(0);
1163
else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1164
return N->getOperand(NumOps-1);
1165
for (unsigned i = 1; i < NumOps-1; ++i)
1166
if (N->getOperand(i).getValueType() == MVT::Other)
1167
return N->getOperand(i);
1172
SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1173
// If N has two operands, where one has an input chain equal to the other,
1174
// the 'other' chain is redundant.
1175
if (N->getNumOperands() == 2) {
1176
if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1177
return N->getOperand(0);
1178
if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1179
return N->getOperand(1);
1182
SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1183
SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1184
SmallPtrSet<SDNode*, 16> SeenOps;
1185
bool Changed = false; // If we should replace this token factor.
1187
// Start out with this token factor.
1190
// Iterate through token factors. The TFs grows when new token factors are
1192
for (unsigned i = 0; i < TFs.size(); ++i) {
1193
SDNode *TF = TFs[i];
1195
// Check each of the operands.
1196
for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1197
SDValue Op = TF->getOperand(i);
1199
switch (Op.getOpcode()) {
1200
case ISD::EntryToken:
1201
// Entry tokens don't need to be added to the list. They are
1206
case ISD::TokenFactor:
1207
if (Op.hasOneUse() &&
1208
std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1209
// Queue up for processing.
1210
TFs.push_back(Op.getNode());
1211
// Clean up in case the token factor is removed.
1212
AddToWorkList(Op.getNode());
1219
// Only add if it isn't already in the list.
1220
if (SeenOps.insert(Op.getNode()))
1231
// If we've change things around then replace token factor.
1234
// The entry token is the only possible outcome.
1235
Result = DAG.getEntryNode();
1237
// New and improved token factor.
1238
Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1239
MVT::Other, &Ops[0], Ops.size());
1242
// Don't add users to work list.
1243
return CombineTo(N, Result, false);
1249
/// MERGE_VALUES can always be eliminated.
1250
SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1251
WorkListRemover DeadNodes(*this);
1252
// Replacing results may cause a different MERGE_VALUES to suddenly
1253
// be CSE'd with N, and carry its uses with it. Iterate until no
1254
// uses remain, to ensure that the node can be safely deleted.
1256
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1257
DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1259
} while (!N->use_empty());
1260
removeFromWorkList(N);
1262
return SDValue(N, 0); // Return N so it doesn't get rechecked!
1266
SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1267
SelectionDAG &DAG) {
1268
EVT VT = N0.getValueType();
1269
SDValue N00 = N0.getOperand(0);
1270
SDValue N01 = N0.getOperand(1);
1271
ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1273
if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1274
isa<ConstantSDNode>(N00.getOperand(1))) {
1275
// fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1276
N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1277
DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1278
N00.getOperand(0), N01),
1279
DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1280
N00.getOperand(1), N01));
1281
return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1287
SDValue DAGCombiner::visitADD(SDNode *N) {
1288
SDValue N0 = N->getOperand(0);
1289
SDValue N1 = N->getOperand(1);
1290
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1291
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1292
EVT VT = N0.getValueType();
1295
if (VT.isVector()) {
1296
SDValue FoldedVOp = SimplifyVBinOp(N);
1297
if (FoldedVOp.getNode()) return FoldedVOp;
1300
// fold (add x, undef) -> undef
1301
if (N0.getOpcode() == ISD::UNDEF)
1303
if (N1.getOpcode() == ISD::UNDEF)
1305
// fold (add c1, c2) -> c1+c2
1307
return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1308
// canonicalize constant to RHS
1310
return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1311
// fold (add x, 0) -> x
1312
if (N1C && N1C->isNullValue())
1314
// fold (add Sym, c) -> Sym+c
1315
if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1316
if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1317
GA->getOpcode() == ISD::GlobalAddress)
1318
return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1320
(uint64_t)N1C->getSExtValue());
1321
// fold ((c1-A)+c2) -> (c1+c2)-A
1322
if (N1C && N0.getOpcode() == ISD::SUB)
1323
if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1324
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1325
DAG.getConstant(N1C->getAPIntValue()+
1326
N0C->getAPIntValue(), VT),
1329
SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1330
if (RADD.getNode() != 0)
1332
// fold ((0-A) + B) -> B-A
1333
if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1334
cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1335
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1336
// fold (A + (0-B)) -> A-B
1337
if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1338
cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1339
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1340
// fold (A+(B-A)) -> B
1341
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1342
return N1.getOperand(0);
1343
// fold ((B-A)+A) -> B
1344
if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1345
return N0.getOperand(0);
1346
// fold (A+(B-(A+C))) to (B-C)
1347
if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1348
N0 == N1.getOperand(1).getOperand(0))
1349
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1350
N1.getOperand(1).getOperand(1));
1351
// fold (A+(B-(C+A))) to (B-C)
1352
if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1353
N0 == N1.getOperand(1).getOperand(1))
1354
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1355
N1.getOperand(1).getOperand(0));
1356
// fold (A+((B-A)+or-C)) to (B+or-C)
1357
if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1358
N1.getOperand(0).getOpcode() == ISD::SUB &&
1359
N0 == N1.getOperand(0).getOperand(1))
1360
return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1361
N1.getOperand(0).getOperand(0), N1.getOperand(1));
1363
// fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1364
if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1365
SDValue N00 = N0.getOperand(0);
1366
SDValue N01 = N0.getOperand(1);
1367
SDValue N10 = N1.getOperand(0);
1368
SDValue N11 = N1.getOperand(1);
1370
if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1371
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1372
DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1373
DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1376
if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1377
return SDValue(N, 0);
1379
// fold (a+b) -> (a|b) iff a and b share no bits.
1380
if (VT.isInteger() && !VT.isVector()) {
1381
APInt LHSZero, LHSOne;
1382
APInt RHSZero, RHSOne;
1383
APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1384
DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1386
if (LHSZero.getBoolValue()) {
1387
DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1389
// If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1390
// If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1391
if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1392
(LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1393
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1397
// fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1398
if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1399
SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1400
if (Result.getNode()) return Result;
1402
if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1403
SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1404
if (Result.getNode()) return Result;
1407
// fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1408
if (N1.getOpcode() == ISD::SHL &&
1409
N1.getOperand(0).getOpcode() == ISD::SUB)
1410
if (ConstantSDNode *C =
1411
dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1412
if (C->getAPIntValue() == 0)
1413
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1414
DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1415
N1.getOperand(0).getOperand(1),
1417
if (N0.getOpcode() == ISD::SHL &&
1418
N0.getOperand(0).getOpcode() == ISD::SUB)
1419
if (ConstantSDNode *C =
1420
dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1421
if (C->getAPIntValue() == 0)
1422
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1423
DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1424
N0.getOperand(0).getOperand(1),
1430
SDValue DAGCombiner::visitADDC(SDNode *N) {
1431
SDValue N0 = N->getOperand(0);
1432
SDValue N1 = N->getOperand(1);
1433
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1434
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1435
EVT VT = N0.getValueType();
1437
// If the flag result is dead, turn this into an ADD.
1438
if (N->hasNUsesOfValue(0, 1))
1439
return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1440
DAG.getNode(ISD::CARRY_FALSE,
1441
N->getDebugLoc(), MVT::Flag));
1443
// canonicalize constant to RHS.
1445
return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1447
// fold (addc x, 0) -> x + no carry out
1448
if (N1C && N1C->isNullValue())
1449
return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1450
N->getDebugLoc(), MVT::Flag));
1452
// fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1453
APInt LHSZero, LHSOne;
1454
APInt RHSZero, RHSOne;
1455
APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1456
DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1458
if (LHSZero.getBoolValue()) {
1459
DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1461
// If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1462
// If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1463
if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1464
(LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1465
return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1466
DAG.getNode(ISD::CARRY_FALSE,
1467
N->getDebugLoc(), MVT::Flag));
1473
SDValue DAGCombiner::visitADDE(SDNode *N) {
1474
SDValue N0 = N->getOperand(0);
1475
SDValue N1 = N->getOperand(1);
1476
SDValue CarryIn = N->getOperand(2);
1477
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1478
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1480
// canonicalize constant to RHS
1482
return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1485
// fold (adde x, y, false) -> (addc x, y)
1486
if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1487
return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1492
SDValue DAGCombiner::visitSUB(SDNode *N) {
1493
SDValue N0 = N->getOperand(0);
1494
SDValue N1 = N->getOperand(1);
1495
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1496
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1497
EVT VT = N0.getValueType();
1500
if (VT.isVector()) {
1501
SDValue FoldedVOp = SimplifyVBinOp(N);
1502
if (FoldedVOp.getNode()) return FoldedVOp;
1505
// fold (sub x, x) -> 0
1507
return DAG.getConstant(0, N->getValueType(0));
1508
// fold (sub c1, c2) -> c1-c2
1510
return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1511
// fold (sub x, c) -> (add x, -c)
1513
return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1514
DAG.getConstant(-N1C->getAPIntValue(), VT));
1515
// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1516
if (N0C && N0C->isAllOnesValue())
1517
return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1518
// fold (A+B)-A -> B
1519
if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1520
return N0.getOperand(1);
1521
// fold (A+B)-B -> A
1522
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1523
return N0.getOperand(0);
1524
// fold ((A+(B+or-C))-B) -> A+or-C
1525
if (N0.getOpcode() == ISD::ADD &&
1526
(N0.getOperand(1).getOpcode() == ISD::SUB ||
1527
N0.getOperand(1).getOpcode() == ISD::ADD) &&
1528
N0.getOperand(1).getOperand(0) == N1)
1529
return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1530
N0.getOperand(0), N0.getOperand(1).getOperand(1));
1531
// fold ((A+(C+B))-B) -> A+C
1532
if (N0.getOpcode() == ISD::ADD &&
1533
N0.getOperand(1).getOpcode() == ISD::ADD &&
1534
N0.getOperand(1).getOperand(1) == N1)
1535
return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1536
N0.getOperand(0), N0.getOperand(1).getOperand(0));
1537
// fold ((A-(B-C))-C) -> A-B
1538
if (N0.getOpcode() == ISD::SUB &&
1539
N0.getOperand(1).getOpcode() == ISD::SUB &&
1540
N0.getOperand(1).getOperand(1) == N1)
1541
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1542
N0.getOperand(0), N0.getOperand(1).getOperand(0));
1544
// If either operand of a sub is undef, the result is undef
1545
if (N0.getOpcode() == ISD::UNDEF)
1547
if (N1.getOpcode() == ISD::UNDEF)
1550
// If the relocation model supports it, consider symbol offsets.
1551
if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1552
if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1553
// fold (sub Sym, c) -> Sym-c
1554
if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1555
return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1557
(uint64_t)N1C->getSExtValue());
1558
// fold (sub Sym+c1, Sym+c2) -> c1-c2
1559
if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1560
if (GA->getGlobal() == GB->getGlobal())
1561
return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1568
SDValue DAGCombiner::visitMUL(SDNode *N) {
1569
SDValue N0 = N->getOperand(0);
1570
SDValue N1 = N->getOperand(1);
1571
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1572
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1573
EVT VT = N0.getValueType();
1576
if (VT.isVector()) {
1577
SDValue FoldedVOp = SimplifyVBinOp(N);
1578
if (FoldedVOp.getNode()) return FoldedVOp;
1581
// fold (mul x, undef) -> 0
1582
if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1583
return DAG.getConstant(0, VT);
1584
// fold (mul c1, c2) -> c1*c2
1586
return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1587
// canonicalize constant to RHS
1589
return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1590
// fold (mul x, 0) -> 0
1591
if (N1C && N1C->isNullValue())
1593
// fold (mul x, -1) -> 0-x
1594
if (N1C && N1C->isAllOnesValue())
1595
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1596
DAG.getConstant(0, VT), N0);
1597
// fold (mul x, (1 << c)) -> x << c
1598
if (N1C && N1C->getAPIntValue().isPowerOf2())
1599
return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1600
DAG.getConstant(N1C->getAPIntValue().logBase2(),
1601
getShiftAmountTy()));
1602
// fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1603
if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1604
unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1605
// FIXME: If the input is something that is easily negated (e.g. a
1606
// single-use add), we should put the negate there.
1607
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1608
DAG.getConstant(0, VT),
1609
DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1610
DAG.getConstant(Log2Val, getShiftAmountTy())));
1612
// (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1613
if (N1C && N0.getOpcode() == ISD::SHL &&
1614
isa<ConstantSDNode>(N0.getOperand(1))) {
1615
SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1616
N1, N0.getOperand(1));
1617
AddToWorkList(C3.getNode());
1618
return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1619
N0.getOperand(0), C3);
1622
// Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1625
SDValue Sh(0,0), Y(0,0);
1626
// Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1627
if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1628
N0.getNode()->hasOneUse()) {
1630
} else if (N1.getOpcode() == ISD::SHL &&
1631
isa<ConstantSDNode>(N1.getOperand(1)) &&
1632
N1.getNode()->hasOneUse()) {
1637
SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1638
Sh.getOperand(0), Y);
1639
return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1640
Mul, Sh.getOperand(1));
1644
// fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1645
if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1646
isa<ConstantSDNode>(N0.getOperand(1)))
1647
return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1648
DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1649
N0.getOperand(0), N1),
1650
DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1651
N0.getOperand(1), N1));
1654
SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1655
if (RMUL.getNode() != 0)
1661
SDValue DAGCombiner::visitSDIV(SDNode *N) {
1662
SDValue N0 = N->getOperand(0);
1663
SDValue N1 = N->getOperand(1);
1664
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1665
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1666
EVT VT = N->getValueType(0);
1669
if (VT.isVector()) {
1670
SDValue FoldedVOp = SimplifyVBinOp(N);
1671
if (FoldedVOp.getNode()) return FoldedVOp;
1674
// fold (sdiv c1, c2) -> c1/c2
1675
if (N0C && N1C && !N1C->isNullValue())
1676
return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1677
// fold (sdiv X, 1) -> X
1678
if (N1C && N1C->getSExtValue() == 1LL)
1680
// fold (sdiv X, -1) -> 0-X
1681
if (N1C && N1C->isAllOnesValue())
1682
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1683
DAG.getConstant(0, VT), N0);
1684
// If we know the sign bits of both operands are zero, strength reduce to a
1685
// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1686
if (!VT.isVector()) {
1687
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1688
return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1691
// fold (sdiv X, pow2) -> simple ops after legalize
1692
if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1693
(isPowerOf2_64(N1C->getSExtValue()) ||
1694
isPowerOf2_64(-N1C->getSExtValue()))) {
1695
// If dividing by powers of two is cheap, then don't perform the following
1697
if (TLI.isPow2DivCheap())
1700
int64_t pow2 = N1C->getSExtValue();
1701
int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1702
unsigned lg2 = Log2_64(abs2);
1704
// Splat the sign bit into the register
1705
SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1706
DAG.getConstant(VT.getSizeInBits()-1,
1707
getShiftAmountTy()));
1708
AddToWorkList(SGN.getNode());
1710
// Add (N0 < 0) ? abs2 - 1 : 0;
1711
SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1712
DAG.getConstant(VT.getSizeInBits() - lg2,
1713
getShiftAmountTy()));
1714
SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1715
AddToWorkList(SRL.getNode());
1716
AddToWorkList(ADD.getNode()); // Divide by pow2
1717
SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1718
DAG.getConstant(lg2, getShiftAmountTy()));
1720
// If we're dividing by a positive value, we're done. Otherwise, we must
1721
// negate the result.
1725
AddToWorkList(SRA.getNode());
1726
return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1727
DAG.getConstant(0, VT), SRA);
1730
// if integer divide is expensive and we satisfy the requirements, emit an
1731
// alternate sequence.
1732
if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1733
!TLI.isIntDivCheap()) {
1734
SDValue Op = BuildSDIV(N);
1735
if (Op.getNode()) return Op;
1739
if (N0.getOpcode() == ISD::UNDEF)
1740
return DAG.getConstant(0, VT);
1741
// X / undef -> undef
1742
if (N1.getOpcode() == ISD::UNDEF)
1748
SDValue DAGCombiner::visitUDIV(SDNode *N) {
1749
SDValue N0 = N->getOperand(0);
1750
SDValue N1 = N->getOperand(1);
1751
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1752
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1753
EVT VT = N->getValueType(0);
1756
if (VT.isVector()) {
1757
SDValue FoldedVOp = SimplifyVBinOp(N);
1758
if (FoldedVOp.getNode()) return FoldedVOp;
1761
// fold (udiv c1, c2) -> c1/c2
1762
if (N0C && N1C && !N1C->isNullValue())
1763
return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1764
// fold (udiv x, (1 << c)) -> x >>u c
1765
if (N1C && N1C->getAPIntValue().isPowerOf2())
1766
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1767
DAG.getConstant(N1C->getAPIntValue().logBase2(),
1768
getShiftAmountTy()));
1769
// fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1770
if (N1.getOpcode() == ISD::SHL) {
1771
if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1772
if (SHC->getAPIntValue().isPowerOf2()) {
1773
EVT ADDVT = N1.getOperand(1).getValueType();
1774
SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1776
DAG.getConstant(SHC->getAPIntValue()
1779
AddToWorkList(Add.getNode());
1780
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1784
// fold (udiv x, c) -> alternate
1785
if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1786
SDValue Op = BuildUDIV(N);
1787
if (Op.getNode()) return Op;
1791
if (N0.getOpcode() == ISD::UNDEF)
1792
return DAG.getConstant(0, VT);
1793
// X / undef -> undef
1794
if (N1.getOpcode() == ISD::UNDEF)
1800
SDValue DAGCombiner::visitSREM(SDNode *N) {
1801
SDValue N0 = N->getOperand(0);
1802
SDValue N1 = N->getOperand(1);
1803
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1804
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1805
EVT VT = N->getValueType(0);
1807
// fold (srem c1, c2) -> c1%c2
1808
if (N0C && N1C && !N1C->isNullValue())
1809
return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1810
// If we know the sign bits of both operands are zero, strength reduce to a
1811
// urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1812
if (!VT.isVector()) {
1813
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1814
return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1817
// If X/C can be simplified by the division-by-constant logic, lower
1818
// X%C to the equivalent of X-X/C*C.
1819
if (N1C && !N1C->isNullValue()) {
1820
SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1821
AddToWorkList(Div.getNode());
1822
SDValue OptimizedDiv = combine(Div.getNode());
1823
if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1824
SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1826
SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1827
AddToWorkList(Mul.getNode());
1833
if (N0.getOpcode() == ISD::UNDEF)
1834
return DAG.getConstant(0, VT);
1835
// X % undef -> undef
1836
if (N1.getOpcode() == ISD::UNDEF)
1842
SDValue DAGCombiner::visitUREM(SDNode *N) {
1843
SDValue N0 = N->getOperand(0);
1844
SDValue N1 = N->getOperand(1);
1845
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1846
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1847
EVT VT = N->getValueType(0);
1849
// fold (urem c1, c2) -> c1%c2
1850
if (N0C && N1C && !N1C->isNullValue())
1851
return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1852
// fold (urem x, pow2) -> (and x, pow2-1)
1853
if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1854
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1855
DAG.getConstant(N1C->getAPIntValue()-1,VT));
1856
// fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1857
if (N1.getOpcode() == ISD::SHL) {
1858
if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1859
if (SHC->getAPIntValue().isPowerOf2()) {
1861
DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1862
DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1864
AddToWorkList(Add.getNode());
1865
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1870
// If X/C can be simplified by the division-by-constant logic, lower
1871
// X%C to the equivalent of X-X/C*C.
1872
if (N1C && !N1C->isNullValue()) {
1873
SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1874
AddToWorkList(Div.getNode());
1875
SDValue OptimizedDiv = combine(Div.getNode());
1876
if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1877
SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1879
SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1880
AddToWorkList(Mul.getNode());
1886
if (N0.getOpcode() == ISD::UNDEF)
1887
return DAG.getConstant(0, VT);
1888
// X % undef -> undef
1889
if (N1.getOpcode() == ISD::UNDEF)
1895
SDValue DAGCombiner::visitMULHS(SDNode *N) {
1896
SDValue N0 = N->getOperand(0);
1897
SDValue N1 = N->getOperand(1);
1898
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1899
EVT VT = N->getValueType(0);
1901
// fold (mulhs x, 0) -> 0
1902
if (N1C && N1C->isNullValue())
1904
// fold (mulhs x, 1) -> (sra x, size(x)-1)
1905
if (N1C && N1C->getAPIntValue() == 1)
1906
return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1907
DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1908
getShiftAmountTy()));
1909
// fold (mulhs x, undef) -> 0
1910
if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1911
return DAG.getConstant(0, VT);
1916
SDValue DAGCombiner::visitMULHU(SDNode *N) {
1917
SDValue N0 = N->getOperand(0);
1918
SDValue N1 = N->getOperand(1);
1919
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1920
EVT VT = N->getValueType(0);
1922
// fold (mulhu x, 0) -> 0
1923
if (N1C && N1C->isNullValue())
1925
// fold (mulhu x, 1) -> 0
1926
if (N1C && N1C->getAPIntValue() == 1)
1927
return DAG.getConstant(0, N0.getValueType());
1928
// fold (mulhu x, undef) -> 0
1929
if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1930
return DAG.getConstant(0, VT);
1935
/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1936
/// compute two values. LoOp and HiOp give the opcodes for the two computations
1937
/// that are being performed. Return true if a simplification was made.
1939
SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1941
// If the high half is not needed, just compute the low half.
1942
bool HiExists = N->hasAnyUseOfValue(1);
1944
(!LegalOperations ||
1945
TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1946
SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1947
N->op_begin(), N->getNumOperands());
1948
return CombineTo(N, Res, Res);
1951
// If the low half is not needed, just compute the high half.
1952
bool LoExists = N->hasAnyUseOfValue(0);
1954
(!LegalOperations ||
1955
TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1956
SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1957
N->op_begin(), N->getNumOperands());
1958
return CombineTo(N, Res, Res);
1961
// If both halves are used, return as it is.
1962
if (LoExists && HiExists)
1965
// If the two computed results can be simplified separately, separate them.
1967
SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1968
N->op_begin(), N->getNumOperands());
1969
AddToWorkList(Lo.getNode());
1970
SDValue LoOpt = combine(Lo.getNode());
1971
if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1972
(!LegalOperations ||
1973
TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1974
return CombineTo(N, LoOpt, LoOpt);
1978
SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1979
N->op_begin(), N->getNumOperands());
1980
AddToWorkList(Hi.getNode());
1981
SDValue HiOpt = combine(Hi.getNode());
1982
if (HiOpt.getNode() && HiOpt != Hi &&
1983
(!LegalOperations ||
1984
TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1985
return CombineTo(N, HiOpt, HiOpt);
1991
SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1992
SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1993
if (Res.getNode()) return Res;
1998
SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1999
SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2000
if (Res.getNode()) return Res;
2005
SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2006
SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2007
if (Res.getNode()) return Res;
2012
SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2013
SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2014
if (Res.getNode()) return Res;
2019
/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2020
/// two operands of the same opcode, try to simplify it.
2021
SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2022
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2023
EVT VT = N0.getValueType();
2024
assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2026
// Bail early if none of these transforms apply.
2027
if (N0.getNode()->getNumOperands() == 0) return SDValue();
2029
// For each of OP in AND/OR/XOR:
2030
// fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2031
// fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2032
// fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2033
// fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2035
// do not sink logical op inside of a vector extend, since it may combine
2037
EVT Op0VT = N0.getOperand(0).getValueType();
2038
if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2039
N0.getOpcode() == ISD::SIGN_EXTEND ||
2040
// Avoid infinite looping with PromoteIntBinOp.
2041
(N0.getOpcode() == ISD::ANY_EXTEND &&
2042
(!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2043
(N0.getOpcode() == ISD::TRUNCATE &&
2044
(!TLI.isZExtFree(VT, Op0VT) ||
2045
!TLI.isTruncateFree(Op0VT, VT)) &&
2046
TLI.isTypeLegal(Op0VT))) &&
2048
Op0VT == N1.getOperand(0).getValueType() &&
2049
(!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2050
SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2051
N0.getOperand(0).getValueType(),
2052
N0.getOperand(0), N1.getOperand(0));
2053
AddToWorkList(ORNode.getNode());
2054
return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2057
// For each of OP in SHL/SRL/SRA/AND...
2058
// fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2059
// fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2060
// fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2061
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2062
N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2063
N0.getOperand(1) == N1.getOperand(1)) {
2064
SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2065
N0.getOperand(0).getValueType(),
2066
N0.getOperand(0), N1.getOperand(0));
2067
AddToWorkList(ORNode.getNode());
2068
return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2069
ORNode, N0.getOperand(1));
2075
SDValue DAGCombiner::visitAND(SDNode *N) {
2076
SDValue N0 = N->getOperand(0);
2077
SDValue N1 = N->getOperand(1);
2078
SDValue LL, LR, RL, RR, CC0, CC1;
2079
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2080
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2081
EVT VT = N1.getValueType();
2082
unsigned BitWidth = VT.getScalarType().getSizeInBits();
2085
if (VT.isVector()) {
2086
SDValue FoldedVOp = SimplifyVBinOp(N);
2087
if (FoldedVOp.getNode()) return FoldedVOp;
2090
// fold (and x, undef) -> 0
2091
if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2092
return DAG.getConstant(0, VT);
2093
// fold (and c1, c2) -> c1&c2
2095
return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2096
// canonicalize constant to RHS
2098
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2099
// fold (and x, -1) -> x
2100
if (N1C && N1C->isAllOnesValue())
2102
// if (and x, c) is known to be zero, return 0
2103
if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2104
APInt::getAllOnesValue(BitWidth)))
2105
return DAG.getConstant(0, VT);
2107
SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2108
if (RAND.getNode() != 0)
2110
// fold (and (or x, C), D) -> D if (C & D) == D
2111
if (N1C && N0.getOpcode() == ISD::OR)
2112
if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2113
if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2115
// fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2116
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2117
SDValue N0Op0 = N0.getOperand(0);
2118
APInt Mask = ~N1C->getAPIntValue();
2119
Mask.trunc(N0Op0.getValueSizeInBits());
2120
if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2121
SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2122
N0.getValueType(), N0Op0);
2124
// Replace uses of the AND with uses of the Zero extend node.
2127
// We actually want to replace all uses of the any_extend with the
2128
// zero_extend, to avoid duplicating things. This will later cause this
2129
// AND to be folded.
2130
CombineTo(N0.getNode(), Zext);
2131
return SDValue(N, 0); // Return N so it doesn't get rechecked!
2134
// fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2135
if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2136
ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2137
ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2139
if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2140
LL.getValueType().isInteger()) {
2141
// fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2142
if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2143
SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2144
LR.getValueType(), LL, RL);
2145
AddToWorkList(ORNode.getNode());
2146
return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2148
// fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2149
if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2150
SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2151
LR.getValueType(), LL, RL);
2152
AddToWorkList(ANDNode.getNode());
2153
return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2155
// fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2156
if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2157
SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2158
LR.getValueType(), LL, RL);
2159
AddToWorkList(ORNode.getNode());
2160
return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2163
// canonicalize equivalent to ll == rl
2164
if (LL == RR && LR == RL) {
2165
Op1 = ISD::getSetCCSwappedOperands(Op1);
2168
if (LL == RL && LR == RR) {
2169
bool isInteger = LL.getValueType().isInteger();
2170
ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2171
if (Result != ISD::SETCC_INVALID &&
2172
(!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2173
return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2178
// Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2179
if (N0.getOpcode() == N1.getOpcode()) {
2180
SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2181
if (Tmp.getNode()) return Tmp;
2184
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2185
// fold (and (sra)) -> (and (srl)) when possible.
2186
if (!VT.isVector() &&
2187
SimplifyDemandedBits(SDValue(N, 0)))
2188
return SDValue(N, 0);
2190
// fold (zext_inreg (extload x)) -> (zextload x)
2191
if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2192
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2193
EVT MemVT = LN0->getMemoryVT();
2194
// If we zero all the possible extended bits, then we can turn this into
2195
// a zextload if we are running before legalize or the operation is legal.
2196
unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2197
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2198
BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2199
((!LegalOperations && !LN0->isVolatile()) ||
2200
TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2201
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(),
2202
LN0->getChain(), LN0->getBasePtr(),
2204
LN0->getSrcValueOffset(), MemVT,
2205
LN0->isVolatile(), LN0->isNonTemporal(),
2206
LN0->getAlignment());
2208
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2209
return SDValue(N, 0); // Return N so it doesn't get rechecked!
2212
// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2213
if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2215
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2216
EVT MemVT = LN0->getMemoryVT();
2217
// If we zero all the possible extended bits, then we can turn this into
2218
// a zextload if we are running before legalize or the operation is legal.
2219
unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2220
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2221
BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2222
((!LegalOperations && !LN0->isVolatile()) ||
2223
TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2224
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(),
2226
LN0->getBasePtr(), LN0->getSrcValue(),
2227
LN0->getSrcValueOffset(), MemVT,
2228
LN0->isVolatile(), LN0->isNonTemporal(),
2229
LN0->getAlignment());
2231
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2232
return SDValue(N, 0); // Return N so it doesn't get rechecked!
2236
// fold (and (load x), 255) -> (zextload x, i8)
2237
// fold (and (extload x, i16), 255) -> (zextload x, i8)
2238
// fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2239
if (N1C && (N0.getOpcode() == ISD::LOAD ||
2240
(N0.getOpcode() == ISD::ANY_EXTEND &&
2241
N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2242
bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2243
LoadSDNode *LN0 = HasAnyExt
2244
? cast<LoadSDNode>(N0.getOperand(0))
2245
: cast<LoadSDNode>(N0);
2246
if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2247
LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2248
uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2249
if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2250
EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2251
EVT LoadedVT = LN0->getMemoryVT();
2253
if (ExtVT == LoadedVT &&
2254
(!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2255
EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2258
DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(),
2259
LN0->getChain(), LN0->getBasePtr(),
2260
LN0->getSrcValue(), LN0->getSrcValueOffset(),
2261
ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2262
LN0->getAlignment());
2264
CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2265
return SDValue(N, 0); // Return N so it doesn't get rechecked!
2268
// Do not change the width of a volatile load.
2269
// Do not generate loads of non-round integer types since these can
2270
// be expensive (and would be wrong if the type is not byte sized).
2271
if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2272
(!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2273
EVT PtrType = LN0->getOperand(1).getValueType();
2275
unsigned Alignment = LN0->getAlignment();
2276
SDValue NewPtr = LN0->getBasePtr();
2278
// For big endian targets, we need to add an offset to the pointer
2279
// to load the correct bytes. For little endian systems, we merely
2280
// need to read fewer bytes from the same pointer.
2281
if (TLI.isBigEndian()) {
2282
unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2283
unsigned EVTStoreBytes = ExtVT.getStoreSize();
2284
unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2285
NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2286
NewPtr, DAG.getConstant(PtrOff, PtrType));
2287
Alignment = MinAlign(Alignment, PtrOff);
2290
AddToWorkList(NewPtr.getNode());
2292
EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2294
DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(),
2295
LN0->getChain(), NewPtr,
2296
LN0->getSrcValue(), LN0->getSrcValueOffset(),
2297
ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2300
CombineTo(LN0, Load, Load.getValue(1));
2301
return SDValue(N, 0); // Return N so it doesn't get rechecked!
2310
SDValue DAGCombiner::visitOR(SDNode *N) {
2311
SDValue N0 = N->getOperand(0);
2312
SDValue N1 = N->getOperand(1);
2313
SDValue LL, LR, RL, RR, CC0, CC1;
2314
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2315
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2316
EVT VT = N1.getValueType();
2319
if (VT.isVector()) {
2320
SDValue FoldedVOp = SimplifyVBinOp(N);
2321
if (FoldedVOp.getNode()) return FoldedVOp;
2324
// fold (or x, undef) -> -1
2325
if (!LegalOperations &&
2326
(N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2327
EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2328
return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2330
// fold (or c1, c2) -> c1|c2
2332
return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2333
// canonicalize constant to RHS
2335
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2336
// fold (or x, 0) -> x
2337
if (N1C && N1C->isNullValue())
2339
// fold (or x, -1) -> -1
2340
if (N1C && N1C->isAllOnesValue())
2342
// fold (or x, c) -> c iff (x & ~c) == 0
2343
if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2346
SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2347
if (ROR.getNode() != 0)
2349
// Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2350
// iff (c1 & c2) == 0.
2351
if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2352
isa<ConstantSDNode>(N0.getOperand(1))) {
2353
ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2354
if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2355
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2356
DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2357
N0.getOperand(0), N1),
2358
DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2360
// fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2361
if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2362
ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2363
ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2365
if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2366
LL.getValueType().isInteger()) {
2367
// fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2368
// fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2369
if (cast<ConstantSDNode>(LR)->isNullValue() &&
2370
(Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2371
SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2372
LR.getValueType(), LL, RL);
2373
AddToWorkList(ORNode.getNode());
2374
return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2376
// fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2377
// fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2378
if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2379
(Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2380
SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2381
LR.getValueType(), LL, RL);
2382
AddToWorkList(ANDNode.getNode());
2383
return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2386
// canonicalize equivalent to ll == rl
2387
if (LL == RR && LR == RL) {
2388
Op1 = ISD::getSetCCSwappedOperands(Op1);
2391
if (LL == RL && LR == RR) {
2392
bool isInteger = LL.getValueType().isInteger();
2393
ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2394
if (Result != ISD::SETCC_INVALID &&
2395
(!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2396
return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2401
// Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2402
if (N0.getOpcode() == N1.getOpcode()) {
2403
SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2404
if (Tmp.getNode()) return Tmp;
2407
// (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2408
if (N0.getOpcode() == ISD::AND &&
2409
N1.getOpcode() == ISD::AND &&
2410
N0.getOperand(1).getOpcode() == ISD::Constant &&
2411
N1.getOperand(1).getOpcode() == ISD::Constant &&
2412
// Don't increase # computations.
2413
(N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2414
// We can only do this xform if we know that bits from X that are set in C2
2415
// but not in C1 are already zero. Likewise for Y.
2416
const APInt &LHSMask =
2417
cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2418
const APInt &RHSMask =
2419
cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2421
if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2422
DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2423
SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2424
N0.getOperand(0), N1.getOperand(0));
2425
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2426
DAG.getConstant(LHSMask | RHSMask, VT));
2430
// See if this is some rotate idiom.
2431
if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2432
return SDValue(Rot, 0);
2434
// Simplify the operands using demanded-bits information.
2435
if (!VT.isVector() &&
2436
SimplifyDemandedBits(SDValue(N, 0)))
2437
return SDValue(N, 0);
2442
/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2443
static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2444
if (Op.getOpcode() == ISD::AND) {
2445
if (isa<ConstantSDNode>(Op.getOperand(1))) {
2446
Mask = Op.getOperand(1);
2447
Op = Op.getOperand(0);
2453
if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2461
// MatchRotate - Handle an 'or' of two operands. If this is one of the many
2462
// idioms for rotate, and if the target supports rotation instructions, generate
2464
SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2465
// Must be a legal type. Expanded 'n promoted things won't work with rotates.
2466
EVT VT = LHS.getValueType();
2467
if (!TLI.isTypeLegal(VT)) return 0;
2469
// The target must have at least one rotate flavor.
2470
bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2471
bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2472
if (!HasROTL && !HasROTR) return 0;
2474
// Match "(X shl/srl V1) & V2" where V2 may not be present.
2475
SDValue LHSShift; // The shift.
2476
SDValue LHSMask; // AND value if any.
2477
if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2478
return 0; // Not part of a rotate.
2480
SDValue RHSShift; // The shift.
2481
SDValue RHSMask; // AND value if any.
2482
if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2483
return 0; // Not part of a rotate.
2485
if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2486
return 0; // Not shifting the same value.
2488
if (LHSShift.getOpcode() == RHSShift.getOpcode())
2489
return 0; // Shifts must disagree.
2491
// Canonicalize shl to left side in a shl/srl pair.
2492
if (RHSShift.getOpcode() == ISD::SHL) {
2493
std::swap(LHS, RHS);
2494
std::swap(LHSShift, RHSShift);
2495
std::swap(LHSMask , RHSMask );
2498
unsigned OpSizeInBits = VT.getSizeInBits();
2499
SDValue LHSShiftArg = LHSShift.getOperand(0);
2500
SDValue LHSShiftAmt = LHSShift.getOperand(1);
2501
SDValue RHSShiftAmt = RHSShift.getOperand(1);
2503
// fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2504
// fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2505
if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2506
RHSShiftAmt.getOpcode() == ISD::Constant) {
2507
uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2508
uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2509
if ((LShVal + RShVal) != OpSizeInBits)
2514
Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2516
Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2518
// If there is an AND of either shifted operand, apply it to the result.
2519
if (LHSMask.getNode() || RHSMask.getNode()) {
2520
APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2522
if (LHSMask.getNode()) {
2523
APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2524
Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2526
if (RHSMask.getNode()) {
2527
APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2528
Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2531
Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2534
return Rot.getNode();
2537
// If there is a mask here, and we have a variable shift, we can't be sure
2538
// that we're masking out the right stuff.
2539
if (LHSMask.getNode() || RHSMask.getNode())
2542
// fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2543
// fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2544
if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2545
LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2546
if (ConstantSDNode *SUBC =
2547
dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2548
if (SUBC->getAPIntValue() == OpSizeInBits) {
2550
return DAG.getNode(ISD::ROTL, DL, VT,
2551
LHSShiftArg, LHSShiftAmt).getNode();
2553
return DAG.getNode(ISD::ROTR, DL, VT,
2554
LHSShiftArg, RHSShiftAmt).getNode();
2559
// fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2560
// fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2561
if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2562
RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2563
if (ConstantSDNode *SUBC =
2564
dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2565
if (SUBC->getAPIntValue() == OpSizeInBits) {
2567
return DAG.getNode(ISD::ROTR, DL, VT,
2568
LHSShiftArg, RHSShiftAmt).getNode();
2570
return DAG.getNode(ISD::ROTL, DL, VT,
2571
LHSShiftArg, LHSShiftAmt).getNode();
2576
// Look for sign/zext/any-extended or truncate cases:
2577
if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2578
|| LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2579
|| LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2580
|| LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2581
(RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2582
|| RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2583
|| RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2584
|| RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2585
SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2586
SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2587
if (RExtOp0.getOpcode() == ISD::SUB &&
2588
RExtOp0.getOperand(1) == LExtOp0) {
2589
// fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2591
// fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2592
// (rotr x, (sub 32, y))
2593
if (ConstantSDNode *SUBC =
2594
dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2595
if (SUBC->getAPIntValue() == OpSizeInBits) {
2596
return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2598
HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2601
} else if (LExtOp0.getOpcode() == ISD::SUB &&
2602
RExtOp0 == LExtOp0.getOperand(1)) {
2603
// fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2605
// fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2606
// (rotl x, (sub 32, y))
2607
if (ConstantSDNode *SUBC =
2608
dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2609
if (SUBC->getAPIntValue() == OpSizeInBits) {
2610
return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2612
HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2621
SDValue DAGCombiner::visitXOR(SDNode *N) {
2622
SDValue N0 = N->getOperand(0);
2623
SDValue N1 = N->getOperand(1);
2624
SDValue LHS, RHS, CC;
2625
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2626
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2627
EVT VT = N0.getValueType();
2630
if (VT.isVector()) {
2631
SDValue FoldedVOp = SimplifyVBinOp(N);
2632
if (FoldedVOp.getNode()) return FoldedVOp;
2635
// fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2636
if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2637
return DAG.getConstant(0, VT);
2638
// fold (xor x, undef) -> undef
2639
if (N0.getOpcode() == ISD::UNDEF)
2641
if (N1.getOpcode() == ISD::UNDEF)
2643
// fold (xor c1, c2) -> c1^c2
2645
return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2646
// canonicalize constant to RHS
2648
return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2649
// fold (xor x, 0) -> x
2650
if (N1C && N1C->isNullValue())
2653
SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2654
if (RXOR.getNode() != 0)
2657
// fold !(x cc y) -> (x !cc y)
2658
if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2659
bool isInt = LHS.getValueType().isInteger();
2660
ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2663
if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2664
switch (N0.getOpcode()) {
2666
llvm_unreachable("Unhandled SetCC Equivalent!");
2668
return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2669
case ISD::SELECT_CC:
2670
return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2671
N0.getOperand(3), NotCC);
2676
// fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2677
if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2678
N0.getNode()->hasOneUse() &&
2679
isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2680
SDValue V = N0.getOperand(0);
2681
V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2682
DAG.getConstant(1, V.getValueType()));
2683
AddToWorkList(V.getNode());
2684
return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2687
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2688
if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2689
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2690
SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2691
if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2692
unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2693
LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2694
RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2695
AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2696
return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2699
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2700
if (N1C && N1C->isAllOnesValue() &&
2701
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2702
SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2703
if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2704
unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2705
LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2706
RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2707
AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2708
return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2711
// fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2712
if (N1C && N0.getOpcode() == ISD::XOR) {
2713
ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2714
ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2716
return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2717
DAG.getConstant(N1C->getAPIntValue() ^
2718
N00C->getAPIntValue(), VT));
2720
return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2721
DAG.getConstant(N1C->getAPIntValue() ^
2722
N01C->getAPIntValue(), VT));
2724
// fold (xor x, x) -> 0
2726
if (!VT.isVector()) {
2727
return DAG.getConstant(0, VT);
2728
} else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2729
// Produce a vector of zeros.
2730
SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2731
std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2732
return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2733
&Ops[0], Ops.size());
2737
// Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2738
if (N0.getOpcode() == N1.getOpcode()) {
2739
SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2740
if (Tmp.getNode()) return Tmp;
2743
// Simplify the expression using non-local knowledge.
2744
if (!VT.isVector() &&
2745
SimplifyDemandedBits(SDValue(N, 0)))
2746
return SDValue(N, 0);
2751
/// visitShiftByConstant - Handle transforms common to the three shifts, when
2752
/// the shift amount is a constant.
2753
SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2754
SDNode *LHS = N->getOperand(0).getNode();
2755
if (!LHS->hasOneUse()) return SDValue();
2757
// We want to pull some binops through shifts, so that we have (and (shift))
2758
// instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2759
// thing happens with address calculations, so it's important to canonicalize
2761
bool HighBitSet = false; // Can we transform this if the high bit is set?
2763
switch (LHS->getOpcode()) {
2764
default: return SDValue();
2767
HighBitSet = false; // We can only transform sra if the high bit is clear.
2770
HighBitSet = true; // We can only transform sra if the high bit is set.
2773
if (N->getOpcode() != ISD::SHL)
2774
return SDValue(); // only shl(add) not sr[al](add).
2775
HighBitSet = false; // We can only transform sra if the high bit is clear.
2779
// We require the RHS of the binop to be a constant as well.
2780
ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2781
if (!BinOpCst) return SDValue();
2783
// FIXME: disable this unless the input to the binop is a shift by a constant.
2784
// If it is not a shift, it pessimizes some common cases like:
2786
// void foo(int *X, int i) { X[i & 1235] = 1; }
2787
// int bar(int *X, int i) { return X[i & 255]; }
2788
SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2789
if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2790
BinOpLHSVal->getOpcode() != ISD::SRA &&
2791
BinOpLHSVal->getOpcode() != ISD::SRL) ||
2792
!isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2795
EVT VT = N->getValueType(0);
2797
// If this is a signed shift right, and the high bit is modified by the
2798
// logical operation, do not perform the transformation. The highBitSet
2799
// boolean indicates the value of the high bit of the constant which would
2800
// cause it to be modified for this operation.
2801
if (N->getOpcode() == ISD::SRA) {
2802
bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2803
if (BinOpRHSSignSet != HighBitSet)
2807
// Fold the constants, shifting the binop RHS by the shift amount.
2808
SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2810
LHS->getOperand(1), N->getOperand(1));
2812
// Create the new shift.
2813
SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2814
VT, LHS->getOperand(0), N->getOperand(1));
2816
// Create the new binop.
2817
return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2820
SDValue DAGCombiner::visitSHL(SDNode *N) {
2821
SDValue N0 = N->getOperand(0);
2822
SDValue N1 = N->getOperand(1);
2823
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2824
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2825
EVT VT = N0.getValueType();
2826
unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2828
// fold (shl c1, c2) -> c1<<c2
2830
return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2831
// fold (shl 0, x) -> 0
2832
if (N0C && N0C->isNullValue())
2834
// fold (shl x, c >= size(x)) -> undef
2835
if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2836
return DAG.getUNDEF(VT);
2837
// fold (shl x, 0) -> x
2838
if (N1C && N1C->isNullValue())
2840
// if (shl x, c) is known to be zero, return 0
2841
if (DAG.MaskedValueIsZero(SDValue(N, 0),
2842
APInt::getAllOnesValue(OpSizeInBits)))
2843
return DAG.getConstant(0, VT);
2844
// fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2845
if (N1.getOpcode() == ISD::TRUNCATE &&
2846
N1.getOperand(0).getOpcode() == ISD::AND &&
2847
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2848
SDValue N101 = N1.getOperand(0).getOperand(1);
2849
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2850
EVT TruncVT = N1.getValueType();
2851
SDValue N100 = N1.getOperand(0).getOperand(0);
2852
APInt TruncC = N101C->getAPIntValue();
2853
TruncC.trunc(TruncVT.getSizeInBits());
2854
return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2855
DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2856
DAG.getNode(ISD::TRUNCATE,
2859
DAG.getConstant(TruncC, TruncVT)));
2863
if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2864
return SDValue(N, 0);
2866
// fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2867
if (N1C && N0.getOpcode() == ISD::SHL &&
2868
N0.getOperand(1).getOpcode() == ISD::Constant) {
2869
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2870
uint64_t c2 = N1C->getZExtValue();
2871
if (c1 + c2 > OpSizeInBits)
2872
return DAG.getConstant(0, VT);
2873
return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2874
DAG.getConstant(c1 + c2, N1.getValueType()));
2876
// fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2877
// (srl (and x, (shl -1, c1)), (sub c1, c2))
2878
if (N1C && N0.getOpcode() == ISD::SRL &&
2879
N0.getOperand(1).getOpcode() == ISD::Constant) {
2880
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2881
if (c1 < VT.getSizeInBits()) {
2882
uint64_t c2 = N1C->getZExtValue();
2883
SDValue HiBitsMask =
2884
DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2885
VT.getSizeInBits() - c1),
2887
SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
2891
return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2892
DAG.getConstant(c2-c1, N1.getValueType()));
2894
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2895
DAG.getConstant(c1-c2, N1.getValueType()));
2898
// fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2899
if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
2900
SDValue HiBitsMask =
2901
DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2902
VT.getSizeInBits() -
2903
N1C->getZExtValue()),
2905
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2910
SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
2911
if (NewSHL.getNode())
2918
SDValue DAGCombiner::visitSRA(SDNode *N) {
2919
SDValue N0 = N->getOperand(0);
2920
SDValue N1 = N->getOperand(1);
2921
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2922
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2923
EVT VT = N0.getValueType();
2924
unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2926
// fold (sra c1, c2) -> (sra c1, c2)
2928
return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2929
// fold (sra 0, x) -> 0
2930
if (N0C && N0C->isNullValue())
2932
// fold (sra -1, x) -> -1
2933
if (N0C && N0C->isAllOnesValue())
2935
// fold (sra x, (setge c, size(x))) -> undef
2936
if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2937
return DAG.getUNDEF(VT);
2938
// fold (sra x, 0) -> x
2939
if (N1C && N1C->isNullValue())
2941
// fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2943
if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2944
unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
2945
EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
2947
ExtVT = EVT::getVectorVT(*DAG.getContext(),
2948
ExtVT, VT.getVectorNumElements());
2949
if ((!LegalOperations ||
2950
TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
2951
return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2952
N0.getOperand(0), DAG.getValueType(ExtVT));
2955
// fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2956
if (N1C && N0.getOpcode() == ISD::SRA) {
2957
if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2958
unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2959
if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
2960
return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2961
DAG.getConstant(Sum, N1C->getValueType(0)));
2965
// fold (sra (shl X, m), (sub result_size, n))
2966
// -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2967
// result_size - n != m.
2968
// If truncate is free for the target sext(shl) is likely to result in better
2970
if (N0.getOpcode() == ISD::SHL) {
2971
// Get the two constanst of the shifts, CN0 = m, CN = n.
2972
const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2974
// Determine what the truncate's result bitsize and type would be.
2976
EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue());
2977
// Determine the residual right-shift amount.
2978
signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2980
// If the shift is not a no-op (in which case this should be just a sign
2981
// extend already), the truncated to type is legal, sign_extend is legal
2982
// on that type, and the truncate to that type is both legal and free,
2983
// perform the transform.
2984
if ((ShiftAmt > 0) &&
2985
TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2986
TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2987
TLI.isTruncateFree(VT, TruncVT)) {
2989
SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2990
SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2991
N0.getOperand(0), Amt);
2992
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2994
return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2995
N->getValueType(0), Trunc);
3000
// fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3001
if (N1.getOpcode() == ISD::TRUNCATE &&
3002
N1.getOperand(0).getOpcode() == ISD::AND &&
3003
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3004
SDValue N101 = N1.getOperand(0).getOperand(1);
3005
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3006
EVT TruncVT = N1.getValueType();
3007
SDValue N100 = N1.getOperand(0).getOperand(0);
3008
APInt TruncC = N101C->getAPIntValue();
3009
TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3010
return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3011
DAG.getNode(ISD::AND, N->getDebugLoc(),
3013
DAG.getNode(ISD::TRUNCATE,
3016
DAG.getConstant(TruncC, TruncVT)));
3020
// Simplify, based on bits shifted out of the LHS.
3021
if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3022
return SDValue(N, 0);
3025
// If the sign bit is known to be zero, switch this to a SRL.
3026
if (DAG.SignBitIsZero(N0))
3027
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3030
SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3031
if (NewSRA.getNode())
3038
SDValue DAGCombiner::visitSRL(SDNode *N) {
3039
SDValue N0 = N->getOperand(0);
3040
SDValue N1 = N->getOperand(1);
3041
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3042
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3043
EVT VT = N0.getValueType();
3044
unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3046
// fold (srl c1, c2) -> c1 >>u c2
3048
return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3049
// fold (srl 0, x) -> 0
3050
if (N0C && N0C->isNullValue())
3052
// fold (srl x, c >= size(x)) -> undef
3053
if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3054
return DAG.getUNDEF(VT);
3055
// fold (srl x, 0) -> x
3056
if (N1C && N1C->isNullValue())
3058
// if (srl x, c) is known to be zero, return 0
3059
if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3060
APInt::getAllOnesValue(OpSizeInBits)))
3061
return DAG.getConstant(0, VT);
3063
// fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3064
if (N1C && N0.getOpcode() == ISD::SRL &&
3065
N0.getOperand(1).getOpcode() == ISD::Constant) {
3066
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3067
uint64_t c2 = N1C->getZExtValue();
3068
if (c1 + c2 > OpSizeInBits)
3069
return DAG.getConstant(0, VT);
3070
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3071
DAG.getConstant(c1 + c2, N1.getValueType()));
3074
// fold (srl (shl x, c), c) -> (and x, cst2)
3075
if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3076
N0.getValueSizeInBits() <= 64) {
3077
uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3078
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3079
DAG.getConstant(~0ULL >> ShAmt, VT));
3083
// fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3084
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3085
// Shifting in all undef bits?
3086
EVT SmallVT = N0.getOperand(0).getValueType();
3087
if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3088
return DAG.getUNDEF(VT);
3090
if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3091
SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3092
N0.getOperand(0), N1);
3093
AddToWorkList(SmallShift.getNode());
3094
return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3098
// fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3099
// bit, which is unmodified by sra.
3100
if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3101
if (N0.getOpcode() == ISD::SRA)
3102
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3105
// fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3106
if (N1C && N0.getOpcode() == ISD::CTLZ &&
3107
N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3108
APInt KnownZero, KnownOne;
3109
APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3110
DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3112
// If any of the input bits are KnownOne, then the input couldn't be all
3113
// zeros, thus the result of the srl will always be zero.
3114
if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3116
// If all of the bits input the to ctlz node are known to be zero, then
3117
// the result of the ctlz is "32" and the result of the shift is one.
3118
APInt UnknownBits = ~KnownZero & Mask;
3119
if (UnknownBits == 0) return DAG.getConstant(1, VT);
3121
// Otherwise, check to see if there is exactly one bit input to the ctlz.
3122
if ((UnknownBits & (UnknownBits - 1)) == 0) {
3123
// Okay, we know that only that the single bit specified by UnknownBits
3124
// could be set on input to the CTLZ node. If this bit is set, the SRL
3125
// will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3126
// to an SRL/XOR pair, which is likely to simplify more.
3127
unsigned ShAmt = UnknownBits.countTrailingZeros();
3128
SDValue Op = N0.getOperand(0);
3131
Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3132
DAG.getConstant(ShAmt, getShiftAmountTy()));
3133
AddToWorkList(Op.getNode());
3136
return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3137
Op, DAG.getConstant(1, VT));
3141
// fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3142
if (N1.getOpcode() == ISD::TRUNCATE &&
3143
N1.getOperand(0).getOpcode() == ISD::AND &&
3144
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3145
SDValue N101 = N1.getOperand(0).getOperand(1);
3146
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3147
EVT TruncVT = N1.getValueType();
3148
SDValue N100 = N1.getOperand(0).getOperand(0);
3149
APInt TruncC = N101C->getAPIntValue();
3150
TruncC.trunc(TruncVT.getSizeInBits());
3151
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3152
DAG.getNode(ISD::AND, N->getDebugLoc(),
3154
DAG.getNode(ISD::TRUNCATE,
3157
DAG.getConstant(TruncC, TruncVT)));
3161
// fold operands of srl based on knowledge that the low bits are not
3163
if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3164
return SDValue(N, 0);
3167
SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3168
if (NewSRL.getNode())
3172
// Attempt to convert a srl of a load into a narrower zero-extending load.
3173
SDValue NarrowLoad = ReduceLoadWidth(N);
3174
if (NarrowLoad.getNode())
3177
// Here is a common situation. We want to optimize:
3180
// %b = and i32 %a, 2
3181
// %c = srl i32 %b, 1
3182
// brcond i32 %c ...
3188
// %c = setcc eq %b, 0
3191
// However when after the source operand of SRL is optimized into AND, the SRL
3192
// itself may not be optimized further. Look for it and add the BRCOND into
3194
if (N->hasOneUse()) {
3195
SDNode *Use = *N->use_begin();
3196
if (Use->getOpcode() == ISD::BRCOND)
3198
else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3199
// Also look pass the truncate.
3200
Use = *Use->use_begin();
3201
if (Use->getOpcode() == ISD::BRCOND)
3209
SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3210
SDValue N0 = N->getOperand(0);
3211
EVT VT = N->getValueType(0);
3213
// fold (ctlz c1) -> c2
3214
if (isa<ConstantSDNode>(N0))
3215
return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3219
SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3220
SDValue N0 = N->getOperand(0);
3221
EVT VT = N->getValueType(0);
3223
// fold (cttz c1) -> c2
3224
if (isa<ConstantSDNode>(N0))
3225
return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3229
SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3230
SDValue N0 = N->getOperand(0);
3231
EVT VT = N->getValueType(0);
3233
// fold (ctpop c1) -> c2
3234
if (isa<ConstantSDNode>(N0))
3235
return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3239
SDValue DAGCombiner::visitSELECT(SDNode *N) {
3240
SDValue N0 = N->getOperand(0);
3241
SDValue N1 = N->getOperand(1);
3242
SDValue N2 = N->getOperand(2);
3243
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3244
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3245
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3246
EVT VT = N->getValueType(0);
3247
EVT VT0 = N0.getValueType();
3249
// fold (select C, X, X) -> X
3252
// fold (select true, X, Y) -> X
3253
if (N0C && !N0C->isNullValue())
3255
// fold (select false, X, Y) -> Y
3256
if (N0C && N0C->isNullValue())
3258
// fold (select C, 1, X) -> (or C, X)
3259
if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3260
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3261
// fold (select C, 0, 1) -> (xor C, 1)
3262
if (VT.isInteger() &&
3265
TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
3266
N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3269
return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3270
N0, DAG.getConstant(1, VT0));
3271
XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3272
N0, DAG.getConstant(1, VT0));
3273
AddToWorkList(XORNode.getNode());
3275
return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3276
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3278
// fold (select C, 0, X) -> (and (not C), X)
3279
if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3280
SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3281
AddToWorkList(NOTNode.getNode());
3282
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3284
// fold (select C, X, 1) -> (or (not C), X)
3285
if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3286
SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3287
AddToWorkList(NOTNode.getNode());
3288
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3290
// fold (select C, X, 0) -> (and C, X)
3291
if (VT == MVT::i1 && N2C && N2C->isNullValue())
3292
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3293
// fold (select X, X, Y) -> (or X, Y)
3294
// fold (select X, 1, Y) -> (or X, Y)
3295
if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3296
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3297
// fold (select X, Y, X) -> (and X, Y)
3298
// fold (select X, Y, 0) -> (and X, Y)
3299
if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3300
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3302
// If we can fold this based on the true/false value, do so.
3303
if (SimplifySelectOps(N, N1, N2))
3304
return SDValue(N, 0); // Don't revisit N.
3306
// fold selects based on a setcc into other things, such as min/max/abs
3307
if (N0.getOpcode() == ISD::SETCC) {
3309
// Check against MVT::Other for SELECT_CC, which is a workaround for targets
3310
// having to say they don't support SELECT_CC on every type the DAG knows
3311
// about, since there is no way to mark an opcode illegal at all value types
3312
if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3313
TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3314
return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3315
N0.getOperand(0), N0.getOperand(1),
3316
N1, N2, N0.getOperand(2));
3317
return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3323
SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3324
SDValue N0 = N->getOperand(0);
3325
SDValue N1 = N->getOperand(1);
3326
SDValue N2 = N->getOperand(2);
3327
SDValue N3 = N->getOperand(3);
3328
SDValue N4 = N->getOperand(4);
3329
ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3331
// fold select_cc lhs, rhs, x, x, cc -> x
3335
// Determine if the condition we're dealing with is constant
3336
SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3337
N0, N1, CC, N->getDebugLoc(), false);
3338
if (SCC.getNode()) AddToWorkList(SCC.getNode());
3340
if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3341
if (!SCCC->isNullValue())
3342
return N2; // cond always true -> true val
3344
return N3; // cond always false -> false val
3347
// Fold to a simpler select_cc
3348
if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3349
return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3350
SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3353
// If we can fold this based on the true/false value, do so.
3354
if (SimplifySelectOps(N, N2, N3))
3355
return SDValue(N, 0); // Don't revisit N.
3357
// fold select_cc into other things, such as min/max/abs
3358
return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3361
SDValue DAGCombiner::visitSETCC(SDNode *N) {
3362
return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3363
cast<CondCodeSDNode>(N->getOperand(2))->get(),
3367
// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3368
// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3369
// transformation. Returns true if extension are possible and the above
3370
// mentioned transformation is profitable.
3371
static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3373
SmallVector<SDNode*, 4> &ExtendNodes,
3374
const TargetLowering &TLI) {
3375
bool HasCopyToRegUses = false;
3376
bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3377
for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3378
UE = N0.getNode()->use_end();
3383
if (UI.getUse().getResNo() != N0.getResNo())
3385
// FIXME: Only extend SETCC N, N and SETCC N, c for now.
3386
if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3387
ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3388
if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3389
// Sign bits will be lost after a zext.
3392
for (unsigned i = 0; i != 2; ++i) {
3393
SDValue UseOp = User->getOperand(i);
3396
if (!isa<ConstantSDNode>(UseOp))
3401
ExtendNodes.push_back(User);
3404
// If truncates aren't free and there are users we can't
3405
// extend, it isn't worthwhile.
3408
// Remember if this value is live-out.
3409
if (User->getOpcode() == ISD::CopyToReg)
3410
HasCopyToRegUses = true;
3413
if (HasCopyToRegUses) {
3414
bool BothLiveOut = false;
3415
for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3417
SDUse &Use = UI.getUse();
3418
if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3424
// Both unextended and extended values are live out. There had better be
3425
// good a reason for the transformation.
3426
return ExtendNodes.size();
3431
SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3432
SDValue N0 = N->getOperand(0);
3433
EVT VT = N->getValueType(0);
3435
// fold (sext c1) -> c1
3436
if (isa<ConstantSDNode>(N0))
3437
return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3439
// fold (sext (sext x)) -> (sext x)
3440
// fold (sext (aext x)) -> (sext x)
3441
if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3442
return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3445
if (N0.getOpcode() == ISD::TRUNCATE) {
3446
// fold (sext (truncate (load x))) -> (sext (smaller load x))
3447
// fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3448
SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3449
if (NarrowLoad.getNode()) {
3450
SDNode* oye = N0.getNode()->getOperand(0).getNode();
3451
if (NarrowLoad.getNode() != N0.getNode()) {
3452
CombineTo(N0.getNode(), NarrowLoad);
3453
// CombineTo deleted the truncate, if needed, but not what's under it.
3456
return SDValue(N, 0); // Return N so it doesn't get rechecked!
3459
// See if the value being truncated is already sign extended. If so, just
3460
// eliminate the trunc/sext pair.
3461
SDValue Op = N0.getOperand(0);
3462
unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3463
unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3464
unsigned DestBits = VT.getScalarType().getSizeInBits();
3465
unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3467
if (OpBits == DestBits) {
3468
// Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3469
// bits, it is already ready.
3470
if (NumSignBits > DestBits-MidBits)
3472
} else if (OpBits < DestBits) {
3473
// Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3474
// bits, just sext from i32.
3475
if (NumSignBits > OpBits-MidBits)
3476
return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3478
// Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3479
// bits, just truncate to i32.
3480
if (NumSignBits > OpBits-MidBits)
3481
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3484
// fold (sext (truncate x)) -> (sextinreg x).
3485
if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3486
N0.getValueType())) {
3487
if (OpBits < DestBits)
3488
Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3489
else if (OpBits > DestBits)
3490
Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3491
return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3492
DAG.getValueType(N0.getValueType()));
3496
// fold (sext (load x)) -> (sext (truncate (sextload x)))
3497
if (ISD::isNON_EXTLoad(N0.getNode()) &&
3498
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3499
TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3500
bool DoXform = true;
3501
SmallVector<SDNode*, 4> SetCCs;
3502
if (!N0.hasOneUse())
3503
DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3505
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3506
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
3508
LN0->getBasePtr(), LN0->getSrcValue(),
3509
LN0->getSrcValueOffset(),
3511
LN0->isVolatile(), LN0->isNonTemporal(),
3512
LN0->getAlignment());
3513
CombineTo(N, ExtLoad);
3514
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3515
N0.getValueType(), ExtLoad);
3516
CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3518
// Extend SetCC uses if necessary.
3519
for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3520
SDNode *SetCC = SetCCs[i];
3521
SmallVector<SDValue, 4> Ops;
3523
for (unsigned j = 0; j != 2; ++j) {
3524
SDValue SOp = SetCC->getOperand(j);
3526
Ops.push_back(ExtLoad);
3528
Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3529
N->getDebugLoc(), VT, SOp));
3532
Ops.push_back(SetCC->getOperand(2));
3533
CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3534
SetCC->getValueType(0),
3535
&Ops[0], Ops.size()));
3538
return SDValue(N, 0); // Return N so it doesn't get rechecked!
3542
// fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3543
// fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3544
if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3545
ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3546
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3547
EVT MemVT = LN0->getMemoryVT();
3548
if ((!LegalOperations && !LN0->isVolatile()) ||
3549
TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
3550
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
3552
LN0->getBasePtr(), LN0->getSrcValue(),
3553
LN0->getSrcValueOffset(), MemVT,
3554
LN0->isVolatile(), LN0->isNonTemporal(),
3555
LN0->getAlignment());
3556
CombineTo(N, ExtLoad);
3557
CombineTo(N0.getNode(),
3558
DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3559
N0.getValueType(), ExtLoad),
3560
ExtLoad.getValue(1));
3561
return SDValue(N, 0); // Return N so it doesn't get rechecked!
3565
if (N0.getOpcode() == ISD::SETCC) {
3566
// sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3567
// Only do this before legalize for now.
3568
if (VT.isVector() && !LegalOperations) {
3569
EVT N0VT = N0.getOperand(0).getValueType();
3570
// We know that the # elements of the results is the same as the
3571
// # elements of the compare (and the # elements of the compare result
3572
// for that matter). Check to see that they are the same size. If so,
3573
// we know that the element size of the sext'd result matches the
3574
// element size of the compare operands.
3575
if (VT.getSizeInBits() == N0VT.getSizeInBits())
3576
return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3578
cast<CondCodeSDNode>(N0.getOperand(2))->get());
3579
// If the desired elements are smaller or larger than the source
3580
// elements we can use a matching integer vector type and then
3581
// truncate/sign extend
3583
EVT MatchingElementType =
3584
EVT::getIntegerVT(*DAG.getContext(),
3585
N0VT.getScalarType().getSizeInBits());
3586
EVT MatchingVectorType =
3587
EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3588
N0VT.getVectorNumElements());
3590
DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3592
cast<CondCodeSDNode>(N0.getOperand(2))->get());
3593
return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
3597
// sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3598
unsigned ElementWidth = VT.getScalarType().getSizeInBits();
3600
DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
3602
SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3603
NegOne, DAG.getConstant(0, VT),
3604
cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3605
if (SCC.getNode()) return SCC;
3606
if (!LegalOperations ||
3607
TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
3608
return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3609
DAG.getSetCC(N->getDebugLoc(),
3610
TLI.getSetCCResultType(VT),
3611
N0.getOperand(0), N0.getOperand(1),
3612
cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3613
NegOne, DAG.getConstant(0, VT));
3616
// fold (sext x) -> (zext x) if the sign bit is known zero.
3617
if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3618
DAG.SignBitIsZero(N0))
3619
return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3624
SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3625
SDValue N0 = N->getOperand(0);
3626
EVT VT = N->getValueType(0);
3628
// fold (zext c1) -> c1
3629
if (isa<ConstantSDNode>(N0))
3630
return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3631
// fold (zext (zext x)) -> (zext x)
3632
// fold (zext (aext x)) -> (zext x)
3633
if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3634
return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3637
// fold (zext (truncate (load x))) -> (zext (smaller load x))
3638
// fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3639
if (N0.getOpcode() == ISD::TRUNCATE) {
3640
SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3641
if (NarrowLoad.getNode()) {
3642
SDNode* oye = N0.getNode()->getOperand(0).getNode();
3643
if (NarrowLoad.getNode() != N0.getNode()) {
3644
CombineTo(N0.getNode(), NarrowLoad);
3645
// CombineTo deleted the truncate, if needed, but not what's under it.
3648
return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3652
// fold (zext (truncate x)) -> (and x, mask)
3653
if (N0.getOpcode() == ISD::TRUNCATE &&
3654
(!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3655
SDValue Op = N0.getOperand(0);
3656
if (Op.getValueType().bitsLT(VT)) {
3657
Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3658
} else if (Op.getValueType().bitsGT(VT)) {
3659
Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3661
return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
3662
N0.getValueType().getScalarType());
3665
// Fold (zext (and (trunc x), cst)) -> (and x, cst),
3666
// if either of the casts is not free.
3667
if (N0.getOpcode() == ISD::AND &&
3668
N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3669
N0.getOperand(1).getOpcode() == ISD::Constant &&
3670
(!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3671
N0.getValueType()) ||
3672
!TLI.isZExtFree(N0.getValueType(), VT))) {
3673
SDValue X = N0.getOperand(0).getOperand(0);
3674
if (X.getValueType().bitsLT(VT)) {
3675
X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3676
} else if (X.getValueType().bitsGT(VT)) {
3677
X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3679
APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3680
Mask.zext(VT.getSizeInBits());
3681
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3682
X, DAG.getConstant(Mask, VT));
3685
// fold (zext (load x)) -> (zext (truncate (zextload x)))
3686
if (ISD::isNON_EXTLoad(N0.getNode()) &&
3687
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3688
TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3689
bool DoXform = true;
3690
SmallVector<SDNode*, 4> SetCCs;
3691
if (!N0.hasOneUse())
3692
DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3694
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3695
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(),
3697
LN0->getBasePtr(), LN0->getSrcValue(),
3698
LN0->getSrcValueOffset(),
3700
LN0->isVolatile(), LN0->isNonTemporal(),
3701
LN0->getAlignment());
3702
CombineTo(N, ExtLoad);
3703
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3704
N0.getValueType(), ExtLoad);
3705
CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3707
// Extend SetCC uses if necessary.
3708
for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3709
SDNode *SetCC = SetCCs[i];
3710
SmallVector<SDValue, 4> Ops;
3712
for (unsigned j = 0; j != 2; ++j) {
3713
SDValue SOp = SetCC->getOperand(j);
3715
Ops.push_back(ExtLoad);
3717
Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3718
N->getDebugLoc(), VT, SOp));
3721
Ops.push_back(SetCC->getOperand(2));
3722
CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3723
SetCC->getValueType(0),
3724
&Ops[0], Ops.size()));
3727
return SDValue(N, 0); // Return N so it doesn't get rechecked!
3731
// fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3732
// fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3733
if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3734
ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3735
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3736
EVT MemVT = LN0->getMemoryVT();
3737
if ((!LegalOperations && !LN0->isVolatile()) ||
3738
TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
3739
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(),
3741
LN0->getBasePtr(), LN0->getSrcValue(),
3742
LN0->getSrcValueOffset(), MemVT,
3743
LN0->isVolatile(), LN0->isNonTemporal(),
3744
LN0->getAlignment());
3745
CombineTo(N, ExtLoad);
3746
CombineTo(N0.getNode(),
3747
DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3749
ExtLoad.getValue(1));
3750
return SDValue(N, 0); // Return N so it doesn't get rechecked!
3754
if (N0.getOpcode() == ISD::SETCC) {
3755
if (!LegalOperations && VT.isVector()) {
3756
// zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
3757
// Only do this before legalize for now.
3758
EVT N0VT = N0.getOperand(0).getValueType();
3759
EVT EltVT = VT.getVectorElementType();
3760
SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
3761
DAG.getConstant(1, EltVT));
3762
if (VT.getSizeInBits() == N0VT.getSizeInBits()) {
3763
// We know that the # elements of the results is the same as the
3764
// # elements of the compare (and the # elements of the compare result
3765
// for that matter). Check to see that they are the same size. If so,
3766
// we know that the element size of the sext'd result matches the
3767
// element size of the compare operands.
3768
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3769
DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3771
cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3772
DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
3773
&OneOps[0], OneOps.size()));
3775
// If the desired elements are smaller or larger than the source
3776
// elements we can use a matching integer vector type and then
3777
// truncate/sign extend
3778
EVT MatchingElementType =
3779
EVT::getIntegerVT(*DAG.getContext(),
3780
N0VT.getScalarType().getSizeInBits());
3781
EVT MatchingVectorType =
3782
EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3783
N0VT.getVectorNumElements());
3785
DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3787
cast<CondCodeSDNode>(N0.getOperand(2))->get());
3788
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3789
DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
3790
DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
3791
&OneOps[0], OneOps.size()));
3795
// zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3797
SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3798
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3799
cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3800
if (SCC.getNode()) return SCC;
3803
// (zext (shl (zext x), cst)) -> (shl (zext x), cst)
3804
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
3805
isa<ConstantSDNode>(N0.getOperand(1)) &&
3806
N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
3808
if (N0.getOpcode() == ISD::SHL) {
3809
// If the original shl may be shifting out bits, do not perform this
3811
unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3812
unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() -
3813
N0.getOperand(0).getOperand(0).getValueType().getSizeInBits();
3814
if (ShAmt > KnownZeroBits)
3817
DebugLoc dl = N->getDebugLoc();
3818
return DAG.getNode(N0.getOpcode(), dl, VT,
3819
DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),
3820
DAG.getNode(ISD::ZERO_EXTEND, dl,
3821
N0.getOperand(1).getValueType(),
3828
SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3829
SDValue N0 = N->getOperand(0);
3830
EVT VT = N->getValueType(0);
3832
// fold (aext c1) -> c1
3833
if (isa<ConstantSDNode>(N0))
3834
return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3835
// fold (aext (aext x)) -> (aext x)
3836
// fold (aext (zext x)) -> (zext x)
3837
// fold (aext (sext x)) -> (sext x)
3838
if (N0.getOpcode() == ISD::ANY_EXTEND ||
3839
N0.getOpcode() == ISD::ZERO_EXTEND ||
3840
N0.getOpcode() == ISD::SIGN_EXTEND)
3841
return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3843
// fold (aext (truncate (load x))) -> (aext (smaller load x))
3844
// fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3845
if (N0.getOpcode() == ISD::TRUNCATE) {
3846
SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3847
if (NarrowLoad.getNode()) {
3848
SDNode* oye = N0.getNode()->getOperand(0).getNode();
3849
if (NarrowLoad.getNode() != N0.getNode()) {
3850
CombineTo(N0.getNode(), NarrowLoad);
3851
// CombineTo deleted the truncate, if needed, but not what's under it.
3854
return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3858
// fold (aext (truncate x))
3859
if (N0.getOpcode() == ISD::TRUNCATE) {
3860
SDValue TruncOp = N0.getOperand(0);
3861
if (TruncOp.getValueType() == VT)
3862
return TruncOp; // x iff x size == zext size.
3863
if (TruncOp.getValueType().bitsGT(VT))
3864
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3865
return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3868
// Fold (aext (and (trunc x), cst)) -> (and x, cst)
3869
// if the trunc is not free.
3870
if (N0.getOpcode() == ISD::AND &&
3871
N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3872
N0.getOperand(1).getOpcode() == ISD::Constant &&
3873
!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3874
N0.getValueType())) {
3875
SDValue X = N0.getOperand(0).getOperand(0);
3876
if (X.getValueType().bitsLT(VT)) {
3877
X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3878
} else if (X.getValueType().bitsGT(VT)) {
3879
X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3881
APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3882
Mask.zext(VT.getSizeInBits());
3883
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3884
X, DAG.getConstant(Mask, VT));
3887
// fold (aext (load x)) -> (aext (truncate (extload x)))
3888
if (ISD::isNON_EXTLoad(N0.getNode()) &&
3889
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3890
TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3891
bool DoXform = true;
3892
SmallVector<SDNode*, 4> SetCCs;
3893
if (!N0.hasOneUse())
3894
DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
3896
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3897
SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(),
3899
LN0->getBasePtr(), LN0->getSrcValue(),
3900
LN0->getSrcValueOffset(),
3902
LN0->isVolatile(), LN0->isNonTemporal(),
3903
LN0->getAlignment());
3904
CombineTo(N, ExtLoad);
3905
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3906
N0.getValueType(), ExtLoad);
3907
CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3909
// Extend SetCC uses if necessary.
3910
for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3911
SDNode *SetCC = SetCCs[i];
3912
SmallVector<SDValue, 4> Ops;
3914
for (unsigned j = 0; j != 2; ++j) {
3915
SDValue SOp = SetCC->getOperand(j);
3917
Ops.push_back(ExtLoad);
3919
Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
3920
N->getDebugLoc(), VT, SOp));
3923
Ops.push_back(SetCC->getOperand(2));
3924
CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3925
SetCC->getValueType(0),
3926
&Ops[0], Ops.size()));
3929
return SDValue(N, 0); // Return N so it doesn't get rechecked!
3933
// fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3934
// fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3935
// fold (aext ( extload x)) -> (aext (truncate (extload x)))
3936
if (N0.getOpcode() == ISD::LOAD &&
3937
!ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3939
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3940
EVT MemVT = LN0->getMemoryVT();
3941
SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
3943
LN0->getChain(), LN0->getBasePtr(),
3945
LN0->getSrcValueOffset(), MemVT,
3946
LN0->isVolatile(), LN0->isNonTemporal(),
3947
LN0->getAlignment());
3948
CombineTo(N, ExtLoad);
3949
CombineTo(N0.getNode(),
3950
DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3951
N0.getValueType(), ExtLoad),
3952
ExtLoad.getValue(1));
3953
return SDValue(N, 0); // Return N so it doesn't get rechecked!
3956
if (N0.getOpcode() == ISD::SETCC) {
3957
// aext(setcc) -> sext_in_reg(vsetcc) for vectors.
3958
// Only do this before legalize for now.
3959
if (VT.isVector() && !LegalOperations) {
3960
EVT N0VT = N0.getOperand(0).getValueType();
3961
// We know that the # elements of the results is the same as the
3962
// # elements of the compare (and the # elements of the compare result
3963
// for that matter). Check to see that they are the same size. If so,
3964
// we know that the element size of the sext'd result matches the
3965
// element size of the compare operands.
3966
if (VT.getSizeInBits() == N0VT.getSizeInBits())
3967
return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3969
cast<CondCodeSDNode>(N0.getOperand(2))->get());
3970
// If the desired elements are smaller or larger than the source
3971
// elements we can use a matching integer vector type and then
3972
// truncate/sign extend
3974
EVT MatchingElementType =
3975
EVT::getIntegerVT(*DAG.getContext(),
3976
N0VT.getScalarType().getSizeInBits());
3977
EVT MatchingVectorType =
3978
EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3979
N0VT.getVectorNumElements());
3981
DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3983
cast<CondCodeSDNode>(N0.getOperand(2))->get());
3984
return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
3988
// aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3990
SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3991
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3992
cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4000
/// GetDemandedBits - See if the specified operand can be simplified with the
4001
/// knowledge that only the bits specified by Mask are used. If so, return the
4002
/// simpler operand, otherwise return a null SDValue.
4003
SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4004
switch (V.getOpcode()) {
4008
// If the LHS or RHS don't contribute bits to the or, drop them.
4009
if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4010
return V.getOperand(1);
4011
if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4012
return V.getOperand(0);
4015
// Only look at single-use SRLs.
4016
if (!V.getNode()->hasOneUse())
4018
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4019
// See if we can recursively simplify the LHS.
4020
unsigned Amt = RHSC->getZExtValue();
4022
// Watch out for shift count overflow though.
4023
if (Amt >= Mask.getBitWidth()) break;
4024
APInt NewMask = Mask << Amt;
4025
SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4026
if (SimplifyLHS.getNode())
4027
return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4028
SimplifyLHS, V.getOperand(1));
4034
/// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4035
/// bits and then truncated to a narrower type and where N is a multiple
4036
/// of number of bits of the narrower type, transform it to a narrower load
4037
/// from address + N / num of bits of new type. If the result is to be
4038
/// extended, also fold the extension to form a extending load.
4039
SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4040
unsigned Opc = N->getOpcode();
4042
ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4043
SDValue N0 = N->getOperand(0);
4044
EVT VT = N->getValueType(0);
4047
// This transformation isn't valid for vector loads.
4051
// Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4053
if (Opc == ISD::SIGN_EXTEND_INREG) {
4054
ExtType = ISD::SEXTLOAD;
4055
ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4056
if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
4058
} else if (Opc == ISD::SRL) {
4059
// Annother special-case: SRL is basically zero-extending a narrower
4061
ExtType = ISD::ZEXTLOAD;
4063
ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4064
if (!N01) return SDValue();
4065
ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4066
VT.getSizeInBits() - N01->getZExtValue());
4069
unsigned EVTBits = ExtVT.getSizeInBits();
4071
if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) {
4072
if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4073
ShAmt = N01->getZExtValue();
4074
// Is the shift amount a multiple of size of VT?
4075
if ((ShAmt & (EVTBits-1)) == 0) {
4076
N0 = N0.getOperand(0);
4077
// Is the load width a multiple of size of VT?
4078
if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4084
// Do not generate loads of non-round integer types since these can
4085
// be expensive (and would be wrong if the type is not byte sized).
4086
if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
4087
cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits &&
4088
// Do not change the width of a volatile load.
4089
!cast<LoadSDNode>(N0)->isVolatile()) {
4090
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4091
EVT PtrType = N0.getOperand(1).getValueType();
4093
// For big endian targets, we need to adjust the offset to the pointer to
4094
// load the correct bytes.
4095
if (TLI.isBigEndian()) {
4096
unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4097
unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4098
ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4101
uint64_t PtrOff = ShAmt / 8;
4102
unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4103
SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4104
PtrType, LN0->getBasePtr(),
4105
DAG.getConstant(PtrOff, PtrType));
4106
AddToWorkList(NewPtr.getNode());
4108
SDValue Load = (ExtType == ISD::NON_EXTLOAD)
4109
? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4110
LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
4111
LN0->isVolatile(), LN0->isNonTemporal(), NewAlign)
4112
: DAG.getExtLoad(ExtType, VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4113
LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
4114
ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4117
// Replace the old load's chain with the new load's chain.
4118
WorkListRemover DeadNodes(*this);
4119
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4122
// Return the new loaded value.
4129
SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4130
SDValue N0 = N->getOperand(0);
4131
SDValue N1 = N->getOperand(1);
4132
EVT VT = N->getValueType(0);
4133
EVT EVT = cast<VTSDNode>(N1)->getVT();
4134
unsigned VTBits = VT.getScalarType().getSizeInBits();
4135
unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4137
// fold (sext_in_reg c1) -> c1
4138
if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4139
return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4141
// If the input is already sign extended, just drop the extension.
4142
if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4145
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4146
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4147
EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4148
return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4149
N0.getOperand(0), N1);
4152
// fold (sext_in_reg (sext x)) -> (sext x)
4153
// fold (sext_in_reg (aext x)) -> (sext x)
4154
// if x is small enough.
4155
if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4156
SDValue N00 = N0.getOperand(0);
4157
if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4158
(!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4159
return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4162
// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4163
if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4164
return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4166
// fold operands of sext_in_reg based on knowledge that the top bits are not
4168
if (SimplifyDemandedBits(SDValue(N, 0)))
4169
return SDValue(N, 0);
4171
// fold (sext_in_reg (load x)) -> (smaller sextload x)
4172
// fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4173
SDValue NarrowLoad = ReduceLoadWidth(N);
4174
if (NarrowLoad.getNode())
4177
// fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4178
// fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4179
// We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4180
if (N0.getOpcode() == ISD::SRL) {
4181
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4182
if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4183
// We can turn this into an SRA iff the input to the SRL is already sign
4185
unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4186
if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4187
return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4188
N0.getOperand(0), N0.getOperand(1));
4192
// fold (sext_inreg (extload x)) -> (sextload x)
4193
if (ISD::isEXTLoad(N0.getNode()) &&
4194
ISD::isUNINDEXEDLoad(N0.getNode()) &&
4195
EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4196
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4197
TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4198
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4199
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
4201
LN0->getBasePtr(), LN0->getSrcValue(),
4202
LN0->getSrcValueOffset(), EVT,
4203
LN0->isVolatile(), LN0->isNonTemporal(),
4204
LN0->getAlignment());
4205
CombineTo(N, ExtLoad);
4206
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4207
return SDValue(N, 0); // Return N so it doesn't get rechecked!
4209
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4210
if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4212
EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4213
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4214
TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4215
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4216
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
4218
LN0->getBasePtr(), LN0->getSrcValue(),
4219
LN0->getSrcValueOffset(), EVT,
4220
LN0->isVolatile(), LN0->isNonTemporal(),
4221
LN0->getAlignment());
4222
CombineTo(N, ExtLoad);
4223
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4224
return SDValue(N, 0); // Return N so it doesn't get rechecked!
4229
SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4230
SDValue N0 = N->getOperand(0);
4231
EVT VT = N->getValueType(0);
4234
if (N0.getValueType() == N->getValueType(0))
4236
// fold (truncate c1) -> c1
4237
if (isa<ConstantSDNode>(N0))
4238
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4239
// fold (truncate (truncate x)) -> (truncate x)
4240
if (N0.getOpcode() == ISD::TRUNCATE)
4241
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4242
// fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4243
if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4244
N0.getOpcode() == ISD::SIGN_EXTEND ||
4245
N0.getOpcode() == ISD::ANY_EXTEND) {
4246
if (N0.getOperand(0).getValueType().bitsLT(VT))
4247
// if the source is smaller than the dest, we still need an extend
4248
return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4250
else if (N0.getOperand(0).getValueType().bitsGT(VT))
4251
// if the source is larger than the dest, than we just need the truncate
4252
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4254
// if the source and dest are the same type, we can drop both the extend
4255
// and the truncate.
4256
return N0.getOperand(0);
4259
// See if we can simplify the input to this truncate through knowledge that
4260
// only the low bits are being used. For example "trunc (or (shl x, 8), y)"
4263
GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4264
VT.getSizeInBits()));
4265
if (Shorter.getNode())
4266
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
4268
// fold (truncate (load x)) -> (smaller load x)
4269
// fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
4270
if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
4271
SDValue Reduced = ReduceLoadWidth(N);
4272
if (Reduced.getNode())
4276
// Simplify the operands using demanded-bits information.
4277
if (!VT.isVector() &&
4278
SimplifyDemandedBits(SDValue(N, 0)))
4279
return SDValue(N, 0);
4284
static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
4285
SDValue Elt = N->getOperand(i);
4286
if (Elt.getOpcode() != ISD::MERGE_VALUES)
4287
return Elt.getNode();
4288
return Elt.getOperand(Elt.getResNo()).getNode();
4291
/// CombineConsecutiveLoads - build_pair (load, load) -> load
4292
/// if load locations are consecutive.
4293
SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
4294
assert(N->getOpcode() == ISD::BUILD_PAIR);
4296
LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
4297
LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
4298
if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
4300
EVT LD1VT = LD1->getValueType(0);
4302
if (ISD::isNON_EXTLoad(LD2) &&
4304
// If both are volatile this would reduce the number of volatile loads.
4305
// If one is volatile it might be ok, but play conservative and bail out.
4306
!LD1->isVolatile() &&
4307
!LD2->isVolatile() &&
4308
DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
4309
unsigned Align = LD1->getAlignment();
4310
unsigned NewAlign = TLI.getTargetData()->
4311
getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4313
if (NewAlign <= Align &&
4314
(!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
4315
return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
4316
LD1->getBasePtr(), LD1->getSrcValue(),
4317
LD1->getSrcValueOffset(), false, false, Align);
4323
SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
4324
SDValue N0 = N->getOperand(0);
4325
EVT VT = N->getValueType(0);
4327
// If the input is a BUILD_VECTOR with all constant elements, fold this now.
4328
// Only do this before legalize, since afterward the target may be depending
4329
// on the bitconvert.
4330
// First check to see if this is all constant.
4332
N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4334
bool isSimple = true;
4335
for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4336
if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4337
N0.getOperand(i).getOpcode() != ISD::Constant &&
4338
N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4343
EVT DestEltVT = N->getValueType(0).getVectorElementType();
4344
assert(!DestEltVT.isVector() &&
4345
"Element type of vector ValueType must not be vector!");
4347
return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4350
// If the input is a constant, let getNode fold it.
4351
if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4352
SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
4353
if (Res.getNode() != N) {
4354
if (!LegalOperations ||
4355
TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4358
// Folding it resulted in an illegal node, and it's too late to
4359
// do that. Clean up the old node and forego the transformation.
4360
// Ideally this won't happen very often, because instcombine
4361
// and the earlier dagcombine runs (where illegal nodes are
4362
// permitted) should have folded most of them already.
4363
DAG.DeleteNode(Res.getNode());
4367
// (conv (conv x, t1), t2) -> (conv x, t2)
4368
if (N0.getOpcode() == ISD::BIT_CONVERT)
4369
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
4372
// fold (conv (load x)) -> (load (conv*)x)
4373
// If the resultant load doesn't need a higher alignment than the original!
4374
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4375
// Do not change the width of a volatile load.
4376
!cast<LoadSDNode>(N0)->isVolatile() &&
4377
(!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
4378
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4379
unsigned Align = TLI.getTargetData()->
4380
getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4381
unsigned OrigAlign = LN0->getAlignment();
4383
if (Align <= OrigAlign) {
4384
SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
4386
LN0->getSrcValue(), LN0->getSrcValueOffset(),
4387
LN0->isVolatile(), LN0->isNonTemporal(),
4390
CombineTo(N0.getNode(),
4391
DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4392
N0.getValueType(), Load),
4398
// fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
4399
// fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
4400
// This often reduces constant pool loads.
4401
if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
4402
N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
4403
SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
4405
AddToWorkList(NewConv.getNode());
4407
APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4408
if (N0.getOpcode() == ISD::FNEG)
4409
return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
4410
NewConv, DAG.getConstant(SignBit, VT));
4411
assert(N0.getOpcode() == ISD::FABS);
4412
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4413
NewConv, DAG.getConstant(~SignBit, VT));
4416
// fold (bitconvert (fcopysign cst, x)) ->
4417
// (or (and (bitconvert x), sign), (and cst, (not sign)))
4418
// Note that we don't handle (copysign x, cst) because this can always be
4419
// folded to an fneg or fabs.
4420
if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
4421
isa<ConstantFPSDNode>(N0.getOperand(0)) &&
4422
VT.isInteger() && !VT.isVector()) {
4423
unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
4424
EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
4425
if (isTypeLegal(IntXVT)) {
4426
SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4427
IntXVT, N0.getOperand(1));
4428
AddToWorkList(X.getNode());
4430
// If X has a different width than the result/lhs, sext it or truncate it.
4431
unsigned VTWidth = VT.getSizeInBits();
4432
if (OrigXWidth < VTWidth) {
4433
X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
4434
AddToWorkList(X.getNode());
4435
} else if (OrigXWidth > VTWidth) {
4436
// To get the sign bit in the right place, we have to shift it right
4437
// before truncating.
4438
X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
4439
X.getValueType(), X,
4440
DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
4441
AddToWorkList(X.getNode());
4442
X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4443
AddToWorkList(X.getNode());
4446
APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4447
X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
4448
X, DAG.getConstant(SignBit, VT));
4449
AddToWorkList(X.getNode());
4451
SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4452
VT, N0.getOperand(0));
4453
Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
4454
Cst, DAG.getConstant(~SignBit, VT));
4455
AddToWorkList(Cst.getNode());
4457
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
4461
// bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
4462
if (N0.getOpcode() == ISD::BUILD_PAIR) {
4463
SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
4464
if (CombineLD.getNode())
4471
SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
4472
EVT VT = N->getValueType(0);
4473
return CombineConsecutiveLoads(N, VT);
4476
/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
4477
/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
4478
/// destination element value type.
4479
SDValue DAGCombiner::
4480
ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
4481
EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
4483
// If this is already the right type, we're done.
4484
if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
4486
unsigned SrcBitSize = SrcEltVT.getSizeInBits();
4487
unsigned DstBitSize = DstEltVT.getSizeInBits();
4489
// If this is a conversion of N elements of one type to N elements of another
4490
// type, convert each element. This handles FP<->INT cases.
4491
if (SrcBitSize == DstBitSize) {
4492
EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4493
BV->getValueType(0).getVectorNumElements());
4495
// Due to the FP element handling below calling this routine recursively,
4496
// we can end up with a scalar-to-vector node here.
4497
if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
4498
return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4499
DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
4500
DstEltVT, BV->getOperand(0)));
4502
SmallVector<SDValue, 8> Ops;
4503
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4504
SDValue Op = BV->getOperand(i);
4505
// If the vector element type is not legal, the BUILD_VECTOR operands
4506
// are promoted and implicitly truncated. Make that explicit here.
4507
if (Op.getValueType() != SrcEltVT)
4508
Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
4509
Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
4511
AddToWorkList(Ops.back().getNode());
4513
return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4514
&Ops[0], Ops.size());
4517
// Otherwise, we're growing or shrinking the elements. To avoid having to
4518
// handle annoying details of growing/shrinking FP values, we convert them to
4520
if (SrcEltVT.isFloatingPoint()) {
4521
// Convert the input float vector to a int vector where the elements are the
4523
assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
4524
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
4525
BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
4529
// Now we know the input is an integer vector. If the output is a FP type,
4530
// convert to integer first, then to FP of the right size.
4531
if (DstEltVT.isFloatingPoint()) {
4532
assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
4533
EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
4534
SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
4536
// Next, convert to FP elements of the same size.
4537
return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
4540
// Okay, we know the src/dst types are both integers of differing types.
4541
// Handling growing first.
4542
assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
4543
if (SrcBitSize < DstBitSize) {
4544
unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
4546
SmallVector<SDValue, 8> Ops;
4547
for (unsigned i = 0, e = BV->getNumOperands(); i != e;
4548
i += NumInputsPerOutput) {
4549
bool isLE = TLI.isLittleEndian();
4550
APInt NewBits = APInt(DstBitSize, 0);
4551
bool EltIsUndef = true;
4552
for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
4553
// Shift the previously computed bits over.
4554
NewBits <<= SrcBitSize;
4555
SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
4556
if (Op.getOpcode() == ISD::UNDEF) continue;
4559
NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).
4560
zextOrTrunc(SrcBitSize).zext(DstBitSize);
4564
Ops.push_back(DAG.getUNDEF(DstEltVT));
4566
Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
4569
EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
4570
return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4571
&Ops[0], Ops.size());
4574
// Finally, this must be the case where we are shrinking elements: each input
4575
// turns into multiple outputs.
4576
bool isS2V = ISD::isScalarToVector(BV);
4577
unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
4578
EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4579
NumOutputsPerInput*BV->getNumOperands());
4580
SmallVector<SDValue, 8> Ops;
4582
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4583
if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
4584
for (unsigned j = 0; j != NumOutputsPerInput; ++j)
4585
Ops.push_back(DAG.getUNDEF(DstEltVT));
4589
APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))->
4590
getAPIntValue()).zextOrTrunc(SrcBitSize);
4592
for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
4593
APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
4594
Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
4595
if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
4596
// Simply turn this into a SCALAR_TO_VECTOR of the new type.
4597
return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4599
OpVal = OpVal.lshr(DstBitSize);
4602
// For big endian targets, swap the order of the pieces of each element.
4603
if (TLI.isBigEndian())
4604
std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
4607
return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4608
&Ops[0], Ops.size());
4611
SDValue DAGCombiner::visitFADD(SDNode *N) {
4612
SDValue N0 = N->getOperand(0);
4613
SDValue N1 = N->getOperand(1);
4614
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4615
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4616
EVT VT = N->getValueType(0);
4619
if (VT.isVector()) {
4620
SDValue FoldedVOp = SimplifyVBinOp(N);
4621
if (FoldedVOp.getNode()) return FoldedVOp;
4624
// fold (fadd c1, c2) -> (fadd c1, c2)
4625
if (N0CFP && N1CFP && VT != MVT::ppcf128)
4626
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
4627
// canonicalize constant to RHS
4628
if (N0CFP && !N1CFP)
4629
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
4630
// fold (fadd A, 0) -> A
4631
if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4633
// fold (fadd A, (fneg B)) -> (fsub A, B)
4634
if (isNegatibleForFree(N1, LegalOperations) == 2)
4635
return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
4636
GetNegatedExpression(N1, DAG, LegalOperations));
4637
// fold (fadd (fneg A), B) -> (fsub B, A)
4638
if (isNegatibleForFree(N0, LegalOperations) == 2)
4639
return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
4640
GetNegatedExpression(N0, DAG, LegalOperations));
4642
// If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
4643
if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
4644
N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4645
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
4646
DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
4647
N0.getOperand(1), N1));
4652
SDValue DAGCombiner::visitFSUB(SDNode *N) {
4653
SDValue N0 = N->getOperand(0);
4654
SDValue N1 = N->getOperand(1);
4655
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4656
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4657
EVT VT = N->getValueType(0);
4660
if (VT.isVector()) {
4661
SDValue FoldedVOp = SimplifyVBinOp(N);
4662
if (FoldedVOp.getNode()) return FoldedVOp;
4665
// fold (fsub c1, c2) -> c1-c2
4666
if (N0CFP && N1CFP && VT != MVT::ppcf128)
4667
return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4668
// fold (fsub A, 0) -> A
4669
if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4671
// fold (fsub 0, B) -> -B
4672
if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4673
if (isNegatibleForFree(N1, LegalOperations))
4674
return GetNegatedExpression(N1, DAG, LegalOperations);
4675
if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4676
return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4678
// fold (fsub A, (fneg B)) -> (fadd A, B)
4679
if (isNegatibleForFree(N1, LegalOperations))
4680
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4681
GetNegatedExpression(N1, DAG, LegalOperations));
4686
SDValue DAGCombiner::visitFMUL(SDNode *N) {
4687
SDValue N0 = N->getOperand(0);
4688
SDValue N1 = N->getOperand(1);
4689
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4690
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4691
EVT VT = N->getValueType(0);
4694
if (VT.isVector()) {
4695
SDValue FoldedVOp = SimplifyVBinOp(N);
4696
if (FoldedVOp.getNode()) return FoldedVOp;
4699
// fold (fmul c1, c2) -> c1*c2
4700
if (N0CFP && N1CFP && VT != MVT::ppcf128)
4701
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4702
// canonicalize constant to RHS
4703
if (N0CFP && !N1CFP)
4704
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4705
// fold (fmul A, 0) -> 0
4706
if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4708
// fold (fmul A, 0) -> 0, vector edition.
4709
if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
4711
// fold (fmul X, 2.0) -> (fadd X, X)
4712
if (N1CFP && N1CFP->isExactlyValue(+2.0))
4713
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4714
// fold (fmul X, -1.0) -> (fneg X)
4715
if (N1CFP && N1CFP->isExactlyValue(-1.0))
4716
if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4717
return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4719
// fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4720
if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4721
if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4722
// Both can be negated for free, check to see if at least one is cheaper
4724
if (LHSNeg == 2 || RHSNeg == 2)
4725
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4726
GetNegatedExpression(N0, DAG, LegalOperations),
4727
GetNegatedExpression(N1, DAG, LegalOperations));
4731
// If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4732
if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4733
N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4734
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4735
DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4736
N0.getOperand(1), N1));
4741
SDValue DAGCombiner::visitFDIV(SDNode *N) {
4742
SDValue N0 = N->getOperand(0);
4743
SDValue N1 = N->getOperand(1);
4744
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4745
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4746
EVT VT = N->getValueType(0);
4749
if (VT.isVector()) {
4750
SDValue FoldedVOp = SimplifyVBinOp(N);
4751
if (FoldedVOp.getNode()) return FoldedVOp;
4754
// fold (fdiv c1, c2) -> c1/c2
4755
if (N0CFP && N1CFP && VT != MVT::ppcf128)
4756
return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4759
// (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4760
if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4761
if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4762
// Both can be negated for free, check to see if at least one is cheaper
4764
if (LHSNeg == 2 || RHSNeg == 2)
4765
return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4766
GetNegatedExpression(N0, DAG, LegalOperations),
4767
GetNegatedExpression(N1, DAG, LegalOperations));
4774
SDValue DAGCombiner::visitFREM(SDNode *N) {
4775
SDValue N0 = N->getOperand(0);
4776
SDValue N1 = N->getOperand(1);
4777
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4778
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4779
EVT VT = N->getValueType(0);
4781
// fold (frem c1, c2) -> fmod(c1,c2)
4782
if (N0CFP && N1CFP && VT != MVT::ppcf128)
4783
return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4788
SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4789
SDValue N0 = N->getOperand(0);
4790
SDValue N1 = N->getOperand(1);
4791
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4792
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4793
EVT VT = N->getValueType(0);
4795
if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4796
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4799
const APFloat& V = N1CFP->getValueAPF();
4800
// copysign(x, c1) -> fabs(x) iff ispos(c1)
4801
// copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4802
if (!V.isNegative()) {
4803
if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4804
return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4806
if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4807
return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4808
DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4812
// copysign(fabs(x), y) -> copysign(x, y)
4813
// copysign(fneg(x), y) -> copysign(x, y)
4814
// copysign(copysign(x,z), y) -> copysign(x, y)
4815
if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4816
N0.getOpcode() == ISD::FCOPYSIGN)
4817
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4818
N0.getOperand(0), N1);
4820
// copysign(x, abs(y)) -> abs(x)
4821
if (N1.getOpcode() == ISD::FABS)
4822
return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4824
// copysign(x, copysign(y,z)) -> copysign(x, z)
4825
if (N1.getOpcode() == ISD::FCOPYSIGN)
4826
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4827
N0, N1.getOperand(1));
4829
// copysign(x, fp_extend(y)) -> copysign(x, y)
4830
// copysign(x, fp_round(y)) -> copysign(x, y)
4831
if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4832
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4833
N0, N1.getOperand(0));
4838
SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4839
SDValue N0 = N->getOperand(0);
4840
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4841
EVT VT = N->getValueType(0);
4842
EVT OpVT = N0.getValueType();
4844
// fold (sint_to_fp c1) -> c1fp
4845
if (N0C && OpVT != MVT::ppcf128)
4846
return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4848
// If the input is a legal type, and SINT_TO_FP is not legal on this target,
4849
// but UINT_TO_FP is legal on this target, try to convert.
4850
if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4851
TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4852
// If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4853
if (DAG.SignBitIsZero(N0))
4854
return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4860
SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4861
SDValue N0 = N->getOperand(0);
4862
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4863
EVT VT = N->getValueType(0);
4864
EVT OpVT = N0.getValueType();
4866
// fold (uint_to_fp c1) -> c1fp
4867
if (N0C && OpVT != MVT::ppcf128)
4868
return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4870
// If the input is a legal type, and UINT_TO_FP is not legal on this target,
4871
// but SINT_TO_FP is legal on this target, try to convert.
4872
if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4873
TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4874
// If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4875
if (DAG.SignBitIsZero(N0))
4876
return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4882
SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4883
SDValue N0 = N->getOperand(0);
4884
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4885
EVT VT = N->getValueType(0);
4887
// fold (fp_to_sint c1fp) -> c1
4889
return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4894
SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4895
SDValue N0 = N->getOperand(0);
4896
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4897
EVT VT = N->getValueType(0);
4899
// fold (fp_to_uint c1fp) -> c1
4900
if (N0CFP && VT != MVT::ppcf128)
4901
return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4906
SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4907
SDValue N0 = N->getOperand(0);
4908
SDValue N1 = N->getOperand(1);
4909
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4910
EVT VT = N->getValueType(0);
4912
// fold (fp_round c1fp) -> c1fp
4913
if (N0CFP && N0.getValueType() != MVT::ppcf128)
4914
return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4916
// fold (fp_round (fp_extend x)) -> x
4917
if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4918
return N0.getOperand(0);
4920
// fold (fp_round (fp_round x)) -> (fp_round x)
4921
if (N0.getOpcode() == ISD::FP_ROUND) {
4922
// This is a value preserving truncation if both round's are.
4923
bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4924
N0.getNode()->getConstantOperandVal(1) == 1;
4925
return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4926
DAG.getIntPtrConstant(IsTrunc));
4929
// fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4930
if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4931
SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4932
N0.getOperand(0), N1);
4933
AddToWorkList(Tmp.getNode());
4934
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4935
Tmp, N0.getOperand(1));
4941
SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4942
SDValue N0 = N->getOperand(0);
4943
EVT VT = N->getValueType(0);
4944
EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4945
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4947
// fold (fp_round_inreg c1fp) -> c1fp
4948
if (N0CFP && isTypeLegal(EVT)) {
4949
SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4950
return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4956
SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4957
SDValue N0 = N->getOperand(0);
4958
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4959
EVT VT = N->getValueType(0);
4961
// If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4962
if (N->hasOneUse() &&
4963
N->use_begin()->getOpcode() == ISD::FP_ROUND)
4966
// fold (fp_extend c1fp) -> c1fp
4967
if (N0CFP && VT != MVT::ppcf128)
4968
return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4970
// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4972
if (N0.getOpcode() == ISD::FP_ROUND
4973
&& N0.getNode()->getConstantOperandVal(1) == 1) {
4974
SDValue In = N0.getOperand(0);
4975
if (In.getValueType() == VT) return In;
4976
if (VT.bitsLT(In.getValueType()))
4977
return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4978
In, N0.getOperand(1));
4979
return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4982
// fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4983
if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4984
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4985
TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4986
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4987
SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(),
4989
LN0->getBasePtr(), LN0->getSrcValue(),
4990
LN0->getSrcValueOffset(),
4992
LN0->isVolatile(), LN0->isNonTemporal(),
4993
LN0->getAlignment());
4994
CombineTo(N, ExtLoad);
4995
CombineTo(N0.getNode(),
4996
DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4997
N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4998
ExtLoad.getValue(1));
4999
return SDValue(N, 0); // Return N so it doesn't get rechecked!
5005
SDValue DAGCombiner::visitFNEG(SDNode *N) {
5006
SDValue N0 = N->getOperand(0);
5007
EVT VT = N->getValueType(0);
5009
if (isNegatibleForFree(N0, LegalOperations))
5010
return GetNegatedExpression(N0, DAG, LegalOperations);
5012
// Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5013
// constant pool values.
5014
if (N0.getOpcode() == ISD::BIT_CONVERT &&
5016
N0.getNode()->hasOneUse() &&
5017
N0.getOperand(0).getValueType().isInteger()) {
5018
SDValue Int = N0.getOperand(0);
5019
EVT IntVT = Int.getValueType();
5020
if (IntVT.isInteger() && !IntVT.isVector()) {
5021
Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5022
DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5023
AddToWorkList(Int.getNode());
5024
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
5032
SDValue DAGCombiner::visitFABS(SDNode *N) {
5033
SDValue N0 = N->getOperand(0);
5034
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5035
EVT VT = N->getValueType(0);
5037
// fold (fabs c1) -> fabs(c1)
5038
if (N0CFP && VT != MVT::ppcf128)
5039
return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5040
// fold (fabs (fabs x)) -> (fabs x)
5041
if (N0.getOpcode() == ISD::FABS)
5042
return N->getOperand(0);
5043
// fold (fabs (fneg x)) -> (fabs x)
5044
// fold (fabs (fcopysign x, y)) -> (fabs x)
5045
if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5046
return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5048
// Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5049
// constant pool values.
5050
if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
5051
N0.getOperand(0).getValueType().isInteger() &&
5052
!N0.getOperand(0).getValueType().isVector()) {
5053
SDValue Int = N0.getOperand(0);
5054
EVT IntVT = Int.getValueType();
5055
if (IntVT.isInteger() && !IntVT.isVector()) {
5056
Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5057
DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5058
AddToWorkList(Int.getNode());
5059
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
5060
N->getValueType(0), Int);
5067
SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5068
SDValue Chain = N->getOperand(0);
5069
SDValue N1 = N->getOperand(1);
5070
SDValue N2 = N->getOperand(2);
5072
// If N is a constant we could fold this into a fallthrough or unconditional
5073
// branch. However that doesn't happen very often in normal code, because
5074
// Instcombine/SimplifyCFG should have handled the available opportunities.
5075
// If we did this folding here, it would be necessary to update the
5076
// MachineBasicBlock CFG, which is awkward.
5078
// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5080
if (N1.getOpcode() == ISD::SETCC &&
5081
TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5082
return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5083
Chain, N1.getOperand(2),
5084
N1.getOperand(0), N1.getOperand(1), N2);
5088
if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) {
5089
// Look past truncate.
5090
Trunc = N1.getNode();
5091
N1 = N1.getOperand(0);
5094
if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) {
5095
// Match this pattern so that we can generate simpler code:
5098
// %b = and i32 %a, 2
5099
// %c = srl i32 %b, 1
5100
// brcond i32 %c ...
5105
// %b = and i32 %a, 2
5106
// %c = setcc eq %b, 0
5109
// This applies only when the AND constant value has one bit set and the
5110
// SRL constant is equal to the log2 of the AND constant. The back-end is
5111
// smart enough to convert the result into a TEST/JMP sequence.
5112
SDValue Op0 = N1.getOperand(0);
5113
SDValue Op1 = N1.getOperand(1);
5115
if (Op0.getOpcode() == ISD::AND &&
5116
Op1.getOpcode() == ISD::Constant) {
5117
SDValue AndOp1 = Op0.getOperand(1);
5119
if (AndOp1.getOpcode() == ISD::Constant) {
5120
const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5122
if (AndConst.isPowerOf2() &&
5123
cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5125
DAG.getSetCC(N->getDebugLoc(),
5126
TLI.getSetCCResultType(Op0.getValueType()),
5127
Op0, DAG.getConstant(0, Op0.getValueType()),
5130
SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5131
MVT::Other, Chain, SetCC, N2);
5132
// Don't add the new BRCond into the worklist or else SimplifySelectCC
5133
// will convert it back to (X & C1) >> C2.
5134
CombineTo(N, NewBRCond, false);
5135
// Truncate is dead.
5137
removeFromWorkList(Trunc);
5138
DAG.DeleteNode(Trunc);
5140
// Replace the uses of SRL with SETCC
5141
WorkListRemover DeadNodes(*this);
5142
DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5143
removeFromWorkList(N1.getNode());
5144
DAG.DeleteNode(N1.getNode());
5145
return SDValue(N, 0); // Return N so it doesn't get rechecked!
5151
// Transform br(xor(x, y)) -> br(x != y)
5152
// Transform br(xor(xor(x,y), 1)) -> br (x == y)
5153
if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5154
SDNode *TheXor = N1.getNode();
5155
SDValue Op0 = TheXor->getOperand(0);
5156
SDValue Op1 = TheXor->getOperand(1);
5157
if (Op0.getOpcode() == Op1.getOpcode()) {
5158
// Avoid missing important xor optimizations.
5159
SDValue Tmp = visitXOR(TheXor);
5160
if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5161
DEBUG(dbgs() << "\nReplacing.8 ";
5163
dbgs() << "\nWith: ";
5164
Tmp.getNode()->dump(&DAG);
5166
WorkListRemover DeadNodes(*this);
5167
DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5168
removeFromWorkList(TheXor);
5169
DAG.DeleteNode(TheXor);
5170
return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5171
MVT::Other, Chain, Tmp, N2);
5175
if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5177
if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5178
if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5179
Op0.getOpcode() == ISD::XOR) {
5180
TheXor = Op0.getNode();
5184
SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1;
5186
EVT SetCCVT = NodeToReplace.getValueType();
5188
SetCCVT = TLI.getSetCCResultType(SetCCVT);
5189
SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5192
Equal ? ISD::SETEQ : ISD::SETNE);
5193
// Replace the uses of XOR with SETCC
5194
WorkListRemover DeadNodes(*this);
5195
DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes);
5196
removeFromWorkList(NodeToReplace.getNode());
5197
DAG.DeleteNode(NodeToReplace.getNode());
5198
return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5199
MVT::Other, Chain, SetCC, N2);
5206
// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5208
SDValue DAGCombiner::visitBR_CC(SDNode *N) {
5209
CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5210
SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5212
// If N is a constant we could fold this into a fallthrough or unconditional
5213
// branch. However that doesn't happen very often in normal code, because
5214
// Instcombine/SimplifyCFG should have handled the available opportunities.
5215
// If we did this folding here, it would be necessary to update the
5216
// MachineBasicBlock CFG, which is awkward.
5218
// Use SimplifySetCC to simplify SETCC's.
5219
SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
5220
CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
5222
if (Simp.getNode()) AddToWorkList(Simp.getNode());
5224
// fold to a simpler setcc
5225
if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
5226
return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5227
N->getOperand(0), Simp.getOperand(2),
5228
Simp.getOperand(0), Simp.getOperand(1),
5234
/// CombineToPreIndexedLoadStore - Try turning a load / store into a
5235
/// pre-indexed load / store when the base pointer is an add or subtract
5236
/// and it has other uses besides the load / store. After the
5237
/// transformation, the new indexed load / store has effectively folded
5238
/// the add / subtract in and all of its other uses are redirected to the
5239
/// new load / store.
5240
bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
5241
if (!LegalOperations)
5247
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5248
if (LD->isIndexed())
5250
VT = LD->getMemoryVT();
5251
if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
5252
!TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
5254
Ptr = LD->getBasePtr();
5255
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5256
if (ST->isIndexed())
5258
VT = ST->getMemoryVT();
5259
if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
5260
!TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
5262
Ptr = ST->getBasePtr();
5268
// If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
5269
// out. There is no reason to make this a preinc/predec.
5270
if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
5271
Ptr.getNode()->hasOneUse())
5274
// Ask the target to do addressing mode selection.
5277
ISD::MemIndexedMode AM = ISD::UNINDEXED;
5278
if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5280
// Don't create a indexed load / store with zero offset.
5281
if (isa<ConstantSDNode>(Offset) &&
5282
cast<ConstantSDNode>(Offset)->isNullValue())
5285
// Try turning it into a pre-indexed load / store except when:
5286
// 1) The new base ptr is a frame index.
5287
// 2) If N is a store and the new base ptr is either the same as or is a
5288
// predecessor of the value being stored.
5289
// 3) Another use of old base ptr is a predecessor of N. If ptr is folded
5290
// that would create a cycle.
5291
// 4) All uses are load / store ops that use it as old base ptr.
5293
// Check #1. Preinc'ing a frame index would require copying the stack pointer
5294
// (plus the implicit offset) to a register to preinc anyway.
5295
if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5300
SDValue Val = cast<StoreSDNode>(N)->getValue();
5301
if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
5305
// Now check for #3 and #4.
5306
bool RealUse = false;
5307
for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5308
E = Ptr.getNode()->use_end(); I != E; ++I) {
5312
if (Use->isPredecessorOf(N))
5315
if (!((Use->getOpcode() == ISD::LOAD &&
5316
cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
5317
(Use->getOpcode() == ISD::STORE &&
5318
cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
5327
Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5328
BasePtr, Offset, AM);
5330
Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5331
BasePtr, Offset, AM);
5334
DEBUG(dbgs() << "\nReplacing.4 ";
5336
dbgs() << "\nWith: ";
5337
Result.getNode()->dump(&DAG);
5339
WorkListRemover DeadNodes(*this);
5341
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5343
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5346
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5350
// Finally, since the node is now dead, remove it from the graph.
5353
// Replace the uses of Ptr with uses of the updated base value.
5354
DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5356
removeFromWorkList(Ptr.getNode());
5357
DAG.DeleteNode(Ptr.getNode());
5362
/// CombineToPostIndexedLoadStore - Try to combine a load / store with a
5363
/// add / sub of the base pointer node into a post-indexed load / store.
5364
/// The transformation folded the add / subtract into the new indexed
5365
/// load / store effectively and all of its uses are redirected to the
5366
/// new load / store.
5367
bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
5368
if (!LegalOperations)
5374
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5375
if (LD->isIndexed())
5377
VT = LD->getMemoryVT();
5378
if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
5379
!TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
5381
Ptr = LD->getBasePtr();
5382
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5383
if (ST->isIndexed())
5385
VT = ST->getMemoryVT();
5386
if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
5387
!TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
5389
Ptr = ST->getBasePtr();
5395
if (Ptr.getNode()->hasOneUse())
5398
for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5399
E = Ptr.getNode()->use_end(); I != E; ++I) {
5402
(Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
5407
ISD::MemIndexedMode AM = ISD::UNINDEXED;
5408
if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
5409
// Don't create a indexed load / store with zero offset.
5410
if (isa<ConstantSDNode>(Offset) &&
5411
cast<ConstantSDNode>(Offset)->isNullValue())
5414
// Try turning it into a post-indexed load / store except when
5415
// 1) All uses are load / store ops that use it as base ptr.
5416
// 2) Op must be independent of N, i.e. Op is neither a predecessor
5417
// nor a successor of N. Otherwise, if Op is folded that would
5420
if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5424
bool TryNext = false;
5425
for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
5426
EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
5428
if (Use == Ptr.getNode())
5431
// If all the uses are load / store addresses, then don't do the
5433
if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
5434
bool RealUse = false;
5435
for (SDNode::use_iterator III = Use->use_begin(),
5436
EEE = Use->use_end(); III != EEE; ++III) {
5437
SDNode *UseUse = *III;
5438
if (!((UseUse->getOpcode() == ISD::LOAD &&
5439
cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
5440
(UseUse->getOpcode() == ISD::STORE &&
5441
cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
5456
if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
5457
SDValue Result = isLoad
5458
? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5459
BasePtr, Offset, AM)
5460
: DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5461
BasePtr, Offset, AM);
5464
DEBUG(dbgs() << "\nReplacing.5 ";
5466
dbgs() << "\nWith: ";
5467
Result.getNode()->dump(&DAG);
5469
WorkListRemover DeadNodes(*this);
5471
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5473
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5476
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5480
// Finally, since the node is now dead, remove it from the graph.
5483
// Replace the uses of Use with uses of the updated base value.
5484
DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
5485
Result.getValue(isLoad ? 1 : 0),
5487
removeFromWorkList(Op);
5497
SDValue DAGCombiner::visitLOAD(SDNode *N) {
5498
LoadSDNode *LD = cast<LoadSDNode>(N);
5499
SDValue Chain = LD->getChain();
5500
SDValue Ptr = LD->getBasePtr();
5502
// If load is not volatile and there are no uses of the loaded value (and
5503
// the updated indexed value in case of indexed loads), change uses of the
5504
// chain value into uses of the chain input (i.e. delete the dead load).
5505
if (!LD->isVolatile()) {
5506
if (N->getValueType(1) == MVT::Other) {
5508
if (N->hasNUsesOfValue(0, 0)) {
5509
// It's not safe to use the two value CombineTo variant here. e.g.
5510
// v1, chain2 = load chain1, loc
5511
// v2, chain3 = load chain2, loc
5513
// Now we replace use of chain2 with chain1. This makes the second load
5514
// isomorphic to the one we are deleting, and thus makes this load live.
5515
DEBUG(dbgs() << "\nReplacing.6 ";
5517
dbgs() << "\nWith chain: ";
5518
Chain.getNode()->dump(&DAG);
5520
WorkListRemover DeadNodes(*this);
5521
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
5523
if (N->use_empty()) {
5524
removeFromWorkList(N);
5528
return SDValue(N, 0); // Return N so it doesn't get rechecked!
5532
assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
5533
if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
5534
SDValue Undef = DAG.getUNDEF(N->getValueType(0));
5535
DEBUG(dbgs() << "\nReplacing.7 ";
5537
dbgs() << "\nWith: ";
5538
Undef.getNode()->dump(&DAG);
5539
dbgs() << " and 2 other values\n");
5540
WorkListRemover DeadNodes(*this);
5541
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
5542
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
5543
DAG.getUNDEF(N->getValueType(1)),
5545
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
5546
removeFromWorkList(N);
5548
return SDValue(N, 0); // Return N so it doesn't get rechecked!
5553
// If this load is directly stored, replace the load value with the stored
5555
// TODO: Handle store large -> read small portion.
5556
// TODO: Handle TRUNCSTORE/LOADEXT
5557
if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
5558
!LD->isVolatile()) {
5559
if (ISD::isNON_TRUNCStore(Chain.getNode())) {
5560
StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
5561
if (PrevST->getBasePtr() == Ptr &&
5562
PrevST->getValue().getValueType() == N->getValueType(0))
5563
return CombineTo(N, Chain.getOperand(1), Chain);
5567
// Try to infer better alignment information than the load already has.
5568
if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
5569
if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5570
if (Align > LD->getAlignment())
5571
return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
5573
Chain, Ptr, LD->getSrcValue(),
5574
LD->getSrcValueOffset(), LD->getMemoryVT(),
5575
LD->isVolatile(), LD->isNonTemporal(), Align);
5580
// Walk up chain skipping non-aliasing memory nodes.
5581
SDValue BetterChain = FindBetterChain(N, Chain);
5583
// If there is a better chain.
5584
if (Chain != BetterChain) {
5587
// Replace the chain to void dependency.
5588
if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
5589
ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
5591
LD->getSrcValue(), LD->getSrcValueOffset(),
5592
LD->isVolatile(), LD->isNonTemporal(),
5593
LD->getAlignment());
5595
ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
5597
BetterChain, Ptr, LD->getSrcValue(),
5598
LD->getSrcValueOffset(),
5601
LD->isNonTemporal(),
5602
LD->getAlignment());
5605
// Create token factor to keep old chain connected.
5606
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5607
MVT::Other, Chain, ReplLoad.getValue(1));
5609
// Make sure the new and old chains are cleaned up.
5610
AddToWorkList(Token.getNode());
5612
// Replace uses with load result and token factor. Don't add users
5614
return CombineTo(N, ReplLoad.getValue(0), Token, false);
5618
// Try transforming N to an indexed load.
5619
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5620
return SDValue(N, 0);
5625
/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
5626
/// load is having specific bytes cleared out. If so, return the byte size
5627
/// being masked out and the shift amount.
5628
static std::pair<unsigned, unsigned>
5629
CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
5630
std::pair<unsigned, unsigned> Result(0, 0);
5632
// Check for the structure we're looking for.
5633
if (V->getOpcode() != ISD::AND ||
5634
!isa<ConstantSDNode>(V->getOperand(1)) ||
5635
!ISD::isNormalLoad(V->getOperand(0).getNode()))
5638
// Check the chain and pointer.
5639
LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
5640
if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
5642
// The store should be chained directly to the load or be an operand of a
5644
if (LD == Chain.getNode())
5646
else if (Chain->getOpcode() != ISD::TokenFactor)
5647
return Result; // Fail.
5650
for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
5651
if (Chain->getOperand(i).getNode() == LD) {
5655
if (!isOk) return Result;
5658
// This only handles simple types.
5659
if (V.getValueType() != MVT::i16 &&
5660
V.getValueType() != MVT::i32 &&
5661
V.getValueType() != MVT::i64)
5664
// Check the constant mask. Invert it so that the bits being masked out are
5665
// 0 and the bits being kept are 1. Use getSExtValue so that leading bits
5666
// follow the sign bit for uniformity.
5667
uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
5668
unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
5669
if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
5670
unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
5671
if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
5672
if (NotMaskLZ == 64) return Result; // All zero mask.
5674
// See if we have a continuous run of bits. If so, we have 0*1+0*
5675
if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
5678
// Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
5679
if (V.getValueType() != MVT::i64 && NotMaskLZ)
5680
NotMaskLZ -= 64-V.getValueSizeInBits();
5682
unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
5683
switch (MaskedBytes) {
5687
default: return Result; // All one mask, or 5-byte mask.
5690
// Verify that the first bit starts at a multiple of mask so that the access
5691
// is aligned the same as the access width.
5692
if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
5694
Result.first = MaskedBytes;
5695
Result.second = NotMaskTZ/8;
5700
/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
5701
/// provides a value as specified by MaskInfo. If so, replace the specified
5702
/// store with a narrower store of truncated IVal.
5704
ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
5705
SDValue IVal, StoreSDNode *St,
5707
unsigned NumBytes = MaskInfo.first;
5708
unsigned ByteShift = MaskInfo.second;
5709
SelectionDAG &DAG = DC->getDAG();
5711
// Check to see if IVal is all zeros in the part being masked in by the 'or'
5712
// that uses this. If not, this is not a replacement.
5713
APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
5714
ByteShift*8, (ByteShift+NumBytes)*8);
5715
if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
5717
// Check that it is legal on the target to do this. It is legal if the new
5718
// VT we're shrinking to (i8/i16/i32) is legal or we're still before type
5720
MVT VT = MVT::getIntegerVT(NumBytes*8);
5721
if (!DC->isTypeLegal(VT))
5724
// Okay, we can do this! Replace the 'St' store with a store of IVal that is
5725
// shifted by ByteShift and truncated down to NumBytes.
5727
IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
5728
DAG.getConstant(ByteShift*8, DC->getShiftAmountTy()));
5730
// Figure out the offset for the store and the alignment of the access.
5732
unsigned NewAlign = St->getAlignment();
5734
if (DAG.getTargetLoweringInfo().isLittleEndian())
5735
StOffset = ByteShift;
5737
StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
5739
SDValue Ptr = St->getBasePtr();
5741
Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
5742
Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
5743
NewAlign = MinAlign(NewAlign, StOffset);
5746
// Truncate down to the new size.
5747
IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
5750
return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
5751
St->getSrcValue(), St->getSrcValueOffset()+StOffset,
5752
false, false, NewAlign).getNode();
5756
/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
5757
/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
5758
/// of the loaded bits, try narrowing the load and store if it would end up
5759
/// being a win for performance or code size.
5760
SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
5761
StoreSDNode *ST = cast<StoreSDNode>(N);
5762
if (ST->isVolatile())
5765
SDValue Chain = ST->getChain();
5766
SDValue Value = ST->getValue();
5767
SDValue Ptr = ST->getBasePtr();
5768
EVT VT = Value.getValueType();
5770
if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
5773
unsigned Opc = Value.getOpcode();
5775
// If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
5776
// is a byte mask indicating a consecutive number of bytes, check to see if
5777
// Y is known to provide just those bytes. If so, we try to replace the
5778
// load + replace + store sequence with a single (narrower) store, which makes
5780
if (Opc == ISD::OR) {
5781
std::pair<unsigned, unsigned> MaskedLoad;
5782
MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
5783
if (MaskedLoad.first)
5784
if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5785
Value.getOperand(1), ST,this))
5786
return SDValue(NewST, 0);
5788
// Or is commutative, so try swapping X and Y.
5789
MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
5790
if (MaskedLoad.first)
5791
if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5792
Value.getOperand(0), ST,this))
5793
return SDValue(NewST, 0);
5796
if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
5797
Value.getOperand(1).getOpcode() != ISD::Constant)
5800
SDValue N0 = Value.getOperand(0);
5801
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5802
Chain == SDValue(N0.getNode(), 1)) {
5803
LoadSDNode *LD = cast<LoadSDNode>(N0);
5804
if (LD->getBasePtr() != Ptr)
5807
// Find the type to narrow it the load / op / store to.
5808
SDValue N1 = Value.getOperand(1);
5809
unsigned BitWidth = N1.getValueSizeInBits();
5810
APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
5811
if (Opc == ISD::AND)
5812
Imm ^= APInt::getAllOnesValue(BitWidth);
5813
if (Imm == 0 || Imm.isAllOnesValue())
5815
unsigned ShAmt = Imm.countTrailingZeros();
5816
unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
5817
unsigned NewBW = NextPowerOf2(MSB - ShAmt);
5818
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5819
while (NewBW < BitWidth &&
5820
!(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
5821
TLI.isNarrowingProfitable(VT, NewVT))) {
5822
NewBW = NextPowerOf2(NewBW);
5823
NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5825
if (NewBW >= BitWidth)
5828
// If the lsb changed does not start at the type bitwidth boundary,
5829
// start at the previous one.
5831
ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
5832
APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
5833
if ((Imm & Mask) == Imm) {
5834
APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
5835
if (Opc == ISD::AND)
5836
NewImm ^= APInt::getAllOnesValue(NewBW);
5837
uint64_t PtrOff = ShAmt / 8;
5838
// For big endian targets, we need to adjust the offset to the pointer to
5839
// load the correct bytes.
5840
if (TLI.isBigEndian())
5841
PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
5843
unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
5844
const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
5845
if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
5848
SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
5849
Ptr.getValueType(), Ptr,
5850
DAG.getConstant(PtrOff, Ptr.getValueType()));
5851
SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
5852
LD->getChain(), NewPtr,
5853
LD->getSrcValue(), LD->getSrcValueOffset(),
5854
LD->isVolatile(), LD->isNonTemporal(),
5856
SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
5857
DAG.getConstant(NewImm, NewVT));
5858
SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
5860
ST->getSrcValue(), ST->getSrcValueOffset(),
5861
false, false, NewAlign);
5863
AddToWorkList(NewPtr.getNode());
5864
AddToWorkList(NewLD.getNode());
5865
AddToWorkList(NewVal.getNode());
5866
WorkListRemover DeadNodes(*this);
5867
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
5877
SDValue DAGCombiner::visitSTORE(SDNode *N) {
5878
StoreSDNode *ST = cast<StoreSDNode>(N);
5879
SDValue Chain = ST->getChain();
5880
SDValue Value = ST->getValue();
5881
SDValue Ptr = ST->getBasePtr();
5883
// If this is a store of a bit convert, store the input value if the
5884
// resultant store does not need a higher alignment than the original.
5885
if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
5886
ST->isUnindexed()) {
5887
unsigned OrigAlign = ST->getAlignment();
5888
EVT SVT = Value.getOperand(0).getValueType();
5889
unsigned Align = TLI.getTargetData()->
5890
getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
5891
if (Align <= OrigAlign &&
5892
((!LegalOperations && !ST->isVolatile()) ||
5893
TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
5894
return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5895
Ptr, ST->getSrcValue(),
5896
ST->getSrcValueOffset(), ST->isVolatile(),
5897
ST->isNonTemporal(), OrigAlign);
5900
// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
5901
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
5902
// NOTE: If the original store is volatile, this transform must not increase
5903
// the number of stores. For example, on x86-32 an f64 can be stored in one
5904
// processor operation but an i64 (which is not legal) requires two. So the
5905
// transform should not be done in this case.
5906
if (Value.getOpcode() != ISD::TargetConstantFP) {
5908
switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
5909
default: llvm_unreachable("Unknown FP type");
5910
case MVT::f80: // We don't do this for these yet.
5915
if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
5916
TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5917
Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
5918
bitcastToAPInt().getZExtValue(), MVT::i32);
5919
return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5920
Ptr, ST->getSrcValue(),
5921
ST->getSrcValueOffset(), ST->isVolatile(),
5922
ST->isNonTemporal(), ST->getAlignment());
5926
if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
5927
!ST->isVolatile()) ||
5928
TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
5929
Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
5930
getZExtValue(), MVT::i64);
5931
return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5932
Ptr, ST->getSrcValue(),
5933
ST->getSrcValueOffset(), ST->isVolatile(),
5934
ST->isNonTemporal(), ST->getAlignment());
5935
} else if (!ST->isVolatile() &&
5936
TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5937
// Many FP stores are not made apparent until after legalize, e.g. for
5938
// argument passing. Since this is so common, custom legalize the
5939
// 64-bit integer store into two 32-bit stores.
5940
uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
5941
SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
5942
SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
5943
if (TLI.isBigEndian()) std::swap(Lo, Hi);
5945
int SVOffset = ST->getSrcValueOffset();
5946
unsigned Alignment = ST->getAlignment();
5947
bool isVolatile = ST->isVolatile();
5948
bool isNonTemporal = ST->isNonTemporal();
5950
SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
5951
Ptr, ST->getSrcValue(),
5952
ST->getSrcValueOffset(),
5953
isVolatile, isNonTemporal,
5954
ST->getAlignment());
5955
Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
5956
DAG.getConstant(4, Ptr.getValueType()));
5958
Alignment = MinAlign(Alignment, 4U);
5959
SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
5960
Ptr, ST->getSrcValue(),
5961
SVOffset, isVolatile, isNonTemporal,
5963
return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
5972
// Try to infer better alignment information than the store already has.
5973
if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
5974
if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5975
if (Align > ST->getAlignment())
5976
return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
5977
Ptr, ST->getSrcValue(),
5978
ST->getSrcValueOffset(), ST->getMemoryVT(),
5979
ST->isVolatile(), ST->isNonTemporal(), Align);
5984
// Walk up chain skipping non-aliasing memory nodes.
5985
SDValue BetterChain = FindBetterChain(N, Chain);
5987
// If there is a better chain.
5988
if (Chain != BetterChain) {
5991
// Replace the chain to avoid dependency.
5992
if (ST->isTruncatingStore()) {
5993
ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5994
ST->getSrcValue(),ST->getSrcValueOffset(),
5995
ST->getMemoryVT(), ST->isVolatile(),
5996
ST->isNonTemporal(), ST->getAlignment());
5998
ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5999
ST->getSrcValue(), ST->getSrcValueOffset(),
6000
ST->isVolatile(), ST->isNonTemporal(),
6001
ST->getAlignment());
6004
// Create token to keep both nodes around.
6005
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6006
MVT::Other, Chain, ReplStore);
6008
// Make sure the new and old chains are cleaned up.
6009
AddToWorkList(Token.getNode());
6011
// Don't add users to work list.
6012
return CombineTo(N, Token, false);
6016
// Try transforming N to an indexed store.
6017
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6018
return SDValue(N, 0);
6020
// FIXME: is there such a thing as a truncating indexed store?
6021
if (ST->isTruncatingStore() && ST->isUnindexed() &&
6022
Value.getValueType().isInteger()) {
6023
// See if we can simplify the input to this truncstore with knowledge that
6024
// only the low bits are being used. For example:
6025
// "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
6027
GetDemandedBits(Value,
6028
APInt::getLowBitsSet(Value.getValueSizeInBits(),
6029
ST->getMemoryVT().getSizeInBits()));
6030
AddToWorkList(Value.getNode());
6031
if (Shorter.getNode())
6032
return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
6033
Ptr, ST->getSrcValue(),
6034
ST->getSrcValueOffset(), ST->getMemoryVT(),
6035
ST->isVolatile(), ST->isNonTemporal(),
6036
ST->getAlignment());
6038
// Otherwise, see if we can simplify the operation with
6039
// SimplifyDemandedBits, which only works if the value has a single use.
6040
if (SimplifyDemandedBits(Value,
6041
APInt::getLowBitsSet(
6042
Value.getValueType().getScalarType().getSizeInBits(),
6043
ST->getMemoryVT().getScalarType().getSizeInBits())))
6044
return SDValue(N, 0);
6047
// If this is a load followed by a store to the same location, then the store
6049
if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6050
if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6051
ST->isUnindexed() && !ST->isVolatile() &&
6052
// There can't be any side effects between the load and store, such as
6054
Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6055
// The store is dead, remove it.
6060
// If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6061
// truncating store. We can do this even if this is already a truncstore.
6062
if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6063
&& Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6064
TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6065
ST->getMemoryVT())) {
6066
return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6067
Ptr, ST->getSrcValue(),
6068
ST->getSrcValueOffset(), ST->getMemoryVT(),
6069
ST->isVolatile(), ST->isNonTemporal(),
6070
ST->getAlignment());
6073
return ReduceLoadOpStoreWidth(N);
6076
SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6077
SDValue InVec = N->getOperand(0);
6078
SDValue InVal = N->getOperand(1);
6079
SDValue EltNo = N->getOperand(2);
6081
// If the inserted element is an UNDEF, just use the input vector.
6082
if (InVal.getOpcode() == ISD::UNDEF)
6085
// If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
6086
// vector with the inserted element.
6087
if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
6088
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6089
SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
6090
InVec.getNode()->op_end());
6091
if (Elt < Ops.size())
6093
return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6094
InVec.getValueType(), &Ops[0], Ops.size());
6096
// If the invec is an UNDEF and if EltNo is a constant, create a new
6097
// BUILD_VECTOR with undef elements and the inserted element.
6098
if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
6099
isa<ConstantSDNode>(EltNo)) {
6100
EVT VT = InVec.getValueType();
6101
EVT EltVT = VT.getVectorElementType();
6102
unsigned NElts = VT.getVectorNumElements();
6103
SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
6105
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6106
if (Elt < Ops.size())
6108
return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6109
InVec.getValueType(), &Ops[0], Ops.size());
6114
SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
6115
// (vextract (scalar_to_vector val, 0) -> val
6116
SDValue InVec = N->getOperand(0);
6118
if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6119
// Check if the result type doesn't match the inserted element type. A
6120
// SCALAR_TO_VECTOR may truncate the inserted element and the
6121
// EXTRACT_VECTOR_ELT may widen the extracted vector.
6122
SDValue InOp = InVec.getOperand(0);
6123
EVT NVT = N->getValueType(0);
6124
if (InOp.getValueType() != NVT) {
6125
assert(InOp.getValueType().isInteger() && NVT.isInteger());
6126
return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
6131
// Perform only after legalization to ensure build_vector / vector_shuffle
6132
// optimizations have already been done.
6133
if (!LegalOperations) return SDValue();
6135
// (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
6136
// (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
6137
// (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
6138
SDValue EltNo = N->getOperand(1);
6140
if (isa<ConstantSDNode>(EltNo)) {
6141
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6142
bool NewLoad = false;
6143
bool BCNumEltsChanged = false;
6144
EVT VT = InVec.getValueType();
6145
EVT ExtVT = VT.getVectorElementType();
6148
if (InVec.getOpcode() == ISD::BIT_CONVERT) {
6149
EVT BCVT = InVec.getOperand(0).getValueType();
6150
if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6152
if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
6153
BCNumEltsChanged = true;
6154
InVec = InVec.getOperand(0);
6155
ExtVT = BCVT.getVectorElementType();
6159
LoadSDNode *LN0 = NULL;
6160
const ShuffleVectorSDNode *SVN = NULL;
6161
if (ISD::isNormalLoad(InVec.getNode())) {
6162
LN0 = cast<LoadSDNode>(InVec);
6163
} else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6164
InVec.getOperand(0).getValueType() == ExtVT &&
6165
ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
6166
LN0 = cast<LoadSDNode>(InVec.getOperand(0));
6167
} else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
6168
// (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
6170
// (load $addr+1*size)
6172
// If the bit convert changed the number of elements, it is unsafe
6173
// to examine the mask.
6174
if (BCNumEltsChanged)
6177
// Select the input vector, guarding against out of range extract vector.
6178
unsigned NumElems = VT.getVectorNumElements();
6179
int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt);
6180
InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
6182
if (InVec.getOpcode() == ISD::BIT_CONVERT)
6183
InVec = InVec.getOperand(0);
6184
if (ISD::isNormalLoad(InVec.getNode())) {
6185
LN0 = cast<LoadSDNode>(InVec);
6186
Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
6190
if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
6193
unsigned Align = LN0->getAlignment();
6195
// Check the resultant load doesn't need a higher alignment than the
6198
TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
6200
if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
6206
SDValue NewPtr = LN0->getBasePtr();
6208
unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
6209
EVT PtrType = NewPtr.getValueType();
6210
if (TLI.isBigEndian())
6211
PtrOff = VT.getSizeInBits() / 8 - PtrOff;
6212
NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
6213
DAG.getConstant(PtrOff, PtrType));
6216
return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
6217
LN0->getSrcValue(), LN0->getSrcValueOffset(),
6218
LN0->isVolatile(), LN0->isNonTemporal(), Align);
6224
SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
6225
unsigned NumInScalars = N->getNumOperands();
6226
EVT VT = N->getValueType(0);
6228
// Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
6229
// operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
6230
// at most two distinct vectors, turn this into a shuffle node.
6231
SDValue VecIn1, VecIn2;
6232
for (unsigned i = 0; i != NumInScalars; ++i) {
6233
// Ignore undef inputs.
6234
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6236
// If this input is something other than a EXTRACT_VECTOR_ELT with a
6237
// constant index, bail out.
6238
if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6239
!isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
6240
VecIn1 = VecIn2 = SDValue(0, 0);
6244
// If the input vector type disagrees with the result of the build_vector,
6245
// we can't make a shuffle.
6246
SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
6247
if (ExtractedFromVec.getValueType() != VT) {
6248
VecIn1 = VecIn2 = SDValue(0, 0);
6252
// Otherwise, remember this. We allow up to two distinct input vectors.
6253
if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
6256
if (VecIn1.getNode() == 0) {
6257
VecIn1 = ExtractedFromVec;
6258
} else if (VecIn2.getNode() == 0) {
6259
VecIn2 = ExtractedFromVec;
6262
VecIn1 = VecIn2 = SDValue(0, 0);
6267
// If everything is good, we can make a shuffle operation.
6268
if (VecIn1.getNode()) {
6269
SmallVector<int, 8> Mask;
6270
for (unsigned i = 0; i != NumInScalars; ++i) {
6271
if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
6276
// If extracting from the first vector, just use the index directly.
6277
SDValue Extract = N->getOperand(i);
6278
SDValue ExtVal = Extract.getOperand(1);
6279
if (Extract.getOperand(0) == VecIn1) {
6280
unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6281
if (ExtIndex > VT.getVectorNumElements())
6284
Mask.push_back(ExtIndex);
6288
// Otherwise, use InIdx + VecSize
6289
unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6290
Mask.push_back(Idx+NumInScalars);
6293
// Add count and size info.
6294
if (!isTypeLegal(VT))
6297
// Return the new VECTOR_SHUFFLE node.
6300
Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6301
return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
6307
SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
6308
// TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
6309
// EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
6310
// inputs come from at most two distinct vectors, turn this into a shuffle
6313
// If we only have one input vector, we don't need to do any concatenation.
6314
if (N->getNumOperands() == 1)
6315
return N->getOperand(0);
6320
SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
6321
EVT VT = N->getValueType(0);
6322
unsigned NumElts = VT.getVectorNumElements();
6324
SDValue N0 = N->getOperand(0);
6326
assert(N0.getValueType().getVectorNumElements() == NumElts &&
6327
"Vector shuffle must be normalized in DAG");
6329
// FIXME: implement canonicalizations from DAG.getVectorShuffle()
6331
// If it is a splat, check if the argument vector is a build_vector with
6332
// all scalar elements the same.
6333
if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
6334
SDNode *V = N0.getNode();
6336
// If this is a bit convert that changes the element type of the vector but
6337
// not the number of vector elements, look through it. Be careful not to
6338
// look though conversions that change things like v4f32 to v2f64.
6339
if (V->getOpcode() == ISD::BIT_CONVERT) {
6340
SDValue ConvInput = V->getOperand(0);
6341
if (ConvInput.getValueType().isVector() &&
6342
ConvInput.getValueType().getVectorNumElements() == NumElts)
6343
V = ConvInput.getNode();
6346
if (V->getOpcode() == ISD::BUILD_VECTOR) {
6347
unsigned NumElems = V->getNumOperands();
6348
unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
6349
if (NumElems > BaseIdx) {
6351
bool AllSame = true;
6352
for (unsigned i = 0; i != NumElems; ++i) {
6353
if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
6354
Base = V->getOperand(i);
6358
// Splat of <u, u, u, u>, return <u, u, u, u>
6359
if (!Base.getNode())
6361
for (unsigned i = 0; i != NumElems; ++i) {
6362
if (V->getOperand(i) != Base) {
6367
// Splat of <x, x, x, x>, return <x, x, x, x>
6376
SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
6377
if (!TLI.getShouldFoldAtomicFences())
6380
SDValue atomic = N->getOperand(0);
6381
switch (atomic.getOpcode()) {
6382
case ISD::ATOMIC_CMP_SWAP:
6383
case ISD::ATOMIC_SWAP:
6384
case ISD::ATOMIC_LOAD_ADD:
6385
case ISD::ATOMIC_LOAD_SUB:
6386
case ISD::ATOMIC_LOAD_AND:
6387
case ISD::ATOMIC_LOAD_OR:
6388
case ISD::ATOMIC_LOAD_XOR:
6389
case ISD::ATOMIC_LOAD_NAND:
6390
case ISD::ATOMIC_LOAD_MIN:
6391
case ISD::ATOMIC_LOAD_MAX:
6392
case ISD::ATOMIC_LOAD_UMIN:
6393
case ISD::ATOMIC_LOAD_UMAX:
6399
SDValue fence = atomic.getOperand(0);
6400
if (fence.getOpcode() != ISD::MEMBARRIER)
6403
switch (atomic.getOpcode()) {
6404
case ISD::ATOMIC_CMP_SWAP:
6405
return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6406
fence.getOperand(0),
6407
atomic.getOperand(1), atomic.getOperand(2),
6408
atomic.getOperand(3)), atomic.getResNo());
6409
case ISD::ATOMIC_SWAP:
6410
case ISD::ATOMIC_LOAD_ADD:
6411
case ISD::ATOMIC_LOAD_SUB:
6412
case ISD::ATOMIC_LOAD_AND:
6413
case ISD::ATOMIC_LOAD_OR:
6414
case ISD::ATOMIC_LOAD_XOR:
6415
case ISD::ATOMIC_LOAD_NAND:
6416
case ISD::ATOMIC_LOAD_MIN:
6417
case ISD::ATOMIC_LOAD_MAX:
6418
case ISD::ATOMIC_LOAD_UMIN:
6419
case ISD::ATOMIC_LOAD_UMAX:
6420
return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6421
fence.getOperand(0),
6422
atomic.getOperand(1), atomic.getOperand(2)),
6429
/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
6430
/// an AND to a vector_shuffle with the destination vector and a zero vector.
6431
/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
6432
/// vector_shuffle V, Zero, <0, 4, 2, 4>
6433
SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
6434
EVT VT = N->getValueType(0);
6435
DebugLoc dl = N->getDebugLoc();
6436
SDValue LHS = N->getOperand(0);
6437
SDValue RHS = N->getOperand(1);
6438
if (N->getOpcode() == ISD::AND) {
6439
if (RHS.getOpcode() == ISD::BIT_CONVERT)
6440
RHS = RHS.getOperand(0);
6441
if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
6442
SmallVector<int, 8> Indices;
6443
unsigned NumElts = RHS.getNumOperands();
6444
for (unsigned i = 0; i != NumElts; ++i) {
6445
SDValue Elt = RHS.getOperand(i);
6446
if (!isa<ConstantSDNode>(Elt))
6448
else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
6449
Indices.push_back(i);
6450
else if (cast<ConstantSDNode>(Elt)->isNullValue())
6451
Indices.push_back(NumElts);
6456
// Let's see if the target supports this vector_shuffle.
6457
EVT RVT = RHS.getValueType();
6458
if (!TLI.isVectorClearMaskLegal(Indices, RVT))
6461
// Return the new VECTOR_SHUFFLE node.
6462
EVT EltVT = RVT.getVectorElementType();
6463
SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
6464
DAG.getConstant(0, EltVT));
6465
SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6466
RVT, &ZeroOps[0], ZeroOps.size());
6467
LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
6468
SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
6469
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
6476
/// SimplifyVBinOp - Visit a binary vector operation, like ADD.
6477
SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
6478
// After legalize, the target may be depending on adds and other
6479
// binary ops to provide legal ways to construct constants or other
6480
// things. Simplifying them may result in a loss of legality.
6481
if (LegalOperations) return SDValue();
6483
EVT VT = N->getValueType(0);
6484
assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
6486
EVT EltType = VT.getVectorElementType();
6487
SDValue LHS = N->getOperand(0);
6488
SDValue RHS = N->getOperand(1);
6489
SDValue Shuffle = XformToShuffleWithZero(N);
6490
if (Shuffle.getNode()) return Shuffle;
6492
// If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
6494
if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
6495
RHS.getOpcode() == ISD::BUILD_VECTOR) {
6496
SmallVector<SDValue, 8> Ops;
6497
for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
6498
SDValue LHSOp = LHS.getOperand(i);
6499
SDValue RHSOp = RHS.getOperand(i);
6500
// If these two elements can't be folded, bail out.
6501
if ((LHSOp.getOpcode() != ISD::UNDEF &&
6502
LHSOp.getOpcode() != ISD::Constant &&
6503
LHSOp.getOpcode() != ISD::ConstantFP) ||
6504
(RHSOp.getOpcode() != ISD::UNDEF &&
6505
RHSOp.getOpcode() != ISD::Constant &&
6506
RHSOp.getOpcode() != ISD::ConstantFP))
6509
// Can't fold divide by zero.
6510
if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
6511
N->getOpcode() == ISD::FDIV) {
6512
if ((RHSOp.getOpcode() == ISD::Constant &&
6513
cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
6514
(RHSOp.getOpcode() == ISD::ConstantFP &&
6515
cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
6519
// If the vector element type is not legal, the BUILD_VECTOR operands
6520
// are promoted and implicitly truncated. Make that explicit here.
6521
if (LHSOp.getValueType() != EltType)
6522
LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp);
6523
if (RHSOp.getValueType() != EltType)
6524
RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp);
6526
SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType,
6528
if (FoldOp.getOpcode() != ISD::UNDEF &&
6529
FoldOp.getOpcode() != ISD::Constant &&
6530
FoldOp.getOpcode() != ISD::ConstantFP)
6532
Ops.push_back(FoldOp);
6533
AddToWorkList(FoldOp.getNode());
6536
if (Ops.size() == LHS.getNumOperands()) {
6537
EVT VT = LHS.getValueType();
6538
return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
6539
&Ops[0], Ops.size());
6546
SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
6547
SDValue N1, SDValue N2){
6548
assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
6550
SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
6551
cast<CondCodeSDNode>(N0.getOperand(2))->get());
6553
// If we got a simplified select_cc node back from SimplifySelectCC, then
6554
// break it down into a new SETCC node, and a new SELECT node, and then return
6555
// the SELECT node, since we were called with a SELECT node.
6556
if (SCC.getNode()) {
6557
// Check to see if we got a select_cc back (to turn into setcc/select).
6558
// Otherwise, just return whatever node we got back, like fabs.
6559
if (SCC.getOpcode() == ISD::SELECT_CC) {
6560
SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
6562
SCC.getOperand(0), SCC.getOperand(1),
6564
AddToWorkList(SETCC.getNode());
6565
return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
6566
SCC.getOperand(2), SCC.getOperand(3), SETCC);
6574
/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
6575
/// are the two values being selected between, see if we can simplify the
6576
/// select. Callers of this should assume that TheSelect is deleted if this
6577
/// returns true. As such, they should return the appropriate thing (e.g. the
6578
/// node) back to the top-level of the DAG combiner loop to avoid it being
6580
bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
6583
// If this is a select from two identical things, try to pull the operation
6584
// through the select.
6585
if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
6586
// If this is a load and the token chain is identical, replace the select
6587
// of two loads with a load through a select of the address to load from.
6588
// This triggers in things like "select bool X, 10.0, 123.0" after the FP
6589
// constants have been dropped into the constant pool.
6590
if (LHS.getOpcode() == ISD::LOAD &&
6591
// Do not let this transformation reduce the number of volatile loads.
6592
!cast<LoadSDNode>(LHS)->isVolatile() &&
6593
!cast<LoadSDNode>(RHS)->isVolatile() &&
6594
// Token chains must be identical.
6595
LHS.getOperand(0) == RHS.getOperand(0)) {
6596
LoadSDNode *LLD = cast<LoadSDNode>(LHS);
6597
LoadSDNode *RLD = cast<LoadSDNode>(RHS);
6599
// If this is an EXTLOAD, the VT's must match.
6600
if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
6601
// FIXME: this discards src value information. This is
6602
// over-conservative. It would be beneficial to be able to remember
6603
// both potential memory locations. Since we are discarding
6604
// src value info, don't do the transformation if the memory
6605
// locations are not in the default address space.
6606
unsigned LLDAddrSpace = 0, RLDAddrSpace = 0;
6607
if (const Value *LLDVal = LLD->getMemOperand()->getValue()) {
6608
if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType()))
6609
LLDAddrSpace = PT->getAddressSpace();
6611
if (const Value *RLDVal = RLD->getMemOperand()->getValue()) {
6612
if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType()))
6613
RLDAddrSpace = PT->getAddressSpace();
6616
if (LLDAddrSpace == 0 && RLDAddrSpace == 0) {
6617
if (TheSelect->getOpcode() == ISD::SELECT) {
6618
// Check that the condition doesn't reach either load. If so, folding
6619
// this will induce a cycle into the DAG.
6620
if ((!LLD->hasAnyUseOfValue(1) ||
6621
!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) &&
6622
(!RLD->hasAnyUseOfValue(1) ||
6623
!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) {
6624
Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
6625
LLD->getBasePtr().getValueType(),
6626
TheSelect->getOperand(0), LLD->getBasePtr(),
6630
// Check that the condition doesn't reach either load. If so, folding
6631
// this will induce a cycle into the DAG.
6632
if ((!LLD->hasAnyUseOfValue(1) ||
6633
(!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
6634
!LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) &&
6635
(!RLD->hasAnyUseOfValue(1) ||
6636
(!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
6637
!RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) {
6638
Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
6639
LLD->getBasePtr().getValueType(),
6640
TheSelect->getOperand(0),
6641
TheSelect->getOperand(1),
6642
LLD->getBasePtr(), RLD->getBasePtr(),
6643
TheSelect->getOperand(4));
6648
if (Addr.getNode()) {
6650
if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
6651
Load = DAG.getLoad(TheSelect->getValueType(0),
6652
TheSelect->getDebugLoc(),
6656
LLD->isNonTemporal(),
6657
LLD->getAlignment());
6659
Load = DAG.getExtLoad(LLD->getExtensionType(),
6660
TheSelect->getValueType(0),
6661
TheSelect->getDebugLoc(),
6662
LLD->getChain(), Addr, 0, 0,
6665
LLD->isNonTemporal(),
6666
LLD->getAlignment());
6669
// Users of the select now use the result of the load.
6670
CombineTo(TheSelect, Load);
6672
// Users of the old loads now use the new load's chain. We know the
6673
// old-load value is dead now.
6674
CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
6675
CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
6685
/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
6686
/// where 'cond' is the comparison specified by CC.
6687
SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
6688
SDValue N2, SDValue N3,
6689
ISD::CondCode CC, bool NotExtCompare) {
6690
// (x ? y : y) -> y.
6691
if (N2 == N3) return N2;
6693
EVT VT = N2.getValueType();
6694
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
6695
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
6696
ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
6698
// Determine if the condition we're dealing with is constant
6699
SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
6700
N0, N1, CC, DL, false);
6701
if (SCC.getNode()) AddToWorkList(SCC.getNode());
6702
ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
6704
// fold select_cc true, x, y -> x
6705
if (SCCC && !SCCC->isNullValue())
6707
// fold select_cc false, x, y -> y
6708
if (SCCC && SCCC->isNullValue())
6711
// Check to see if we can simplify the select into an fabs node
6712
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
6713
// Allow either -0.0 or 0.0
6714
if (CFP->getValueAPF().isZero()) {
6715
// select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
6716
if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
6717
N0 == N2 && N3.getOpcode() == ISD::FNEG &&
6718
N2 == N3.getOperand(0))
6719
return DAG.getNode(ISD::FABS, DL, VT, N0);
6721
// select (setl[te] X, +/-0.0), fneg(X), X -> fabs
6722
if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
6723
N0 == N3 && N2.getOpcode() == ISD::FNEG &&
6724
N2.getOperand(0) == N3)
6725
return DAG.getNode(ISD::FABS, DL, VT, N3);
6729
// Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
6730
// where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
6731
// in it. This is a win when the constant is not otherwise available because
6732
// it replaces two constant pool loads with one. We only do this if the FP
6733
// type is known to be legal, because if it isn't, then we are before legalize
6734
// types an we want the other legalization to happen first (e.g. to avoid
6735
// messing with soft float) and if the ConstantFP is not legal, because if
6736
// it is legal, we may not need to store the FP constant in a constant pool.
6737
if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
6738
if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
6739
if (TLI.isTypeLegal(N2.getValueType()) &&
6740
(TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
6741
TargetLowering::Legal) &&
6742
// If both constants have multiple uses, then we won't need to do an
6743
// extra load, they are likely around in registers for other users.
6744
(TV->hasOneUse() || FV->hasOneUse())) {
6745
Constant *Elts[] = {
6746
const_cast<ConstantFP*>(FV->getConstantFPValue()),
6747
const_cast<ConstantFP*>(TV->getConstantFPValue())
6749
const Type *FPTy = Elts[0]->getType();
6750
const TargetData &TD = *TLI.getTargetData();
6752
// Create a ConstantArray of the two constants.
6753
Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
6754
SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
6755
TD.getPrefTypeAlignment(FPTy));
6756
unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6758
// Get the offsets to the 0 and 1 element of the array so that we can
6759
// select between them.
6760
SDValue Zero = DAG.getIntPtrConstant(0);
6761
unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
6762
SDValue One = DAG.getIntPtrConstant(EltSize);
6764
SDValue Cond = DAG.getSetCC(DL,
6765
TLI.getSetCCResultType(N0.getValueType()),
6767
SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
6769
CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
6771
return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
6772
PseudoSourceValue::getConstantPool(), 0, false,
6778
// Check to see if we can perform the "gzip trick", transforming
6779
// (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
6780
if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
6781
N0.getValueType().isInteger() &&
6782
N2.getValueType().isInteger() &&
6783
(N1C->isNullValue() || // (a < 0) ? b : 0
6784
(N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
6785
EVT XType = N0.getValueType();
6786
EVT AType = N2.getValueType();
6787
if (XType.bitsGE(AType)) {
6788
// and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
6789
// single-bit constant.
6790
if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
6791
unsigned ShCtV = N2C->getAPIntValue().logBase2();
6792
ShCtV = XType.getSizeInBits()-ShCtV-1;
6793
SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
6794
SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
6796
AddToWorkList(Shift.getNode());
6798
if (XType.bitsGT(AType)) {
6799
Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6800
AddToWorkList(Shift.getNode());
6803
return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6806
SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
6808
DAG.getConstant(XType.getSizeInBits()-1,
6809
getShiftAmountTy()));
6810
AddToWorkList(Shift.getNode());
6812
if (XType.bitsGT(AType)) {
6813
Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6814
AddToWorkList(Shift.getNode());
6817
return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6821
// fold select C, 16, 0 -> shl C, 4
6822
if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
6823
TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
6825
// If the caller doesn't want us to simplify this into a zext of a compare,
6827
if (NotExtCompare && N2C->getAPIntValue() == 1)
6830
// Get a SetCC of the condition
6831
// FIXME: Should probably make sure that setcc is legal if we ever have a
6832
// target where it isn't.
6834
// cast from setcc result type to select result type
6836
SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
6838
if (N2.getValueType().bitsLT(SCC.getValueType()))
6839
Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
6841
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6842
N2.getValueType(), SCC);
6844
SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
6845
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6846
N2.getValueType(), SCC);
6849
AddToWorkList(SCC.getNode());
6850
AddToWorkList(Temp.getNode());
6852
if (N2C->getAPIntValue() == 1)
6855
// shl setcc result by log2 n2c
6856
return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
6857
DAG.getConstant(N2C->getAPIntValue().logBase2(),
6858
getShiftAmountTy()));
6861
// Check to see if this is the equivalent of setcc
6862
// FIXME: Turn all of these into setcc if setcc if setcc is legal
6863
// otherwise, go ahead with the folds.
6864
if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
6865
EVT XType = N0.getValueType();
6866
if (!LegalOperations ||
6867
TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
6868
SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
6869
if (Res.getValueType() != VT)
6870
Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
6874
// fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
6875
if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
6876
(!LegalOperations ||
6877
TLI.isOperationLegal(ISD::CTLZ, XType))) {
6878
SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
6879
return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
6880
DAG.getConstant(Log2_32(XType.getSizeInBits()),
6881
getShiftAmountTy()));
6883
// fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
6884
if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
6885
SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
6886
XType, DAG.getConstant(0, XType), N0);
6887
SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
6888
return DAG.getNode(ISD::SRL, DL, XType,
6889
DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
6890
DAG.getConstant(XType.getSizeInBits()-1,
6891
getShiftAmountTy()));
6893
// fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
6894
if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
6895
SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
6896
DAG.getConstant(XType.getSizeInBits()-1,
6897
getShiftAmountTy()));
6898
return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
6902
// Check to see if this is an integer abs.
6903
// select_cc setg[te] X, 0, X, -X ->
6904
// select_cc setgt X, -1, X, -X ->
6905
// select_cc setl[te] X, 0, -X, X ->
6906
// select_cc setlt X, 1, -X, X ->
6907
// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6909
ConstantSDNode *SubC = NULL;
6910
if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
6911
(N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
6912
N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
6913
SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
6914
else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
6915
(N1C->isOne() && CC == ISD::SETLT)) &&
6916
N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
6917
SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
6919
EVT XType = N0.getValueType();
6920
if (SubC && SubC->isNullValue() && XType.isInteger()) {
6921
SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
6923
DAG.getConstant(XType.getSizeInBits()-1,
6924
getShiftAmountTy()));
6925
SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
6927
AddToWorkList(Shift.getNode());
6928
AddToWorkList(Add.getNode());
6929
return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6936
/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
6937
SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
6938
SDValue N1, ISD::CondCode Cond,
6939
DebugLoc DL, bool foldBooleans) {
6940
TargetLowering::DAGCombinerInfo
6941
DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
6942
return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
6945
/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
6946
/// return a DAG expression to select that will generate the same value by
6947
/// multiplying by a magic number. See:
6948
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6949
SDValue DAGCombiner::BuildSDIV(SDNode *N) {
6950
std::vector<SDNode*> Built;
6951
SDValue S = TLI.BuildSDIV(N, DAG, &Built);
6953
for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6959
/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
6960
/// return a DAG expression to select that will generate the same value by
6961
/// multiplying by a magic number. See:
6962
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6963
SDValue DAGCombiner::BuildUDIV(SDNode *N) {
6964
std::vector<SDNode*> Built;
6965
SDValue S = TLI.BuildUDIV(N, DAG, &Built);
6967
for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6973
/// FindBaseOffset - Return true if base is a frame index, which is known not
6974
// to alias with anything but itself. Provides base object and offset as results.
6975
static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
6976
const GlobalValue *&GV, void *&CV) {
6977
// Assume it is a primitive operation.
6978
Base = Ptr; Offset = 0; GV = 0; CV = 0;
6980
// If it's an adding a simple constant then integrate the offset.
6981
if (Base.getOpcode() == ISD::ADD) {
6982
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
6983
Base = Base.getOperand(0);
6984
Offset += C->getZExtValue();
6988
// Return the underlying GlobalValue, and update the Offset. Return false
6989
// for GlobalAddressSDNode since the same GlobalAddress may be represented
6990
// by multiple nodes with different offsets.
6991
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
6992
GV = G->getGlobal();
6993
Offset += G->getOffset();
6997
// Return the underlying Constant value, and update the Offset. Return false
6998
// for ConstantSDNodes since the same constant pool entry may be represented
6999
// by multiple nodes with different offsets.
7000
if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
7001
CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
7002
: (void *)C->getConstVal();
7003
Offset += C->getOffset();
7006
// If it's any of the following then it can't alias with anything but itself.
7007
return isa<FrameIndexSDNode>(Base);
7010
/// isAlias - Return true if there is any possibility that the two addresses
7012
bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
7013
const Value *SrcValue1, int SrcValueOffset1,
7014
unsigned SrcValueAlign1,
7015
SDValue Ptr2, int64_t Size2,
7016
const Value *SrcValue2, int SrcValueOffset2,
7017
unsigned SrcValueAlign2) const {
7018
// If they are the same then they must be aliases.
7019
if (Ptr1 == Ptr2) return true;
7021
// Gather base node and offset information.
7022
SDValue Base1, Base2;
7023
int64_t Offset1, Offset2;
7024
const GlobalValue *GV1, *GV2;
7026
bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
7027
bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
7029
// If they have a same base address then check to see if they overlap.
7030
if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
7031
return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7033
// If we know what the bases are, and they aren't identical, then we know they
7035
if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
7038
// If we know required SrcValue1 and SrcValue2 have relatively large alignment
7039
// compared to the size and offset of the access, we may be able to prove they
7040
// do not alias. This check is conservative for now to catch cases created by
7041
// splitting vector types.
7042
if ((SrcValueAlign1 == SrcValueAlign2) &&
7043
(SrcValueOffset1 != SrcValueOffset2) &&
7044
(Size1 == Size2) && (SrcValueAlign1 > Size1)) {
7045
int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
7046
int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
7048
// There is no overlap between these relatively aligned accesses of similar
7049
// size, return no alias.
7050
if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
7054
if (CombinerGlobalAA) {
7055
// Use alias analysis information.
7056
int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
7057
int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
7058
int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
7059
AliasAnalysis::AliasResult AAResult =
7060
AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
7061
if (AAResult == AliasAnalysis::NoAlias)
7065
// Otherwise we have to assume they alias.
7069
/// FindAliasInfo - Extracts the relevant alias information from the memory
7070
/// node. Returns true if the operand was a load.
7071
bool DAGCombiner::FindAliasInfo(SDNode *N,
7072
SDValue &Ptr, int64_t &Size,
7073
const Value *&SrcValue,
7074
int &SrcValueOffset,
7075
unsigned &SrcValueAlign) const {
7076
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7077
Ptr = LD->getBasePtr();
7078
Size = LD->getMemoryVT().getSizeInBits() >> 3;
7079
SrcValue = LD->getSrcValue();
7080
SrcValueOffset = LD->getSrcValueOffset();
7081
SrcValueAlign = LD->getOriginalAlignment();
7083
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7084
Ptr = ST->getBasePtr();
7085
Size = ST->getMemoryVT().getSizeInBits() >> 3;
7086
SrcValue = ST->getSrcValue();
7087
SrcValueOffset = ST->getSrcValueOffset();
7088
SrcValueAlign = ST->getOriginalAlignment();
7090
llvm_unreachable("FindAliasInfo expected a memory operand");
7096
/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
7097
/// looking for aliasing nodes and adding them to the Aliases vector.
7098
void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
7099
SmallVector<SDValue, 8> &Aliases) {
7100
SmallVector<SDValue, 8> Chains; // List of chains to visit.
7101
SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
7103
// Get alias information for node.
7106
const Value *SrcValue;
7108
unsigned SrcValueAlign;
7109
bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
7113
Chains.push_back(OriginalChain);
7116
// Look at each chain and determine if it is an alias. If so, add it to the
7117
// aliases list. If not, then continue up the chain looking for the next
7119
while (!Chains.empty()) {
7120
SDValue Chain = Chains.back();
7123
// For TokenFactor nodes, look at each operand and only continue up the
7124
// chain until we find two aliases. If we've seen two aliases, assume we'll
7125
// find more and revert to original chain since the xform is unlikely to be
7128
// FIXME: The depth check could be made to return the last non-aliasing
7129
// chain we found before we hit a tokenfactor rather than the original
7131
if (Depth > 6 || Aliases.size() == 2) {
7133
Aliases.push_back(OriginalChain);
7137
// Don't bother if we've been before.
7138
if (!Visited.insert(Chain.getNode()))
7141
switch (Chain.getOpcode()) {
7142
case ISD::EntryToken:
7143
// Entry token is ideal chain operand, but handled in FindBetterChain.
7148
// Get alias information for Chain.
7151
const Value *OpSrcValue;
7152
int OpSrcValueOffset;
7153
unsigned OpSrcValueAlign;
7154
bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
7155
OpSrcValue, OpSrcValueOffset,
7158
// If chain is alias then stop here.
7159
if (!(IsLoad && IsOpLoad) &&
7160
isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
7161
OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
7163
Aliases.push_back(Chain);
7165
// Look further up the chain.
7166
Chains.push_back(Chain.getOperand(0));
7172
case ISD::TokenFactor:
7173
// We have to check each of the operands of the token factor for "small"
7174
// token factors, so we queue them up. Adding the operands to the queue
7175
// (stack) in reverse order maintains the original order and increases the
7176
// likelihood that getNode will find a matching token factor (CSE.)
7177
if (Chain.getNumOperands() > 16) {
7178
Aliases.push_back(Chain);
7181
for (unsigned n = Chain.getNumOperands(); n;)
7182
Chains.push_back(Chain.getOperand(--n));
7187
// For all other instructions we will just have to take what we can get.
7188
Aliases.push_back(Chain);
7194
/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
7195
/// for a better chain (aliasing node.)
7196
SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
7197
SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
7199
// Accumulate all the aliases to this node.
7200
GatherAllAliases(N, OldChain, Aliases);
7202
if (Aliases.size() == 0) {
7203
// If no operands then chain to entry token.
7204
return DAG.getEntryNode();
7205
} else if (Aliases.size() == 1) {
7206
// If a single operand then chain to it. We don't need to revisit it.
7210
// Construct a custom tailored token factor.
7211
return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7212
&Aliases[0], Aliases.size());
7215
// SelectionDAG::Combine - This is the entry point for the file.
7217
void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
7218
CodeGenOpt::Level OptLevel) {
7219
/// run - This is the main entry point to this class.
7221
DAGCombiner(*this, AA, OptLevel).Run(Level);
added
removed
libclamav/c++/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
