2
* Copyright (C) 2005 Texas Instruments, <www.ti.com>
5
* Texas Instruments, <www.ti.com>
6
* Richard Woodruff <r-woodruff2@ti.com>
8
* See file CREDITS for list of people who contributed to this
11
* This program is free software; you can redistribute it and/or
12
* modify it under the terms of the GNU General Public License as
13
* published by the Free Software Foundation; either version 2 of
14
* the License, or (at your option) any later version.
16
* This program is distributed in the hope that it will be useful,
17
* but WITHOUT ANY WARRANTY; without even the implied warranty of
18
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19
* GNU General Public License for more details.
21
* You should have received a copy of the GNU General Public License
22
* along with this program; if not, write to the Free Software
23
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27
#ifndef _OMAP2420_SYS_H_
28
#define _OMAP2420_SYS_H_
30
#include <asm/arch/sizes.h>
33
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
34
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
35
#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
37
#define __raw_readb(a) (*(volatile unsigned char *)(a))
38
#define __raw_readw(a) (*(volatile unsigned short *)(a))
39
#define __raw_readl(a) (*(volatile unsigned int *)(a))
43
* 2420 specific Section
47
#define OMAP2420_CTRL_BASE (0x48000000)
48
#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8)
51
#define OMAP2420_TAP_BASE (0x48014000)
52
#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204)
55
#define OMAP2420_GPMC_BASE (0x6800A000)
56
#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10)
57
#define GPMC_SYSSTATUS (OMAP2420_GPMC_BASE+0x14)
58
#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C)
59
#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40)
60
#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50)
61
#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60)
62
#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64)
63
#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68)
64
#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C)
65
#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70)
66
#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74)
67
#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78)
68
#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90)
69
#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94)
70
#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98)
71
#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C)
72
#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0)
73
#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4)
74
#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8)
77
#define OMAP2420_SMS_BASE 0x68008000
78
#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10)
81
#define OMAP2420_SDRC_BASE 0x68009000
82
#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10)
83
#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14)
84
#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44)
85
#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60)
86
#define SDRC_DLLA_STATUS (OMAP2420_SDRC_BASE+0x64)
87
#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68)
88
#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70)
89
#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80)
90
#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84)
91
#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C)
92
#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0)
93
#define SDRC_MCFG_1 (OMAP2420_SDRC_BASE+0xB0)
94
#define SDRC_MR_1 (OMAP2420_SDRC_BASE+0xB4)
95
#define SDRC_EMR2_1 (OMAP2420_SDRC_BASE+0xBC)
96
#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4)
97
#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8)
98
#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4)
99
#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8)
100
#define SDRC_RFR_CTRL1 (OMAP2420_SDRC_BASE+0xD4)
101
#define SDRC_MANUAL_1 (OMAP2420_SDRC_BASE+0xD8)
103
#define OMAP2420_SDRC_CS0 0x80000000
104
#define OMAP2420_SDRC_CS1 0xA0000000
108
#define CMD_PRECHARGE 0x1
109
#define CMD_AUTOREFRESH 0x2
110
#define CMD_ENTR_PWRDOWN 0x3
111
#define CMD_EXIT_PWRDOWN 0x4
112
#define CMD_ENTR_SRFRSH 0x5
113
#define CMD_CKE_HIGH 0x6
114
#define CMD_CKE_LOW 0x7
115
#define SOFTRESET BIT1
116
#define SMART_IDLE (0x2 << 3)
117
#define REF_ON_IDLE (0x1 << 6)
121
#define OMAP2420_UART1 0x4806A000
122
#define OMAP2420_UART2 0x4806C000
123
#define OMAP2420_UART3 0x4806E000
125
/* General Purpose Timers */
126
#define OMAP2420_GPT1 0x48028000
127
#define OMAP2420_GPT2 0x4802A000
128
#define OMAP2420_GPT3 0x48078000
129
#define OMAP2420_GPT4 0x4807A000
130
#define OMAP2420_GPT5 0x4807C000
131
#define OMAP2420_GPT6 0x4807E000
132
#define OMAP2420_GPT7 0x48080000
133
#define OMAP2420_GPT8 0x48082000
134
#define OMAP2420_GPT9 0x48084000
135
#define OMAP2420_GPT10 0x48086000
136
#define OMAP2420_GPT11 0x48088000
137
#define OMAP2420_GPT12 0x4808A000
139
/* timer regs offsets (32 bit regs) */
140
#define TIDR 0x0 /* r */
141
#define TIOCP_CFG 0x10 /* rw */
142
#define TISTAT 0x14 /* r */
143
#define TISR 0x18 /* rw */
144
#define TIER 0x1C /* rw */
145
#define TWER 0x20 /* rw */
146
#define TCLR 0x24 /* rw */
147
#define TCRR 0x28 /* rw */
148
#define TLDR 0x2C /* rw */
149
#define TTGR 0x30 /* rw */
150
#define TWPS 0x34 /* r */
151
#define TMAR 0x38 /* rw */
152
#define TCAR1 0x3c /* r */
153
#define TSICR 0x40 /* rw */
154
#define TCAR2 0x44 /* r */
156
/* WatchDog Timers (1 secure, 3 GP) */
157
#define WD1_BASE 0x48020000
158
#define WD2_BASE 0x48022000
159
#define WD3_BASE 0x48024000
160
#define WD4_BASE 0x48026000
161
#define WWPS 0x34 /* r */
162
#define WSPR 0x48 /* rw */
163
#define WD_UNLOCK1 0xAAAA
164
#define WD_UNLOCK2 0x5555
167
#define OMAP2420_CM_BASE 0x48008000
168
#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080)
169
#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140)
170
#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200)
171
#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204)
172
#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210)
173
#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214)
174
#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240)
175
#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440)
176
#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244)
177
#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340)
178
#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450)
179
#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500)
180
#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520)
181
#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540)
182
#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544)
183
#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840)
186
* H4 specific Section
190
* The 2420's chip selects are programmable. The mask ROM
191
* does configure CS0 to 0x08000000 before dispatch. So, if
192
* you want your code to live below that address, you have to
193
* be prepared to jump though hoops, to reset the base address.
195
#if defined(CONFIG_OMAP2420H4)
197
#ifdef CONFIG_VIRTIO_A /* Pre version B */
198
# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */
199
# define H4_CS1_BASE 0x04000000 /* debug board */
200
# define H4_CS2_BASE 0x0A000000 /* wifi board */
202
# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */
203
# define H4_CS1_BASE 0x08000000 /* debug board */
204
# define H4_CS2_BASE 0x0A000000 /* wifi board */
207
/* base address for indirect vectors (internal boot mode) */
208
#define SRAM_OFFSET0 0x40000000
209
#define SRAM_OFFSET1 0x00200000
210
#define SRAM_OFFSET2 0x0000F800
211
#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
213
#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
215
#define PERIFERAL_PORT_BASE 0x480FE003
217
/* FPGA on Debug board.*/
218
#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b)
219
#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c)
220
#endif /* endif CONFIG_2420H4 */