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- Committer: Package Import Robot
- Author(s): Cyril Brulebois
- Date: 2012-02-24 14:16:47 UTC
- mfrom: (12.1.17) (0.1.27 experimental)
- Revision ID: package-import@ubuntu.com-20120224141647-umzxgwe5e54ixbn4
Tags: 2:2.18.0-1
* New upstream release.
* No SNA for unstable, it's too fast of a moving target for now.
* Since we're building for unstable, let's go back to the previous
xorg-server build-dep.
* No SNA for unstable, it's too fast of a moving target for now.
* Since we're building for unstable, let's go back to the previous
xorg-server build-dep.
- files added:
- config.log
- files modified:
- ChangeLog
- build-aux/config.sub *
- build-aux/depcomp *
- build-aux/install-sh *
- build-aux/ltmain.sh *
- build-aux/missing *
added
removed
src/i965_video.c
380
380
#define URB_CS_ENTRIES 0
381
381
#define URB_CS_ENTRY_SIZE 0
382
382
383
static int
384
intel_alloc_and_map(intel_screen_private *intel, char *name, int size,
385
drm_intel_bo ** bop, void *virtualp)
386
{
387
drm_intel_bo *bo;
388
389
bo = drm_intel_bo_alloc(intel->bufmgr, name, size, 4096);
390
if (!bo)
391
return -1;
392
if (drm_intel_bo_map(bo, TRUE) != 0) {
393
drm_intel_bo_unreference(bo);
394
return -1;
395
}
396
*bop = bo;
397
*(void **)virtualp = bo->virtual;
398
memset(bo->virtual, 0, size);
399
return 0;
400
}
401
402
383
static void i965_create_dst_surface_state(ScrnInfoPtr scrn,
403
384
PixmapPtr pixmap,
404
385
drm_intel_bo *surf_bo,
405
386
uint32_t offset)
406
387
{
407
388
intel_screen_private *intel = intel_get_screen_private(scrn);
408
struct brw_surface_state *dest_surf_state;
389
struct brw_surface_state dest_surf_state;
409
390
drm_intel_bo *pixmap_bo = intel_get_pixmap_bo(pixmap);
410
391
411
if (drm_intel_bo_map(surf_bo, TRUE) != 0)
412
return;
413
414
dest_surf_state = (struct brw_surface_state *)((char *)surf_bo->virtual + offset);
415
memset(dest_surf_state, 0, sizeof(*dest_surf_state));
416
417
dest_surf_state->ss0.surface_type = BRW_SURFACE_2D;
418
dest_surf_state->ss0.data_return_format =
392
memset(&dest_surf_state, 0, sizeof(dest_surf_state));
393
394
dest_surf_state.ss0.surface_type = BRW_SURFACE_2D;
395
dest_surf_state.ss0.data_return_format =
419
396
BRW_SURFACERETURNFORMAT_FLOAT32;
420
397
if (intel->cpp == 2) {
421
dest_surf_state->ss0.surface_format =
398
dest_surf_state.ss0.surface_format =
422
399
BRW_SURFACEFORMAT_B5G6R5_UNORM;
423
400
} else {
424
dest_surf_state->ss0.surface_format =
401
dest_surf_state.ss0.surface_format =
425
402
BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
426
403
}
427
dest_surf_state->ss0.writedisable_alpha = 0;
428
dest_surf_state->ss0.writedisable_red = 0;
429
dest_surf_state->ss0.writedisable_green = 0;
430
dest_surf_state->ss0.writedisable_blue = 0;
431
dest_surf_state->ss0.color_blend = 1;
432
dest_surf_state->ss0.vert_line_stride = 0;
433
dest_surf_state->ss0.vert_line_stride_ofs = 0;
434
dest_surf_state->ss0.mipmap_layout_mode = 0;
435
dest_surf_state->ss0.render_cache_read_mode = 0;
404
dest_surf_state.ss0.writedisable_alpha = 0;
405
dest_surf_state.ss0.writedisable_red = 0;
406
dest_surf_state.ss0.writedisable_green = 0;
407
dest_surf_state.ss0.writedisable_blue = 0;
408
dest_surf_state.ss0.color_blend = 1;
409
dest_surf_state.ss0.vert_line_stride = 0;
410
dest_surf_state.ss0.vert_line_stride_ofs = 0;
411
dest_surf_state.ss0.mipmap_layout_mode = 0;
412
dest_surf_state.ss0.render_cache_read_mode = 0;
436
413
437
dest_surf_state->ss1.base_addr =
414
dest_surf_state.ss1.base_addr =
438
415
intel_emit_reloc(surf_bo, offset + offsetof(struct brw_surface_state, ss1),
439
pixmap_bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
440
441
dest_surf_state->ss2.height = pixmap->drawable.height - 1;
442
dest_surf_state->ss2.width = pixmap->drawable.width - 1;
443
dest_surf_state->ss2.mip_count = 0;
444
dest_surf_state->ss2.render_target_rotation = 0;
445
dest_surf_state->ss3.pitch = intel_pixmap_pitch(pixmap) - 1;
446
dest_surf_state->ss3.tiled_surface = intel_pixmap_tiled(pixmap);
447
dest_surf_state->ss3.tile_walk = 0; /* TileX */
448
449
drm_intel_bo_unmap(surf_bo);
416
pixmap_bo, 0, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
417
418
dest_surf_state.ss2.height = pixmap->drawable.height - 1;
419
dest_surf_state.ss2.width = pixmap->drawable.width - 1;
420
dest_surf_state.ss2.mip_count = 0;
421
dest_surf_state.ss2.render_target_rotation = 0;
422
dest_surf_state.ss3.pitch = intel_pixmap_pitch(pixmap) - 1;
423
dest_surf_state.ss3.tiled_surface = intel_pixmap_tiled(pixmap);
424
dest_surf_state.ss3.tile_walk = 0; /* TileX */
425
426
dri_bo_subdata(surf_bo,
427
offset, sizeof(dest_surf_state),
428
&dest_surf_state);
450
429
}
451
430
452
431
static void i965_create_src_surface_state(ScrnInfoPtr scrn,
459
438
drm_intel_bo *surface_bo,
460
439
uint32_t offset)
461
440
{
462
struct brw_surface_state *src_surf_state;
463
464
if (drm_intel_bo_map(surface_bo, TRUE) != 0)
465
return;
466
467
src_surf_state = (struct brw_surface_state *)((char *)surface_bo->virtual + offset);
468
memset(src_surf_state, 0, sizeof(*src_surf_state));
441
struct brw_surface_state src_surf_state;
442
443
memset(&src_surf_state, 0, sizeof(src_surf_state));
469
444
470
445
/* Set up the source surface state buffer */
471
src_surf_state->ss0.surface_type = BRW_SURFACE_2D;
472
src_surf_state->ss0.surface_format = src_surf_format;
473
src_surf_state->ss0.writedisable_alpha = 0;
474
src_surf_state->ss0.writedisable_red = 0;
475
src_surf_state->ss0.writedisable_green = 0;
476
src_surf_state->ss0.writedisable_blue = 0;
477
src_surf_state->ss0.color_blend = 1;
478
src_surf_state->ss0.vert_line_stride = 0;
479
src_surf_state->ss0.vert_line_stride_ofs = 0;
480
src_surf_state->ss0.mipmap_layout_mode = 0;
481
src_surf_state->ss0.render_cache_read_mode = 0;
446
src_surf_state.ss0.surface_type = BRW_SURFACE_2D;
447
src_surf_state.ss0.surface_format = src_surf_format;
448
src_surf_state.ss0.writedisable_alpha = 0;
449
src_surf_state.ss0.writedisable_red = 0;
450
src_surf_state.ss0.writedisable_green = 0;
451
src_surf_state.ss0.writedisable_blue = 0;
452
src_surf_state.ss0.color_blend = 1;
453
src_surf_state.ss0.vert_line_stride = 0;
454
src_surf_state.ss0.vert_line_stride_ofs = 0;
455
src_surf_state.ss0.mipmap_layout_mode = 0;
456
src_surf_state.ss0.render_cache_read_mode = 0;
482
457
483
src_surf_state->ss2.width = src_width - 1;
484
src_surf_state->ss2.height = src_height - 1;
485
src_surf_state->ss2.mip_count = 0;
486
src_surf_state->ss2.render_target_rotation = 0;
487
src_surf_state->ss3.pitch = src_pitch - 1;
458
src_surf_state.ss2.width = src_width - 1;
459
src_surf_state.ss2.height = src_height - 1;
460
src_surf_state.ss2.mip_count = 0;
461
src_surf_state.ss2.render_target_rotation = 0;
462
src_surf_state.ss3.pitch = src_pitch - 1;
488
463
489
464
if (src_bo) {
490
src_surf_state->ss1.base_addr =
465
src_surf_state.ss1.base_addr =
491
466
intel_emit_reloc(surface_bo,
492
467
offset + offsetof(struct brw_surface_state, ss1),
493
468
src_bo, src_offset,
494
469
I915_GEM_DOMAIN_SAMPLER, 0);
495
470
} else {
496
src_surf_state->ss1.base_addr = src_offset;
471
src_surf_state.ss1.base_addr = src_offset;
497
472
}
498
473
499
drm_intel_bo_unmap(surface_bo);
474
dri_bo_subdata(surface_bo,
475
offset, sizeof(src_surf_state),
476
&src_surf_state);
500
477
}
501
478
502
479
static void gen7_create_dst_surface_state(ScrnInfoPtr scrn,
505
482
uint32_t offset)
506
483
{
507
484
intel_screen_private *intel = intel_get_screen_private(scrn);
508
struct gen7_surface_state *dest_surf_state;
485
struct gen7_surface_state dest_surf_state;
509
486
drm_intel_bo *pixmap_bo = intel_get_pixmap_bo(pixmap);
510
487
511
if (drm_intel_bo_map(surf_bo, TRUE) != 0)
512
return;
513
514
dest_surf_state = (struct gen7_surface_state *)((char *)surf_bo->virtual + offset);
515
memset(dest_surf_state, 0, sizeof(*dest_surf_state));
516
517
dest_surf_state->ss0.surface_type = BRW_SURFACE_2D;
518
dest_surf_state->ss0.tiled_surface = intel_pixmap_tiled(pixmap);
519
dest_surf_state->ss0.tile_walk = 0; /* TileX */
488
memset(&dest_surf_state, 0, sizeof(dest_surf_state));
489
490
dest_surf_state.ss0.surface_type = BRW_SURFACE_2D;
491
dest_surf_state.ss0.tiled_surface = intel_pixmap_tiled(pixmap);
492
dest_surf_state.ss0.tile_walk = 0; /* TileX */
520
493
521
494
if (intel->cpp == 2) {
522
dest_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
495
dest_surf_state.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
523
496
} else {
524
dest_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
497
dest_surf_state.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
525
498
}
526
499
527
dest_surf_state->ss1.base_addr =
528
intel_emit_reloc(surf_bo,
500
dest_surf_state.ss1.base_addr =
501
intel_emit_reloc(surf_bo,
529
502
offset + offsetof(struct gen7_surface_state, ss1),
530
pixmap_bo, 0,
503
pixmap_bo, 0,
531
504
I915_GEM_DOMAIN_SAMPLER, 0);
532
505
533
dest_surf_state->ss2.height = pixmap->drawable.height - 1;
534
dest_surf_state->ss2.width = pixmap->drawable.width - 1;
535
536
dest_surf_state->ss3.pitch = intel_pixmap_pitch(pixmap) - 1;
537
538
drm_intel_bo_unmap(surf_bo);
506
dest_surf_state.ss2.height = pixmap->drawable.height - 1;
507
dest_surf_state.ss2.width = pixmap->drawable.width - 1;
508
509
dest_surf_state.ss3.pitch = intel_pixmap_pitch(pixmap) - 1;
510
511
dri_bo_subdata(surf_bo,
512
offset, sizeof(dest_surf_state),
513
&dest_surf_state);
539
514
}
540
515
541
516
static void gen7_create_src_surface_state(ScrnInfoPtr scrn,
548
523
drm_intel_bo *surface_bo,
549
524
uint32_t offset)
550
525
{
551
struct gen7_surface_state *src_surf_state;
552
553
if (drm_intel_bo_map(surface_bo, TRUE) != 0)
554
return;
555
556
src_surf_state = (struct gen7_surface_state *)((char *)surface_bo->virtual + offset);
557
memset(src_surf_state, 0, sizeof(*src_surf_state));
558
559
src_surf_state->ss0.surface_type = BRW_SURFACE_2D;
560
src_surf_state->ss0.surface_format = src_surf_format;
526
struct gen7_surface_state src_surf_state;
527
528
memset(&src_surf_state, 0, sizeof(src_surf_state));
529
530
src_surf_state.ss0.surface_type = BRW_SURFACE_2D;
531
src_surf_state.ss0.surface_format = src_surf_format;
561
532
562
533
if (src_bo) {
563
src_surf_state->ss1.base_addr =
534
src_surf_state.ss1.base_addr =
564
535
intel_emit_reloc(surface_bo,
565
536
offset + offsetof(struct gen7_surface_state, ss1),
566
537
src_bo, src_offset,
567
538
I915_GEM_DOMAIN_SAMPLER, 0);
568
539
} else {
569
src_surf_state->ss1.base_addr = src_offset;
540
src_surf_state.ss1.base_addr = src_offset;
570
541
}
571
542
572
src_surf_state->ss2.width = src_width - 1;
573
src_surf_state->ss2.height = src_height - 1;
574
575
src_surf_state->ss3.pitch = src_pitch - 1;
576
577
drm_intel_bo_unmap(surface_bo);
543
src_surf_state.ss2.width = src_width - 1;
544
src_surf_state.ss2.height = src_height - 1;
545
546
src_surf_state.ss3.pitch = src_pitch - 1;
547
548
dri_bo_subdata(surface_bo,
549
offset, sizeof(src_surf_state),
550
&src_surf_state);
578
551
}
579
552
580
553
static void i965_create_binding_table(ScrnInfoPtr scrn,
581
drm_intel_bo *bind_bo,
582
int n_surf)
554
drm_intel_bo *bind_bo,
555
int n_surf)
583
556
{
584
uint32_t *binding_table;
557
uint32_t binding_table[n_surf];
585
558
int i;
586
559
587
560
/* Set up a binding table for our surfaces. Only the PS will use it */
588
if (drm_intel_bo_map(bind_bo, TRUE) != 0)
589
return;
590
591
binding_table = (uint32_t*)((char *)bind_bo->virtual + n_surf * SURFACE_STATE_PADDED_SIZE);
592
593
561
for (i = 0; i < n_surf; i++)
594
562
binding_table[i] = i * SURFACE_STATE_PADDED_SIZE;
595
563
596
drm_intel_bo_unmap(bind_bo);
564
dri_bo_subdata(bind_bo,
565
n_surf * SURFACE_STATE_PADDED_SIZE,
566
sizeof(binding_table), binding_table);
597
567
}
598
568
599
569
static drm_intel_bo *i965_create_sampler_state(ScrnInfoPtr scrn)
600
570
{
601
571
intel_screen_private *intel = intel_get_screen_private(scrn);
602
drm_intel_bo *sampler_bo;
603
struct brw_sampler_state *sampler_state;
604
605
if (intel_alloc_and_map(intel, "textured video sampler state", 4096,
606
&sampler_bo, &sampler_state) != 0)
607
return NULL;
608
609
sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR;
610
sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
611
sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
612
sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
613
sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
614
615
drm_intel_bo_unmap(sampler_bo);
616
return sampler_bo;
572
struct brw_sampler_state sampler_state;
573
574
memset(&sampler_state, 0, sizeof(sampler_state));
575
sampler_state.ss0.min_filter = BRW_MAPFILTER_LINEAR;
576
sampler_state.ss0.mag_filter = BRW_MAPFILTER_LINEAR;
577
sampler_state.ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
578
sampler_state.ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
579
sampler_state.ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
580
581
return intel_bo_alloc_for_data(intel,
582
&sampler_state, sizeof(sampler_state),
583
"textured video sampler state");
617
584
}
618
585
619
586
static drm_intel_bo *gen7_create_sampler_state(ScrnInfoPtr scrn)
620
587
{
621
588
intel_screen_private *intel = intel_get_screen_private(scrn);
622
drm_intel_bo *sampler_bo;
623
struct gen7_sampler_state *sampler_state;
624
625
if (intel_alloc_and_map(intel, "textured video sampler state", 4096,
626
&sampler_bo, &sampler_state) != 0)
627
return NULL;
628
629
sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR;
630
sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
631
sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
632
sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
633
sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
634
635
drm_intel_bo_unmap(sampler_bo);
636
return sampler_bo;
589
struct gen7_sampler_state sampler_state;
590
591
memset(&sampler_state, 0, sizeof(sampler_state));
592
sampler_state.ss0.min_filter = BRW_MAPFILTER_LINEAR;
593
sampler_state.ss0.mag_filter = BRW_MAPFILTER_LINEAR;
594
sampler_state.ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
595
sampler_state.ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
596
sampler_state.ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
597
598
return intel_bo_alloc_for_data(intel,
599
&sampler_state, sizeof(sampler_state),
600
"textured video sampler state");
637
601
}
638
602
639
603
static drm_intel_bo *i965_create_vs_state(ScrnInfoPtr scrn)
640
604
{
641
605
intel_screen_private *intel = intel_get_screen_private(scrn);
642
drm_intel_bo *vs_bo;
643
struct brw_vs_unit_state *vs_state;
644
645
if (intel_alloc_and_map(intel, "textured video vs state", 4096,
646
&vs_bo, &vs_state) != 0)
647
return NULL;
606
struct brw_vs_unit_state vs_state;
648
607
649
608
/* Set up the vertex shader to be disabled (passthrough) */
609
memset(&vs_state, 0, sizeof(vs_state));
650
610
if (IS_GEN5(intel))
651
vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
611
vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
652
612
else
653
vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
654
vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
655
vs_state->vs6.vs_enable = 0;
656
vs_state->vs6.vert_cache_disable = 1;
613
vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES;
614
vs_state.thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
615
vs_state.vs6.vs_enable = 0;
616
vs_state.vs6.vert_cache_disable = 1;
657
617
658
drm_intel_bo_unmap(vs_bo);
659
return vs_bo;
618
return intel_bo_alloc_for_data(intel,
619
&vs_state, sizeof(vs_state),
620
"textured video vs state");
660
621
}
661
622
662
623
static drm_intel_bo *i965_create_program(ScrnInfoPtr scrn,
664
625
unsigned int program_size)
665
626
{
666
627
intel_screen_private *intel = intel_get_screen_private(scrn);
667
drm_intel_bo *prog_bo;
668
669
prog_bo = drm_intel_bo_alloc(intel->bufmgr, "textured video program",
670
program_size, 4096);
671
if (!prog_bo)
672
return NULL;
673
674
drm_intel_bo_subdata(prog_bo, 0, program_size, program);
675
676
return prog_bo;
628
return intel_bo_alloc_for_data(intel,
629
program, program_size,
630
"textured video program");
677
631
}
678
632
679
633
static drm_intel_bo *i965_create_sf_state(ScrnInfoPtr scrn)
680
634
{
681
635
intel_screen_private *intel = intel_get_screen_private(scrn);
682
636
drm_intel_bo *sf_bo, *kernel_bo;
683
struct brw_sf_unit_state *sf_state;
637
struct brw_sf_unit_state sf_state;
684
638
685
639
if (IS_GEN5(intel))
686
kernel_bo =
687
i965_create_program(scrn, &sf_kernel_static_gen5[0][0],
688
sizeof(sf_kernel_static_gen5));
640
kernel_bo = i965_create_program(scrn,
641
&sf_kernel_static_gen5[0][0],
642
sizeof(sf_kernel_static_gen5));
689
643
else
690
kernel_bo = i965_create_program(scrn, &sf_kernel_static[0][0],
644
kernel_bo = i965_create_program(scrn,
645
&sf_kernel_static[0][0],
691
646
sizeof(sf_kernel_static));
692
693
647
if (!kernel_bo)
694
648
return NULL;
695
649
696
if (intel_alloc_and_map(intel, "textured video sf state", 4096,
697
&sf_bo, &sf_state) != 0) {
650
sf_bo = drm_intel_bo_alloc(intel->bufmgr,
651
"textured video sf state", 4096,
652
sizeof(sf_state));
653
if (sf_bo == NULL) {
698
654
drm_intel_bo_unreference(kernel_bo);
699
655
return NULL;
700
656
}
703
659
* calculate dA/dx and dA/dy. Hand these interpolation coefficients
704
660
* back to SF which then hands pixels off to WM.
705
661
*/
706
sf_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
707
sf_state->thread0.kernel_start_pointer =
662
memset(&sf_state, 0, sizeof(sf_state));
663
sf_state.thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
664
sf_state.thread0.kernel_start_pointer =
708
665
intel_emit_reloc(sf_bo, offsetof(struct brw_sf_unit_state, thread0),
709
kernel_bo, sf_state->thread0.grf_reg_count << 1,
666
kernel_bo, sf_state.thread0.grf_reg_count << 1,
710
667
I915_GEM_DOMAIN_INSTRUCTION, 0) >> 6;
711
sf_state->sf1.single_program_flow = 1; /* XXX */
712
sf_state->sf1.binding_table_entry_count = 0;
713
sf_state->sf1.thread_priority = 0;
714
sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
715
sf_state->sf1.illegal_op_exception_enable = 1;
716
sf_state->sf1.mask_stack_exception_enable = 1;
717
sf_state->sf1.sw_exception_enable = 1;
718
sf_state->thread2.per_thread_scratch_space = 0;
668
sf_state.sf1.single_program_flow = 1; /* XXX */
669
sf_state.sf1.binding_table_entry_count = 0;
670
sf_state.sf1.thread_priority = 0;
671
sf_state.sf1.floating_point_mode = 0; /* Mesa does this */
672
sf_state.sf1.illegal_op_exception_enable = 1;
673
sf_state.sf1.mask_stack_exception_enable = 1;
674
sf_state.sf1.sw_exception_enable = 1;
675
sf_state.thread2.per_thread_scratch_space = 0;
719
676
/* scratch space is not used in our kernel */
720
sf_state->thread2.scratch_space_base_pointer = 0;
721
sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
722
sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
723
sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
724
sf_state->thread3.urb_entry_read_offset = 0;
725
sf_state->thread3.dispatch_grf_start_reg = 3;
726
sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
727
sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
728
sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
729
sf_state->thread4.stats_enable = 1;
730
sf_state->sf5.viewport_transform = FALSE; /* skip viewport */
731
sf_state->sf6.cull_mode = BRW_CULLMODE_NONE;
732
sf_state->sf6.scissor = 0;
733
sf_state->sf7.trifan_pv = 2;
734
sf_state->sf6.dest_org_vbias = 0x8;
735
sf_state->sf6.dest_org_hbias = 0x8;
677
sf_state.thread2.scratch_space_base_pointer = 0;
678
sf_state.thread3.const_urb_entry_read_length = 0; /* no const URBs */
679
sf_state.thread3.const_urb_entry_read_offset = 0; /* no const URBs */
680
sf_state.thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
681
sf_state.thread3.urb_entry_read_offset = 0;
682
sf_state.thread3.dispatch_grf_start_reg = 3;
683
sf_state.thread4.max_threads = SF_MAX_THREADS - 1;
684
sf_state.thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
685
sf_state.thread4.nr_urb_entries = URB_SF_ENTRIES;
686
sf_state.thread4.stats_enable = 1;
687
sf_state.sf5.viewport_transform = FALSE; /* skip viewport */
688
sf_state.sf6.cull_mode = BRW_CULLMODE_NONE;
689
sf_state.sf6.scissor = 0;
690
sf_state.sf7.trifan_pv = 2;
691
sf_state.sf6.dest_org_vbias = 0x8;
692
sf_state.sf6.dest_org_hbias = 0x8;
736
693
737
drm_intel_bo_unmap(sf_bo);
694
dri_bo_subdata(sf_bo, 0, sizeof(sf_state), &sf_state);
738
695
return sf_bo;
739
696
}
740
697
744
701
{
745
702
intel_screen_private *intel = intel_get_screen_private(scrn);
746
703
drm_intel_bo *wm_bo, *kernel_bo;
747
struct brw_wm_unit_state *wm_state;
704
struct brw_wm_unit_state wm_state;
748
705
749
706
if (is_packed) {
750
707
if (IS_GEN5(intel))
778
735
if (!kernel_bo)
779
736
return NULL;
780
737
781
if (intel_alloc_and_map
782
(intel, "textured video wm state", sizeof(*wm_state), &wm_bo,
783
&wm_state)) {
738
wm_bo = drm_intel_bo_alloc(intel->bufmgr,
739
"textured video wm state",
740
sizeof(wm_state), 0);
741
if (wm_bo == NULL) {
784
742
drm_intel_bo_unreference(kernel_bo);
785
743
return NULL;
786
744
}
787
745
788
wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
789
wm_state->thread0.kernel_start_pointer =
746
memset(&wm_state, 0, sizeof(wm_state));
747
wm_state.thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
748
wm_state.thread0.kernel_start_pointer =
790
749
intel_emit_reloc(wm_bo, offsetof(struct brw_wm_unit_state, thread0),
791
kernel_bo, wm_state->thread0.grf_reg_count << 1,
750
kernel_bo, wm_state.thread0.grf_reg_count << 1,
792
751
I915_GEM_DOMAIN_INSTRUCTION, 0) >> 6;
793
wm_state->thread1.single_program_flow = 1; /* XXX */
752
wm_state.thread1.single_program_flow = 1; /* XXX */
794
753
if (is_packed)
795
wm_state->thread1.binding_table_entry_count = 2;
754
wm_state.thread1.binding_table_entry_count = 2;
796
755
else
797
wm_state->thread1.binding_table_entry_count = 7;
756
wm_state.thread1.binding_table_entry_count = 7;
798
757
799
758
/* binding table entry count is only used for prefetching, and it has to
800
759
* be set 0 for Ironlake
801
760
*/
802
761
if (IS_GEN5(intel))
803
wm_state->thread1.binding_table_entry_count = 0;
762
wm_state.thread1.binding_table_entry_count = 0;
804
763
805
764
/* Though we never use the scratch space in our WM kernel, it has to be
806
765
* set, and the minimum allocation is 1024 bytes.
807
766
*/
808
wm_state->thread2.scratch_space_base_pointer = 0;
809
wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
810
wm_state->thread3.dispatch_grf_start_reg = 3; /* XXX */
811
wm_state->thread3.const_urb_entry_read_length = 0;
812
wm_state->thread3.const_urb_entry_read_offset = 0;
813
wm_state->thread3.urb_entry_read_length = 1; /* XXX */
814
wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
815
wm_state->wm4.stats_enable = 1;
816
wm_state->wm4.sampler_state_pointer =
767
wm_state.thread2.scratch_space_base_pointer = 0;
768
wm_state.thread2.per_thread_scratch_space = 0; /* 1024 bytes */
769
wm_state.thread3.dispatch_grf_start_reg = 3; /* XXX */
770
wm_state.thread3.const_urb_entry_read_length = 0;
771
wm_state.thread3.const_urb_entry_read_offset = 0;
772
wm_state.thread3.urb_entry_read_length = 1; /* XXX */
773
wm_state.thread3.urb_entry_read_offset = 0; /* XXX */
774
wm_state.wm4.stats_enable = 1;
775
wm_state.wm4.sampler_state_pointer =
817
776
intel_emit_reloc(wm_bo, offsetof(struct brw_wm_unit_state, wm4),
818
777
sampler_bo, 0,
819
778
I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
820
779
if (IS_GEN5(intel))
821
wm_state->wm4.sampler_count = 0;
780
wm_state.wm4.sampler_count = 0;
822
781
else
823
wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
824
wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
825
wm_state->wm5.thread_dispatch_enable = 1;
826
wm_state->wm5.enable_16_pix = 1;
827
wm_state->wm5.enable_8_pix = 0;
828
wm_state->wm5.early_depth_test = 1;
782
wm_state.wm4.sampler_count = 1; /* 1-4 samplers used */
783
wm_state.wm5.max_threads = PS_MAX_THREADS - 1;
784
wm_state.wm5.thread_dispatch_enable = 1;
785
wm_state.wm5.enable_16_pix = 1;
786
wm_state.wm5.enable_8_pix = 0;
787
wm_state.wm5.early_depth_test = 1;
829
788
789
dri_bo_subdata(wm_bo, 0, sizeof(wm_state), &wm_state);
830
790
drm_intel_bo_unreference(kernel_bo);
831
832
drm_intel_bo_unmap(wm_bo);
833
791
return wm_bo;
834
792
}
835
793
836
794
static drm_intel_bo *i965_create_cc_vp_state(ScrnInfoPtr scrn)
837
795
{
838
796
intel_screen_private *intel = intel_get_screen_private(scrn);
839
drm_intel_bo *cc_vp_bo;
840
struct brw_cc_viewport *cc_viewport;
841
842
if (intel_alloc_and_map(intel, "textured video cc viewport", 4096,
843
&cc_vp_bo, &cc_viewport) != 0)
844
return NULL;
845
846
cc_viewport->min_depth = -1.e35;
847
cc_viewport->max_depth = 1.e35;
848
849
drm_intel_bo_unmap(cc_vp_bo);
850
return cc_vp_bo;
797
struct brw_cc_viewport cc_viewport;
798
799
memset(&cc_viewport, 0, sizeof(cc_viewport));
800
cc_viewport.min_depth = -1.e35;
801
cc_viewport.max_depth = 1.e35;
802
803
return intel_bo_alloc_for_data(intel,
804
&cc_viewport, sizeof(cc_viewport),
805
"textured video cc viewport");
851
806
}
852
807
853
808
static drm_intel_bo *i965_create_cc_state(ScrnInfoPtr scrn)
854
809
{
855
810
intel_screen_private *intel = intel_get_screen_private(scrn);
856
811
drm_intel_bo *cc_bo, *cc_vp_bo;
857
struct brw_cc_unit_state *cc_state;
812
struct brw_cc_unit_state cc_state;
858
813
859
814
cc_vp_bo = i965_create_cc_vp_state(scrn);
860
815
if (!cc_vp_bo)
861
816
return NULL;
862
817
863
if (intel_alloc_and_map
864
(intel, "textured video cc state", sizeof(*cc_state), &cc_bo,
865
&cc_state) != 0) {
818
cc_bo = drm_intel_bo_alloc(intel->bufmgr,
819
"textured video cc state",
820
sizeof(cc_state), 0);
821
if (cc_bo == NULL){
866
822
drm_intel_bo_unreference(cc_vp_bo);
867
823
return NULL;
868
824
}
869
825
870
826
/* Color calculator state */
871
memset(cc_state, 0, sizeof(*cc_state));
872
cc_state->cc0.stencil_enable = 0; /* disable stencil */
873
cc_state->cc2.depth_test = 0; /* disable depth test */
874
cc_state->cc2.logicop_enable = 1; /* enable logic op */
875
cc_state->cc3.ia_blend_enable = 1; /* blend alpha just like colors */
876
cc_state->cc3.blend_enable = 0; /* disable color blend */
877
cc_state->cc3.alpha_test = 0; /* disable alpha test */
878
cc_state->cc4.cc_viewport_state_offset =
827
memset(&cc_state, 0, sizeof(cc_state));
828
cc_state.cc0.stencil_enable = 0; /* disable stencil */
829
cc_state.cc2.depth_test = 0; /* disable depth test */
830
cc_state.cc2.logicop_enable = 1; /* enable logic op */
831
cc_state.cc3.ia_blend_enable = 1; /* blend alpha just like colors */
832
cc_state.cc3.blend_enable = 0; /* disable color blend */
833
cc_state.cc3.alpha_test = 0; /* disable alpha test */
834
cc_state.cc4.cc_viewport_state_offset =
879
835
intel_emit_reloc(cc_bo, offsetof(struct brw_cc_unit_state, cc4),
880
836
cc_vp_bo, 0, I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
881
cc_state->cc5.dither_enable = 0; /* disable dither */
882
cc_state->cc5.logicop_func = 0xc; /* WHITE */
883
cc_state->cc5.statistics_enable = 1;
884
cc_state->cc5.ia_blend_function = BRW_BLENDFUNCTION_ADD;
885
cc_state->cc5.ia_src_blend_factor = BRW_BLENDFACTOR_ONE;
886
cc_state->cc5.ia_dest_blend_factor = BRW_BLENDFACTOR_ONE;
887
888
drm_intel_bo_unmap(cc_bo);
889
837
cc_state.cc5.dither_enable = 0; /* disable dither */
838
cc_state.cc5.logicop_func = 0xc; /* WHITE */
839
cc_state.cc5.statistics_enable = 1;
840
cc_state.cc5.ia_blend_function = BRW_BLENDFUNCTION_ADD;
841
cc_state.cc5.ia_src_blend_factor = BRW_BLENDFACTOR_ONE;
842
cc_state.cc5.ia_dest_blend_factor = BRW_BLENDFACTOR_ONE;
843
844
dri_bo_subdata(cc_bo, 0, sizeof(cc_state), &cc_state);
890
845
drm_intel_bo_unreference(cc_vp_bo);
846
891
847
return cc_bo;
892
848
}
893
849
1281
1237
int box_x2 = pbox->x2;
1282
1238
int box_y2 = pbox->y2;
1283
1239
int i;
1284
drm_intel_bo *vb_bo;
1285
float *vb;
1240
float vb[12];
1286
1241
drm_intel_bo *bo_table[] = {
1287
1242
NULL, /* vb_bo */
1288
1243
intel->batch_bo,
1298
1253
1299
1254
pbox++;
1300
1255
1301
if (intel_alloc_and_map(intel, "textured video vb", 4096,
1302
&vb_bo, &vb) != 0)
1303
break;
1304
bo_table[0] = vb_bo;
1305
1306
1256
i = 0;
1307
1257
vb[i++] = (box_x2 - dxo) * src_scale_x;
1308
1258
vb[i++] = (box_y2 - dyo) * src_scale_y;
1319
1269
vb[i++] = (float)box_x1 + pix_xoff;
1320
1270
vb[i++] = (float)box_y1 + pix_yoff;
1321
1271
1322
drm_intel_bo_unmap(vb_bo);
1272
bo_table[0] = intel_bo_alloc_for_data(intel,
1273
vb, sizeof(vb),
1274
"textured video vbo");
1323
1275
1324
1276
if (IS_GEN4(intel))
1325
1277
i965_pre_draw_debug(scrn);
1342
1294
/* four 32-bit floats per vertex */
1343
1295
OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
1344
1296
VB0_VERTEXDATA | ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1345
OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
1297
OUT_RELOC(bo_table[0], I915_GEM_DOMAIN_VERTEX, 0, 0);
1346
1298
if (IS_GEN5(intel))
1347
OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
1299
OUT_RELOC(bo_table[0], I915_GEM_DOMAIN_VERTEX, 0,
1348
1300
i * 4);
1349
1301
else
1350
1302
OUT_BATCH(3); /* four corners to our rectangle */
1361
1313
1362
1314
intel_batch_end_atomic(scrn);
1363
1315
1364
drm_intel_bo_unreference(vb_bo);
1316
drm_intel_bo_unreference(bo_table[0]);
1365
1317
1366
1318
if (IS_GEN4(intel))
1367
1319
i965_post_draw_debug(scrn);
1409
1361
gen6_create_cc_state(ScrnInfoPtr scrn)
1410
1362
{
1411
1363
intel_screen_private *intel = intel_get_screen_private(scrn);
1412
struct gen6_color_calc_state *cc_state;
1413
drm_intel_bo *cc_bo;
1414
1415
if (intel_alloc_and_map(
1416
intel,
1417
"textured video cc state",
1418
sizeof(*cc_state),
1419
&cc_bo,
1420
&cc_state) != 0)
1421
return NULL;
1422
1423
cc_state->constant_r = 1.0;
1424
cc_state->constant_g = 0.0;
1425
cc_state->constant_b = 1.0;
1426
cc_state->constant_a = 1.0;
1427
1428
drm_intel_bo_unmap(cc_bo);
1429
return cc_bo;
1364
struct gen6_color_calc_state cc_state;
1365
1366
memset(&cc_state, 0, sizeof(cc_state));
1367
cc_state.constant_r = 1.0;
1368
cc_state.constant_g = 0.0;
1369
cc_state.constant_b = 1.0;
1370
cc_state.constant_a = 1.0;
1371
1372
return intel_bo_alloc_for_data(intel,
1373
&cc_state, sizeof(cc_state),
1374
"textured video cc state");
1430
1375
}
1431
1376
1432
1377
static drm_intel_bo *
1433
1378
gen6_create_blend_state(ScrnInfoPtr scrn)
1434
1379
{
1435
1380
intel_screen_private *intel = intel_get_screen_private(scrn);
1436
struct gen6_blend_state *blend_state;
1437
drm_intel_bo *blend_bo;
1438
1439
if (intel_alloc_and_map(
1440
intel,
1441
"textured video blend state",
1442
sizeof(*blend_state),
1443
&blend_bo,
1444
&blend_state) != 0)
1445
return NULL;
1446
1447
blend_state->blend1.logic_op_enable = 1;
1448
blend_state->blend1.logic_op_func = 0xc;
1449
blend_state->blend1.pre_blend_clamp_enable = 1;
1450
1451
drm_intel_bo_unmap(blend_bo);
1452
return blend_bo;
1381
struct gen6_blend_state blend_state;
1382
1383
memset(&blend_state, 0, sizeof(blend_state));
1384
blend_state.blend1.logic_op_enable = 1;
1385
blend_state.blend1.logic_op_func = 0xc;
1386
blend_state.blend1.pre_blend_clamp_enable = 1;
1387
1388
return intel_bo_alloc_for_data(intel,
1389
&blend_state, sizeof(blend_state),
1390
"textured video blend state");
1453
1391
}
1454
1392
1455
1393
static drm_intel_bo *
1456
1394
gen6_create_depth_stencil_state(ScrnInfoPtr scrn)
1457
1395
{
1458
1396
intel_screen_private *intel = intel_get_screen_private(scrn);
1459
struct gen6_depth_stencil_state *depth_stencil_state;
1460
drm_intel_bo *depth_stencil_bo;
1461
1462
if (intel_alloc_and_map(
1463
intel,
1464
"textured video blend state",
1465
sizeof(*depth_stencil_state),
1466
&depth_stencil_bo,
1467
&depth_stencil_state) != 0)
1468
return NULL;
1469
1470
drm_intel_bo_unmap(depth_stencil_bo);
1471
return depth_stencil_bo;
1397
struct gen6_depth_stencil_state depth_stencil_state;
1398
1399
memset(&depth_stencil_state, 0, sizeof(depth_stencil_state));
1400
return intel_bo_alloc_for_data(intel,
1401
&depth_stencil_state,
1402
sizeof(depth_stencil_state),
1403
"textured video blend state");
1472
1404
}
1473
1405
1474
1406
static Bool
1928
1860
int box_x2 = pbox->x2;
1929
1861
int box_y2 = pbox->y2;
1930
1862
int i;
1931
drm_intel_bo *vb_bo;
1932
float *vb;
1863
float vb[12];
1933
1864
drm_intel_bo *bo_table[] = {
1934
1865
NULL, /* vb_bo */
1935
1866
intel->batch_bo,
1945
1876
1946
1877
pbox++;
1947
1878
1948
if (intel_alloc_and_map(intel, "textured video vb", 4096,
1949
&vb_bo, &vb) != 0)
1950
break;
1951
bo_table[0] = vb_bo;
1952
1953
1879
i = 0;
1954
1880
vb[i++] = (box_x2 - dxo) * src_scale_x;
1955
1881
vb[i++] = (box_y2 - dyo) * src_scale_y;
1966
1892
vb[i++] = (float)box_x1 + pix_xoff;
1967
1893
vb[i++] = (float)box_y1 + pix_yoff;
1968
1894
1969
drm_intel_bo_unmap(vb_bo);
1895
bo_table[0] = intel_bo_alloc_for_data(intel,
1896
vb, sizeof(vb),
1897
"video vbo");
1970
1898
1971
1899
/* If this command won't fit in the current batch, flush.
1972
1900
* Assume that it does after being flushed.
1975
1903
intel_batch_submit(scrn);
1976
1904
1977
1905
intel_batch_start_atomic(scrn, 200);
1978
emit_video_setup(scrn, surface_state_binding_table_bo, n_src_surf, pixmap, vb_bo, i * 4);
1906
emit_video_setup(scrn, surface_state_binding_table_bo, n_src_surf, pixmap, bo_table[0], i * 4);
1979
1907
intel_batch_end_atomic(scrn);
1980
1908
1981
drm_intel_bo_unreference(vb_bo);
1909
drm_intel_bo_unreference(bo_table[0]);
1982
1910
}
1983
1911
1984
1912
/* release reference once we're finished */
Loggerhead is a web-based interface for Breezy
Version: 2.0.1