2
* GRUB -- GRand Unified Bootloader
3
* Copyright (C) 2000,2001,2002,2003,2004,2005,2007,2008,2009,2010 Free Software Foundation, Inc.
5
* GRUB is free software: you can redistribute it and/or modify
6
* it under the terms of the GNU General Public License as published by
7
* the Free Software Foundation, either version 3 of the License, or
8
* (at your option) any later version.
10
* GRUB is distributed in the hope that it will be useful,
11
* but WITHOUT ANY WARRANTY; without even the implied warranty of
12
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13
* GNU General Public License for more details.
15
* You should have received a copy of the GNU General Public License
16
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
19
#include <grub/mips/yeeloong/serial.h>
20
#include <grub/mips/yeeloong/pci.h>
21
#include <grub/mips/loongson.h>
23
#include <grub/serial.h>
24
#include <grub/cs5536.h>
25
#include <grub/smbus.h>
31
.global start,_start,__start
37
/* Find CS5536 controller. */
38
/* $t4 chooses device in priority encoding. */
39
/* Resulting value is kept in GRUB_MACHINE_PCI_CONF_CTRL_REG.
40
This way we don't need to sacrifice a register for it. */
41
/* We have only one bus (0). Function is 0. */
42
lui $t0, %hi(GRUB_MACHINE_PCI_CONF_CTRL_REG_ADDR)
43
lui $t1, %hi(GRUB_MACHINE_PCI_CONFSPACE)
44
lui $t3, %hi(GRUB_CS5536_PCIID)
45
addiu $t3, $t3, %lo(GRUB_CS5536_PCIID)
47
lui $a0, %hi(no_cs5536)
49
andi $t4, $t4, ((1 << GRUB_PCI_NUM_DEVICES) - 1)
50
beql $t4, $zero, fatal
51
addiu $a0, $a0, %lo(no_cs5536)
52
sw $t4, %lo(GRUB_MACHINE_PCI_CONF_CTRL_REG_ADDR) ($t0)
53
lw $t2, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_PCI_REG_PCI_ID) ($t1)
58
addiu $a0, $a0, %lo(cs5536_found)
62
/* Initialise SMBus controller. */
64
lui $a0, %hi(GRUB_CS5536_MSR_GPIO_BAR)
65
addiu $a0, $a0, %lo(GRUB_CS5536_MSR_GPIO_BAR)
66
ori $a1, $zero, GRUB_CS5536_LBAR_GPIO
67
/* Set mask to 0xf and enabled bit to 1. */
69
ori $a2, $zero, ((GRUB_CS5536_LBAR_MASK_MASK \
70
| GRUB_CS5536_LBAR_ENABLE) >> 32)
73
lui $a0, %hi(GRUB_CS5536_MSR_SMB_BAR)
74
addiu $a0, $a0, %lo(GRUB_CS5536_MSR_SMB_BAR)
75
ori $a1, $zero, GRUB_CS5536_LBAR_SMBUS
76
/* Set mask to 0xf and enabled bit to 1. */
78
ori $a2, $zero, ((GRUB_CS5536_LBAR_MASK_MASK \
79
| GRUB_CS5536_LBAR_ENABLE) >> 32)
81
lui $a0, %hi(smbus_enabled)
83
addiu $a0, $a0, %lo(smbus_enabled)
85
/* Enable SMBus controller pins. */
86
lui $t0, %hi(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO)
87
ori $t1, $zero, GRUB_GPIO_SMBUS_PINS
88
sw $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO + GRUB_GPIO_REG_OUT_EN) ($t0)
89
sw $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO + GRUB_GPIO_REG_OUT_AUX1) ($t0)
90
sw $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO + GRUB_GPIO_REG_IN_EN) ($t0)
91
sw $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO + GRUB_GPIO_REG_IN_AUX1) ($t0)
93
lui $t0, %hi(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS)
96
sb $zero, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL2) ($t0)
98
/* Disable interrupts. */
99
sb $zero, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1) ($t0)
102
sb $zero, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_ADDR) ($t0)
104
/* Launch SMBus controller at slowest speed possible. */
106
sb $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL3) ($t0)
107
sb $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL2) ($t0)
109
/* Yeeloong has only one memory slot. */
110
/* Output first byte on serial for debugging. */
111
ori $a1, $zero, GRUB_SMB_RAM_START_ADDR
118
ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_TYPE_ADDR
119
ori $t0, $zero, GRUB_SMBUS_SPD_MEMORY_TYPE_DDR2
120
lui $a0, %hi(unimplemented_memory_type)
122
addiu $a0, $a0, %hi(unimplemented_memory_type)
124
/* And here is our goal: DDR2 controller initialisation. */
125
lui $t0, %hi(GRUB_CPU_LOONGSON_CORECFG)
126
ld $t1, %lo(GRUB_CPU_LOONGSON_CORECFG) ($t0)
127
/* Use addiu for sign-extension. */
128
addiu $t2, $zero, ~(GRUB_CPU_LOONGSON_CORECFG_DISABLE_DDR2_SPACE|GRUB_CPU_LOONGSON_CORECFG_BUFFER_CPU)
130
sd $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
134
. = start + GRUB_CPU_LOONGSON_FLASH_TLB_REFILL - GRUB_CPU_LOONGSON_FLASH_START
136
mfc0 $s1, GRUB_CPU_LOONGSON_COP0_EPC
137
mfc0 $s2, GRUB_CPU_LOONGSON_COP0_BADVADDR
141
addiu $a0, $a0, %lo(epc)
146
lui $a0, %hi(badvaddr)
148
addiu $a0, $a0, %lo(badvaddr)
153
lui $a0, %hi(return_msg)
155
addiu $a0, $a0, %lo(return_msg)
160
lui $a0, %hi(newline)
162
addiu $a0, $a0, %lo(newline)
164
lui $a0, %hi(unhandled_tlb_refill)
166
addiu $a0, $a0, %lo(unhandled_tlb_refill)
168
. = start + GRUB_CPU_LOONGSON_FLASH_CACHE_ERROR - GRUB_CPU_LOONGSON_FLASH_START
170
lui $a0, %hi(unhandled_cache_error)
172
addiu $a0, $a0, %lo(unhandled_cache_error)
174
. = start + GRUB_CPU_LOONGSON_FLASH_OTHER_EXCEPTION - GRUB_CPU_LOONGSON_FLASH_START
176
mfc0 $s0, GRUB_CPU_LOONGSON_COP0_CAUSE
177
mfc0 $s1, GRUB_CPU_LOONGSON_COP0_EPC
178
mfc0 $s2, GRUB_CPU_LOONGSON_COP0_BADVADDR
181
addiu $a0, $a0, %lo(cause)
188
addiu $a0, $a0, %lo(epc)
193
lui $a0, %hi(badvaddr)
195
addiu $a0, $a0, %lo(badvaddr)
200
lui $a0, %hi(newline)
202
addiu $a0, $a0, %lo(newline)
204
lui $a0, %hi(unhandled_exception)
206
addiu $a0, $a0, %lo(unhandled_exception)
208
/* Same as similarly named C function but in asm since
210
/* In: none. Out: none. Clobbered: $t0, $t1, $a0. */
212
lui $t0, %hi (GRUB_MACHINE_SERIAL_PORT)
214
/* Turn off the interrupt. */
215
sb $zero, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_IER)($t0)
218
ori $t1, $zero, UART_DLAB
219
sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LCR)($t0)
221
/* Set the baud rate 115200. */
222
ori $t1, $zero, GRUB_MACHINE_SERIAL_DIVISOR_115200
223
sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_DLL)($t0)
224
sb $zero, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_DLH)($t0)
226
/* Set the line status. */
227
ori $t1, $zero, (UART_NO_PARITY | UART_8BITS_WORD | UART_1_STOP_BIT)
228
sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LCR)($t0)
230
/* Enable the FIFO. */
231
ori $t1, $zero, UART_ENABLE_FIFO_TRIGGER1
232
sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_FCR)($t0)
234
/* Turn on DTR and RTS. */
235
ori $t1, $zero, UART_ENABLE_DTRRTS
236
sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_MCR)($t0)
238
/* Let message return to original caller. */
239
lui $a0, %hi(notification_string)
240
addiu $a0, $a0, %lo(notification_string)
242
/* Print message on serial console. */
243
/* In: $a0 = asciiz message. Out: none. Clobbered: $t0, $t1, $a0. */
245
lui $t0, %hi (GRUB_MACHINE_SERIAL_PORT)
247
lb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LSR)($t0)
248
andi $t1, $t1, UART_EMPTY_TRANSMITTER
252
sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_TX)($t0)
258
/* Print 32-bit hexadecimal on serial.
259
In: $a0. Out: None. Clobbered: $a0, $t0, $t1, $t2
262
lui $t0, %hi (GRUB_MACHINE_SERIAL_PORT)
265
lb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LSR)($t0)
266
andi $t1, $t1, UART_EMPTY_TRANSMITTER
273
addiu $t1, $t1, 'A'-10-'0'
274
2: addiu $t1, $t1, '0'+10
275
sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_TX)($t0)
290
In: $a0 address, $a1 lower word, $a2 upper word.
295
lui $t0, %hi(GRUB_MACHINE_PCI_CONFSPACE)
296
sw $a0, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_CS5536_MSR_MAILBOX_ADDR) ($t0)
297
sw $a1, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_CS5536_MSR_MAILBOX_DATA0) ($t0)
299
sw $a2, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_CS5536_MSR_MAILBOX_DATA1) ($t0)
301
/* Wait for SMBus data or empty transmitter. */
302
/* In: $a0 = exception handler. Out: none. Clobbered: $t0, $t1 */
305
lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_STATUS + GRUB_MACHINE_PCI_IO_BASE)
306
lb $t0, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_STATUS + GRUB_MACHINE_PCI_IO_BASE) ($t0)
307
andi $t1, $t0, GRUB_CS5536_SMB_REG_STATUS_SDAST
308
bne $t1, $zero, return
310
andi $t1, $t0, (GRUB_CS5536_SMB_REG_STATUS_BER | GRUB_CS5536_SMB_REG_STATUS_NACK)
319
/* Read SPD byte. In: $a0 byte, $a1 device. Out: $v0 read byte (0x100 on failure).
320
Clobbered: $t0, $t1, $t2, $t3, $a0. */
324
lui $a0, %hi(read_spd_fail)
325
addiu $a0, $a0, %hi(read_spd_fail)
328
lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
329
lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
330
ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_START
332
sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
334
/* Send device address. */
335
lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
338
sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
341
lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
342
lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
343
ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_ACK
344
sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
346
/* Send byte address. */
347
lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
349
sb $t2, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
352
lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
353
lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
354
ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_START
356
sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
358
/* Send device address. */
359
lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
363
sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
366
lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
367
lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
368
ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_STOP
370
sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
372
lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
373
lb $v0, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
380
notification_string: .asciz "GRUB "
381
no_cs5536: .asciz "No CS5536 found.\n\r"
382
cs5536_found: .asciz "CS5536 at "
383
sm_failed: .asciz "SM transaction failed.\n\r"
384
unhandled_tlb_refill: .asciz "Unhandled TLB refill.\n\r"
385
unhandled_cache_error: .asciz "Unhandled cache error.\n\r"
386
unhandled_exception: .asciz "Unhandled exception.\n\r"
387
smbus_enabled: .asciz "SMBus controller enabled.\n\r"
388
unimplemented_memory_type: .asciz "non-DDR2 memory isn't supported.\n\r"
389
no_cas_latency: .asciz "Couldn't determine CAS latency.\n\r"
390
cause: .asciz "Cause: "
391
epc: .asciz "\n\rEPC: "
392
badvaddr: .asciz "\n\rBadVaddr: "
393
newline: .asciz "\n\r"
394
return_msg: .asciz "\n\rReturn address: "
395
caches_enabled: .asciz "Caches enabled\n\r"
400
.quad 0x0100010000000101 /* 0 */
401
.quad 0x0100010100000000 /* 2 */
402
.quad 0x0101000001000000 /* 3 */
403
.quad 0x0100020200010101 /* 4 */
404
.quad 0x0a04030603050203 /* 6 */
405
.quad 0x0f0e040000010a0b /* 7 */
406
.quad 0x0000010200000102 /* 8 */
407
.quad 0x0000060c00000000 /* 9 */
408
.quad 0x2323233f3f1f0200 /* a */
409
.quad 0x5f7f232323232323 /* b */
410
.quad 0x002a3c0615000000 /* c */
411
.quad 0x002a002a002a002a /* d */
412
.quad 0x002a002a002a002a /* e */
413
.quad 0x00b40020006d0004 /* f */
414
.quad 0x070007ff00000087 /* 10 */
415
.quad 0x000000000016101f /* 11 */
416
.quad 0x001c000000000000 /* 12 */
417
.quad 0x28e1000200c8006b /* 13 */
418
.quad 0x0000204200c8002f /* 14 */
419
.quad 0x0000000000030d40 /* 15 */
433
addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
435
addiu $t6, $t6, GRUB_CPU_LOONGSON_DDR2_REG_SIZE
438
lui $t4, %hi(GRUB_CPU_LOONGSON_DDR2_BASE)
439
addiu $t4, $t4, %lo(GRUB_CPU_LOONGSON_DDR2_BASE)
440
lui $t6, %hi(regdump)
444
addiu $t6, $t6, %lo(regdump)
447
ori $a1, $a1, GRUB_SMB_RAM_START_ADDR
451
ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_BANKS_ADDR
455
ori $t8, $t8, GRUB_CPU_LOONGSON_DDR2_REG1_HI_8BANKS
460
addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
475
/* FIXME: figure termination resistance. */
478
ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_ROWS_ADDR
479
/* $v0 = 15 - $v0. */
485
/* Find the fastest supported CAS latency. */
487
ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_ADDR
488
ori $t0, $zero, GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_MIN_VALUE
489
ori $t1, $zero, (1 << GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_MIN_VALUE)
494
lui $a0, %hi(no_cas_latency)
496
addiu $a0, $a0, %lo(no_cas_latency)
505
ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_COLUMNS_ADDR
506
/* $v0 = 15 - ($v0 + 1) = 14 - $v0. */
514
addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
521
addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
524
addiu $t6, $t6, GRUB_CPU_LOONGSON_DDR2_REG_SIZE
526
lui $t4, %hi(GRUB_CPU_LOONGSON_DDR2_BASE)
527
ld $t5, (%lo(GRUB_CPU_LOONGSON_DDR2_BASE) + 0x30) ($t4)
531
sd $t5, (%lo(GRUB_CPU_LOONGSON_DDR2_BASE) + 0x30) ($t4)
533
/* Desactivate DDR2 registers. */
534
lui $t0, %hi (GRUB_CPU_LOONGSON_CORECFG)
535
ld $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
536
ori $t1, $t1, GRUB_CPU_LOONGSON_CORECFG_DISABLE_DDR2_SPACE
537
sd $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
540
mfc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
541
addiu $t1, $zero, ~GRUB_CPU_LOONGSON_CACHE_TYPE_MASK
543
/* Set line size to 32 bytes and disabled cache. */
544
ori $t0, $t0, (GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG_ILINESIZE \
545
| GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG_DLINESIZE \
546
| GRUB_CPU_LOONGSON_CACHE_ACCELERATED)
547
mtc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
549
/* Invalidate all I-cache entries. */
550
srl $t1, $t0, GRUB_CPU_LOONGSON_COP0_CACHE_ISIZE_SHIFT
551
andi $t1, $t1, GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_MASK
552
ori $t2, $zero, (1 << (GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_OFFSET \
553
- GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
554
- GRUB_CPU_LOONGSON_I_CACHE_LOG_WAYS))
559
cache GRUB_CPU_LOONGSON_COP0_I_INDEX_INVALIDATE, 0($t2)
562
addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_I_INDEX_BIT_OFFSET)
564
/* Invalidate all D-cache entries. */
565
srl $t1, $t0, GRUB_CPU_LOONGSON_COP0_CACHE_DSIZE_SHIFT
566
andi $t1, $t1, GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_MASK
567
ori $t2, $zero, (1 << (GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_OFFSET \
568
- GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
569
- GRUB_CPU_LOONGSON_D_CACHE_LOG_WAYS))
572
mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGLO
573
mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGHI
576
cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 0($t2)
577
cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 1($t2)
578
cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 2($t2)
579
cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 3($t2)
582
addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_D_INDEX_BIT_OFFSET)
584
/* Invalidate all S-cache entries. */
585
ori $t1, $zero, (1 << (GRUB_CPU_LOONGSON_SECONDARY_CACHE_LOG_SIZE \
586
- GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
587
- GRUB_CPU_LOONGSON_S_CACHE_LOG_WAYS))
589
mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGLO
590
mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGHI
593
cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 0($t2)
594
cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 1($t2)
595
cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 2($t2)
596
cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 3($t2)
599
addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_D_INDEX_BIT_OFFSET)
601
/* Finally enable cache. */
602
mfc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
603
addiu $t1, $zero, ~GRUB_CPU_LOONGSON_CACHE_TYPE_MASK
605
ori $t0, $t0, GRUB_CPU_LOONGSON_CACHE_CACHED
606
mtc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
608
lui $a0, %hi(caches_enabled)
610
addiu $a0, $a0, %lo(caches_enabled)
612
/* Set ROM delay cycles to 1. */
613
lui $t0, %hi(GRUB_CPU_LOONGSON_LIOCFG)
614
lw $t1, %lo(GRUB_CPU_LOONGSON_LIOCFG) ($t0)
615
addiu $t2, $zero, ~(GRUB_CPU_LOONGSON_ROM_DELAY_MASK \
616
<< GRUB_CPU_LOONGSON_ROM_DELAY_OFFSET)
618
ori $t1, $t1, (1 << GRUB_CPU_LOONGSON_ROM_DELAY_OFFSET)
619
sw $t1, %lo(GRUB_CPU_LOONGSON_LIOCFG) ($t0)
624
/* Take advantage of cache. */
625
lui $t0, %hi(cached_continue - 0x20000000)
626
addiu $t0, $t0, %lo(cached_continue - 0x20000000)
b'\\ No newline at end of file'