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  • Committer: Package Import Robot
  • Author(s): Cyril Brulebois, Timo Aaltonen
  • Date: 2011-11-19 12:46:57 UTC
  • mfrom: (26.1.11 sid)
  • Revision ID: package-import@ubuntu.com-20111119124657-zpht20ygj578uqwn
Tags: 2:2.17.0-1
http://bugs.debian.org/635953
[ Timo Aaltonen ]
New upstream release. (Closes: #635953)

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src/intel_batchbuffer.c
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#include "i915_drm.h"
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#include "i965_reg.h"
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#include "uxa.h"
 
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#define DUMP_BATCHBUFFERS NULL // "/tmp/i915-batchbuffers.dump"
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static void intel_end_vertex(intel_screen_private *intel)
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                list_del(intel->flush_pixmaps.next);
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}
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static void intel_emit_post_sync_nonzero_flush(ScrnInfoPtr scrn)
 
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{
 
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        intel_screen_private *intel = intel_get_screen_private(scrn);
 
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        /* keep this entire sequence of 3 PIPE_CONTROL cmds in one batch to
 
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         * avoid upsetting the gpu. */
 
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        BEGIN_BATCH(3*4);
 
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        OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
 
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        OUT_BATCH(BRW_PIPE_CONTROL_CS_STALL |
 
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                  BRW_PIPE_CONTROL_STALL_AT_SCOREBOARD);
 
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        OUT_BATCH(0); /* address */
 
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        OUT_BATCH(0); /* write data */
 
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        OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
 
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        OUT_BATCH(BRW_PIPE_CONTROL_WRITE_QWORD);
 
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        OUT_RELOC(intel->wa_scratch_bo,
 
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                  I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
 
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        OUT_BATCH(0); /* write data */
 
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        /* now finally the _real flush */
 
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        OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
 
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        OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH |
 
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                  BRW_PIPE_CONTROL_TC_FLUSH |
 
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                  BRW_PIPE_CONTROL_NOWRITE);
 
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        OUT_BATCH(0); /* write address */
 
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        OUT_BATCH(0); /* write data */
 
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        ADVANCE_BATCH();
 
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}
 
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void intel_batch_emit_flush(ScrnInfoPtr scrn)
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{
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        intel_screen_private *intel = intel_get_screen_private(scrn);
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                        OUT_BATCH(0);
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                        ADVANCE_BATCH();
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                } else  {
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                        BEGIN_BATCH(4);
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                        OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
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                        OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH |
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                                  BRW_PIPE_CONTROL_TC_FLUSH |
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                                  BRW_PIPE_CONTROL_NOWRITE);
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                        OUT_BATCH(0); /* write address */
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                        OUT_BATCH(0); /* write data */
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                        ADVANCE_BATCH();
 
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                        if ((INTEL_INFO(intel)->gen == 60)) {
 
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                                /* HW-Workaround for Sandybdrige */
 
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                                intel_emit_post_sync_nonzero_flush(scrn);
 
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                        } else {
 
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                                BEGIN_BATCH(4);
 
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                                OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
 
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                                OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH |
 
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                                          BRW_PIPE_CONTROL_TC_FLUSH |
 
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                                          BRW_PIPE_CONTROL_NOWRITE);
 
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                                OUT_BATCH(0); /* write address */
 
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                                OUT_BATCH(0); /* write data */
 
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                                ADVANCE_BATCH();
 
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                        }
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                }
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        } else {
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                flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;