3
This file #defines the internal register addresses for ATMEGA603.
11
/*==========================*/
12
/* Predefined SFR Addresses */
13
/*==========================*/
15
/* Input Pins, Port F */
18
/* Input Pins, Port E */
21
/* Data Direction Register, Port E */
24
/* Data Register, Port E */
31
/* ADC Control and status register */
34
/* ADC Multiplexer select */
37
/* Analog Comparator Control and Status Register */
40
/* UART Baud Rate Register */
43
/* UART Control Register */
46
/* UART Status Register */
49
/* UART I/O Data Register */
52
/* SPI Control Register */
55
/* SPI Status Register */
58
/* SPI I/O Data Register */
61
/* Input Pins, Port D */
64
/* Data Direction Register, Port D */
67
/* Data Register, Port D */
70
/* Data Register, Port C */
73
/* Input Pins, Port B */
76
/* Data Direction Register, Port B */
79
/* Data Register, Port B */
82
/* Input Pins, Port A */
85
/* Data Direction Register, Port A */
88
/* Data Register, Port A */
91
/* EEPROM Control Register */
94
/* EEPROM Data Register */
97
/* EEPROM Address Register */
101
/* Watchdog Timer Control Register */
104
/* Timer2 Output Compare Register */
107
/* Timer/Counter 2 */
110
/* Timer/Counter 2 Control register */
113
/* T/C 1 Input Capture Register */
117
/* Timer/Counter1 Output Compare Register B */
121
/* Timer/Counter1 Output Compare Register A */
125
/* Timer/Counter 1 */
129
/* Timer/Counter 1 Control and Status Register */
132
/* Timer/Counter 1 Control Register */
135
/* Timer/Counter 0 Asynchronous Control & Status Register */
138
/* Output Compare Register 0 */
141
/* Timer/Counter 0 */
144
/* Timer/Counter 0 Control Register */
147
/* MCU Status Register */
150
/* MCU general Control Register */
153
/* Timer/Counter Interrupt Flag Register */
156
/* Timer/Counter Interrupt MaSK register */
159
/* �xternal Interrupt Flag Register */
162
/* External Interrupt MaSK register */
165
/* External Interrupt Control Register */
168
/* RAM Page Z select register */
169
/* #define RAMPZ 0x3B */
171
/* XDIV Divide control register */
178
/* Status REGister */
182
/*==============================*/
183
/* Interrupt Vector Definitions */
184
/*==============================*/
186
#define SIG_INTERRUPT0 _vector_1
187
#define SIG_INTERRUPT1 _vector_2
188
#define SIG_INTERRUPT2 _vector_3
189
#define SIG_INTERRUPT3 _vector_4
190
#define SIG_INTERRUPT4 _vector_5
191
#define SIG_INTERRUPT5 _vector_6
192
#define SIG_INTERRUPT6 _vector_7
193
#define SIG_INTERRUPT7 _vector_8
194
#define SIG_OUTPUT_COMPARE2 _vector_9
195
#define SIG_OVERFLOW2 _vector_10
196
#define SIG_INPUT_CAPTURE1 _vector_11
197
#define SIG_OUTPUT_COMPARE1A _vector_12
198
#define SIG_OUTPUT_COMPARE1B _vector_13
199
#define SIG_OVERFLOW1 _vector_14
200
#define SIG_OUTPUT_COMPARE0 _vector_15
201
#define SIG_OVERFLOW0 _vector_16
202
#define SIG_SPI _vector_17
203
#define SIG_UART_RECV _vector_18
204
#define SIG_UART_DATA _vector_19
205
#define SIG_UART_TRANS _vector_20
206
#define SIG_ADC _vector_21
207
#define SIG_EEPROM_READY _vector_22
208
#define SIG_COMPARATOR _vector_23
210
#define END_VECTOR (23)
211
#define INT_VECT_SIZE (0x60)
214
The Register Bit names are represented by their bit number (0-7).
217
/* XDIV Divide control register*/
227
/* RAM Page Z select register */
228
/* #define RAMPZ0 0 */
230
/* External Interrupt Control Register */
240
/* External Interrupt MaSK register */
250
/* �xternal Interrupt Flag Register */
256
/* Timer/Counter Interrupt MaSK register */
266
/* Timer/Counter Interrupt Flag Register */
276
/* MCU general Control Register */
283
/* MCU Status Register */
287
/* Timer/Counter 0 Control Register */
296
/* Timer/Counter 0 Asynchronous Control & Status Register */
302
/* Timer/Counter 1 Control Register */
310
/* Timer/Counter 1 Control and Status Register */
318
/* Timer/Counter 2 Control register */
327
/* Watchdog Timer Control Register */
334
/* EEPROM Control Register */
340
/* Data Register, Port A */
350
/* Data Direction Register, Port A */
360
/* Input Pins, Port A */
370
/* Data Register, Port B */
380
/* Data Direction Register, Port B */
390
/* Input Pins, Port B */
400
/* Data Register, Port C */
410
/* Data Register, Port D */
420
/* Data Direction Register, Port D */
430
/* Input Pins, Port D */
440
/* Data Register, Port E */
450
/* Data Direction Register, Port E */
460
/* Input Pins, Port E */
470
/* Input Pins, Port F */
480
/* SPI Status Register */
484
/* SPI Control Register */
494
/* UART Status Register */
499
#define OVR 3 /*This definition differs from the databook */
500
/*definition to avoid problems with the OR instruction */
502
/* UART Control Register */
512
/* Analog Comparator Control and Status Register */
521
/* ADC Control and status register */
531
/* ADC Multiplexer select */
536
/* Pointer definition */
545
#define RAMEND 0x0FFF /*Last On-Chip SRAM Location*/
546
#define XRAMEND 0xFFFF
548
#define FLASHEND 0xFFFF
added
removed
include/iom603.h
