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: drivers/net/tg3.c
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- Committer: Bazaar Package Importer
- Author(s): Ben Collins
- Date: 2007-10-22 10:08:49 UTC
- mfrom: (35.1.5 dapper-security)
- Revision ID: james.westby@ubuntu.com-20071022100849-jux4812fgj01wu02
Tags: 2.6.15-51.61
* Fix for kernel crash on lvremove
- LP: #103729
* e1000: Disable MSI by default. Allow it to be enabled with module param.
Some chip implementations seem to not work well with MSI.
- LP: #56885
* tg3: Backport from 2.6.16.y
- LP: #72696
* Add r1000 to nic-modules
- LP: #81782
* Add bnx2 to nic-modules
- LP: #73647
* usb-serial: Fix oops with pilot-link
- LP: #39518
* megaraid: Move AMI/Megaraid3 IDs from megaraid_mbox.ko to megaraid.ko
- LP: #57233
- LP: #103729
* e1000: Disable MSI by default. Allow it to be enabled with module param.
Some chip implementations seem to not work well with MSI.
- LP: #56885
* tg3: Backport from 2.6.16.y
- LP: #72696
* Add r1000 to nic-modules
- LP: #81782
* Add bnx2 to nic-modules
- LP: #73647
* usb-serial: Fix oops with pilot-link
- LP: #39518
* megaraid: Move AMI/Megaraid3 IDs from megaraid_mbox.ko to megaraid.ko
- LP: #57233
- files added:
- debian/abi
- debian/abi/2.6.15-29.59
- debian/abi/2.6.15-29.59/amd64
- debian/abi/2.6.15-29.59/hppa
- debian/abi/2.6.15-29.59/i386
- debian/abi/2.6.15-29.59/ia64
- debian/abi/2.6.15-29.59/powerpc
- debian/abi/2.6.15-29.59/sparc
- files removed:
- drivers/net/netdriver_compat.h
- files modified:
- Documentation/networking/ip-sysctl.txt
added
removed
drivers/net/tg3.c
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* notice is accompanying it.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#define TG3_VLAN_TAG_USED 0
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#endif
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#if 0
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#ifdef NETIF_F_TSO
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#define TG3_TSO_SUPPORT 1
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#else
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#define TG3_TSO_SUPPORT 0
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#include "tg3.h"
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#include "netdriver_compat.h"
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "3.69"
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#define DRV_MODULE_RELDATE "November 15, 2006"
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#define DRV_MODULE_VERSION "3.49"
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#define DRV_MODULE_RELDATE "Feb 2, 2006"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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TG3_RX_RCB_RING_SIZE(tp))
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#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
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TG3_TX_RING_SIZE)
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#define TX_BUFFS_AVAIL(TP) \
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((TP)->tx_pending - \
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(((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
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#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
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#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
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#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
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/* minimum number of free TX descriptors required to wake up TX process */
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#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
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#define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
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/* number of ETHTOOL_GSTATS u64's */
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#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
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MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
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static struct pci_device_id tg3_pci_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
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{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
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{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
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{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
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{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
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{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
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{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
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{PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
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{}
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
230
{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
231
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
232
{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
234
{ PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
235
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
236
{ PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
237
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238
{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
239
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240
{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
241
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
242
{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
243
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
244
{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
245
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
246
{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
247
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
248
{ 0, }
214
249
};
215
250
216
251
MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
217
252
218
static const struct {
253
static struct {
219
254
const char string[ETH_GSTRING_LEN];
220
255
} ethtool_stats_keys[TG3_NUM_STATS] = {
221
256
{ "rx_octets" },
296
331
{ "nic_tx_threshold_hit" }
297
332
};
298
333
299
static const struct {
334
static struct {
300
335
const char string[ETH_GSTRING_LEN];
301
336
} ethtool_test_keys[TG3_NUM_TEST] = {
302
337
{ "nvram test (online) " },
314
349
315
350
static u32 tg3_read32(struct tg3 *tp, u32 off)
316
351
{
317
return (readl(tp->regs + off));
352
return (readl(tp->regs + off));
318
353
}
319
354
320
355
static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
430
465
readl(mbox);
431
466
}
432
467
433
static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
434
{
435
return (readl(tp->regs + off + GRCMBOX_BASE));
436
}
437
438
static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
439
{
440
writel(val, tp->regs + off + GRCMBOX_BASE);
441
}
442
443
468
#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
444
469
#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
445
470
#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
455
480
{
456
481
unsigned long flags;
457
482
458
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
459
(off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
460
return;
461
462
483
spin_lock_irqsave(&tp->indirect_lock, flags);
463
if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
464
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
465
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
466
467
/* Always leave this as zero. */
468
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
469
} else {
470
tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
471
tw32_f(TG3PCI_MEM_WIN_DATA, val);
472
473
/* Always leave this as zero. */
474
tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
475
}
484
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
485
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
486
487
/* Always leave this as zero. */
488
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
476
489
spin_unlock_irqrestore(&tp->indirect_lock, flags);
477
490
}
478
491
492
static void tg3_write_mem_fast(struct tg3 *tp, u32 off, u32 val)
493
{
494
/* If no workaround is needed, write to mem space directly */
495
if (tp->write32 != tg3_write_indirect_reg32)
496
tw32(NIC_SRAM_WIN_BASE + off, val);
497
else
498
tg3_write_mem(tp, off, val);
499
}
500
479
501
static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
480
502
{
481
503
unsigned long flags;
482
504
483
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
484
(off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
485
*val = 0;
486
return;
487
}
488
489
505
spin_lock_irqsave(&tp->indirect_lock, flags);
490
if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
491
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
492
pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
493
494
/* Always leave this as zero. */
495
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
496
} else {
497
tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
498
*val = tr32(TG3PCI_MEM_WIN_DATA);
499
500
/* Always leave this as zero. */
501
tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
502
}
506
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507
pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
508
509
/* Always leave this as zero. */
510
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
503
511
spin_unlock_irqrestore(&tp->indirect_lock, flags);
504
512
}
505
513
515
523
if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
516
524
(tp->hw_status->status & SD_STATUS_UPDATED))
517
525
tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
518
else
519
tw32(HOSTCC_MODE, tp->coalesce_mode |
520
(HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
521
526
}
522
527
523
528
static void tg3_enable_ints(struct tg3 *tp)
529
534
(tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
530
535
tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
531
536
(tp->last_tag << 24));
532
if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
533
tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
534
(tp->last_tag << 24));
535
537
tg3_cond_int(tp);
536
538
}
537
539
558
560
/* tg3_restart_ints
559
561
* similar to tg3_enable_ints, but it accurately determines whether there
560
562
* is new work pending and can return without flushing the PIO write
561
* which reenables interrupts
563
* which reenables interrupts
562
564
*/
563
565
static void tg3_restart_ints(struct tg3 *tp)
564
566
{
647
649
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
648
650
MI_COM_REG_ADDR_MASK);
649
651
frame_val |= (MI_COM_CMD_READ | MI_COM_START);
650
652
651
653
tw32_f(MAC_MI_COM, frame_val);
652
654
653
655
loops = PHY_BUSY_LOOPS;
683
685
unsigned int loops;
684
686
int ret;
685
687
686
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
687
(reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
688
return 0;
689
690
688
if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
691
689
tw32_f(MAC_MI_MODE,
692
690
(tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
699
697
MI_COM_REG_ADDR_MASK);
700
698
frame_val |= (val & MI_COM_DATA_MASK);
701
699
frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
702
700
703
701
tw32_f(MAC_MI_COM, frame_val);
704
702
705
703
loops = PHY_BUSY_LOOPS;
950
948
return err;
951
949
}
952
950
953
static void tg3_link_report(struct tg3 *);
954
955
951
/* This will reset the tigon3 PHY if there is no valid
956
952
* link unless the FORCE argument is non-zero.
957
953
*/
965
961
if (err != 0)
966
962
return -EBUSY;
967
963
968
if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
969
netif_carrier_off(tp->dev);
970
tg3_link_report(tp);
971
}
972
973
964
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
974
965
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
975
966
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1006
997
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1007
998
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1008
999
}
1009
else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1010
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1011
tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1012
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1013
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1014
}
1015
1000
/* Set Extended packet length bit (bit 14) on all chips that */
1016
1001
/* support jumbo frames */
1017
1002
if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1037
1022
phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1038
1023
}
1039
1024
1040
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1041
u32 phy_reg;
1042
1043
/* adjust output voltage */
1044
tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1045
1046
if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1047
u32 phy_reg2;
1048
1049
tg3_writephy(tp, MII_TG3_EPHY_TEST,
1050
phy_reg | MII_TG3_EPHY_SHADOW_EN);
1051
/* Enable auto-MDIX */
1052
if (!tg3_readphy(tp, 0x10, &phy_reg2))
1053
tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1054
tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1055
}
1056
}
1057
1058
1025
tg3_phy_set_wirespeed(tp);
1059
1026
return 0;
1060
1027
}
1071
1038
struct net_device *dev_peer;
1072
1039
1073
1040
dev_peer = pci_get_drvdata(tp->pdev_peer);
1074
/* remove_one() may have been run on the peer. */
1075
1041
if (!dev_peer)
1076
tp_peer = tp;
1077
else
1078
tp_peer = netdev_priv(dev_peer);
1042
BUG();
1043
tp_peer = netdev_priv(dev_peer);
1079
1044
}
1080
1045
1081
1046
if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1166
1131
static int tg3_nvram_lock(struct tg3 *);
1167
1132
static void tg3_nvram_unlock(struct tg3 *);
1168
1133
1169
static void tg3_power_down_phy(struct tg3 *tp)
1170
{
1171
if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1172
return;
1173
1174
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1175
tg3_writephy(tp, MII_TG3_EXT_CTRL,
1176
MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1177
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1178
}
1179
1180
/* The PHY should not be powered down on some chips because
1181
* of bugs.
1182
*/
1183
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1184
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1185
(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1186
(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1187
return;
1188
tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1189
}
1190
1191
static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1134
static int tg3_set_power_state(struct tg3 *tp, int state)
1192
1135
{
1193
1136
u32 misc_host_ctrl;
1194
1137
u16 power_control, power_caps;
1207
1150
power_control |= PCI_PM_CTRL_PME_STATUS;
1208
1151
power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1209
1152
switch (state) {
1210
case PCI_D0:
1153
case 0:
1211
1154
power_control |= 0;
1212
1155
pci_write_config_word(tp->pdev,
1213
1156
pm + PCI_PM_CTRL,
1220
1163
1221
1164
return 0;
1222
1165
1223
case PCI_D1:
1166
case 1:
1224
1167
power_control |= 1;
1225
1168
break;
1226
1169
1227
case PCI_D2:
1170
case 2:
1228
1171
power_control |= 2;
1229
1172
break;
1230
1173
1231
case PCI_D3hot:
1174
case 3:
1232
1175
power_control |= 3;
1233
1176
break;
1234
1177
1259
1202
tg3_setup_phy(tp, 0);
1260
1203
}
1261
1204
1262
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1263
u32 val;
1264
1265
val = tr32(GRC_VCPU_EXT_CTRL);
1266
tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1267
} else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1205
if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1268
1206
int i;
1269
1207
u32 val;
1270
1208
1288
1226
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1289
1227
udelay(40);
1290
1228
1291
if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1292
mac_mode = MAC_MODE_PORT_MODE_GMII;
1293
else
1294
mac_mode = MAC_MODE_PORT_MODE_MII;
1229
mac_mode = MAC_MODE_PORT_MODE_MII;
1295
1230
1296
1231
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1297
1232
!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1369
1304
}
1370
1305
1371
1306
if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1372
!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1373
tg3_power_down_phy(tp);
1307
!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1308
/* Turn off the PHY */
1309
if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1310
tg3_writephy(tp, MII_TG3_EXT_CTRL,
1311
MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1312
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1313
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
1314
tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1315
}
1316
}
1374
1317
1375
1318
tg3_frob_aux_power(tp);
1376
1319
1391
1334
}
1392
1335
}
1393
1336
1394
tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1395
1396
1337
/* Finally, set the new power state. */
1397
1338
pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1398
1339
udelay(100); /* Delay after power state change */
1399
1340
1341
tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1342
1400
1343
return 0;
1401
1344
}
1402
1345
1483
1426
if (old_rx_mode != tp->rx_mode) {
1484
1427
tw32_f(MAC_RX_MODE, tp->rx_mode);
1485
1428
}
1486
1429
1487
1430
if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1488
1431
tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1489
1432
else
1528
1471
break;
1529
1472
1530
1473
default:
1531
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1532
*speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1533
SPEED_10;
1534
*duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1535
DUPLEX_HALF;
1536
break;
1537
}
1538
1474
*speed = SPEED_INVALID;
1539
1475
*duplex = DUPLEX_INVALID;
1540
1476
break;
1817
1753
1818
1754
if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1819
1755
tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1820
else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1756
else
1821
1757
tg3_writephy(tp, MII_TG3_IMASK, ~0);
1822
1758
1823
1759
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2474
2410
expected_sg_dig_ctrl |= (1 << 12);
2475
2411
2476
2412
if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2477
if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2478
tp->serdes_counter &&
2479
((mac_status & (MAC_STATUS_PCS_SYNCED |
2480
MAC_STATUS_RCVD_CFG)) ==
2481
MAC_STATUS_PCS_SYNCED)) {
2482
tp->serdes_counter--;
2483
current_link_up = 1;
2484
goto out;
2485
}
2486
restart_autoneg:
2487
2413
if (workaround)
2488
2414
tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2489
2415
tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2490
2416
udelay(5);
2491
2417
tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2492
2418
2493
tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2494
tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2419
tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2495
2420
} else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2496
2421
MAC_STATUS_SIGNAL_DET)) {
2497
sg_dig_status = tr32(SG_DIG_STATUS);
2422
int i;
2423
2424
/* Giver time to negotiate (~200ms) */
2425
for (i = 0; i < 40000; i++) {
2426
sg_dig_status = tr32(SG_DIG_STATUS);
2427
if (sg_dig_status & (0x3))
2428
break;
2429
udelay(5);
2430
}
2498
2431
mac_status = tr32(MAC_STATUS);
2499
2432
2500
2433
if ((sg_dig_status & (1 << 1)) &&
2510
2443
2511
2444
tg3_setup_flow_control(tp, local_adv, remote_adv);
2512
2445
current_link_up = 1;
2513
tp->serdes_counter = 0;
2514
tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2446
tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2515
2447
} else if (!(sg_dig_status & (1 << 1))) {
2516
if (tp->serdes_counter)
2517
tp->serdes_counter--;
2448
if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2449
tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2518
2450
else {
2519
2451
if (workaround) {
2520
2452
u32 val = serdes_cfg;
2538
2470
!(mac_status & MAC_STATUS_RCVD_CFG)) {
2539
2471
tg3_setup_flow_control(tp, 0, 0);
2540
2472
current_link_up = 1;
2541
tp->tg3_flags2 |=
2542
TG3_FLG2_PARALLEL_DETECT;
2543
tp->serdes_counter =
2544
SERDES_PARALLEL_DET_TIMEOUT;
2545
} else
2546
goto restart_autoneg;
2473
}
2547
2474
}
2548
2475
}
2549
} else {
2550
tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2551
tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2552
2476
}
2553
2477
2554
2478
out:
2567
2491
if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2568
2492
u32 flags;
2569
2493
int i;
2570
2494
2571
2495
if (fiber_autoneg(tp, &flags)) {
2572
2496
u32 local_adv, remote_adv;
2573
2497
2679
2603
MAC_STATUS_CFG_CHANGED));
2680
2604
udelay(5);
2681
2605
if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2682
MAC_STATUS_CFG_CHANGED |
2683
MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2606
MAC_STATUS_CFG_CHANGED)) == 0)
2684
2607
break;
2685
2608
}
2686
2609
2687
2610
mac_status = tr32(MAC_STATUS);
2688
2611
if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2689
2612
current_link_up = 0;
2690
if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2691
tp->serdes_counter == 0) {
2613
if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2692
2614
tw32_f(MAC_MODE, (tp->mac_mode |
2693
2615
MAC_MODE_SEND_CONFIGS));
2694
2616
udelay(1);
2758
2680
2759
2681
err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2760
2682
err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2761
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2762
if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2763
bmsr |= BMSR_LSTATUS;
2764
else
2765
bmsr &= ~BMSR_LSTATUS;
2766
}
2767
2683
2768
2684
err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2769
2685
2793
2709
tg3_writephy(tp, MII_BMCR, bmcr);
2794
2710
2795
2711
tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2796
tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2712
tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2797
2713
tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2798
2714
2799
2715
return err;
2832
2748
bmcr = new_bmcr;
2833
2749
err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2834
2750
err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2835
if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2836
ASIC_REV_5714) {
2837
if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2838
bmsr |= BMSR_LSTATUS;
2839
else
2840
bmsr &= ~BMSR_LSTATUS;
2841
}
2842
2751
tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2843
2752
}
2844
2753
}
2898
2807
2899
2808
static void tg3_serdes_parallel_detect(struct tg3 *tp)
2900
2809
{
2901
if (tp->serdes_counter) {
2810
if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2902
2811
/* Give autoneg time to complete. */
2903
tp->serdes_counter--;
2812
tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2904
2813
return;
2905
2814
}
2906
2815
if (!netif_carrier_ok(tp->dev) &&
2990
2899
return err;
2991
2900
}
2992
2901
2993
/* This is called whenever we suspect that the system chipset is re-
2994
* ordering the sequence of MMIO to the tx send mailbox. The symptom
2995
* is bogus tx completions. We try to recover by setting the
2996
* TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
2997
* in the workqueue.
2998
*/
2999
static void tg3_tx_recover(struct tg3 *tp)
3000
{
3001
BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3002
tp->write32_tx_mbox == tg3_write_indirect_mbox);
3003
3004
printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3005
"mapped I/O cycles to the network device, attempting to "
3006
"recover. Please report the problem to the driver maintainer "
3007
"and include system chipset information.\n", tp->dev->name);
3008
3009
spin_lock(&tp->lock);
3010
tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3011
spin_unlock(&tp->lock);
3012
}
3013
3014
static inline u32 tg3_tx_avail(struct tg3 *tp)
3015
{
3016
smp_mb();
3017
return (tp->tx_pending -
3018
((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3019
}
3020
3021
2902
/* Tigon3 never reports partial packet sends. So we do not
3022
2903
* need special logic to handle SKBs that have not had all
3023
2904
* of their frags sent yet, like SunGEM does.
3030
2911
while (sw_idx != hw_idx) {
3031
2912
struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3032
2913
struct sk_buff *skb = ri->skb;
3033
int i, tx_bug = 0;
2914
int i;
3034
2915
3035
if (unlikely(skb == NULL)) {
3036
tg3_tx_recover(tp);
3037
return;
3038
}
2916
if (unlikely(skb == NULL))
2917
BUG();
3039
2918
3040
2919
pci_unmap_single(tp->pdev,
3041
2920
pci_unmap_addr(ri, mapping),
3047
2926
sw_idx = NEXT_TX(sw_idx);
3048
2927
3049
2928
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2929
if (unlikely(sw_idx == hw_idx))
2930
BUG();
2931
3050
2932
ri = &tp->tx_buffers[sw_idx];
3051
if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3052
tx_bug = 1;
2933
if (unlikely(ri->skb != NULL))
2934
BUG();
3053
2935
3054
2936
pci_unmap_page(tp->pdev,
3055
2937
pci_unmap_addr(ri, mapping),
3060
2942
}
3061
2943
3062
2944
dev_kfree_skb(skb);
3063
3064
if (unlikely(tx_bug)) {
3065
tg3_tx_recover(tp);
3066
return;
3067
}
3068
2945
}
3069
2946
3070
2947
tp->tx_cons = sw_idx;
3071
2948
3072
/* Need to make the tx_cons update visible to tg3_start_xmit()
3073
* before checking for netif_queue_stopped(). Without the
3074
* memory barrier, there is a small possibility that tg3_start_xmit()
3075
* will miss it and cause the queue to be stopped forever.
3076
*/
3077
smp_mb();
3078
3079
if (unlikely(netif_queue_stopped(tp->dev) &&
3080
(tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3081
netif_tx_lock(tp->dev);
2949
if (unlikely(netif_queue_stopped(tp->dev))) {
2950
spin_lock(&tp->tx_lock);
3082
2951
if (netif_queue_stopped(tp->dev) &&
3083
(tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
2952
(TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
3084
2953
netif_wake_queue(tp->dev);
3085
netif_tx_unlock(tp->dev);
2954
spin_unlock(&tp->tx_lock);
3086
2955
}
3087
2956
}
3088
2957
3136
3005
* Callers depend upon this behavior and assume that
3137
3006
* we leave everything unchanged if we fail.
3138
3007
*/
3139
skb = netdev_alloc_skb(tp->dev, skb_size);
3008
skb = dev_alloc_skb(skb_size);
3140
3009
if (skb == NULL)
3141
3010
return -ENOMEM;
3142
3011
3012
skb->dev = tp->dev;
3143
3013
skb_reserve(skb, tp->rx_offset);
3144
3014
3145
3015
mapping = pci_map_single(tp->pdev, skb->data,
3232
3102
*/
3233
3103
static int tg3_rx(struct tg3 *tp, int budget)
3234
3104
{
3235
u32 work_mask, rx_std_posted = 0;
3105
u32 work_mask;
3236
3106
u32 sw_idx = tp->rx_rcb_ptr;
3237
3107
u16 hw_idx;
3238
3108
int received;
3259
3129
mapping);
3260
3130
skb = tp->rx_std_buffers[desc_idx].skb;
3261
3131
post_ptr = &tp->rx_std_ptr;
3262
rx_std_posted++;
3263
3132
} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3264
3133
dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3265
3134
mapping);
3285
3154
3286
3155
len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3287
3156
3288
if (len > RX_COPY_THRESHOLD
3157
if (len > RX_COPY_THRESHOLD
3289
3158
&& tp->rx_offset == 2
3290
3159
/* rx_offset != 2 iff this is a 5701 card running
3291
3160
* in PCI-X mode [see tg3_get_invariants()] */
3308
3177
tg3_recycle_rx(tp, opaque_key,
3309
3178
desc_idx, *post_ptr);
3310
3179
3311
copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3180
copy_skb = dev_alloc_skb(len + 2);
3312
3181
if (copy_skb == NULL)
3313
3182
goto drop_it_no_recycle;
3314
3183
3184
copy_skb->dev = tp->dev;
3315
3185
skb_reserve(copy_skb, 2);
3316
3186
skb_put(copy_skb, len);
3317
3187
pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3346
3216
3347
3217
next_pkt:
3348
3218
(*post_ptr)++;
3349
3350
if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3351
u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3352
3353
tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3354
TG3_64BIT_REG_LOW, idx);
3355
work_mask &= ~RXD_OPAQUE_RING_STD;
3356
rx_std_posted = 0;
3357
}
3358
3219
next_pkt_nopost:
3359
3220
sw_idx++;
3360
3221
sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3408
3269
/* run TX completion thread */
3409
3270
if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3410
3271
tg3_tx(tp);
3411
if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3412
netif_rx_complete(netdev);
3413
schedule_work(&tp->reset_task);
3414
return 0;
3415
}
3416
3272
}
3417
3273
3418
3274
/* run RX thread, within the bounds set by NAPI.
3473
3329
if (irq_sync)
3474
3330
tg3_irq_quiesce(tp);
3475
3331
spin_lock_bh(&tp->lock);
3332
spin_lock(&tp->tx_lock);
3476
3333
}
3477
3334
3478
3335
static inline void tg3_full_unlock(struct tg3 *tp)
3479
3336
{
3337
spin_unlock(&tp->tx_lock);
3480
3338
spin_unlock_bh(&tp->lock);
3481
3339
}
3482
3340
3483
/* One-shot MSI handler - Chip automatically disables interrupt
3484
* after sending MSI so driver doesn't have to do it.
3485
*/
3486
static irqreturn_t tg3_msi_1shot(int irq, void *dev_id, struct pt_regs *regs)
3487
{
3488
struct net_device *dev = dev_id;
3489
struct tg3 *tp = netdev_priv(dev);
3490
3491
prefetch(tp->hw_status);
3492
prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3493
3494
if (likely(!tg3_irq_sync(tp)))
3495
netif_rx_schedule(dev); /* schedule NAPI poll */
3496
3497
return IRQ_HANDLED;
3498
}
3499
3500
3341
/* MSI ISR - No need to check for interrupt sharing and no need to
3501
3342
* flush status block and interrupt mailbox. PCI ordering rules
3502
3343
* guarantee that MSI will arrive after the status block.
3608
3449
}
3609
3450
3610
3451
/* ISR for interrupt test */
3611
static irqreturn_t tg3_test_isr(int irq, void *dev_id, struct pt_regs *regs)
3452
static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3453
struct pt_regs *regs)
3612
3454
{
3613
3455
struct net_device *dev = dev_id;
3614
3456
struct tg3 *tp = netdev_priv(dev);
3616
3458
3617
3459
if ((sblk->status & SD_STATUS_UPDATED) ||
3618
3460
!(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3619
tg3_disable_ints(tp);
3461
tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3462
0x00000001);
3620
3463
return IRQ_RETVAL(1);
3621
3464
}
3622
3465
return IRQ_RETVAL(0);
3623
3466
}
3624
3467
3625
static int tg3_init_hw(struct tg3 *, int);
3468
static int tg3_init_hw(struct tg3 *);
3626
3469
static int tg3_halt(struct tg3 *, int, int);
3627
3470
3628
/* Restart hardware after configuration changes, self-test, etc.
3629
* Invoked with tp->lock held.
3630
*/
3631
static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3632
{
3633
int err;
3634
3635
err = tg3_init_hw(tp, reset_phy);
3636
if (err) {
3637
printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3638
"aborting.\n", tp->dev->name);
3639
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3640
tg3_full_unlock(tp);
3641
del_timer_sync(&tp->timer);
3642
tp->irq_sync = 0;
3643
netif_poll_enable(tp->dev);
3644
dev_close(tp->dev);
3645
tg3_full_lock(tp, 0);
3646
}
3647
return err;
3648
}
3649
3650
3471
#ifdef CONFIG_NET_POLL_CONTROLLER
3651
3472
static void tg3_poll_controller(struct net_device *dev)
3652
3473
{
3679
3500
restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3680
3501
tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3681
3502
3682
if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3683
tp->write32_tx_mbox = tg3_write32_tx_mbox;
3684
tp->write32_rx_mbox = tg3_write_flush_reg32;
3685
tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3686
tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3687
}
3688
3689
3503
tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3690
if (tg3_init_hw(tp, 1))
3691
goto out;
3504
tg3_init_hw(tp);
3692
3505
3693
3506
tg3_netif_start(tp);
3694
3507
3695
3508
if (restart_timer)
3696
3509
mod_timer(&tp->timer, jiffies + 1);
3697
3510
3698
out:
3699
3511
tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3700
3512
3701
3513
tg3_full_unlock(tp);
3725
3537
int len)
3726
3538
{
3727
3539
#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3728
if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3540
if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
3729
3541
return (((u64) mapping + len) > DMA_40BIT_MASK);
3730
3542
return 0;
3731
3543
#else
3816
3628
txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3817
3629
}
3818
3630
3819
/* hard_start_xmit for devices that don't have any bugs and
3820
* support TG3_FLG2_HW_TSO_2 only.
3821
*/
3822
3631
static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3823
3632
{
3824
3633
struct tg3 *tp = netdev_priv(dev);
3825
3634
dma_addr_t mapping;
3826
3635
u32 len, entry, base_flags, mss;
3636
int would_hit_hwbug;
3827
3637
3828
3638
len = skb_headlen(skb);
3829
3639
3830
/* We are running in BH disabled context with netif_tx_lock
3831
* and TX reclaim runs via tp->poll inside of a software
3640
/* No BH disabling for tx_lock here. We are running in BH disabled
3641
* context and TX reclaim runs via tp->poll inside of a software
3832
3642
* interrupt. Furthermore, IRQ processing runs lockless so we have
3833
3643
* no IRQ context deadlocks to worry about either. Rejoice!
3834
3644
*/
3835
if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3645
if (!spin_trylock(&tp->tx_lock))
3646
return NETDEV_TX_LOCKED;
3647
3648
if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3836
3649
if (!netif_queue_stopped(dev)) {
3837
3650
netif_stop_queue(dev);
3838
3651
3840
3653
printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3841
3654
"queue awake!\n", dev->name);
3842
3655
}
3656
spin_unlock(&tp->tx_lock);
3843
3657
return NETDEV_TX_BUSY;
3844
3658
}
3845
3659
3846
3660
entry = tp->tx_prod;
3847
3661
base_flags = 0;
3662
if (skb->ip_summed == CHECKSUM_HW)
3663
base_flags |= TXD_FLAG_TCPUDP_CSUM;
3848
3664
#if TG3_TSO_SUPPORT != 0
3849
3665
mss = 0;
3850
3666
if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3851
(mss = skb_shinfo(skb)->gso_size) != 0) {
3667
(mss = skb_shinfo(skb)->tso_size) != 0) {
3852
3668
int tcp_opt_len, ip_tcp_len;
3853
3669
3854
3670
if (skb_header_cloned(skb) &&
3857
3673
goto out_unlock;
3858
3674
}
3859
3675
3860
if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3861
mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3862
else {
3863
tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3864
ip_tcp_len = (skb->nh.iph->ihl * 4) +
3865
sizeof(struct tcphdr);
3866
3867
skb->nh.iph->check = 0;
3868
skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3869
tcp_opt_len);
3870
mss |= (ip_tcp_len + tcp_opt_len) << 9;
3871
}
3872
3873
base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3874
TXD_FLAG_CPU_POST_DMA);
3875
3876
skb->h.th->check = 0;
3877
3878
}
3879
else if (skb->ip_summed == CHECKSUM_PARTIAL)
3880
base_flags |= TXD_FLAG_TCPUDP_CSUM;
3881
#else
3882
mss = 0;
3883
if (skb->ip_summed == CHECKSUM_PARTIAL)
3884
base_flags |= TXD_FLAG_TCPUDP_CSUM;
3885
#endif
3886
#if TG3_VLAN_TAG_USED
3887
if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3888
base_flags |= (TXD_FLAG_VLAN |
3889
(vlan_tx_tag_get(skb) << 16));
3890
#endif
3891
3892
/* Queue skb data, a.k.a. the main skb fragment. */
3893
mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3894
3895
tp->tx_buffers[entry].skb = skb;
3896
pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3897
3898
tg3_set_txd(tp, entry, mapping, len, base_flags,
3899
(skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3900
3901
entry = NEXT_TX(entry);
3902
3903
/* Now loop through additional data fragments, and queue them. */
3904
if (skb_shinfo(skb)->nr_frags > 0) {
3905
unsigned int i, last;
3906
3907
last = skb_shinfo(skb)->nr_frags - 1;
3908
for (i = 0; i <= last; i++) {
3909
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3910
3911
len = frag->size;
3912
mapping = pci_map_page(tp->pdev,
3913
frag->page,
3914
frag->page_offset,
3915
len, PCI_DMA_TODEVICE);
3916
3917
tp->tx_buffers[entry].skb = NULL;
3918
pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3919
3920
tg3_set_txd(tp, entry, mapping, len,
3921
base_flags, (i == last) | (mss << 1));
3922
3923
entry = NEXT_TX(entry);
3924
}
3925
}
3926
3927
/* Packets are ready, update Tx producer idx local and on card. */
3928
tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3929
3930
tp->tx_prod = entry;
3931
if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3932
netif_stop_queue(dev);
3933
if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3934
netif_wake_queue(tp->dev);
3935
}
3936
3937
out_unlock:
3938
mmiowb();
3939
3940
dev->trans_start = jiffies;
3941
3942
return NETDEV_TX_OK;
3943
}
3944
3945
#if TG3_TSO_SUPPORT != 0
3946
static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3947
3948
/* Use GSO to workaround a rare TSO bug that may be triggered when the
3949
* TSO header is greater than 80 bytes.
3950
*/
3951
static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3952
{
3953
struct sk_buff *segs, *nskb;
3954
3955
/* Estimate the number of fragments in the worst case */
3956
if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3957
netif_stop_queue(tp->dev);
3958
return NETDEV_TX_BUSY;
3959
}
3960
3961
segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3962
if (unlikely(IS_ERR(segs)))
3963
goto tg3_tso_bug_end;
3964
3965
do {
3966
nskb = segs;
3967
segs = segs->next;
3968
nskb->next = NULL;
3969
tg3_start_xmit_dma_bug(nskb, tp->dev);
3970
} while (segs);
3971
3972
tg3_tso_bug_end:
3973
dev_kfree_skb(skb);
3974
3975
return NETDEV_TX_OK;
3976
}
3977
#endif
3978
3979
/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3980
* support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3981
*/
3982
static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3983
{
3984
struct tg3 *tp = netdev_priv(dev);
3985
dma_addr_t mapping;
3986
u32 len, entry, base_flags, mss;
3987
int would_hit_hwbug;
3988
3989
len = skb_headlen(skb);
3990
3991
/* We are running in BH disabled context with netif_tx_lock
3992
* and TX reclaim runs via tp->poll inside of a software
3993
* interrupt. Furthermore, IRQ processing runs lockless so we have
3994
* no IRQ context deadlocks to worry about either. Rejoice!
3995
*/
3996
if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3997
if (!netif_queue_stopped(dev)) {
3998
netif_stop_queue(dev);
3999
4000
/* This is a hard error, log it. */
4001
printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4002
"queue awake!\n", dev->name);
4003
}
4004
return NETDEV_TX_BUSY;
4005
}
4006
4007
entry = tp->tx_prod;
4008
base_flags = 0;
4009
if (skb->ip_summed == CHECKSUM_PARTIAL)
4010
base_flags |= TXD_FLAG_TCPUDP_CSUM;
4011
#if TG3_TSO_SUPPORT != 0
4012
mss = 0;
4013
if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4014
(mss = skb_shinfo(skb)->gso_size) != 0) {
4015
int tcp_opt_len, ip_tcp_len, hdr_len;
4016
4017
if (skb_header_cloned(skb) &&
4018
pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4019
dev_kfree_skb(skb);
4020
goto out_unlock;
4021
}
4022
4023
3676
tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4024
3677
ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4025
3678
4026
hdr_len = ip_tcp_len + tcp_opt_len;
4027
if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4028
(tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4029
return (tg3_tso_bug(tp, skb));
4030
4031
3679
base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4032
3680
TXD_FLAG_CPU_POST_DMA);
4033
3681
4034
3682
skb->nh.iph->check = 0;
4035
skb->nh.iph->tot_len = htons(mss + hdr_len);
3683
skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4036
3684
if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4037
3685
skb->h.th->check = 0;
4038
3686
base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4143
3791
tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4144
3792
4145
3793
tp->tx_prod = entry;
4146
if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3794
if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
4147
3795
netif_stop_queue(dev);
4148
if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3796
if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
4149
3797
netif_wake_queue(tp->dev);
4150
3798
}
4151
3799
4152
3800
out_unlock:
4153
3801
mmiowb();
3802
spin_unlock(&tp->tx_lock);
4154
3803
4155
3804
dev->trans_start = jiffies;
4156
3805
4179
3828
static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4180
3829
{
4181
3830
struct tg3 *tp = netdev_priv(dev);
4182
int err;
4183
3831
4184
3832
if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4185
3833
return -EINVAL;
4200
3848
4201
3849
tg3_set_mtu(dev, tp, new_mtu);
4202
3850
4203
err = tg3_restart_hw(tp, 0);
3851
tg3_init_hw(tp);
4204
3852
4205
if (!err)
4206
tg3_netif_start(tp);
3853
tg3_netif_start(tp);
4207
3854
4208
3855
tg3_full_unlock(tp);
4209
3856
4210
return err;
3857
return 0;
4211
3858
}
4212
3859
4213
3860
/* Free up pending packets in all rx/tx rings.
4289
3936
* end up in the driver. tp->{tx,}lock are held and thus
4290
3937
* we may not sleep.
4291
3938
*/
4292
static int tg3_init_rings(struct tg3 *tp)
3939
static void tg3_init_rings(struct tg3 *tp)
4293
3940
{
4294
3941
u32 i;
4295
3942
4338
3985
4339
3986
/* Now allocate fresh SKBs for each rx ring. */
4340
3987
for (i = 0; i < tp->rx_pending; i++) {
4341
if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4342
printk(KERN_WARNING PFX
4343
"%s: Using a smaller RX standard ring, "
4344
"only %d out of %d buffers were allocated "
4345
"successfully.\n",
4346
tp->dev->name, i, tp->rx_pending);
4347
if (i == 0)
4348
return -ENOMEM;
4349
tp->rx_pending = i;
3988
if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3989
-1, i) < 0)
4350
3990
break;
4351
}
4352
3991
}
4353
3992
4354
3993
if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4355
3994
for (i = 0; i < tp->rx_jumbo_pending; i++) {
4356
3995
if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4357
-1, i) < 0) {
4358
printk(KERN_WARNING PFX
4359
"%s: Using a smaller RX jumbo ring, "
4360
"only %d out of %d buffers were "
4361
"allocated successfully.\n",
4362
tp->dev->name, i, tp->rx_jumbo_pending);
4363
if (i == 0) {
4364
tg3_free_rings(tp);
4365
return -ENOMEM;
4366
}
4367
tp->rx_jumbo_pending = i;
3996
-1, i) < 0)
4368
3997
break;
4369
}
4370
3998
}
4371
3999
}
4372
return 0;
4373
4000
}
4374
4001
4375
4002
/*
4651
4278
/* tp->lock is held. */
4652
4279
static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4653
4280
{
4654
tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4655
NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4281
if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4282
tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4283
NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4656
4284
4657
4285
if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4658
4286
switch (kind) {
4724
4352
}
4725
4353
}
4726
4354
4727
static int tg3_poll_fw(struct tg3 *tp)
4728
{
4729
int i;
4730
u32 val;
4731
4732
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4733
/* Wait up to 20ms for init done. */
4734
for (i = 0; i < 200; i++) {
4735
if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4736
return 0;
4737
udelay(100);
4738
}
4739
return -ENODEV;
4740
}
4741
4742
/* Wait for firmware initialization to complete. */
4743
for (i = 0; i < 100000; i++) {
4744
tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4745
if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4746
break;
4747
udelay(10);
4748
}
4749
4750
/* Chip might not be fitted with firmware. Some Sun onboard
4751
* parts are configured like that. So don't signal the timeout
4752
* of the above loop as an error, but do report the lack of
4753
* running firmware once.
4754
*/
4755
if (i >= 100000 &&
4756
!(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4757
tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4758
4759
printk(KERN_INFO PFX "%s: No firmware running.\n",
4760
tp->dev->name);
4761
}
4762
4763
return 0;
4764
}
4765
4766
4355
static void tg3_stop_fw(struct tg3 *);
4767
4356
4768
4357
/* tp->lock is held. */
4770
4359
{
4771
4360
u32 val;
4772
4361
void (*write_op)(struct tg3 *, u32, u32);
4773
int err;
4774
4775
tg3_nvram_lock(tp);
4776
4777
/* No matching tg3_nvram_unlock() after this because
4778
* chip reset below will undo the nvram lock.
4779
*/
4780
tp->nvram_lock_cnt = 0;
4781
4782
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4783
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4784
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4785
tw32(GRC_FASTBOOT_PC, 0);
4362
int i;
4363
4364
if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4365
tg3_nvram_lock(tp);
4366
/* No matching tg3_nvram_unlock() after this because
4367
* chip reset below will undo the nvram lock.
4368
*/
4369
tp->nvram_lock_cnt = 0;
4370
}
4786
4371
4787
4372
/*
4788
4373
* We must avoid the readl() that normally takes place.
4807
4392
}
4808
4393
}
4809
4394
4810
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4811
tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4812
tw32(GRC_VCPU_EXT_CTRL,
4813
tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4814
}
4815
4816
4395
if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4817
4396
val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4818
4397
tw32(GRC_MISC_CFG, val);
4936
4515
tw32_f(MAC_MODE, 0);
4937
4516
udelay(40);
4938
4517
4939
err = tg3_poll_fw(tp);
4940
if (err)
4941
return err;
4518
if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4519
/* Wait for firmware initialization to complete. */
4520
for (i = 0; i < 100000; i++) {
4521
tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4522
if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4523
break;
4524
udelay(10);
4525
}
4526
if (i >= 100000) {
4527
printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4528
"firmware will not restart magic=%08x\n",
4529
tp->dev->name, val);
4530
return -ENODEV;
4531
}
4532
}
4942
4533
4943
4534
if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4944
4535
tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5022
4613
#define TG3_FW_BSS_ADDR 0x08000a70
5023
4614
#define TG3_FW_BSS_LEN 0x10
5024
4615
5025
static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4616
static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5026
4617
0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5027
4618
0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5028
4619
0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5116
4707
0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5117
4708
};
5118
4709
5119
static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4710
static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5120
4711
0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5121
4712
0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5122
4713
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5141
4732
{
5142
4733
int i;
5143
4734
5144
BUG_ON(offset == TX_CPU_BASE &&
5145
(tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5146
5147
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5148
u32 val = tr32(GRC_VCPU_EXT_CTRL);
5149
5150
tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5151
return 0;
5152
}
4735
if (offset == TX_CPU_BASE &&
4736
(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4737
BUG();
4738
5153
4739
if (offset == RX_CPU_BASE) {
5154
4740
for (i = 0; i < 10000; i++) {
5155
4741
tw32(offset + CPU_STATE, 0xffffffff);
5187
4773
struct fw_info {
5188
4774
unsigned int text_base;
5189
4775
unsigned int text_len;
5190
const u32 *text_data;
4776
u32 *text_data;
5191
4777
unsigned int rodata_base;
5192
4778
unsigned int rodata_len;
5193
const u32 *rodata_data;
4779
u32 *rodata_data;
5194
4780
unsigned int data_base;
5195
4781
unsigned int data_len;
5196
const u32 *data_data;
4782
u32 *data_data;
5197
4783
};
5198
4784
5199
4785
/* tp->lock is held. */
5325
4911
#define TG3_TSO_FW_BSS_ADDR 0x08001b80
5326
4912
#define TG3_TSO_FW_BSS_LEN 0x894
5327
4913
5328
static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4914
static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5329
4915
0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5330
4916
0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5331
4917
0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5612
5198
0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5613
5199
};
5614
5200
5615
static const u32 tg3TsoFwRodata[] = {
5201
static u32 tg3TsoFwRodata[] = {
5616
5202
0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5617
5203
0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5618
5204
0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5620
5206
0x00000000,
5621
5207
};
5622
5208
5623
static const u32 tg3TsoFwData[] = {
5209
static u32 tg3TsoFwData[] = {
5624
5210
0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5625
5211
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5626
5212
0x00000000,
5642
5228
#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5643
5229
#define TG3_TSO5_FW_BSS_LEN 0x88
5644
5230
5645
static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5231
static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5646
5232
0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5647
5233
0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5648
5234
0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5801
5387
0x00000000, 0x00000000, 0x00000000,
5802
5388
};
5803
5389
5804
static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5390
static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5805
5391
0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5806
5392
0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5807
5393
0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5808
5394
0x00000000, 0x00000000, 0x00000000,
5809
5395
};
5810
5396
5811
static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5397
static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5812
5398
0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5813
5399
0x00000000, 0x00000000, 0x00000000,
5814
5400
};
5926
5512
{
5927
5513
struct tg3 *tp = netdev_priv(dev);
5928
5514
struct sockaddr *addr = p;
5929
int err = 0;
5930
5515
5931
5516
if (!is_valid_ether_addr(addr->sa_data))
5932
5517
return -EINVAL;
5933
5518
5934
5519
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5935
5520
5936
if (!netif_running(dev))
5937
return 0;
5938
5939
if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5940
/* Reset chip so that ASF can re-init any MAC addresses it
5941
* needs.
5942
*/
5943
tg3_netif_stop(tp);
5944
tg3_full_lock(tp, 1);
5945
5946
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5947
err = tg3_restart_hw(tp, 0);
5948
if (!err)
5949
tg3_netif_start(tp);
5950
tg3_full_unlock(tp);
5951
} else {
5952
spin_lock_bh(&tp->lock);
5953
__tg3_set_mac_addr(tp);
5954
spin_unlock_bh(&tp->lock);
5955
}
5956
5957
return err;
5521
spin_lock_bh(&tp->lock);
5522
__tg3_set_mac_addr(tp);
5523
spin_unlock_bh(&tp->lock);
5524
5525
return 0;
5958
5526
}
5959
5527
5960
5528
/* tp->lock is held. */
6002
5570
}
6003
5571
6004
5572
/* tp->lock is held. */
6005
static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
5573
static int tg3_reset_hw(struct tg3 *tp)
6006
5574
{
6007
5575
u32 val, rdmac_mode;
6008
5576
int i, err, limit;
6017
5585
tg3_abort_hw(tp, 1);
6018
5586
}
6019
5587
6020
if (reset_phy)
6021
tg3_phy_reset(tp);
6022
6023
5588
err = tg3_chip_reset(tp);
6024
5589
if (err)
6025
5590
return err;
6054
5619
* can only do this after the hardware has been
6055
5620
* successfully reset.
6056
5621
*/
6057
err = tg3_init_rings(tp);
6058
if (err)
6059
return err;
5622
tg3_init_rings(tp);
6060
5623
6061
5624
/* This value is determined during the probe time DMA
6062
5625
* engine test, tg3_test_dma.
6068
5631
GRC_MODE_NO_TX_PHDR_CSUM |
6069
5632
GRC_MODE_NO_RX_PHDR_CSUM);
6070
5633
tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6071
6072
/* Pseudo-header checksum is done by hardware logic and not
6073
* the offload processers, so make the chip do the pseudo-
6074
* header checksums on receive. For transmit it is more
6075
* convenient to do the pseudo-header checksum in software
6076
* as Linux does that on transmit for us in all cases.
6077
*/
6078
tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5634
if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5635
tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5636
if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5637
tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
6079
5638
6080
5639
tw32(GRC_MODE,
6081
5640
tp->grc_mode |
6149
5708
}
6150
5709
6151
5710
/* Setup replenish threshold. */
6152
val = tp->rx_pending / 8;
6153
if (val == 0)
6154
val = 1;
6155
else if (val > tp->rx_std_max_post)
6156
val = tp->rx_std_max_post;
6157
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6158
if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6159
tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6160
6161
if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6162
val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6163
}
6164
6165
tw32(RCVBDI_STD_THRESH, val);
5711
tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
6166
5712
6167
5713
/* Initialize TG3_BDINFO's at:
6168
5714
* RCVDBDI_STD_BD: standard eth size rx ring
6322
5868
#endif
6323
5869
6324
5870
/* Receive/send statistics. */
6325
if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6326
val = tr32(RCVLPC_STATS_ENABLE);
6327
val &= ~RCVLPC_STATSENAB_DACK_FIX;
6328
tw32(RCVLPC_STATS_ENABLE, val);
6329
} else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6330
(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5871
if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5872
(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6331
5873
val = tr32(RCVLPC_STATS_ENABLE);
6332
5874
val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6333
5875
tw32(RCVLPC_STATS_ENABLE, val);
6413
5955
gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6414
5956
GRC_LCLCTRL_GPIO_OUTPUT3;
6415
5957
6416
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6417
gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6418
6419
5958
tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6420
5959
6421
5960
/* GPIO1 must be driven high for eeprom write protect */
6454
5993
}
6455
5994
}
6456
5995
6457
/* Enable host coalescing bug fix */
6458
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6459
(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6460
val |= (1 << 29);
6461
6462
5996
tw32_f(WDMAC_MODE, val);
6463
5997
udelay(40);
6464
5998
6514
6048
udelay(100);
6515
6049
6516
6050
tp->rx_mode = RX_MODE_ENABLE;
6517
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6518
tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6519
6520
6051
tw32_f(MAC_RX_MODE, tp->rx_mode);
6521
6052
udelay(10);
6522
6053
6566
6097
tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6567
6098
}
6568
6099
6569
if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6570
(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6571
u32 tmp;
6572
6573
tmp = tr32(SERDES_RX_CTRL);
6574
tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6575
tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6576
tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6577
tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6578
}
6579
6580
err = tg3_setup_phy(tp, 0);
6100
err = tg3_setup_phy(tp, 1);
6581
6101
if (err)
6582
6102
return err;
6583
6103
6584
if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6585
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6104
if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6586
6105
u32 tmp;
6587
6106
6588
6107
/* Clear CRC stats. */
6651
6170
/* Called at device open time to get the chip ready for
6652
6171
* packet processing. Invoked with tp->lock held.
6653
6172
*/
6654
static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6173
static int tg3_init_hw(struct tg3 *tp)
6655
6174
{
6656
6175
int err;
6657
6176
6658
6177
/* Force the chip into D0. */
6659
err = tg3_set_power_state(tp, PCI_D0);
6178
err = tg3_set_power_state(tp, 0);
6660
6179
if (err)
6661
6180
goto out;
6662
6181
6664
6183
6665
6184
tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6666
6185
6667
err = tg3_reset_hw(tp, reset_phy);
6186
err = tg3_reset_hw(tp);
6668
6187
6669
6188
out:
6670
6189
return err;
6712
6231
TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6713
6232
TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6714
6233
TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6715
6716
TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6717
TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6718
TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6719
6234
}
6720
6235
6721
6236
static void tg3_timer(unsigned long __opaque)
6722
6237
{
6723
6238
struct tg3 *tp = (struct tg3 *) __opaque;
6724
6239
6725
if (tp->irq_sync)
6726
goto restart_timer;
6727
6728
6240
spin_lock(&tp->lock);
6729
6241
6730
6242
if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6782
6294
need_setup = 1;
6783
6295
}
6784
6296
if (need_setup) {
6785
if (!tp->serdes_counter) {
6786
tw32_f(MAC_MODE,
6787
(tp->mac_mode &
6788
~MAC_MODE_PORT_MODE_MASK));
6789
udelay(40);
6790
tw32_f(MAC_MODE, tp->mac_mode);
6791
udelay(40);
6792
}
6297
tw32_f(MAC_MODE,
6298
(tp->mac_mode &
6299
~MAC_MODE_PORT_MODE_MASK));
6300
udelay(40);
6301
tw32_f(MAC_MODE, tp->mac_mode);
6302
udelay(40);
6793
6303
tg3_setup_phy(tp, 0);
6794
6304
}
6795
6305
} else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6798
6308
tp->timer_counter = tp->timer_multiplier;
6799
6309
}
6800
6310
6801
/* Heartbeat is only sent once every 2 seconds.
6802
*
6803
* The heartbeat is to tell the ASF firmware that the host
6804
* driver is still alive. In the event that the OS crashes,
6805
* ASF needs to reset the hardware to free up the FIFO space
6806
* that may be filled with rx packets destined for the host.
6807
* If the FIFO is full, ASF will no longer function properly.
6808
*
6809
* Unintended resets have been reported on real time kernels
6810
* where the timer doesn't run on time. Netpoll will also have
6811
* same problem.
6812
*
6813
* The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6814
* to check the ring condition when the heartbeat is expiring
6815
* before doing the reset. This will prevent most unintended
6816
* resets.
6817
*/
6311
/* Heartbeat is only sent once every 2 seconds. */
6818
6312
if (!--tp->asf_counter) {
6819
6313
if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6820
6314
u32 val;
6821
6315
6822
tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6823
FWCMD_NICDRV_ALIVE3);
6824
tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6316
tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_MBOX,
6317
FWCMD_NICDRV_ALIVE2);
6318
tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6825
6319
/* 5 seconds timeout */
6826
tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6320
tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6827
6321
val = tr32(GRC_RX_CPU_EVENT);
6828
6322
val |= (1 << 14);
6829
6323
tw32(GRC_RX_CPU_EVENT, val);
6833
6327
6834
6328
spin_unlock(&tp->lock);
6835
6329
6836
restart_timer:
6837
6330
tp->timer.expires = jiffies + tp->timer_offset;
6838
6331
add_timer(&tp->timer);
6839
6332
}
6840
6333
6841
static int tg3_request_irq(struct tg3 *tp)
6842
{
6843
irq_handler_t fn;
6844
unsigned long flags;
6845
struct net_device *dev = tp->dev;
6846
6847
if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6848
fn = tg3_msi;
6849
if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6850
fn = tg3_msi_1shot;
6851
flags = IRQF_SAMPLE_RANDOM;
6852
} else {
6853
fn = tg3_interrupt;
6854
if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6855
fn = tg3_interrupt_tagged;
6856
flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6857
}
6858
return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6859
}
6860
6861
6334
static int tg3_test_interrupt(struct tg3 *tp)
6862
6335
{
6863
6336
struct net_device *dev = tp->dev;
6864
int err, i, intr_ok = 0;
6337
int err, i;
6338
u32 int_mbox = 0;
6865
6339
6866
6340
if (!netif_running(dev))
6867
6341
return -ENODEV;
6871
6345
free_irq(tp->pdev->irq, dev);
6872
6346
6873
6347
err = request_irq(tp->pdev->irq, tg3_test_isr,
6874
IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6348
SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6875
6349
if (err)
6876
6350
return err;
6877
6351
6882
6356
HOSTCC_MODE_NOW);
6883
6357
6884
6358
for (i = 0; i < 5; i++) {
6885
u32 int_mbox, misc_host_ctrl;
6886
6887
6359
int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6888
6360
TG3_64BIT_REG_LOW);
6889
misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6890
6891
if ((int_mbox != 0) ||
6892
(misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6893
intr_ok = 1;
6361
if (int_mbox != 0)
6894
6362
break;
6895
}
6896
6897
6363
msleep(10);
6898
6364
}
6899
6365
6900
6366
tg3_disable_ints(tp);
6901
6367
6902
6368
free_irq(tp->pdev->irq, dev);
6903
6904
err = tg3_request_irq(tp);
6369
6370
if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6371
err = request_irq(tp->pdev->irq, tg3_msi,
6372
SA_SAMPLE_RANDOM, dev->name, dev);
6373
else {
6374
irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6375
if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6376
fn = tg3_interrupt_tagged;
6377
err = request_irq(tp->pdev->irq, fn,
6378
SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6379
}
6905
6380
6906
6381
if (err)
6907
6382
return err;
6908
6383
6909
if (intr_ok)
6384
if (int_mbox != 0)
6910
6385
return 0;
6911
6386
6912
6387
return -EIO;
6953
6428
6954
6429
tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6955
6430
6956
err = tg3_request_irq(tp);
6431
{
6432
irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6433
if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6434
fn = tg3_interrupt_tagged;
6435
6436
err = request_irq(tp->pdev->irq, fn,
6437
SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6438
}
6957
6439
if (err)
6958
6440
return err;
6959
6441
6963
6445
tg3_full_lock(tp, 1);
6964
6446
6965
6447
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6966
err = tg3_init_hw(tp, 1);
6448
err = tg3_init_hw(tp);
6967
6449
6968
6450
tg3_full_unlock(tp);
6969
6451
6980
6462
6981
6463
tg3_full_lock(tp, 0);
6982
6464
6983
err = tg3_set_power_state(tp, PCI_D0);
6984
if (err) {
6985
tg3_full_unlock(tp);
6986
return err;
6987
}
6988
6989
6465
tg3_disable_ints(tp);
6990
6466
tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6991
6467
7000
6476
7001
6477
if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7002
6478
(GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
7003
(GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7004
!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7005
(tp->pdev_peer == tp->pdev))) {
6479
(GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
7006
6480
/* All MSI supporting chips should support tagged
7007
6481
* status. Assert that this is the case.
7008
6482
*/
7017
6491
tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7018
6492
}
7019
6493
}
7020
err = tg3_request_irq(tp);
6494
if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6495
err = request_irq(tp->pdev->irq, tg3_msi,
6496
SA_SAMPLE_RANDOM, dev->name, dev);
6497
else {
6498
irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6499
if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6500
fn = tg3_interrupt_tagged;
6501
6502
err = request_irq(tp->pdev->irq, fn,
6503
SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6504
}
7021
6505
7022
6506
if (err) {
7023
6507
if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7030
6514
7031
6515
tg3_full_lock(tp, 0);
7032
6516
7033
err = tg3_init_hw(tp, 1);
6517
err = tg3_init_hw(tp);
7034
6518
if (err) {
7035
6519
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7036
6520
tg3_free_rings(tp);
7082
6566
7083
6567
return err;
7084
6568
}
7085
7086
if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7087
if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7088
u32 val = tr32(PCIE_TRANSACTION_CFG);
7089
7090
tw32(PCIE_TRANSACTION_CFG,
7091
val | PCIE_TRANS_CFG_1SHOT_MSI);
7092
}
7093
}
7094
6569
}
7095
6570
7096
6571
tg3_full_lock(tp, 0);
7364
6839
tp->tg3_flags &=
7365
6840
~(TG3_FLAG_INIT_COMPLETE |
7366
6841
TG3_FLAG_GOT_SERDES_FLOWCTL);
6842
netif_carrier_off(tp->dev);
7367
6843
7368
6844
tg3_full_unlock(tp);
7369
6845
7380
6856
7381
6857
tg3_free_consistent(tp);
7382
6858
7383
tg3_set_power_state(tp, PCI_D3hot);
7384
7385
netif_carrier_off(tp->dev);
7386
7387
6859
return 0;
7388
6860
}
7389
6861
7530
7002
get_stat64(&hw_stats->rx_ucast_packets) +
7531
7003
get_stat64(&hw_stats->rx_mcast_packets) +
7532
7004
get_stat64(&hw_stats->rx_bcast_packets);
7533
7005
7534
7006
stats->tx_packets = old_stats->tx_packets +
7535
7007
get_stat64(&hw_stats->tx_ucast_packets) +
7536
7008
get_stat64(&hw_stats->tx_mcast_packets) +
7678
7150
{
7679
7151
struct tg3 *tp = netdev_priv(dev);
7680
7152
7681
if (!netif_running(dev))
7682
return;
7683
7684
7153
tg3_full_lock(tp, 0);
7685
7154
__tg3_set_rx_mode(dev);
7686
7155
tg3_full_unlock(tp);
7705
7174
7706
7175
memset(p, 0, TG3_REGDUMP_LEN);
7707
7176
7708
if (tp->link_config.phy_is_low_power)
7709
return;
7710
7711
7177
tg3_full_lock(tp, 0);
7712
7178
7713
7179
#define __GET_REG32(reg) (*(p)++ = tr32(reg))
7774
7240
}
7775
7241
7776
7242
static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7777
static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7778
7243
7779
7244
static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7780
7245
{
7783
7248
u8 *pd;
7784
7249
u32 i, offset, len, val, b_offset, b_count;
7785
7250
7786
if (tp->link_config.phy_is_low_power)
7787
return -EAGAIN;
7788
7789
7251
offset = eeprom->offset;
7790
7252
len = eeprom->len;
7791
7253
eeprom->len = 0;
7838
7300
return 0;
7839
7301
}
7840
7302
7841
static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7303
static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7842
7304
7843
7305
static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7844
7306
{
7847
7309
u32 offset, len, b_offset, odd_len, start, end;
7848
7310
u8 *buf;
7849
7311
7850
if (tp->link_config.phy_is_low_power)
7851
return -EAGAIN;
7852
7853
7312
if (eeprom->magic != TG3_EEPROM_MAGIC)
7854
7313
return -EINVAL;
7855
7314
7902
7361
static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7903
7362
{
7904
7363
struct tg3 *tp = netdev_priv(dev);
7905
7364
7906
7365
cmd->supported = (SUPPORTED_Autoneg);
7907
7366
7908
7367
if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7920
7379
cmd->supported |= SUPPORTED_FIBRE;
7921
7380
cmd->port = PORT_FIBRE;
7922
7381
}
7923
7382
7924
7383
cmd->advertising = tp->link_config.advertising;
7925
7384
if (netif_running(dev)) {
7926
7385
cmd->speed = tp->link_config.active_speed;
7933
7392
cmd->maxrxpkt = 0;
7934
7393
return 0;
7935
7394
}
7936
7395
7937
7396
static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7938
7397
{
7939
7398
struct tg3 *tp = netdev_priv(dev);
7940
7941
if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7399
7400
if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7942
7401
/* These are the only valid advertisement bits allowed. */
7943
7402
if (cmd->autoneg == AUTONEG_ENABLE &&
7944
7403
(cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7970
7429
tp->link_config.speed = cmd->speed;
7971
7430
tp->link_config.duplex = cmd->duplex;
7972
7431
}
7973
7432
7974
7433
if (netif_running(dev))
7975
7434
tg3_setup_phy(tp, 1);
7976
7435
7977
7436
tg3_full_unlock(tp);
7978
7437
7979
7438
return 0;
7980
7439
}
7981
7440
7982
7441
static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7983
7442
{
7984
7443
struct tg3 *tp = netdev_priv(dev);
7985
7444
7986
7445
strcpy(info->driver, DRV_MODULE_NAME);
7987
7446
strcpy(info->version, DRV_MODULE_VERSION);
7988
strcpy(info->fw_version, tp->fw_ver);
7989
7447
strcpy(info->bus_info, pci_name(tp->pdev));
7990
7448
}
7991
7449
7992
7450
static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7993
7451
{
7994
7452
struct tg3 *tp = netdev_priv(dev);
7995
7453
7996
7454
wol->supported = WAKE_MAGIC;
7997
7455
wol->wolopts = 0;
7998
7456
if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7999
7457
wol->wolopts = WAKE_MAGIC;
8000
7458
memset(&wol->sopass, 0, sizeof(wol->sopass));
8001
7459
}
8002
7460
8003
7461
static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8004
7462
{
8005
7463
struct tg3 *tp = netdev_priv(dev);
8006
7464
8007
7465
if (wol->wolopts & ~WAKE_MAGIC)
8008
7466
return -EINVAL;
8009
7467
if ((wol->wolopts & WAKE_MAGIC) &&
8010
tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
7468
tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
8011
7469
!(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8012
7470
return -EINVAL;
8013
7471
8014
7472
spin_lock_bh(&tp->lock);
8015
7473
if (wol->wolopts & WAKE_MAGIC)
8016
7474
tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8017
7475
else
8018
7476
tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8019
7477
spin_unlock_bh(&tp->lock);
8020
7478
8021
7479
return 0;
8022
7480
}
8023
7481
8024
7482
static u32 tg3_get_msglevel(struct net_device *dev)
8025
7483
{
8026
7484
struct tg3 *tp = netdev_priv(dev);
8027
7485
return tp->msg_enable;
8028
7486
}
8029
7487
8030
7488
static void tg3_set_msglevel(struct net_device *dev, u32 value)
8031
7489
{
8032
7490
struct tg3 *tp = netdev_priv(dev);
8033
7491
tp->msg_enable = value;
8034
7492
}
8035
7493
8036
7494
#if TG3_TSO_SUPPORT != 0
8037
7495
static int tg3_set_tso(struct net_device *dev, u32 value)
8038
7496
{
8043
7501
return -EINVAL;
8044
7502
return 0;
8045
7503
}
8046
if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8047
(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8048
if (value)
8049
dev->features |= NETIF_F_TSO6;
8050
else
8051
dev->features &= ~NETIF_F_TSO6;
8052
}
8053
7504
return ethtool_op_set_tso(dev, value);
8054
7505
}
8055
7506
#endif
8056
7507
8057
7508
static int tg3_nway_reset(struct net_device *dev)
8058
7509
{
8059
7510
struct tg3 *tp = netdev_priv(dev);
8060
7511
u32 bmcr;
8061
7512
int r;
8062
7513
8063
7514
if (!netif_running(dev))
8064
7515
return -EAGAIN;
8065
7516
8077
7528
r = 0;
8078
7529
}
8079
7530
spin_unlock_bh(&tp->lock);
8080
7531
8081
7532
return r;
8082
7533
}
8083
7534
8084
7535
static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8085
7536
{
8086
7537
struct tg3 *tp = netdev_priv(dev);
8087
7538
8088
7539
ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8089
7540
ering->rx_mini_max_pending = 0;
8090
if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8091
ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8092
else
8093
ering->rx_jumbo_max_pending = 0;
8094
8095
ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
7541
ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8096
7542
8097
7543
ering->rx_pending = tp->rx_pending;
8098
7544
ering->rx_mini_pending = 0;
8099
if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8100
ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8101
else
8102
ering->rx_jumbo_pending = 0;
8103
7545
ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8104
7546
ering->tx_pending = tp->tx_pending;
8105
7547
}
8106
7548
8107
7549
static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8108
7550
{
8109
7551
struct tg3 *tp = netdev_priv(dev);
8110
int irq_sync = 0, err = 0;
8111
7552
int irq_sync = 0;
7553
8112
7554
if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8113
7555
(ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8114
(ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8115
(ering->tx_pending <= MAX_SKB_FRAGS) ||
8116
((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
8117
(ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
7556
(ering->tx_pending > TG3_TX_RING_SIZE - 1))
8118
7557
return -EINVAL;
8119
7558
8120
7559
if (netif_running(dev)) {
8121
7560
tg3_netif_stop(tp);
8122
7561
irq_sync = 1;
8123
7562
}
8124
7563
8125
7564
tg3_full_lock(tp, irq_sync);
8126
7565
8127
7566
tp->rx_pending = ering->rx_pending;
8128
7567
8129
7568
if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8134
7573
8135
7574
if (netif_running(dev)) {
8136
7575
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8137
err = tg3_restart_hw(tp, 1);
8138
if (!err)
8139
tg3_netif_start(tp);
7576
tg3_init_hw(tp);
7577
tg3_netif_start(tp);
8140
7578
}
8141
7579
8142
7580
tg3_full_unlock(tp);
8143
8144
return err;
7581
7582
return 0;
8145
7583
}
8146
7584
8147
7585
static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8148
7586
{
8149
7587
struct tg3 *tp = netdev_priv(dev);
8150
7588
8151
7589
epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8152
7590
epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8153
7591
epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8154
7592
}
8155
7593
8156
7594
static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8157
7595
{
8158
7596
struct tg3 *tp = netdev_priv(dev);
8159
int irq_sync = 0, err = 0;
8160
7597
int irq_sync = 0;
7598
8161
7599
if (netif_running(dev)) {
8162
7600
tg3_netif_stop(tp);
8163
7601
irq_sync = 1;
8180
7618
8181
7619
if (netif_running(dev)) {
8182
7620
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8183
err = tg3_restart_hw(tp, 1);
8184
if (!err)
8185
tg3_netif_start(tp);
7621
tg3_init_hw(tp);
7622
tg3_netif_start(tp);
8186
7623
}
8187
7624
8188
7625
tg3_full_unlock(tp);
8189
8190
return err;
7626
7627
return 0;
8191
7628
}
8192
7629
8193
7630
static u32 tg3_get_rx_csum(struct net_device *dev)
8194
7631
{
8195
7632
struct tg3 *tp = netdev_priv(dev);
8196
7633
return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8197
7634
}
8198
7635
8199
7636
static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8200
7637
{
8201
7638
struct tg3 *tp = netdev_priv(dev);
8202
7639
8203
7640
if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8204
7641
if (data != 0)
8205
7642
return -EINVAL;
8206
7643
return 0;
8207
7644
}
8208
7645
8209
7646
spin_lock_bh(&tp->lock);
8210
7647
if (data)
8211
7648
tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8212
7649
else
8213
7650
tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8214
7651
spin_unlock_bh(&tp->lock);
8215
7652
8216
7653
return 0;
8217
7654
}
8218
7655
8219
7656
static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8220
7657
{
8221
7658
struct tg3 *tp = netdev_priv(dev);
8222
7659
8223
7660
if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8224
7661
if (data != 0)
8225
7662
return -EINVAL;
8226
7663
return 0;
8227
7664
}
8228
8229
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8230
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8231
ethtool_op_set_tx_hw_csum(dev, data);
7665
7666
if (data)
7667
dev->features |= NETIF_F_IP_CSUM;
8232
7668
else
8233
ethtool_op_set_tx_csum(dev, data);
7669
dev->features &= ~NETIF_F_IP_CSUM;
8234
7670
8235
7671
return 0;
8236
7672
}
8280
7716
LED_CTRL_TRAFFIC_OVERRIDE |
8281
7717
LED_CTRL_TRAFFIC_BLINK |
8282
7718
LED_CTRL_TRAFFIC_LED);
8283
7719
8284
7720
else
8285
7721
tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8286
7722
LED_CTRL_TRAFFIC_OVERRIDE);
8300
7736
}
8301
7737
8302
7738
#define NVRAM_TEST_SIZE 0x100
8303
#define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8304
#define NVRAM_SELFBOOT_HW_SIZE 0x20
8305
#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8306
7739
8307
7740
static int tg3_test_nvram(struct tg3 *tp)
8308
7741
{
8309
u32 *buf, csum, magic;
8310
int i, j, err = 0, size;
8311
8312
if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8313
return -EIO;
8314
8315
if (magic == TG3_EEPROM_MAGIC)
8316
size = NVRAM_TEST_SIZE;
8317
else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8318
if ((magic & 0xe00000) == 0x200000)
8319
size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8320
else
8321
return 0;
8322
} else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8323
size = NVRAM_SELFBOOT_HW_SIZE;
8324
else
8325
return -EIO;
8326
8327
buf = kmalloc(size, GFP_KERNEL);
7742
u32 *buf, csum;
7743
int i, j, err = 0;
7744
7745
buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
8328
7746
if (buf == NULL)
8329
7747
return -ENOMEM;
8330
7748
8331
err = -EIO;
8332
for (i = 0, j = 0; i < size; i += 4, j++) {
7749
for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
8333
7750
u32 val;
8334
7751
8335
7752
if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8336
7753
break;
8337
7754
buf[j] = cpu_to_le32(val);
8338
7755
}
8339
if (i < size)
8340
goto out;
8341
8342
/* Selfboot format */
8343
if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8344
TG3_EEPROM_MAGIC_FW) {
8345
u8 *buf8 = (u8 *) buf, csum8 = 0;
8346
8347
for (i = 0; i < size; i++)
8348
csum8 += buf8[i];
8349
8350
if (csum8 == 0) {
8351
err = 0;
8352
goto out;
8353
}
8354
8355
err = -EIO;
8356
goto out;
8357
}
8358
8359
if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8360
TG3_EEPROM_MAGIC_HW) {
8361
u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8362
u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8363
u8 *buf8 = (u8 *) buf;
8364
int j, k;
8365
8366
/* Separate the parity bits and the data bytes. */
8367
for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8368
if ((i == 0) || (i == 8)) {
8369
int l;
8370
u8 msk;
8371
8372
for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8373
parity[k++] = buf8[i] & msk;
8374
i++;
8375
}
8376
else if (i == 16) {
8377
int l;
8378
u8 msk;
8379
8380
for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8381
parity[k++] = buf8[i] & msk;
8382
i++;
8383
8384
for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8385
parity[k++] = buf8[i] & msk;
8386
i++;
8387
}
8388
data[j++] = buf8[i];
8389
}
8390
8391
err = -EIO;
8392
for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8393
u8 hw8 = hweight8(data[i]);
8394
8395
if ((hw8 & 0x1) && parity[i])
8396
goto out;
8397
else if (!(hw8 & 0x1) && !parity[i])
8398
goto out;
8399
}
8400
err = 0;
8401
goto out;
8402
}
7756
if (i < NVRAM_TEST_SIZE)
7757
goto out;
7758
7759
err = -EIO;
7760
if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7761
goto out;
8403
7762
8404
7763
/* Bootstrap checksum at offset 0x10 */
8405
7764
csum = calc_crc((unsigned char *) buf, 0x10);
8447
7806
/* Only test the commonly used registers */
8448
7807
static int tg3_test_registers(struct tg3 *tp)
8449
7808
{
8450
int i, is_5705, is_5750;
7809
int i, is_5705;
8451
7810
u32 offset, read_mask, write_mask, val, save_val, read_val;
8452
7811
static struct {
8453
7812
u16 offset;
8455
7814
#define TG3_FL_5705 0x1
8456
7815
#define TG3_FL_NOT_5705 0x2
8457
7816
#define TG3_FL_NOT_5788 0x4
8458
#define TG3_FL_NOT_5750 0x8
8459
7817
u32 read_mask;
8460
7818
u32 write_mask;
8461
7819
} reg_tbl[] = {
8508
7866
0x00000000, 0xffff0002 },
8509
7867
{ RCVDBDI_STD_BD+0xc, 0x0000,
8510
7868
0x00000000, 0xffffffff },
8511
7869
8512
7870
/* Receive BD Initiator Control Registers. */
8513
7871
{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8514
7872
0x00000000, 0xffffffff },
8516
7874
0x00000000, 0x000003ff },
8517
7875
{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8518
7876
0x00000000, 0xffffffff },
8519
7877
8520
7878
/* Host Coalescing Control Registers. */
8521
7879
{ HOSTCC_MODE, TG3_FL_NOT_5705,
8522
7880
0x00000000, 0x00000004 },
8566
7924
0xffffffff, 0x00000000 },
8567
7925
8568
7926
/* Buffer Manager Control Registers. */
8569
{ BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
7927
{ BUFMGR_MB_POOL_ADDR, 0x0000,
8570
7928
0x00000000, 0x007fff80 },
8571
{ BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
7929
{ BUFMGR_MB_POOL_SIZE, 0x0000,
8572
7930
0x00000000, 0x007fffff },
8573
7931
{ BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8574
7932
0x00000000, 0x0000003f },
8580
7938
0xffffffff, 0x00000000 },
8581
7939
{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8582
7940
0xffffffff, 0x00000000 },
8583
7941
8584
7942
/* Mailbox Registers */
8585
7943
{ GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8586
7944
0x00000000, 0x000001ff },
8594
7952
{ 0xffff, 0x0000, 0x00000000, 0x00000000 },
8595
7953
};
8596
7954
8597
is_5705 = is_5750 = 0;
8598
if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7955
if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8599
7956
is_5705 = 1;
8600
if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8601
is_5750 = 1;
8602
}
7957
else
7958
is_5705 = 0;
8603
7959
8604
7960
for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8605
7961
if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8612
7968
(reg_tbl[i].flags & TG3_FL_NOT_5788))
8613
7969
continue;
8614
7970
8615
if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8616
continue;
8617
8618
7971
offset = (u32) reg_tbl[i].offset;
8619
7972
read_mask = reg_tbl[i].read_mask;
8620
7973
write_mask = reg_tbl[i].write_mask;
8665
8018
8666
8019
static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8667
8020
{
8668
static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8021
static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8669
8022
int i;
8670
8023
u32 j;
8671
8024
8699
8052
{ 0x00008000, 0x02000},
8700
8053
{ 0x00010000, 0x0e000},
8701
8054
{ 0xffffffff, 0x00000}
8702
}, mem_tbl_5755[] = {
8703
{ 0x00000200, 0x00008},
8704
{ 0x00004000, 0x00800},
8705
{ 0x00006000, 0x00800},
8706
{ 0x00008000, 0x02000},
8707
{ 0x00010000, 0x0c000},
8708
{ 0xffffffff, 0x00000}
8709
}, mem_tbl_5906[] = {
8710
{ 0x00000200, 0x00008},
8711
{ 0x00004000, 0x00400},
8712
{ 0x00006000, 0x00400},
8713
{ 0x00008000, 0x01000},
8714
{ 0x00010000, 0x01000},
8715
{ 0xffffffff, 0x00000}
8716
8055
};
8717
8056
struct mem_entry *mem_tbl;
8718
8057
int err = 0;
8719
8058
int i;
8720
8059
8721
if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8722
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8723
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8724
mem_tbl = mem_tbl_5755;
8725
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8726
mem_tbl = mem_tbl_5906;
8727
else
8728
mem_tbl = mem_tbl_5705;
8729
} else
8060
if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8061
mem_tbl = mem_tbl_5705;
8062
else
8730
8063
mem_tbl = mem_tbl_570x;
8731
8064
8732
8065
for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8734
8067
mem_tbl[i].len)) != 0)
8735
8068
break;
8736
8069
}
8737
8070
8738
8071
return err;
8739
8072
}
8740
8073
8760
8093
return 0;
8761
8094
8762
8095
mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8763
MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8764
if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8765
mac_mode |= MAC_MODE_PORT_MODE_MII;
8766
else
8767
mac_mode |= MAC_MODE_PORT_MODE_GMII;
8096
MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8097
MAC_MODE_PORT_MODE_GMII;
8768
8098
tw32(MAC_MODE, mac_mode);
8769
8099
} else if (loopback_mode == TG3_PHY_LOOPBACK) {
8770
u32 val;
8771
8772
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8773
u32 phytest;
8774
8775
if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8776
u32 phy;
8777
8778
tg3_writephy(tp, MII_TG3_EPHY_TEST,
8779
phytest | MII_TG3_EPHY_SHADOW_EN);
8780
if (!tg3_readphy(tp, 0x1b, &phy))
8781
tg3_writephy(tp, 0x1b, phy & ~0x20);
8782
if (!tg3_readphy(tp, 0x10, &phy))
8783
tg3_writephy(tp, 0x10, phy & ~0x4000);
8784
tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8785
}
8786
}
8787
val = BMCR_LOOPBACK | BMCR_FULLDPLX;
8788
if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8789
val |= BMCR_SPEED100;
8790
else
8791
val |= BMCR_SPEED1000;
8792
8793
tg3_writephy(tp, MII_BMCR, val);
8100
tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8101
BMCR_SPEED1000);
8794
8102
udelay(40);
8795
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8796
tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8797
8798
8103
/* reset to prevent losing 1st rx packet intermittently */
8799
8104
if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8800
8105
tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8802
8107
tw32_f(MAC_RX_MODE, tp->rx_mode);
8803
8108
}
8804
8109
mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8805
MAC_MODE_LINK_POLARITY;
8806
if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8807
mac_mode |= MAC_MODE_PORT_MODE_MII;
8808
else
8809
mac_mode |= MAC_MODE_PORT_MODE_GMII;
8810
if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8110
MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8111
if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8811
8112
mac_mode &= ~MAC_MODE_LINK_POLARITY;
8812
tg3_writephy(tp, MII_TG3_EXT_CTRL,
8813
MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8814
}
8815
8113
tw32(MAC_MODE, mac_mode);
8816
8114
}
8817
8115
else
8820
8118
err = -EIO;
8821
8119
8822
8120
tx_len = 1514;
8823
skb = netdev_alloc_skb(tp->dev, tx_len);
8824
if (!skb)
8825
return -ENOMEM;
8826
8121
skb = dev_alloc_skb(tx_len);
8827
8122
tx_data = skb_put(skb, tx_len);
8828
8123
memcpy(tx_data, tp->dev->dev_addr, 6);
8829
8124
memset(tx_data + 6, 0x0, 8);
8855
8150
8856
8151
udelay(10);
8857
8152
8858
/* 250 usec to allow enough time on some 10/100 Mbps devices. */
8859
for (i = 0; i < 25; i++) {
8153
for (i = 0; i < 10; i++) {
8860
8154
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8861
8155
HOSTCC_MODE_NOW);
8862
8156
8902
8196
goto out;
8903
8197
}
8904
8198
err = 0;
8905
8199
8906
8200
/* tg3_free_rings will unmap and free the rx_skb */
8907
8201
out:
8908
8202
return err;
8920
8214
if (!netif_running(tp->dev))
8921
8215
return TG3_LOOPBACK_FAILED;
8922
8216
8923
err = tg3_reset_hw(tp, 1);
8924
if (err)
8925
return TG3_LOOPBACK_FAILED;
8217
tg3_reset_hw(tp);
8926
8218
8927
8219
if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8928
8220
err |= TG3_MAC_LOOPBACK_FAILED;
8939
8231
{
8940
8232
struct tg3 *tp = netdev_priv(dev);
8941
8233
8942
if (tp->link_config.phy_is_low_power)
8943
tg3_set_power_state(tp, PCI_D0);
8944
8945
8234
memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8946
8235
8947
8236
if (tg3_test_nvram(tp) != 0) {
8970
8259
if (!err)
8971
8260
tg3_nvram_unlock(tp);
8972
8261
8973
if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8974
tg3_phy_reset(tp);
8975
8976
8262
if (tg3_test_registers(tp) != 0) {
8977
8263
etest->flags |= ETH_TEST_FL_FAILED;
8978
8264
data[2] = 1;
8996
8282
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8997
8283
if (netif_running(dev)) {
8998
8284
tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8999
if (!tg3_restart_hw(tp, 1))
9000
tg3_netif_start(tp);
8285
tg3_init_hw(tp);
8286
tg3_netif_start(tp);
9001
8287
}
9002
8288
9003
8289
tg3_full_unlock(tp);
9004
8290
}
9005
if (tp->link_config.phy_is_low_power)
9006
tg3_set_power_state(tp, PCI_D3hot);
9007
9008
8291
}
9009
8292
9010
8293
static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9024
8307
if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9025
8308
break; /* We have no PHY */
9026
8309
9027
if (tp->link_config.phy_is_low_power)
9028
return -EAGAIN;
9029
9030
8310
spin_lock_bh(&tp->lock);
9031
8311
err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9032
8312
spin_unlock_bh(&tp->lock);
9043
8323
if (!capable(CAP_NET_ADMIN))
9044
8324
return -EPERM;
9045
8325
9046
if (tp->link_config.phy_is_low_power)
9047
return -EAGAIN;
9048
9049
8326
spin_lock_bh(&tp->lock);
9050
8327
err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9051
8328
spin_unlock_bh(&tp->lock);
9064
8341
{
9065
8342
struct tg3 *tp = netdev_priv(dev);
9066
8343
9067
if (netif_running(dev))
9068
tg3_netif_stop(tp);
9069
9070
8344
tg3_full_lock(tp, 0);
9071
8345
9072
8346
tp->vlgrp = grp;
9075
8349
__tg3_set_rx_mode(dev);
9076
8350
9077
8351
tg3_full_unlock(tp);
9078
9079
if (netif_running(dev))
9080
tg3_netif_start(tp);
9081
8352
}
9082
8353
9083
8354
static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9084
8355
{
9085
8356
struct tg3 *tp = netdev_priv(dev);
9086
8357
9087
if (netif_running(dev))
9088
tg3_netif_stop(tp);
9089
9090
8358
tg3_full_lock(tp, 0);
9091
8359
if (tp->vlgrp)
9092
8360
tp->vlgrp->vlan_devices[vid] = NULL;
9093
8361
tg3_full_unlock(tp);
9094
9095
if (netif_running(dev))
9096
tg3_netif_start(tp);
9097
8362
}
9098
8363
#endif
9099
8364
9159
8424
return 0;
9160
8425
}
9161
8426
9162
static const struct ethtool_ops tg3_ethtool_ops = {
8427
static struct ethtool_ops tg3_ethtool_ops = {
9163
8428
.get_settings = tg3_get_settings,
9164
8429
.set_settings = tg3_set_settings,
9165
8430
.get_drvinfo = tg3_get_drvinfo,
9201
8466
9202
8467
static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9203
8468
{
9204
u32 cursize, val, magic;
8469
u32 cursize, val;
9205
8470
9206
8471
tp->nvram_size = EEPROM_CHIP_SIZE;
9207
8472
9208
if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8473
if (tg3_nvram_read(tp, 0, &val) != 0)
9209
8474
return;
9210
8475
9211
if ((magic != TG3_EEPROM_MAGIC) &&
9212
((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9213
((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
8476
if (swab32(val) != TG3_EEPROM_MAGIC)
9214
8477
return;
9215
8478
9216
8479
/*
9218
8481
* When we encounter our validation signature, we know the addressing
9219
8482
* has wrapped around, and thus have our chip size.
9220
8483
*/
9221
cursize = 0x10;
8484
cursize = 0x800;
9222
8485
9223
8486
while (cursize < tp->nvram_size) {
9224
if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
8487
if (tg3_nvram_read(tp, cursize, &val) != 0)
9225
8488
return;
9226
8489
9227
if (val == magic)
8490
if (swab32(val) == TG3_EEPROM_MAGIC)
9228
8491
break;
9229
8492
9230
8493
cursize <<= 1;
9232
8495
9233
8496
tp->nvram_size = cursize;
9234
8497
}
9235
8498
9236
8499
static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9237
8500
{
9238
8501
u32 val;
9239
8502
9240
if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9241
return;
9242
9243
/* Selfboot format */
9244
if (val != TG3_EEPROM_MAGIC) {
9245
tg3_get_eeprom_size(tp);
9246
return;
9247
}
9248
9249
8503
if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9250
8504
if (val != 0) {
9251
8505
tp->nvram_size = (val >> 16) * 1024;
9369
8623
}
9370
8624
}
9371
8625
9372
static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9373
{
9374
u32 nvcfg1;
9375
9376
nvcfg1 = tr32(NVRAM_CFG1);
9377
9378
/* NVRAM protection for TPM */
9379
if (nvcfg1 & (1 << 27))
9380
tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9381
9382
switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9383
case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9384
case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9385
tp->nvram_jedecnum = JEDEC_ATMEL;
9386
tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9387
tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9388
9389
nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9390
tw32(NVRAM_CFG1, nvcfg1);
9391
break;
9392
case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9393
case FLASH_5755VENDOR_ATMEL_FLASH_1:
9394
case FLASH_5755VENDOR_ATMEL_FLASH_2:
9395
case FLASH_5755VENDOR_ATMEL_FLASH_3:
9396
case FLASH_5755VENDOR_ATMEL_FLASH_4:
9397
tp->nvram_jedecnum = JEDEC_ATMEL;
9398
tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9399
tp->tg3_flags2 |= TG3_FLG2_FLASH;
9400
tp->nvram_pagesize = 264;
9401
break;
9402
case FLASH_5752VENDOR_ST_M45PE10:
9403
case FLASH_5752VENDOR_ST_M45PE20:
9404
case FLASH_5752VENDOR_ST_M45PE40:
9405
tp->nvram_jedecnum = JEDEC_ST;
9406
tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9407
tp->tg3_flags2 |= TG3_FLG2_FLASH;
9408
tp->nvram_pagesize = 256;
9409
break;
9410
}
9411
}
9412
9413
static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9414
{
9415
u32 nvcfg1;
9416
9417
nvcfg1 = tr32(NVRAM_CFG1);
9418
9419
switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9420
case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9421
case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9422
case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9423
case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9424
tp->nvram_jedecnum = JEDEC_ATMEL;
9425
tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9426
tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9427
9428
nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9429
tw32(NVRAM_CFG1, nvcfg1);
9430
break;
9431
case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9432
case FLASH_5755VENDOR_ATMEL_FLASH_1:
9433
case FLASH_5755VENDOR_ATMEL_FLASH_2:
9434
case FLASH_5755VENDOR_ATMEL_FLASH_3:
9435
tp->nvram_jedecnum = JEDEC_ATMEL;
9436
tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9437
tp->tg3_flags2 |= TG3_FLG2_FLASH;
9438
tp->nvram_pagesize = 264;
9439
break;
9440
case FLASH_5752VENDOR_ST_M45PE10:
9441
case FLASH_5752VENDOR_ST_M45PE20:
9442
case FLASH_5752VENDOR_ST_M45PE40:
9443
tp->nvram_jedecnum = JEDEC_ST;
9444
tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9445
tp->tg3_flags2 |= TG3_FLG2_FLASH;
9446
tp->nvram_pagesize = 256;
9447
break;
9448
}
9449
}
9450
9451
static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9452
{
9453
tp->nvram_jedecnum = JEDEC_ATMEL;
9454
tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9455
tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9456
}
9457
9458
8626
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
9459
8627
static void __devinit tg3_nvram_init(struct tg3 *tp)
9460
8628
{
9461
8629
int j;
9462
8630
8631
if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8632
return;
8633
9463
8634
tw32_f(GRC_EEPROM_ADDR,
9464
8635
(EEPROM_ADDR_FSM_RESET |
9465
8636
(EEPROM_DEFAULT_CLOCK_PERIOD <<
9487
8658
9488
8659
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9489
8660
tg3_get_5752_nvram_info(tp);
9490
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9491
tg3_get_5755_nvram_info(tp);
9492
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9493
tg3_get_5787_nvram_info(tp);
9494
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9495
tg3_get_5906_nvram_info(tp);
9496
8661
else
9497
8662
tg3_get_nvram_info(tp);
9498
8663
9562
8727
return 0;
9563
8728
}
9564
8729
9565
static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9566
{
9567
if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9568
(tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9569
(tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9570
(tp->nvram_jedecnum == JEDEC_ATMEL))
9571
9572
addr = ((addr / tp->nvram_pagesize) <<
9573
ATMEL_AT45DB0X1B_PAGE_POS) +
9574
(addr % tp->nvram_pagesize);
9575
9576
return addr;
9577
}
9578
9579
static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9580
{
9581
if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9582
(tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9583
(tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9584
(tp->nvram_jedecnum == JEDEC_ATMEL))
9585
9586
addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9587
tp->nvram_pagesize) +
9588
(addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9589
9590
return addr;
9591
}
9592
9593
8730
static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9594
8731
{
9595
8732
int ret;
9596
8733
8734
if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8735
printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8736
return -EINVAL;
8737
}
8738
9597
8739
if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9598
8740
return tg3_nvram_read_using_eeprom(tp, offset, val);
9599
8741
9600
offset = tg3_nvram_phys_addr(tp, offset);
8742
if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8743
(tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8744
(tp->nvram_jedecnum == JEDEC_ATMEL)) {
8745
8746
offset = ((offset / tp->nvram_pagesize) <<
8747
ATMEL_AT45DB0X1B_PAGE_POS) +
8748
(offset % tp->nvram_pagesize);
8749
}
9601
8750
9602
8751
if (offset > NVRAM_ADDR_MSK)
9603
8752
return -EINVAL;
9622
8771
return ret;
9623
8772
}
9624
8773
9625
static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9626
{
9627
int err;
9628
u32 tmp;
9629
9630
err = tg3_nvram_read(tp, offset, &tmp);
9631
*val = swab32(tmp);
9632
return err;
9633
}
9634
9635
8774
static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9636
8775
u32 offset, u32 len, u8 *buf)
9637
8776
{
9657
8796
(addr & EEPROM_ADDR_ADDR_MASK) |
9658
8797
EEPROM_ADDR_START |
9659
8798
EEPROM_ADDR_WRITE);
9660
8799
9661
8800
for (j = 0; j < 10000; j++) {
9662
8801
val = tr32(GRC_EEPROM_ADDR);
9663
8802
9693
8832
u32 phy_addr, page_off, size;
9694
8833
9695
8834
phy_addr = offset & ~pagemask;
9696
8835
9697
8836
for (j = 0; j < pagesize; j += 4) {
9698
8837
if ((ret = tg3_nvram_read(tp, phy_addr + j,
9699
8838
(u32 *) (tmp + j))))
9784
8923
9785
8924
page_off = offset % tp->nvram_pagesize;
9786
8925
9787
phy_addr = tg3_nvram_phys_addr(tp, offset);
8926
if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8927
(tp->nvram_jedecnum == JEDEC_ATMEL)) {
8928
8929
phy_addr = ((offset / tp->nvram_pagesize) <<
8930
ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8931
}
8932
else {
8933
phy_addr = offset;
8934
}
9788
8935
9789
8936
tw32(NVRAM_ADDR, phy_addr);
9790
8937
9792
8939
9793
8940
if ((page_off == 0) || (i == 0))
9794
8941
nvram_cmd |= NVRAM_CMD_FIRST;
9795
if (page_off == (tp->nvram_pagesize - 4))
8942
else if (page_off == (tp->nvram_pagesize - 4))
9796
8943
nvram_cmd |= NVRAM_CMD_LAST;
9797
8944
9798
8945
if (i == (len - 4))
9799
8946
nvram_cmd |= NVRAM_CMD_LAST;
9800
8947
9801
8948
if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9802
(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9803
(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9804
8949
(tp->nvram_jedecnum == JEDEC_ST) &&
9805
8950
(nvram_cmd & NVRAM_CMD_FIRST)) {
9806
8951
9826
8971
{
9827
8972
int ret;
9828
8973
8974
if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8975
printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8976
return -EINVAL;
8977
}
8978
9829
8979
if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9830
8980
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9831
8981
~GRC_LCLCTRL_GPIO_OUTPUT1);
9933
9083
return NULL;
9934
9084
}
9935
9085
9086
/* Since this function may be called in D3-hot power state during
9087
* tg3_init_one(), only config cycles are allowed.
9088
*/
9936
9089
static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9937
9090
{
9938
9091
u32 val;
9939
u16 pmcsr;
9940
9941
/* On some early chips the SRAM cannot be accessed in D3hot state,
9942
* so need make sure we're in D0.
9943
*/
9944
pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9945
pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9946
pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9947
msleep(1);
9948
9092
9949
9093
/* Make sure register accesses (indirect or otherwise)
9950
9094
* will function correctly.
9952
9096
pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9953
9097
tp->misc_host_ctrl);
9954
9098
9955
/* The memory arbiter has to be enabled in order for SRAM accesses
9956
* to succeed. Normally on powerup the tg3 chip firmware will make
9957
* sure it is enabled, but other entities such as system netboot
9958
* code might disable it.
9959
*/
9960
val = tr32(MEMARB_MODE);
9961
tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9962
9963
9099
tp->phy_id = PHY_ID_INVALID;
9964
9100
tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9965
9101
9966
/* Assume an onboard device by default. */
9967
tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9968
9969
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9970
if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM))
9971
tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9972
return;
9973
}
9974
9975
9102
tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9976
9103
if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9977
9104
u32 nic_cfg, led_cfg;
10068
9195
tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10069
9196
tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10070
9197
10071
if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
9198
if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9199
(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9200
(nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
10072
9201
tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10073
else
10074
tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10075
9202
10076
9203
if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10077
9204
tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10155
9282
if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10156
9283
(bmsr & BMSR_LSTATUS))
10157
9284
goto skip_phy_reset;
10158
9285
10159
9286
err = tg3_phy_reset(tp);
10160
9287
if (err)
10161
9288
return err;
10218
9345
{
10219
9346
unsigned char vpd_data[256];
10220
9347
unsigned int i;
10221
u32 magic;
10222
10223
if (tg3_nvram_read_swab(tp, 0x0, &magic))
10224
goto out_not_found;
10225
10226
if (magic == TG3_EEPROM_MAGIC) {
10227
for (i = 0; i < 256; i += 4) {
10228
u32 tmp;
10229
10230
if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10231
goto out_not_found;
10232
10233
vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10234
vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10235
vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10236
vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10237
}
10238
} else {
10239
int vpd_cap;
10240
10241
vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10242
for (i = 0; i < 256; i += 4) {
10243
u32 tmp, j = 0;
10244
u16 tmp16;
10245
10246
pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10247
i);
10248
while (j++ < 100) {
10249
pci_read_config_word(tp->pdev, vpd_cap +
10250
PCI_VPD_ADDR, &tmp16);
10251
if (tmp16 & 0x8000)
10252
break;
10253
msleep(1);
10254
}
10255
if (!(tmp16 & 0x8000))
10256
goto out_not_found;
10257
10258
pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10259
&tmp);
10260
tmp = cpu_to_le32(tmp);
10261
memcpy(&vpd_data[i], &tmp, 4);
10262
}
9348
9349
if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9350
/* Sun decided not to put the necessary bits in the
9351
* NVRAM of their onboard tg3 parts :(
9352
*/
9353
strcpy(tp->board_part_number, "Sun 570X");
9354
return;
9355
}
9356
9357
for (i = 0; i < 256; i += 4) {
9358
u32 tmp;
9359
9360
if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9361
goto out_not_found;
9362
9363
vpd_data[i + 0] = ((tmp >> 0) & 0xff);
9364
vpd_data[i + 1] = ((tmp >> 8) & 0xff);
9365
vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9366
vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10263
9367
}
10264
9368
10265
9369
/* Now parse and find the part number. */
10308
9412
}
10309
9413
10310
9414
out_not_found:
10311
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10312
strcpy(tp->board_part_number, "BCM95906");
10313
else
10314
strcpy(tp->board_part_number, "none");
9415
strcpy(tp->board_part_number, "none");
10315
9416
}
10316
9417
10317
static void __devinit tg3_read_fw_ver(struct tg3 *tp)
9418
#ifdef CONFIG_SPARC64
9419
static int __devinit tg3_is_sun_570X(struct tg3 *tp)
10318
9420
{
10319
u32 val, offset, start;
10320
10321
if (tg3_nvram_read_swab(tp, 0, &val))
10322
return;
10323
10324
if (val != TG3_EEPROM_MAGIC)
10325
return;
10326
10327
if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10328
tg3_nvram_read_swab(tp, 0x4, &start))
10329
return;
10330
10331
offset = tg3_nvram_logical_addr(tp, offset);
10332
if (tg3_nvram_read_swab(tp, offset, &val))
10333
return;
10334
10335
if ((val & 0xfc000000) == 0x0c000000) {
10336
u32 ver_offset, addr;
10337
int i;
10338
10339
if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10340
tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10341
return;
10342
10343
if (val != 0)
10344
return;
10345
10346
addr = offset + ver_offset - start;
10347
for (i = 0; i < 16; i += 4) {
10348
if (tg3_nvram_read(tp, addr + i, &val))
10349
return;
10350
10351
val = cpu_to_le32(val);
10352
memcpy(tp->fw_ver + i, &val, 4);
10353
}
9421
struct pci_dev *pdev = tp->pdev;
9422
struct pcidev_cookie *pcp = pdev->sysdata;
9423
9424
if (pcp != NULL) {
9425
int node = pcp->prom_node;
9426
u32 venid;
9427
int err;
9428
9429
err = prom_getproperty(node, "subsystem-vendor-id",
9430
(char *) &venid, sizeof(venid));
9431
if (err == 0 || err == -1)
9432
return 0;
9433
if (venid == PCI_VENDOR_ID_SUN)
9434
return 1;
9435
9436
/* TG3 chips onboard the SunBlade-2500 don't have the
9437
* subsystem-vendor-id set to PCI_VENDOR_ID_SUN but they
9438
* are distinguishable from non-Sun variants by being
9439
* named "network" by the firmware. Non-Sun cards will
9440
* show up as being named "ethernet".
9441
*/
9442
if (!strcmp(pcp->prom_name, "network"))
9443
return 1;
10354
9444
}
9445
return 0;
10355
9446
}
9447
#endif
10356
9448
10357
9449
static int __devinit tg3_get_invariants(struct tg3 *tp)
10358
9450
{
10359
9451
static struct pci_device_id write_reorder_chipsets[] = {
10360
9452
{ PCI_DEVICE(PCI_VENDOR_ID_AMD,
10361
9453
PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10362
{ PCI_DEVICE(PCI_VENDOR_ID_AMD,
10363
PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10364
9454
{ PCI_DEVICE(PCI_VENDOR_ID_VIA,
10365
9455
PCI_DEVICE_ID_VIA_8385_0) },
10366
9456
{ },
10370
9460
u32 pci_state_reg, grc_misc_cfg;
10371
9461
u32 val;
10372
9462
u16 pci_cmd;
10373
int err, pcie_cap;
9463
int err;
9464
9465
#ifdef CONFIG_SPARC64
9466
if (tg3_is_sun_570X(tp))
9467
tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
9468
#endif
10374
9469
10375
9470
/* Force memory write invalidate off. If we leave it on,
10376
9471
* then on 5700_BX chips we have to enable a workaround.
10511
9606
10512
9607
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10513
9608
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10514
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10515
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10516
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10517
9609
(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10518
9610
tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10519
9611
10521
9613
(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10522
9614
tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10523
9615
10524
if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10525
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10526
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10527
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10528
tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10529
tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10530
} else {
10531
tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
10532
TG3_FLG2_HW_TSO_1_BUG;
10533
if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10534
ASIC_REV_5750 &&
10535
tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10536
tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
10537
}
10538
}
9616
if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9617
tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
10539
9618
10540
9619
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10541
9620
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10542
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10543
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10544
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10545
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
9621
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
10546
9622
tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10547
9623
10548
pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10549
if (pcie_cap != 0) {
9624
if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
10550
9625
tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10551
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10552
u16 lnkctl;
10553
10554
pci_read_config_word(tp->pdev,
10555
pcie_cap + PCI_EXP_LNKCTL,
10556
&lnkctl);
10557
if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10558
tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10559
}
10560
}
10561
9626
10562
9627
/* If we have an AMD 762 or VIA K8T800 chipset, write
10563
9628
* reordering to the mailbox registers done by the host
10683
9748
pci_cmd &= ~PCI_COMMAND_MEMORY;
10684
9749
pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10685
9750
}
10686
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10687
tp->read32_mbox = tg3_read32_mbox_5906;
10688
tp->write32_mbox = tg3_write32_mbox_5906;
10689
tp->write32_tx_mbox = tg3_write32_mbox_5906;
10690
tp->write32_rx_mbox = tg3_write32_mbox_5906;
10691
}
10692
10693
if (tp->write32 == tg3_write_indirect_reg32 ||
10694
((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10695
(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10696
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10697
tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10698
9751
10699
9752
/* Get eeprom hw config before calling tg3_set_power_state().
10700
9753
* In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
10703
9756
* When the flag is set, it means that GPIO1 is used for eeprom
10704
9757
* write protect and also implies that it is a LOM where GPIOs
10705
9758
* are not used to switch power.
10706
*/
9759
*/
10707
9760
tg3_get_eeprom_hw_cfg(tp);
10708
9761
10709
9762
/* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10721
9774
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10722
9775
tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10723
9776
10724
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10725
tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10726
10727
9777
/* Force the chip into D0. */
10728
err = tg3_set_power_state(tp, PCI_D0);
9778
err = tg3_set_power_state(tp, 0);
10729
9779
if (err) {
10730
9780
printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10731
9781
pci_name(tp->pdev));
10738
9788
if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10739
9789
tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10740
9790
9791
/* Pseudo-header checksum is done by hardware logic and not
9792
* the offload processers, so make the chip do the pseudo-
9793
* header checksums on receive. For transmit it is more
9794
* convenient to do the pseudo-header checksum in software
9795
* as Linux does that on transmit for us in all cases.
9796
*/
9797
tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9798
tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9799
10741
9800
/* Derive initial jumbo mode from MTU assigned in
10742
9801
* ether_setup() via the alloc_etherdev() call
10743
9802
*/
10760
9819
((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10761
9820
(tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10762
9821
(tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10763
(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10764
9822
(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10765
9823
tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10766
9824
10770
9828
if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10771
9829
tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10772
9830
10773
if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10774
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10775
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10776
tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10777
else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10778
tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10779
}
9831
if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9832
tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10780
9833
10781
9834
tp->coalesce_mode = 0;
10782
9835
if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10864
9917
tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10865
9918
(tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10866
9919
(tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10867
tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)) ||
10868
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9920
tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
10869
9921
tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10870
9922
10871
9923
err = tg3_phy_probe(tp);
10876
9928
}
10877
9929
10878
9930
tg3_read_partno(tp);
10879
tg3_read_fw_ver(tp);
10880
9931
10881
9932
if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10882
9933
tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10912
9963
else
10913
9964
tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10914
9965
10915
/* All chips before 5787 can get confused if TX buffers
9966
/* It seems all chips can get confused if TX buffers
10916
9967
* straddle the 4GB address boundary in some cases.
10917
9968
*/
10918
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10919
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10920
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10921
tp->dev->hard_start_xmit = tg3_start_xmit;
10922
else
10923
tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
9969
tp->dev->hard_start_xmit = tg3_start_xmit;
10924
9970
10925
9971
tp->rx_offset = 2;
10926
9972
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10927
9973
(tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10928
9974
tp->rx_offset = 0;
10929
9975
10930
tp->rx_std_max_post = TG3_RX_RING_SIZE;
10931
10932
/* Increment the rx prod index on the rx std ring by at most
10933
* 8 for these chips to workaround hw errata.
10934
*/
10935
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10936
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10937
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10938
tp->rx_std_max_post = 8;
10939
10940
9976
/* By default, disable wake-on-lan. User can change this
10941
9977
* using ETHTOOL_SWOL.
10942
9978
*/
10953
9989
struct pcidev_cookie *pcp = pdev->sysdata;
10954
9990
10955
9991
if (pcp != NULL) {
10956
unsigned char *addr;
10957
int len;
9992
int node = pcp->prom_node;
10958
9993
10959
addr = of_get_property(pcp->prom_node, "local-mac-address",
10960
&len);
10961
if (addr && len == 6) {
10962
memcpy(dev->dev_addr, addr, 6);
9994
if (prom_getproplen(node, "local-mac-address") == 6) {
9995
prom_getproperty(node, "local-mac-address",
9996
dev->dev_addr, 6);
10963
9997
memcpy(dev->perm_addr, dev->dev_addr, 6);
10964
9998
return 0;
10965
9999
}
10981
10015
{
10982
10016
struct net_device *dev = tp->dev;
10983
10017
u32 hi, lo, mac_offset;
10984
int addr_ok = 0;
10985
10018
10986
10019
#ifdef CONFIG_SPARC64
10987
10020
if (!tg3_get_macaddr_sparc(tp))
10989
10022
#endif
10990
10023
10991
10024
mac_offset = 0x7c;
10992
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10025
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10026
!(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
10993
10027
(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10994
10028
if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
10995
10029
mac_offset = 0xcc;
10998
10032
else
10999
10033
tg3_nvram_unlock(tp);
11000
10034
}
11001
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11002
mac_offset = 0x10;
11003
10035
11004
10036
/* First try to get it from MAC address mailbox. */
11005
10037
tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11012
10044
dev->dev_addr[3] = (lo >> 16) & 0xff;
11013
10045
dev->dev_addr[4] = (lo >> 8) & 0xff;
11014
10046
dev->dev_addr[5] = (lo >> 0) & 0xff;
11015
11016
/* Some old bootcode may report a 0 MAC address in SRAM */
11017
addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11018
}
11019
if (!addr_ok) {
11020
/* Next, try NVRAM. */
11021
if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11022
!tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11023
dev->dev_addr[0] = ((hi >> 16) & 0xff);
11024
dev->dev_addr[1] = ((hi >> 24) & 0xff);
11025
dev->dev_addr[2] = ((lo >> 0) & 0xff);
11026
dev->dev_addr[3] = ((lo >> 8) & 0xff);
11027
dev->dev_addr[4] = ((lo >> 16) & 0xff);
11028
dev->dev_addr[5] = ((lo >> 24) & 0xff);
11029
}
11030
/* Finally just fetch it out of the MAC control regs. */
11031
else {
11032
hi = tr32(MAC_ADDR_0_HIGH);
11033
lo = tr32(MAC_ADDR_0_LOW);
11034
11035
dev->dev_addr[5] = lo & 0xff;
11036
dev->dev_addr[4] = (lo >> 8) & 0xff;
11037
dev->dev_addr[3] = (lo >> 16) & 0xff;
11038
dev->dev_addr[2] = (lo >> 24) & 0xff;
11039
dev->dev_addr[1] = hi & 0xff;
11040
dev->dev_addr[0] = (hi >> 8) & 0xff;
11041
}
10047
}
10048
/* Next, try NVRAM. */
10049
else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
10050
!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
10051
!tg3_nvram_read(tp, mac_offset + 4, &lo)) {
10052
dev->dev_addr[0] = ((hi >> 16) & 0xff);
10053
dev->dev_addr[1] = ((hi >> 24) & 0xff);
10054
dev->dev_addr[2] = ((lo >> 0) & 0xff);
10055
dev->dev_addr[3] = ((lo >> 8) & 0xff);
10056
dev->dev_addr[4] = ((lo >> 16) & 0xff);
10057
dev->dev_addr[5] = ((lo >> 24) & 0xff);
10058
}
10059
/* Finally just fetch it out of the MAC control regs. */
10060
else {
10061
hi = tr32(MAC_ADDR_0_HIGH);
10062
lo = tr32(MAC_ADDR_0_LOW);
10063
10064
dev->dev_addr[5] = lo & 0xff;
10065
dev->dev_addr[4] = (lo >> 8) & 0xff;
10066
dev->dev_addr[3] = (lo >> 16) & 0xff;
10067
dev->dev_addr[2] = (lo >> 24) & 0xff;
10068
dev->dev_addr[1] = hi & 0xff;
10069
dev->dev_addr[0] = (hi >> 8) & 0xff;
11042
10070
}
11043
10071
11044
10072
if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11466
10494
tp->link_config.speed = SPEED_INVALID;
11467
10495
tp->link_config.duplex = DUPLEX_INVALID;
11468
10496
tp->link_config.autoneg = AUTONEG_ENABLE;
10497
netif_carrier_off(tp->dev);
11469
10498
tp->link_config.active_speed = SPEED_INVALID;
11470
10499
tp->link_config.active_duplex = DUPLEX_INVALID;
11471
10500
tp->link_config.phy_is_low_power = 0;
11483
10512
DEFAULT_MB_MACRX_LOW_WATER_5705;
11484
10513
tp->bufmgr_config.mbuf_high_water =
11485
10514
DEFAULT_MB_HIGH_WATER_5705;
11486
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11487
tp->bufmgr_config.mbuf_mac_rx_low_water =
11488
DEFAULT_MB_MACRX_LOW_WATER_5906;
11489
tp->bufmgr_config.mbuf_high_water =
11490
DEFAULT_MB_HIGH_WATER_5906;
11491
}
11492
10515
11493
10516
tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11494
10517
DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11530
10553
case PHY_ID_BCM5752: return "5752";
11531
10554
case PHY_ID_BCM5714: return "5714";
11532
10555
case PHY_ID_BCM5780: return "5780";
11533
case PHY_ID_BCM5755: return "5755";
11534
case PHY_ID_BCM5787: return "5787";
11535
case PHY_ID_BCM5756: return "5722/5756";
11536
case PHY_ID_BCM5906: return "5906";
11537
10556
case PHY_ID_BCM8002: return "8002/serdes";
11538
10557
case 0: return "serdes";
11539
10558
default: return "unknown";
11694
10713
SET_MODULE_OWNER(dev);
11695
10714
SET_NETDEV_DEV(dev, &pdev->dev);
11696
10715
10716
dev->features |= NETIF_F_LLTX;
11697
10717
#if TG3_VLAN_TAG_USED
11698
10718
dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11699
10719
dev->vlan_rx_register = tg3_vlan_rx_register;
11735
10755
tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11736
10756
#endif
11737
10757
spin_lock_init(&tp->lock);
10758
spin_lock_init(&tp->tx_lock);
11738
10759
spin_lock_init(&tp->indirect_lock);
11739
10760
INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
11740
10761
11824
10845
else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11825
10846
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11826
10847
tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11827
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11828
10848
(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11829
10849
tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11830
10850
} else {
11831
10851
tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11832
10852
}
11833
10853
11834
/* TSO is on by default on chips that support hardware TSO.
11835
* Firmware TSO on older chips gives lower performance, so it
11836
* is off by default, but can be enabled using ethtool.
11837
*/
11838
if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
10854
/* TSO is off by default, user can enable using ethtool. */
10855
#if 0
10856
if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
11839
10857
dev->features |= NETIF_F_TSO;
11840
if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11841
(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11842
dev->features |= NETIF_F_TSO6;
11843
}
10858
#endif
11844
10859
11845
10860
#endif
11846
10861
11884
10899
* checksumming.
11885
10900
*/
11886
10901
if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11887
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11888
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11889
dev->features |= NETIF_F_HW_CSUM;
11890
else
11891
dev->features |= NETIF_F_IP_CSUM;
11892
dev->features |= NETIF_F_SG;
10902
dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
11893
10903
tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11894
10904
} else
11895
10905
tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11942
10952
(pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11943
10953
(((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11944
10954
11945
netif_carrier_off(tp->dev);
11946
11947
10955
return 0;
11948
10956
11949
10957
err_out_iounmap:
12014
11022
tg3_full_lock(tp, 0);
12015
11023
12016
11024
tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12017
if (tg3_restart_hw(tp, 1))
12018
goto out;
11025
tg3_init_hw(tp);
12019
11026
12020
11027
tp->timer.expires = jiffies + tp->timer_offset;
12021
11028
add_timer(&tp->timer);
12023
11030
netif_device_attach(dev);
12024
11031
tg3_netif_start(tp);
12025
11032
12026
out:
12027
11033
tg3_full_unlock(tp);
12028
11034
}
12029
11035
12041
11047
12042
11048
pci_restore_state(tp->pdev);
12043
11049
12044
err = tg3_set_power_state(tp, PCI_D0);
11050
err = tg3_set_power_state(tp, 0);
12045
11051
if (err)
12046
11052
return err;
12047
11053
12050
11056
tg3_full_lock(tp, 0);
12051
11057
12052
11058
tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12053
err = tg3_restart_hw(tp, 1);
12054
if (err)
12055
goto out;
11059
tg3_init_hw(tp);
12056
11060
12057
11061
tp->timer.expires = jiffies + tp->timer_offset;
12058
11062
add_timer(&tp->timer);
12059
11063
12060
11064
tg3_netif_start(tp);
12061
11065
12062
out:
12063
11066
tg3_full_unlock(tp);
12064
11067
12065
return err;
11068
return 0;
12066
11069
}
12067
11070
12068
11071
static struct pci_driver tg3_driver = {
12076
11079
12077
11080
static int __init tg3_init(void)
12078
11081
{
12079
return pci_register_driver(&tg3_driver);
11082
return pci_module_init(&tg3_driver);
12080
11083
}
12081
11084
12082
11085
static void __exit tg3_cleanup(void)
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Version: 2.0.1