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* NAND flash simulator.
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* Author: Artem B. Bityuckiy <dedekind@oktetlabs.ru>, <dedekind@infradead.org>
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* Copyright (C) 2004 Nokia Corporation
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* Note: NS means "NAND Simulator".
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* Note: Input means input TO flash chip, output means output FROM chip.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any later
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
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* Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
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* $Id: nandsim.c,v 1.7 2004/12/06 11:53:06 dedekind Exp $
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/vmalloc.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/delay.h>
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#ifdef CONFIG_NS_ABS_POS
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/* Default simulator parameters values */
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#if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \
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!defined(CONFIG_NANDSIM_SECOND_ID_BYTE) || \
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!defined(CONFIG_NANDSIM_THIRD_ID_BYTE) || \
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!defined(CONFIG_NANDSIM_FOURTH_ID_BYTE)
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#define CONFIG_NANDSIM_FIRST_ID_BYTE 0x98
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#define CONFIG_NANDSIM_SECOND_ID_BYTE 0x39
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#define CONFIG_NANDSIM_THIRD_ID_BYTE 0xFF /* No byte */
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#define CONFIG_NANDSIM_FOURTH_ID_BYTE 0xFF /* No byte */
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#ifndef CONFIG_NANDSIM_ACCESS_DELAY
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#define CONFIG_NANDSIM_ACCESS_DELAY 25
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#ifndef CONFIG_NANDSIM_PROGRAMM_DELAY
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#define CONFIG_NANDSIM_PROGRAMM_DELAY 200
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#ifndef CONFIG_NANDSIM_ERASE_DELAY
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#define CONFIG_NANDSIM_ERASE_DELAY 2
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#ifndef CONFIG_NANDSIM_OUTPUT_CYCLE
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#define CONFIG_NANDSIM_OUTPUT_CYCLE 40
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#ifndef CONFIG_NANDSIM_INPUT_CYCLE
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#define CONFIG_NANDSIM_INPUT_CYCLE 50
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#ifndef CONFIG_NANDSIM_BUS_WIDTH
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#define CONFIG_NANDSIM_BUS_WIDTH 8
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#ifndef CONFIG_NANDSIM_DO_DELAYS
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#define CONFIG_NANDSIM_DO_DELAYS 0
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#ifndef CONFIG_NANDSIM_LOG
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#define CONFIG_NANDSIM_LOG 0
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#ifndef CONFIG_NANDSIM_DBG
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#define CONFIG_NANDSIM_DBG 0
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static uint first_id_byte = CONFIG_NANDSIM_FIRST_ID_BYTE;
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static uint second_id_byte = CONFIG_NANDSIM_SECOND_ID_BYTE;
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static uint third_id_byte = CONFIG_NANDSIM_THIRD_ID_BYTE;
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static uint fourth_id_byte = CONFIG_NANDSIM_FOURTH_ID_BYTE;
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static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY;
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static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY;
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static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY;
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static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE;
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static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE;
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static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH;
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static uint do_delays = CONFIG_NANDSIM_DO_DELAYS;
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static uint log = CONFIG_NANDSIM_LOG;
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static uint dbg = CONFIG_NANDSIM_DBG;
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module_param(first_id_byte, uint, 0400);
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module_param(second_id_byte, uint, 0400);
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module_param(third_id_byte, uint, 0400);
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module_param(fourth_id_byte, uint, 0400);
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module_param(access_delay, uint, 0400);
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module_param(programm_delay, uint, 0400);
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module_param(erase_delay, uint, 0400);
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module_param(output_cycle, uint, 0400);
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module_param(input_cycle, uint, 0400);
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module_param(bus_width, uint, 0400);
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module_param(do_delays, uint, 0400);
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module_param(log, uint, 0400);
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module_param(dbg, uint, 0400);
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MODULE_PARM_DESC(first_id_byte, "The fist byte returned by NAND Flash 'read ID' command (manufaturer ID)");
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MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID)");
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MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command");
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MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command");
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MODULE_PARM_DESC(access_delay, "Initial page access delay (microiseconds)");
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MODULE_PARM_DESC(programm_delay, "Page programm delay (microseconds");
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MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)");
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MODULE_PARM_DESC(output_cycle, "Word output (from flash) time (nanodeconds)");
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MODULE_PARM_DESC(input_cycle, "Word input (to flash) time (nanodeconds)");
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MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
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MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero");
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MODULE_PARM_DESC(log, "Perform logging if not zero");
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MODULE_PARM_DESC(dbg, "Output debug information if not zero");
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/* The largest possible page size */
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#define NS_LARGEST_PAGE_SIZE 2048
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/* The prefix for simulator output */
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#define NS_OUTPUT_PREFIX "[nandsim]"
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/* Simulator's output macros (logging, debugging, warning, error) */
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#define NS_LOG(args...) \
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do { if (log) printk(KERN_DEBUG NS_OUTPUT_PREFIX " log: " args); } while(0)
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#define NS_DBG(args...) \
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do { if (dbg) printk(KERN_DEBUG NS_OUTPUT_PREFIX " debug: " args); } while(0)
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#define NS_WARN(args...) \
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do { printk(KERN_WARNING NS_OUTPUT_PREFIX " warnig: " args); } while(0)
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#define NS_ERR(args...) \
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do { printk(KERN_ERR NS_OUTPUT_PREFIX " errorr: " args); } while(0)
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/* Busy-wait delay macros (microseconds, milliseconds) */
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#define NS_UDELAY(us) \
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do { if (do_delays) udelay(us); } while(0)
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#define NS_MDELAY(us) \
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do { if (do_delays) mdelay(us); } while(0)
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/* Is the nandsim structure initialized ? */
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#define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0)
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/* Good operation completion status */
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#define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))
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/* Operation failed completion status */
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#define NS_STATUS_FAILED(ns) (NAND_STATUS_FAIL | NS_STATUS_OK(ns))
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/* Calculate the page offset in flash RAM image by (row, column) address */
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#define NS_RAW_OFFSET(ns) \
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(((ns)->regs.row << (ns)->geom.pgshift) + ((ns)->regs.row * (ns)->geom.oobsz) + (ns)->regs.column)
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/* Calculate the OOB offset in flash RAM image by (row, column) address */
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#define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz)
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/* After a command is input, the simulator goes to one of the following states */
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#define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */
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#define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */
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#define STATE_CMD_READSTART 0x00000003 /* read data second command (large page devices) */
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#define STATE_CMD_PAGEPROG 0x00000004 /* start page programm */
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#define STATE_CMD_READOOB 0x00000005 /* read OOB area */
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#define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */
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#define STATE_CMD_STATUS 0x00000007 /* read status */
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#define STATE_CMD_STATUS_M 0x00000008 /* read multi-plane status (isn't implemented) */
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#define STATE_CMD_SEQIN 0x00000009 /* sequential data imput */
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#define STATE_CMD_READID 0x0000000A /* read ID */
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#define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */
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#define STATE_CMD_RESET 0x0000000C /* reset */
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#define STATE_CMD_MASK 0x0000000F /* command states mask */
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/* After an addres is input, the simulator goes to one of these states */
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#define STATE_ADDR_PAGE 0x00000010 /* full (row, column) address is accepted */
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#define STATE_ADDR_SEC 0x00000020 /* sector address was accepted */
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#define STATE_ADDR_ZERO 0x00000030 /* one byte zero address was accepted */
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#define STATE_ADDR_MASK 0x00000030 /* address states mask */
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/* Durind data input/output the simulator is in these states */
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#define STATE_DATAIN 0x00000100 /* waiting for data input */
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#define STATE_DATAIN_MASK 0x00000100 /* data input states mask */
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#define STATE_DATAOUT 0x00001000 /* waiting for page data output */
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#define STATE_DATAOUT_ID 0x00002000 /* waiting for ID bytes output */
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#define STATE_DATAOUT_STATUS 0x00003000 /* waiting for status output */
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#define STATE_DATAOUT_STATUS_M 0x00004000 /* waiting for multi-plane status output */
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#define STATE_DATAOUT_MASK 0x00007000 /* data output states mask */
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/* Previous operation is done, ready to accept new requests */
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#define STATE_READY 0x00000000
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/* This state is used to mark that the next state isn't known yet */
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#define STATE_UNKNOWN 0x10000000
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/* Simulator's actions bit masks */
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#define ACTION_CPY 0x00100000 /* copy page/OOB to the internal buffer */
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#define ACTION_PRGPAGE 0x00200000 /* programm the internal buffer to flash */
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#define ACTION_SECERASE 0x00300000 /* erase sector */
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#define ACTION_ZEROOFF 0x00400000 /* don't add any offset to address */
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#define ACTION_HALFOFF 0x00500000 /* add to address half of page */
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#define ACTION_OOBOFF 0x00600000 /* add to address OOB offset */
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#define ACTION_MASK 0x00700000 /* action mask */
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#define NS_OPER_NUM 12 /* Number of operations supported by the simulator */
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#define NS_OPER_STATES 6 /* Maximum number of states in operation */
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#define OPT_ANY 0xFFFFFFFF /* any chip supports this operation */
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#define OPT_PAGE256 0x00000001 /* 256-byte page chips */
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#define OPT_PAGE512 0x00000002 /* 512-byte page chips */
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#define OPT_PAGE2048 0x00000008 /* 2048-byte page chips */
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#define OPT_SMARTMEDIA 0x00000010 /* SmartMedia technology chips */
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#define OPT_AUTOINCR 0x00000020 /* page number auto inctimentation is possible */
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#define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */
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#define OPT_LARGEPAGE (OPT_PAGE2048) /* 2048-byte page chips */
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#define OPT_SMALLPAGE (OPT_PAGE256 | OPT_PAGE512) /* 256 and 512-byte page chips */
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/* Remove action bits ftom state */
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#define NS_STATE(x) ((x) & ~ACTION_MASK)
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* Maximum previous states which need to be saved. Currently saving is
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* only needed for page programm operation with preceeded read command
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* (which is only valid for 512-byte pages).
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#define NS_MAX_PREVSTATES 1
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* The structure which describes all the internal simulator data.
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struct mtd_partition part;
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uint busw; /* flash chip bus width (8 or 16) */
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u_char ids[4]; /* chip's ID bytes */
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uint32_t options; /* chip's characteristic bits */
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uint32_t state; /* current chip state */
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uint32_t nxstate; /* next expected state */
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uint32_t *op; /* current operation, NULL operations isn't known yet */
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uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */
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uint16_t npstates; /* number of previous states saved */
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uint16_t stateidx; /* current state index */
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/* The simulated NAND flash image */
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/* Internal buffer of page + OOB size bytes */
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union internal_buffer {
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u_char *byte; /* for byte access */
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uint16_t *word; /* for 16-bit word access */
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/* NAND flash "geometry" */
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struct nandsin_geometry {
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uint32_t totsz; /* total flash size, bytes */
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uint32_t secsz; /* flash sector (erase block) size, bytes */
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uint pgsz; /* NAND flash page size, bytes */
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uint oobsz; /* page OOB area size, bytes */
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uint32_t totszoob; /* total flash size including OOB, bytes */
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uint pgszoob; /* page size including OOB , bytes*/
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uint secszoob; /* sector size including OOB, bytes */
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uint pgnum; /* total number of pages */
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uint pgsec; /* number of pages per sector */
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uint secshift; /* bits number in sector size */
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uint pgshift; /* bits number in page size */
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uint oobshift; /* bits number in OOB size */
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uint pgaddrbytes; /* bytes per page address */
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uint secaddrbytes; /* bytes per sector address */
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uint idbytes; /* the number ID bytes that this chip outputs */
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/* NAND flash internal registers */
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struct nandsim_regs {
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unsigned command; /* the command register */
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u_char status; /* the status register */
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uint row; /* the page number */
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uint column; /* the offset within page */
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uint count; /* internal counter */
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uint num; /* number of bytes which must be processed */
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uint off; /* fixed page offset */
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/* NAND flash lines state */
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struct ns_lines_status {
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int ce; /* chip Enable */
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int cle; /* command Latch Enable */
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int ale; /* address Latch Enable */
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int wp; /* write Protect */
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* Operations array. To perform any operation the simulator must pass
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* through the correspondent states chain.
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static struct nandsim_operations {
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uint32_t reqopts; /* options which are required to perform the operation */
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uint32_t states[NS_OPER_STATES]; /* operation's states */
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} ops[NS_OPER_NUM] = {
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/* Read page + OOB from the beginning */
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{OPT_SMALLPAGE, {STATE_CMD_READ0 | ACTION_ZEROOFF, STATE_ADDR_PAGE | ACTION_CPY,
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STATE_DATAOUT, STATE_READY}},
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/* Read page + OOB from the second half */
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{OPT_PAGE512_8BIT, {STATE_CMD_READ1 | ACTION_HALFOFF, STATE_ADDR_PAGE | ACTION_CPY,
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STATE_DATAOUT, STATE_READY}},
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{OPT_SMALLPAGE, {STATE_CMD_READOOB | ACTION_OOBOFF, STATE_ADDR_PAGE | ACTION_CPY,
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STATE_DATAOUT, STATE_READY}},
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/* Programm page starting from the beginning */
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{OPT_ANY, {STATE_CMD_SEQIN, STATE_ADDR_PAGE, STATE_DATAIN,
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STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
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/* Programm page starting from the beginning */
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{OPT_SMALLPAGE, {STATE_CMD_READ0, STATE_CMD_SEQIN | ACTION_ZEROOFF, STATE_ADDR_PAGE,
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STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
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/* Programm page starting from the second half */
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{OPT_PAGE512, {STATE_CMD_READ1, STATE_CMD_SEQIN | ACTION_HALFOFF, STATE_ADDR_PAGE,
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STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
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{OPT_SMALLPAGE, {STATE_CMD_READOOB, STATE_CMD_SEQIN | ACTION_OOBOFF, STATE_ADDR_PAGE,
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STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
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{OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}},
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{OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}},
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/* Read multi-plane status */
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{OPT_SMARTMEDIA, {STATE_CMD_STATUS_M, STATE_DATAOUT_STATUS_M, STATE_READY}},
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{OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}},
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/* Large page devices read page */
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{OPT_LARGEPAGE, {STATE_CMD_READ0, STATE_ADDR_PAGE, STATE_CMD_READSTART | ACTION_CPY,
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STATE_DATAOUT, STATE_READY}}
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/* MTD structure for NAND controller */
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static struct mtd_info *nsmtd;
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static u_char ns_verify_buf[NS_LARGEST_PAGE_SIZE];
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* Initialize the nandsim structure.
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* RETURNS: 0 if success, -ERRNO if failure.
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init_nandsim(struct mtd_info *mtd)
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struct nand_chip *chip = (struct nand_chip *)mtd->priv;
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struct nandsim *ns = (struct nandsim *)(chip->priv);
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if (NS_IS_INITIALIZED(ns)) {
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NS_ERR("init_nandsim: nandsim is already initialized\n");
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/* Force mtd to not do delays */
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chip->chip_delay = 0;
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/* Initialize the NAND flash parameters */
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ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8;
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ns->geom.totsz = mtd->size;
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ns->geom.pgsz = mtd->oobblock;
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ns->geom.oobsz = mtd->oobsize;
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ns->geom.secsz = mtd->erasesize;
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ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz;
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ns->geom.pgnum = ns->geom.totsz / ns->geom.pgsz;
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ns->geom.totszoob = ns->geom.totsz + ns->geom.pgnum * ns->geom.oobsz;
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ns->geom.secshift = ffs(ns->geom.secsz) - 1;
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ns->geom.pgshift = chip->page_shift;
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ns->geom.oobshift = ffs(ns->geom.oobsz) - 1;
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ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz;
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ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec;
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if (ns->geom.pgsz == 256) {
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ns->options |= OPT_PAGE256;
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else if (ns->geom.pgsz == 512) {
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ns->options |= (OPT_PAGE512 | OPT_AUTOINCR);
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ns->options |= OPT_PAGE512_8BIT;
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} else if (ns->geom.pgsz == 2048) {
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ns->options |= OPT_PAGE2048;
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NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz);
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if (ns->options & OPT_SMALLPAGE) {
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if (ns->geom.totsz < (64 << 20)) {
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ns->geom.pgaddrbytes = 3;
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ns->geom.secaddrbytes = 2;
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ns->geom.pgaddrbytes = 4;
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ns->geom.secaddrbytes = 3;
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if (ns->geom.totsz <= (128 << 20)) {
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ns->geom.pgaddrbytes = 5;
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ns->geom.secaddrbytes = 2;
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ns->geom.pgaddrbytes = 5;
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ns->geom.secaddrbytes = 3;
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/* Detect how many ID bytes the NAND chip outputs */
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for (i = 0; nand_flash_ids[i].name != NULL; i++) {
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if (second_id_byte != nand_flash_ids[i].id)
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if (!(nand_flash_ids[i].options & NAND_NO_AUTOINCR))
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ns->options |= OPT_AUTOINCR;
426
NS_WARN("16-bit flashes support wasn't tested\n");
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printk("flash size: %u MiB\n", ns->geom.totsz >> 20);
429
printk("page size: %u bytes\n", ns->geom.pgsz);
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printk("OOB area size: %u bytes\n", ns->geom.oobsz);
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printk("sector size: %u KiB\n", ns->geom.secsz >> 10);
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printk("pages number: %u\n", ns->geom.pgnum);
433
printk("pages per sector: %u\n", ns->geom.pgsec);
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printk("bus width: %u\n", ns->busw);
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printk("bits in sector size: %u\n", ns->geom.secshift);
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printk("bits in page size: %u\n", ns->geom.pgshift);
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printk("bits in OOB size: %u\n", ns->geom.oobshift);
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printk("flash size with OOB: %u KiB\n", ns->geom.totszoob >> 10);
439
printk("page address bytes: %u\n", ns->geom.pgaddrbytes);
440
printk("sector address bytes: %u\n", ns->geom.secaddrbytes);
441
printk("options: %#x\n", ns->options);
443
/* Map / allocate and initialize the flash image */
444
#ifdef CONFIG_NS_ABS_POS
445
ns->mem.byte = ioremap(CONFIG_NS_ABS_POS, ns->geom.totszoob);
447
NS_ERR("init_nandsim: failed to map the NAND flash image at address %p\n",
448
(void *)CONFIG_NS_ABS_POS);
452
ns->mem.byte = vmalloc(ns->geom.totszoob);
454
NS_ERR("init_nandsim: unable to allocate %u bytes for flash image\n",
458
memset(ns->mem.byte, 0xFF, ns->geom.totszoob);
461
/* Allocate / initialize the internal buffer */
462
ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
464
NS_ERR("init_nandsim: unable to allocate %u bytes for the internal buffer\n",
468
memset(ns->buf.byte, 0xFF, ns->geom.pgszoob);
470
/* Fill the partition_info structure */
471
ns->part.name = "NAND simulator partition";
473
ns->part.size = ns->geom.totsz;
478
#ifdef CONFIG_NS_ABS_POS
479
iounmap(ns->mem.byte);
488
* Free the nandsim structure.
491
free_nandsim(struct nandsim *ns)
495
#ifdef CONFIG_NS_ABS_POS
496
iounmap(ns->mem.byte);
505
* Returns the string representation of 'state' state.
508
get_state_name(uint32_t state)
510
switch (NS_STATE(state)) {
511
case STATE_CMD_READ0:
512
return "STATE_CMD_READ0";
513
case STATE_CMD_READ1:
514
return "STATE_CMD_READ1";
515
case STATE_CMD_PAGEPROG:
516
return "STATE_CMD_PAGEPROG";
517
case STATE_CMD_READOOB:
518
return "STATE_CMD_READOOB";
519
case STATE_CMD_READSTART:
520
return "STATE_CMD_READSTART";
521
case STATE_CMD_ERASE1:
522
return "STATE_CMD_ERASE1";
523
case STATE_CMD_STATUS:
524
return "STATE_CMD_STATUS";
525
case STATE_CMD_STATUS_M:
526
return "STATE_CMD_STATUS_M";
527
case STATE_CMD_SEQIN:
528
return "STATE_CMD_SEQIN";
529
case STATE_CMD_READID:
530
return "STATE_CMD_READID";
531
case STATE_CMD_ERASE2:
532
return "STATE_CMD_ERASE2";
533
case STATE_CMD_RESET:
534
return "STATE_CMD_RESET";
535
case STATE_ADDR_PAGE:
536
return "STATE_ADDR_PAGE";
538
return "STATE_ADDR_SEC";
539
case STATE_ADDR_ZERO:
540
return "STATE_ADDR_ZERO";
542
return "STATE_DATAIN";
544
return "STATE_DATAOUT";
545
case STATE_DATAOUT_ID:
546
return "STATE_DATAOUT_ID";
547
case STATE_DATAOUT_STATUS:
548
return "STATE_DATAOUT_STATUS";
549
case STATE_DATAOUT_STATUS_M:
550
return "STATE_DATAOUT_STATUS_M";
552
return "STATE_READY";
554
return "STATE_UNKNOWN";
557
NS_ERR("get_state_name: unknown state, BUG\n");
562
* Check if command is valid.
564
* RETURNS: 1 if wrong command, 0 if right.
567
check_command(int cmd)
572
case NAND_CMD_READSTART:
573
case NAND_CMD_PAGEPROG:
574
case NAND_CMD_READOOB:
575
case NAND_CMD_ERASE1:
576
case NAND_CMD_STATUS:
578
case NAND_CMD_READID:
579
case NAND_CMD_ERASE2:
584
case NAND_CMD_STATUS_MULTI:
591
* Returns state after command is accepted by command number.
594
get_state_by_command(unsigned command)
598
return STATE_CMD_READ0;
600
return STATE_CMD_READ1;
601
case NAND_CMD_PAGEPROG:
602
return STATE_CMD_PAGEPROG;
603
case NAND_CMD_READSTART:
604
return STATE_CMD_READSTART;
605
case NAND_CMD_READOOB:
606
return STATE_CMD_READOOB;
607
case NAND_CMD_ERASE1:
608
return STATE_CMD_ERASE1;
609
case NAND_CMD_STATUS:
610
return STATE_CMD_STATUS;
611
case NAND_CMD_STATUS_MULTI:
612
return STATE_CMD_STATUS_M;
614
return STATE_CMD_SEQIN;
615
case NAND_CMD_READID:
616
return STATE_CMD_READID;
617
case NAND_CMD_ERASE2:
618
return STATE_CMD_ERASE2;
620
return STATE_CMD_RESET;
623
NS_ERR("get_state_by_command: unknown command, BUG\n");
628
* Move an address byte to the correspondent internal register.
631
accept_addr_byte(struct nandsim *ns, u_char bt)
633
uint byte = (uint)bt;
635
if (ns->regs.count < (ns->geom.pgaddrbytes - ns->geom.secaddrbytes))
636
ns->regs.column |= (byte << 8 * ns->regs.count);
638
ns->regs.row |= (byte << 8 * (ns->regs.count -
639
ns->geom.pgaddrbytes +
640
ns->geom.secaddrbytes));
647
* Switch to STATE_READY state.
650
switch_to_ready_state(struct nandsim *ns, u_char status)
652
NS_DBG("switch_to_ready_state: switch to %s state\n", get_state_name(STATE_READY));
654
ns->state = STATE_READY;
655
ns->nxstate = STATE_UNKNOWN;
664
ns->regs.status = status;
668
* If the operation isn't known yet, try to find it in the global array
669
* of supported operations.
671
* Operation can be unknown because of the following.
672
* 1. New command was accepted and this is the firs call to find the
673
* correspondent states chain. In this case ns->npstates = 0;
674
* 2. There is several operations which begin with the same command(s)
675
* (for example program from the second half and read from the
676
* second half operations both begin with the READ1 command). In this
677
* case the ns->pstates[] array contains previous states.
679
* Thus, the function tries to find operation containing the following
680
* states (if the 'flag' parameter is 0):
681
* ns->pstates[0], ... ns->pstates[ns->npstates], ns->state
683
* If (one and only one) matching operation is found, it is accepted (
684
* ns->ops, ns->state, ns->nxstate are initialized, ns->npstate is
687
* If there are several maches, the current state is pushed to the
690
* The operation can be unknown only while commands are input to the chip.
691
* As soon as address command is accepted, the operation must be known.
692
* In such situation the function is called with 'flag' != 0, and the
693
* operation is searched using the following pattern:
694
* ns->pstates[0], ... ns->pstates[ns->npstates], <address input>
696
* It is supposed that this pattern must either match one operation on
697
* none. There can't be ambiguity in that case.
699
* If no matches found, the functions does the following:
700
* 1. if there are saved states present, try to ignore them and search
701
* again only using the last command. If nothing was found, switch
702
* to the STATE_READY state.
703
* 2. if there are no saved states, switch to the STATE_READY state.
705
* RETURNS: -2 - no matched operations found.
706
* -1 - several matches.
707
* 0 - operation is found.
710
find_operation(struct nandsim *ns, uint32_t flag)
715
for (i = 0; i < NS_OPER_NUM; i++) {
719
if (!(ns->options & ops[i].reqopts))
720
/* Ignore operations we can't perform */
724
if (!(ops[i].states[ns->npstates] & STATE_ADDR_MASK))
727
if (NS_STATE(ns->state) != NS_STATE(ops[i].states[ns->npstates]))
731
for (j = 0; j < ns->npstates; j++)
732
if (NS_STATE(ops[i].states[j]) != NS_STATE(ns->pstates[j])
733
&& (ns->options & ops[idx].reqopts)) {
746
ns->op = &ops[idx].states[0];
749
* In this case the find_operation function was
750
* called when address has just began input. But it isn't
751
* yet fully input and the current state must
752
* not be one of STATE_ADDR_*, but the STATE_ADDR_*
753
* state must be the next state (ns->nxstate).
755
ns->stateidx = ns->npstates - 1;
757
ns->stateidx = ns->npstates;
760
ns->state = ns->op[ns->stateidx];
761
ns->nxstate = ns->op[ns->stateidx + 1];
762
NS_DBG("find_operation: operation found, index: %d, state: %s, nxstate %s\n",
763
idx, get_state_name(ns->state), get_state_name(ns->nxstate));
768
/* Nothing was found. Try to ignore previous commands (if any) and search again */
769
if (ns->npstates != 0) {
770
NS_DBG("find_operation: no operation found, try again with state %s\n",
771
get_state_name(ns->state));
773
return find_operation(ns, 0);
776
NS_DBG("find_operation: no operations found\n");
777
switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
782
/* This shouldn't happen */
783
NS_DBG("find_operation: BUG, operation must be known if address is input\n");
787
NS_DBG("find_operation: there is still ambiguity\n");
789
ns->pstates[ns->npstates++] = ns->state;
795
* If state has any action bit, perform this action.
797
* RETURNS: 0 if success, -1 if error.
800
do_state_action(struct nandsim *ns, uint32_t action)
803
int busdiv = ns->busw == 8 ? 1 : 2;
805
action &= ACTION_MASK;
807
/* Check that page address input is correct */
808
if (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) {
809
NS_WARN("do_state_action: wrong page number (%#x)\n", ns->regs.row);
817
* Copy page data to the internal buffer.
820
/* Column shouldn't be very large */
821
if (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) {
822
NS_ERR("do_state_action: column number is too large\n");
825
num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
826
memcpy(ns->buf.byte, ns->mem.byte + NS_RAW_OFFSET(ns) + ns->regs.off, num);
828
NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n",
829
num, NS_RAW_OFFSET(ns) + ns->regs.off);
831
if (ns->regs.off == 0)
832
NS_LOG("read page %d\n", ns->regs.row);
833
else if (ns->regs.off < ns->geom.pgsz)
834
NS_LOG("read page %d (second half)\n", ns->regs.row);
836
NS_LOG("read OOB of page %d\n", ns->regs.row);
838
NS_UDELAY(access_delay);
839
NS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv);
843
case ACTION_SECERASE:
849
NS_ERR("do_state_action: device is write-protected, ignore sector erase\n");
853
if (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec
854
|| (ns->regs.row & ~(ns->geom.secsz - 1))) {
855
NS_ERR("do_state_action: wrong sector address (%#x)\n", ns->regs.row);
859
ns->regs.row = (ns->regs.row <<
860
8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column;
863
NS_DBG("do_state_action: erase sector at address %#x, off = %d\n",
864
ns->regs.row, NS_RAW_OFFSET(ns));
865
NS_LOG("erase sector %d\n", ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift));
867
memset(ns->mem.byte + NS_RAW_OFFSET(ns), 0xFF, ns->geom.secszoob);
869
NS_MDELAY(erase_delay);
875
* Programm page - move internal buffer data to the page.
879
NS_WARN("do_state_action: device is write-protected, programm\n");
883
num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
884
if (num != ns->regs.count) {
885
NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n",
886
ns->regs.count, num);
890
for (i = 0; i < num; i++)
891
ns->mem.byte[NS_RAW_OFFSET(ns) + ns->regs.off + i] &= ns->buf.byte[i];
893
NS_DBG("do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\n",
894
num, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off);
895
NS_LOG("programm page %d\n", ns->regs.row);
897
NS_UDELAY(programm_delay);
898
NS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv);
903
NS_DBG("do_state_action: set internal offset to 0\n");
908
if (!(ns->options & OPT_PAGE512_8BIT)) {
909
NS_ERR("do_state_action: BUG! can't skip half of page for non-512"
910
"byte page size 8x chips\n");
913
NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz/2);
914
ns->regs.off = ns->geom.pgsz/2;
918
NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz);
919
ns->regs.off = ns->geom.pgsz;
923
NS_DBG("do_state_action: BUG! unknown action\n");
930
* Switch simulator's state.
933
switch_state(struct nandsim *ns)
937
* The current operation have already been identified.
938
* Just follow the states chain.
942
ns->state = ns->nxstate;
943
ns->nxstate = ns->op[ns->stateidx + 1];
945
NS_DBG("switch_state: operation is known, switch to the next state, "
946
"state: %s, nxstate: %s\n",
947
get_state_name(ns->state), get_state_name(ns->nxstate));
949
/* See, whether we need to do some action */
950
if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
951
switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
957
* We don't yet know which operation we perform.
958
* Try to identify it.
962
* The only event causing the switch_state function to
963
* be called with yet unknown operation is new command.
965
ns->state = get_state_by_command(ns->regs.command);
967
NS_DBG("switch_state: operation is unknown, try to find it\n");
969
if (find_operation(ns, 0) != 0)
972
if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
973
switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
978
/* For 16x devices column means the page offset in words */
979
if ((ns->nxstate & STATE_ADDR_MASK) && ns->busw == 16) {
980
NS_DBG("switch_state: double the column number for 16x device\n");
981
ns->regs.column <<= 1;
984
if (NS_STATE(ns->nxstate) == STATE_READY) {
986
* The current state is the last. Return to STATE_READY
989
u_char status = NS_STATUS_OK(ns);
991
/* In case of data states, see if all bytes were input/output */
992
if ((ns->state & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK))
993
&& ns->regs.count != ns->regs.num) {
994
NS_WARN("switch_state: not all bytes were processed, %d left\n",
995
ns->regs.num - ns->regs.count);
996
status = NS_STATUS_FAILED(ns);
999
NS_DBG("switch_state: operation complete, switch to STATE_READY state\n");
1001
switch_to_ready_state(ns, status);
1004
} else if (ns->nxstate & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) {
1006
* If the next state is data input/output, switch to it now
1009
ns->state = ns->nxstate;
1010
ns->nxstate = ns->op[++ns->stateidx + 1];
1011
ns->regs.num = ns->regs.count = 0;
1013
NS_DBG("switch_state: the next state is data I/O, switch, "
1014
"state: %s, nxstate: %s\n",
1015
get_state_name(ns->state), get_state_name(ns->nxstate));
1018
* Set the internal register to the count of bytes which
1019
* are expected to be input or output
1021
switch (NS_STATE(ns->state)) {
1024
ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1027
case STATE_DATAOUT_ID:
1028
ns->regs.num = ns->geom.idbytes;
1031
case STATE_DATAOUT_STATUS:
1032
case STATE_DATAOUT_STATUS_M:
1033
ns->regs.count = ns->regs.num = 0;
1037
NS_ERR("switch_state: BUG! unknown data state\n");
1040
} else if (ns->nxstate & STATE_ADDR_MASK) {
1042
* If the next state is address input, set the internal
1043
* register to the number of expected address bytes
1048
switch (NS_STATE(ns->nxstate)) {
1049
case STATE_ADDR_PAGE:
1050
ns->regs.num = ns->geom.pgaddrbytes;
1053
case STATE_ADDR_SEC:
1054
ns->regs.num = ns->geom.secaddrbytes;
1057
case STATE_ADDR_ZERO:
1062
NS_ERR("switch_state: BUG! unknown address state\n");
1066
* Just reset internal counters.
1075
ns_hwcontrol(struct mtd_info *mtd, int cmd)
1077
struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv;
1081
/* set CLE line high */
1082
case NAND_CTL_SETCLE:
1083
NS_DBG("ns_hwcontrol: start command latch cycles\n");
1087
/* set CLE line low */
1088
case NAND_CTL_CLRCLE:
1089
NS_DBG("ns_hwcontrol: stop command latch cycles\n");
1093
/* set ALE line high */
1094
case NAND_CTL_SETALE:
1095
NS_DBG("ns_hwcontrol: start address latch cycles\n");
1099
/* set ALE line low */
1100
case NAND_CTL_CLRALE:
1101
NS_DBG("ns_hwcontrol: stop address latch cycles\n");
1105
/* set WP line high */
1106
case NAND_CTL_SETWP:
1107
NS_DBG("ns_hwcontrol: enable write protection\n");
1111
/* set WP line low */
1112
case NAND_CTL_CLRWP:
1113
NS_DBG("ns_hwcontrol: disable write protection\n");
1117
/* set CE line low */
1118
case NAND_CTL_SETNCE:
1119
NS_DBG("ns_hwcontrol: enable chip\n");
1123
/* set CE line high */
1124
case NAND_CTL_CLRNCE:
1125
NS_DBG("ns_hwcontrol: disable chip\n");
1130
NS_ERR("hwcontrol: unknown command\n");
1137
ns_nand_read_byte(struct mtd_info *mtd)
1139
struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv;
1142
/* Sanity and correctness checks */
1143
if (!ns->lines.ce) {
1144
NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb);
1147
if (ns->lines.ale || ns->lines.cle) {
1148
NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb);
1151
if (!(ns->state & STATE_DATAOUT_MASK)) {
1152
NS_WARN("read_byte: unexpected data output cycle, state is %s "
1153
"return %#x\n", get_state_name(ns->state), (uint)outb);
1157
/* Status register may be read as many times as it is wanted */
1158
if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS) {
1159
NS_DBG("read_byte: return %#x status\n", ns->regs.status);
1160
return ns->regs.status;
1163
/* Check if there is any data in the internal buffer which may be read */
1164
if (ns->regs.count == ns->regs.num) {
1165
NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb);
1169
switch (NS_STATE(ns->state)) {
1171
if (ns->busw == 8) {
1172
outb = ns->buf.byte[ns->regs.count];
1173
ns->regs.count += 1;
1175
outb = (u_char)cpu_to_le16(ns->buf.word[ns->regs.count >> 1]);
1176
ns->regs.count += 2;
1179
case STATE_DATAOUT_ID:
1180
NS_DBG("read_byte: read ID byte %d, total = %d\n", ns->regs.count, ns->regs.num);
1181
outb = ns->ids[ns->regs.count];
1182
ns->regs.count += 1;
1188
if (ns->regs.count == ns->regs.num) {
1189
NS_DBG("read_byte: all bytes were read\n");
1192
* The OPT_AUTOINCR allows to read next conseqitive pages without
1193
* new read operation cycle.
1195
if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) {
1197
if (ns->regs.row + 1 < ns->geom.pgnum)
1199
NS_DBG("read_byte: switch to the next page (%#x)\n", ns->regs.row);
1200
do_state_action(ns, ACTION_CPY);
1202
else if (NS_STATE(ns->nxstate) == STATE_READY)
1211
ns_nand_write_byte(struct mtd_info *mtd, u_char byte)
1213
struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv;
1215
/* Sanity and correctness checks */
1216
if (!ns->lines.ce) {
1217
NS_ERR("write_byte: chip is disabled, ignore write\n");
1220
if (ns->lines.ale && ns->lines.cle) {
1221
NS_ERR("write_byte: ALE and CLE pins are high simultaneously, ignore write\n");
1225
if (ns->lines.cle == 1) {
1227
* The byte written is a command.
1230
if (byte == NAND_CMD_RESET) {
1231
NS_LOG("reset chip\n");
1232
switch_to_ready_state(ns, NS_STATUS_OK(ns));
1237
* Chip might still be in STATE_DATAOUT
1238
* (if OPT_AUTOINCR feature is supported), STATE_DATAOUT_STATUS or
1239
* STATE_DATAOUT_STATUS_M state. If so, switch state.
1241
if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS
1242
|| NS_STATE(ns->state) == STATE_DATAOUT_STATUS_M
1243
|| ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT))
1246
/* Check if chip is expecting command */
1247
if (NS_STATE(ns->nxstate) != STATE_UNKNOWN && !(ns->nxstate & STATE_CMD_MASK)) {
1249
* We are in situation when something else (not command)
1250
* was expected but command was input. In this case ignore
1251
* previous command(s)/state(s) and accept the last one.
1253
NS_WARN("write_byte: command (%#x) wasn't expected, expected state is %s, "
1254
"ignore previous states\n", (uint)byte, get_state_name(ns->nxstate));
1255
switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1258
/* Check that the command byte is correct */
1259
if (check_command(byte)) {
1260
NS_ERR("write_byte: unknown command %#x\n", (uint)byte);
1264
NS_DBG("command byte corresponding to %s state accepted\n",
1265
get_state_name(get_state_by_command(byte)));
1266
ns->regs.command = byte;
1269
} else if (ns->lines.ale == 1) {
1271
* The byte written is an address.
1274
if (NS_STATE(ns->nxstate) == STATE_UNKNOWN) {
1276
NS_DBG("write_byte: operation isn't known yet, identify it\n");
1278
if (find_operation(ns, 1) < 0)
1281
if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1282
switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1287
switch (NS_STATE(ns->nxstate)) {
1288
case STATE_ADDR_PAGE:
1289
ns->regs.num = ns->geom.pgaddrbytes;
1291
case STATE_ADDR_SEC:
1292
ns->regs.num = ns->geom.secaddrbytes;
1294
case STATE_ADDR_ZERO:
1302
/* Check that chip is expecting address */
1303
if (!(ns->nxstate & STATE_ADDR_MASK)) {
1304
NS_ERR("write_byte: address (%#x) isn't expected, expected state is %s, "
1305
"switch to STATE_READY\n", (uint)byte, get_state_name(ns->nxstate));
1306
switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1310
/* Check if this is expected byte */
1311
if (ns->regs.count == ns->regs.num) {
1312
NS_ERR("write_byte: no more address bytes expected\n");
1313
switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1317
accept_addr_byte(ns, byte);
1319
ns->regs.count += 1;
1321
NS_DBG("write_byte: address byte %#x was accepted (%d bytes input, %d expected)\n",
1322
(uint)byte, ns->regs.count, ns->regs.num);
1324
if (ns->regs.count == ns->regs.num) {
1325
NS_DBG("address (%#x, %#x) is accepted\n", ns->regs.row, ns->regs.column);
1331
* The byte written is an input data.
1334
/* Check that chip is expecting data input */
1335
if (!(ns->state & STATE_DATAIN_MASK)) {
1336
NS_ERR("write_byte: data input (%#x) isn't expected, state is %s, "
1337
"switch to %s\n", (uint)byte,
1338
get_state_name(ns->state), get_state_name(STATE_READY));
1339
switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1343
/* Check if this is expected byte */
1344
if (ns->regs.count == ns->regs.num) {
1345
NS_WARN("write_byte: %u input bytes has already been accepted, ignore write\n",
1350
if (ns->busw == 8) {
1351
ns->buf.byte[ns->regs.count] = byte;
1352
ns->regs.count += 1;
1354
ns->buf.word[ns->regs.count >> 1] = cpu_to_le16((uint16_t)byte);
1355
ns->regs.count += 2;
1363
ns_device_ready(struct mtd_info *mtd)
1365
NS_DBG("device_ready\n");
1370
ns_nand_read_word(struct mtd_info *mtd)
1372
struct nand_chip *chip = (struct nand_chip *)mtd->priv;
1374
NS_DBG("read_word\n");
1376
return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8);
1380
ns_nand_write_word(struct mtd_info *mtd, uint16_t word)
1382
struct nand_chip *chip = (struct nand_chip *)mtd->priv;
1384
NS_DBG("write_word\n");
1386
chip->write_byte(mtd, word & 0xFF);
1387
chip->write_byte(mtd, word >> 8);
1391
ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
1393
struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv;
1395
/* Check that chip is expecting data input */
1396
if (!(ns->state & STATE_DATAIN_MASK)) {
1397
NS_ERR("write_buf: data input isn't expected, state is %s, "
1398
"switch to STATE_READY\n", get_state_name(ns->state));
1399
switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1403
/* Check if these are expected bytes */
1404
if (ns->regs.count + len > ns->regs.num) {
1405
NS_ERR("write_buf: too many input bytes\n");
1406
switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1410
memcpy(ns->buf.byte + ns->regs.count, buf, len);
1411
ns->regs.count += len;
1413
if (ns->regs.count == ns->regs.num) {
1414
NS_DBG("write_buf: %d bytes were written\n", ns->regs.count);
1419
ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
1421
struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv;
1423
/* Sanity and correctness checks */
1424
if (!ns->lines.ce) {
1425
NS_ERR("read_buf: chip is disabled\n");
1428
if (ns->lines.ale || ns->lines.cle) {
1429
NS_ERR("read_buf: ALE or CLE pin is high\n");
1432
if (!(ns->state & STATE_DATAOUT_MASK)) {
1433
NS_WARN("read_buf: unexpected data output cycle, current state is %s\n",
1434
get_state_name(ns->state));
1438
if (NS_STATE(ns->state) != STATE_DATAOUT) {
1441
for (i = 0; i < len; i++)
1442
buf[i] = ((struct nand_chip *)mtd->priv)->read_byte(mtd);
1447
/* Check if these are expected bytes */
1448
if (ns->regs.count + len > ns->regs.num) {
1449
NS_ERR("read_buf: too many bytes to read\n");
1450
switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1454
memcpy(buf, ns->buf.byte + ns->regs.count, len);
1455
ns->regs.count += len;
1457
if (ns->regs.count == ns->regs.num) {
1458
if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) {
1460
if (ns->regs.row + 1 < ns->geom.pgnum)
1462
NS_DBG("read_buf: switch to the next page (%#x)\n", ns->regs.row);
1463
do_state_action(ns, ACTION_CPY);
1465
else if (NS_STATE(ns->nxstate) == STATE_READY)
1473
ns_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
1475
ns_nand_read_buf(mtd, (u_char *)&ns_verify_buf[0], len);
1477
if (!memcmp(buf, &ns_verify_buf[0], len)) {
1478
NS_DBG("verify_buf: the buffer is OK\n");
1481
NS_DBG("verify_buf: the buffer is wrong\n");
1487
* Having only NAND chip IDs we call nand_scan which detects NAND flash
1488
* parameters and then calls scan_bbt in order to scan/find/build the
1489
* NAND flash bad block table. But since at that moment the NAND flash
1490
* image isn't allocated in the simulator, errors arise. To avoid this
1491
* we redefine the scan_bbt callback and initialize the nandsim structure
1492
* before the flash media scanning.
1494
int ns_scan_bbt(struct mtd_info *mtd)
1496
struct nand_chip *chip = (struct nand_chip *)mtd->priv;
1497
struct nandsim *ns = (struct nandsim *)(chip->priv);
1500
if (!NS_IS_INITIALIZED(ns))
1501
if ((retval = init_nandsim(mtd)) != 0) {
1502
NS_ERR("scan_bbt: can't initialize the nandsim structure\n");
1505
if ((retval = nand_default_bbt(mtd)) != 0) {
1514
* Module initialization function
1516
int __init ns_init_module(void)
1518
struct nand_chip *chip;
1519
struct nandsim *nand;
1520
int retval = -ENOMEM;
1522
if (bus_width != 8 && bus_width != 16) {
1523
NS_ERR("wrong bus width (%d), use only 8 or 16\n", bus_width);
1527
/* Allocate and initialize mtd_info, nand_chip and nandsim structures */
1528
nsmtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip)
1529
+ sizeof(struct nandsim), GFP_KERNEL);
1531
NS_ERR("unable to allocate core structures.\n");
1534
memset(nsmtd, 0, sizeof(struct mtd_info) + sizeof(struct nand_chip) +
1535
sizeof(struct nandsim));
1536
chip = (struct nand_chip *)(nsmtd + 1);
1537
nsmtd->priv = (void *)chip;
1538
nand = (struct nandsim *)(chip + 1);
1539
chip->priv = (void *)nand;
1542
* Register simulator's callbacks.
1544
chip->hwcontrol = ns_hwcontrol;
1545
chip->read_byte = ns_nand_read_byte;
1546
chip->dev_ready = ns_device_ready;
1547
chip->scan_bbt = ns_scan_bbt;
1548
chip->write_byte = ns_nand_write_byte;
1549
chip->write_buf = ns_nand_write_buf;
1550
chip->read_buf = ns_nand_read_buf;
1551
chip->verify_buf = ns_nand_verify_buf;
1552
chip->write_word = ns_nand_write_word;
1553
chip->read_word = ns_nand_read_word;
1554
chip->eccmode = NAND_ECC_SOFT;
1557
* Perform minimum nandsim structure initialization to handle
1558
* the initial ID read command correctly
1560
if (third_id_byte != 0xFF || fourth_id_byte != 0xFF)
1561
nand->geom.idbytes = 4;
1563
nand->geom.idbytes = 2;
1564
nand->regs.status = NS_STATUS_OK(nand);
1565
nand->nxstate = STATE_UNKNOWN;
1566
nand->options |= OPT_PAGE256; /* temporary value */
1567
nand->ids[0] = first_id_byte;
1568
nand->ids[1] = second_id_byte;
1569
nand->ids[2] = third_id_byte;
1570
nand->ids[3] = fourth_id_byte;
1571
if (bus_width == 16) {
1573
chip->options |= NAND_BUSWIDTH_16;
1576
if ((retval = nand_scan(nsmtd, 1)) != 0) {
1577
NS_ERR("can't register NAND Simulator\n");
1583
/* Register NAND as one big partition */
1584
add_mtd_partitions(nsmtd, &nand->part, 1);
1594
module_init(ns_init_module);
1597
* Module clean-up function
1599
static void __exit ns_cleanup_module(void)
1601
struct nandsim *ns = (struct nandsim *)(((struct nand_chip *)nsmtd->priv)->priv);
1603
free_nandsim(ns); /* Free nandsim private resources */
1604
nand_release(nsmtd); /* Unregisterd drived */
1605
kfree(nsmtd); /* Free other structures */
1608
module_exit(ns_cleanup_module);
1610
MODULE_LICENSE ("GPL");
1611
MODULE_AUTHOR ("Artem B. Bityuckiy");
1612
MODULE_DESCRIPTION ("The NAND flash simulator");
added
removed
drivers/mtd/nand/nandsim.c
