444
/* System bus clock speed (40MHz) for timer 0. Not sure about this value. */
445
#define ICP_BUS_FREQ 40000000
461
/* Calculate the new expiry time of the given timer. */
463
static void icp_pit_reload(icp_pit_state *s, int n)
467
s->loaded[n] = s->expires[n];
468
delay = muldiv64(s->count[n], ticks_per_sec, s->freq[n]);
471
s->expires[n] += delay;
474
/* Check all active timers, and schedule the next timer interrupt. */
476
static void icp_pit_update(icp_pit_state *s, int64_t now)
482
for (n = 0; n < 3; n++) {
483
/* Ignore disabled timers. */
484
if ((s->control[n] & 0x80) == 0)
486
/* Ignore expired one-shot timers. */
487
if (s->count[n] == 0 && s->control[n] & 1)
489
if (s->expires[n] - now <= 0) {
490
/* Timer has expired. */
492
if (s->control[n] & 1) {
496
if ((s->control[n] & 0x40) == 0) {
498
if (s->control[n] & 2)
499
s->count[n] = 0xffffffff;
501
s->count[n] = 0xffff;
504
s->count[n] = s->limit[n];
508
while (s->expires[n] - now <= 0) {
509
icp_pit_reload(s, n);
512
/* Update interrupts. */
513
for (n = 0; n < 3; n++) {
514
if (s->int_level[n] && (s->control[n] & 0x20)) {
515
pic_set_irq_new(s->pic, 5 + n, 1);
517
pic_set_irq_new(s->pic, 5 + n, 0);
519
if (next - s->expires[n] < 0)
520
next = s->expires[n];
522
/* Schedule the next timer interrupt. */
524
qemu_del_timer(s->timer);
526
} else if (next != s->next_time) {
527
qemu_mod_timer(s->timer, next);
532
/* Return the current value of the timer. */
533
static uint32_t icp_pit_getcount(icp_pit_state *s, int n, int64_t now)
538
if (s->count[n] == 0)
540
if ((s->control[n] & 0x80) == 0)
542
elapsed = now - s->loaded[n];
543
period = s->expires[n] - s->loaded[n];
544
/* If the timer should have expired then return 0. This can happen
545
when the host timer signal doesnt occur immediately. It's better to
546
have a timer appear to sit at zero for a while than have it wrap
547
around before the guest interrupt is raised. */
548
/* ??? Could we trigger the interrupt here? */
549
if (elapsed > period)
551
/* We need to calculate count * elapsed / period without overfowing.
552
Scale both elapsed and period so they fit in a 32-bit int. */
553
while (period != (int32_t)period) {
557
return ((uint64_t)s->count[n] * (uint64_t)(int32_t)elapsed)
561
static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
564
icp_pit_state *s = (icp_pit_state *)opaque;
569
cpu_abort (cpu_single_env, "icp_pit_read: Bad timer %x\n", offset);
570
switch ((offset & 0xff) >> 2) {
571
case 0: /* TimerLoad */
572
case 6: /* TimerBGLoad */
574
case 1: /* TimerValue */
575
return icp_pit_getcount(s, n, qemu_get_clock(vm_clock));
576
case 2: /* TimerControl */
577
return s->control[n];
578
case 4: /* TimerRIS */
579
return s->int_level[n];
580
case 5: /* TimerMIS */
581
if ((s->control[n] & 0x20) == 0)
583
return s->int_level[n];
585
cpu_abort (cpu_single_env, "icp_pit_read: Bad offset %x\n", offset);
590
static void icp_pit_write(void *opaque, target_phys_addr_t offset,
593
icp_pit_state *s = (icp_pit_state *)opaque;
597
now = qemu_get_clock(vm_clock);
601
cpu_abort (cpu_single_env, "icp_pit_write: Bad offset %x\n", offset);
603
switch ((offset & 0xff) >> 2) {
604
case 0: /* TimerLoad */
608
icp_pit_reload(s, n);
610
case 1: /* TimerValue */
611
/* ??? Linux seems to want to write to this readonly register.
614
case 2: /* TimerControl */
615
if (s->control[n] & 0x80) {
616
/* Pause the timer if it is running. This may cause some
617
inaccuracy dure to rounding, but avoids a whole lot of other
619
s->count[n] = icp_pit_getcount(s, n, now);
621
s->control[n] = value;
623
s->freq[n] = ICP_BUS_FREQ;
625
s->freq[n] = 1000000;
626
/* ??? Need to recalculate expiry time after changing divisor. */
627
switch ((value >> 2) & 3) {
628
case 1: s->freq[n] >>= 4; break;
629
case 2: s->freq[n] >>= 8; break;
631
if (s->control[n] & 0x80) {
632
/* Restart the timer if still enabled. */
634
icp_pit_reload(s, n);
637
case 3: /* TimerIntClr */
640
case 6: /* TimerBGLoad */
644
cpu_abort (cpu_single_env, "icp_pit_write: Bad offset %x\n", offset);
646
icp_pit_update(s, now);
649
static void icp_pit_tick(void *opaque)
653
now = qemu_get_clock(vm_clock);
654
icp_pit_update((icp_pit_state *)opaque, now);
657
static CPUReadMemoryFunc *icp_pit_readfn[] = {
663
static CPUWriteMemoryFunc *icp_pit_writefn[] = {
669
static void icp_pit_init(uint32_t base, icp_pic_state *pic)
675
s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
678
s->freq[0] = ICP_BUS_FREQ;
679
s->freq[1] = 1000000;
680
s->freq[2] = 1000000;
681
for (n = 0; n < 3; n++) {
682
s->control[n] = 0x20;
683
s->count[n] = 0xffffffff;
686
iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
688
cpu_register_physical_memory(base, 0x007fffff, iomemtype);
689
s->timer = qemu_new_timer(vm_clock, icp_pit_tick, s);
690
/* ??? Save/restore. */
693
/* ARM PrimeCell PL011 UART */
702
uint32_t int_enabled;
704
uint32_t read_fifo[16];
712
CharDriverState *chr;
717
#define PL011_INT_TX 0x20
718
#define PL011_INT_RX 0x10
720
#define PL011_FLAG_TXFE 0x80
721
#define PL011_FLAG_RXFF 0x40
722
#define PL011_FLAG_TXFF 0x20
723
#define PL011_FLAG_RXFE 0x10
725
static const unsigned char pl011_id[] =
726
{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
728
static void pl011_update(pl011_state *s)
732
flags = s->int_level & s->int_enabled;
733
pic_set_irq_new(s->pic, s->irq, flags != 0);
736
static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
738
pl011_state *s = (pl011_state *)opaque;
742
if (offset >= 0xfe0 && offset < 0x1000) {
743
return pl011_id[(offset - 0xfe0) >> 2];
745
switch (offset >> 2) {
747
s->flags &= ~PL011_FLAG_RXFF;
748
c = s->read_fifo[s->read_pos];
749
if (s->read_count > 0) {
751
if (++s->read_pos == 16)
754
if (s->read_count == 0) {
755
s->flags |= PL011_FLAG_RXFE;
757
if (s->read_count == s->read_trigger - 1)
758
s->int_level &= ~ PL011_INT_RX;
765
case 8: /* UARTILPR */
767
case 9: /* UARTIBRD */
769
case 10: /* UARTFBRD */
771
case 11: /* UARTLCR_H */
773
case 12: /* UARTCR */
775
case 13: /* UARTIFLS */
777
case 14: /* UARTIMSC */
778
return s->int_enabled;
779
case 15: /* UARTRIS */
781
case 16: /* UARTMIS */
782
return s->int_level & s->int_enabled;
783
case 18: /* UARTDMACR */
786
cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", offset);
791
static void pl011_set_read_trigger(pl011_state *s)
794
/* The docs say the RX interrupt is triggered when the FIFO exceeds
795
the threshold. However linux only reads the FIFO in response to an
796
interrupt. Triggering the interrupt when the FIFO is non-empty seems
797
to make things work. */
799
s->read_trigger = (s->ifl >> 1) & 0x1c;
805
static void pl011_write(void *opaque, target_phys_addr_t offset,
808
pl011_state *s = (pl011_state *)opaque;
812
switch (offset >> 2) {
814
/* ??? Check if transmitter is enabled. */
817
qemu_chr_write(s->chr, &ch, 1);
818
s->int_level |= PL011_INT_TX;
824
case 8: /* UARTUARTILPR */
827
case 9: /* UARTIBRD */
830
case 10: /* UARTFBRD */
833
case 11: /* UARTLCR_H */
835
pl011_set_read_trigger(s);
837
case 12: /* UARTCR */
838
/* ??? Need to implement the enable and loopback bits. */
841
case 13: /* UARTIFS */
843
pl011_set_read_trigger(s);
845
case 14: /* UARTIMSC */
846
s->int_enabled = value;
849
case 17: /* UARTICR */
850
s->int_level &= ~value;
853
case 18: /* UARTDMACR */
856
cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
859
cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", offset);
863
static int pl011_can_recieve(void *opaque)
865
pl011_state *s = (pl011_state *)opaque;
868
return s->read_count < 16;
870
return s->read_count < 1;
873
static void pl011_recieve(void *opaque, const uint8_t *buf, int size)
875
pl011_state *s = (pl011_state *)opaque;
878
slot = s->read_pos + s->read_count;
881
s->read_fifo[slot] = *buf;
883
s->flags &= ~PL011_FLAG_RXFE;
884
if (s->cr & 0x10 || s->read_count == 16) {
885
s->flags |= PL011_FLAG_RXFF;
887
if (s->read_count == s->read_trigger) {
888
s->int_level |= PL011_INT_RX;
893
static void pl011_event(void *opaque, int event)
895
/* ??? Should probably implement break. */
898
static CPUReadMemoryFunc *pl011_readfn[] = {
904
static CPUWriteMemoryFunc *pl011_writefn[] = {
910
static void pl011_init(uint32_t base, icp_pic_state *pic, int irq,
911
CharDriverState *chr)
916
s = (pl011_state *)qemu_mallocz(sizeof(pl011_state));
917
iomemtype = cpu_register_io_memory(0, pl011_readfn,
919
cpu_register_physical_memory(base, 0x007fffff, iomemtype);
929
qemu_chr_add_read_handler(chr, pl011_can_recieve, pl011_recieve, s);
930
qemu_chr_add_event_handler(chr, pl011_event);
932
/* ??? Save/restore. */
935
404
/* CP control registers. */
1000
/* Keyboard/Mouse Interface. */
1014
static void icp_kmi_update(void *opaque, int level)
1016
icp_kmi_state *s = (icp_kmi_state *)opaque;
1020
raise = (s->pending && (s->cr & 0x10) != 0)
1021
|| (s->cr & 0x08) != 0;
1022
pic_set_irq_new(s->pic, s->irq, raise);
1025
static uint32_t icp_kmi_read(void *opaque, target_phys_addr_t offset)
1027
icp_kmi_state *s = (icp_kmi_state *)opaque;
1029
if (offset >= 0xfe0 && offset < 0x1000)
1032
switch (offset >> 2) {
1035
case 1: /* KMISTAT */
1036
/* KMIC and KMID bits not implemented. */
1042
case 2: /* KMIDATA */
1044
s->last = ps2_read_data(s->dev);
1046
case 3: /* KMICLKDIV */
1049
return s->pending | 2;
1051
cpu_abort (cpu_single_env, "icp_kmi_read: Bad offset %x\n", offset);
1056
static void icp_kmi_write(void *opaque, target_phys_addr_t offset,
1059
icp_kmi_state *s = (icp_kmi_state *)opaque;
1061
switch (offset >> 2) {
1064
icp_kmi_update(s, s->pending);
1065
/* ??? Need to implement the enable/disable bit. */
1067
case 2: /* KMIDATA */
1068
/* ??? This should toggle the TX interrupt line. */
1069
/* ??? This means kbd/mouse can block each other. */
1071
ps2_write_mouse(s->dev, value);
1073
ps2_write_keyboard(s->dev, value);
1076
case 3: /* KMICLKDIV */
1080
cpu_abort (cpu_single_env, "icp_kmi_write: Bad offset %x\n", offset);
1083
static CPUReadMemoryFunc *icp_kmi_readfn[] = {
1089
static CPUWriteMemoryFunc *icp_kmi_writefn[] = {
1095
static void icp_kmi_init(uint32_t base, icp_pic_state * pic, int irq,
1101
s = (icp_kmi_state *)qemu_mallocz(sizeof(icp_kmi_state));
1102
iomemtype = cpu_register_io_memory(0, icp_kmi_readfn,
1103
icp_kmi_writefn, s);
1104
cpu_register_physical_memory(base, 0x007fffff, iomemtype);
1108
s->is_mouse = is_mouse;
1110
s->dev = ps2_mouse_init(icp_kmi_update, s);
1112
s->dev = ps2_kbd_init(icp_kmi_update, s);
1113
/* ??? Save/restore. */
1116
/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
1117
static uint32_t bootloader[] = {
1118
0xe3a00000, /* mov r0, #0 */
1119
0xe3a01013, /* mov r1, #0x13 */
1120
0xe3811c01, /* orr r1, r1, #0x100 */
1121
0xe59f2000, /* ldr r2, [pc, #0] */
1122
0xe59ff000, /* ldr pc, [pc, #0] */
1123
0, /* Address of kernel args. Set by integratorcp_init. */
1124
0 /* Kernel entry point. Set by integratorcp_init. */
1127
static void set_kernel_args(uint32_t ram_size, int initrd_size,
1128
const char *kernel_cmdline)
1132
p = (uint32_t *)(phys_ram_base + KERNEL_ARGS_ADDR);
1135
*(p++) = 0x54410001;
1141
*(p++) = 0x54410002;
1147
*(p++) = 0x54420005;
1148
*(p++) = INITRD_LOAD_ADDR;
1149
*(p++) = initrd_size;
1151
if (kernel_cmdline && *kernel_cmdline) {
1155
cmdline_size = strlen(kernel_cmdline);
1156
memcpy (p + 2, kernel_cmdline, cmdline_size + 1);
1157
cmdline_size = (cmdline_size >> 2) + 1;
1158
*(p++) = cmdline_size + 2;
1159
*(p++) = 0x54410009;
1167
469
/* Board init. */
1169
471
static void integratorcp_init(int ram_size, int vga_ram_size, int boot_device,
1170
472
DisplayState *ds, const char **fd_filename, int snapshot,
1171
473
const char *kernel_filename, const char *kernel_cmdline,
1172
const char *initrd_filename)
474
const char *initrd_filename, uint32_t cpuid)
1175
477
uint32_t bios_offset;
1176
478
icp_pic_state *pic;
1180
481
env = cpu_init();
482
cpu_arm_set_model(env, cpuid);
1181
483
bios_offset = ram_size + vga_ram_size;
1182
484
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
1183
485
/* ??? RAM shoud repeat to fill physical memory space. */
1187
489
cpu_register_physical_memory(0x80000000, ram_size, IO_MEM_RAM);
1189
491
integratorcm_init(ram_size >> 20, bios_offset);
1190
pic = icp_pic_init(0x14000000, env, -1);
1191
icp_pic_init(0xca000000, pic, 26);
1192
icp_pit_init(0x13000000, pic);
492
cpu_pic = arm_pic_init_cpu(env);
493
pic = icp_pic_init(0x14000000, cpu_pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
494
icp_pic_init(0xca000000, pic, 26, -1);
495
icp_pit_init(0x13000000, pic, 5);
1193
496
pl011_init(0x16000000, pic, 1, serial_hds[0]);
1194
497
pl011_init(0x17000000, pic, 2, serial_hds[1]);
1195
498
icp_control_init(0xcb000000);
1196
icp_kmi_init(0x18000000, pic, 3, 0);
1197
icp_kmi_init(0x19000000, pic, 4, 1);
1198
if (nd_table[0].vlan)
1199
smc91c111_init(&nd_table[0], 0xc8000000, pic, 27);
1201
/* Load the kernel. */
1202
if (!kernel_filename) {
1203
fprintf(stderr, "Kernel image must be specified\n");
1206
kernel_size = load_image(kernel_filename,
1207
phys_ram_base + KERNEL_LOAD_ADDR);
1208
if (kernel_size < 0) {
1209
fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
1212
if (initrd_filename) {
1213
initrd_size = load_image(initrd_filename,
1214
phys_ram_base + INITRD_LOAD_ADDR);
1215
if (initrd_size < 0) {
1216
fprintf(stderr, "qemu: could not load initrd '%s'\n",
499
pl050_init(0x18000000, pic, 3, 0);
500
pl050_init(0x19000000, pic, 4, 1);
501
if (nd_table[0].vlan) {
502
if (nd_table[0].model == NULL
503
|| strcmp(nd_table[0].model, "smc91c111") == 0) {
504
smc91c111_init(&nd_table[0], 0xc8000000, pic, 27);
506
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1223
bootloader[5] = KERNEL_ARGS_ADDR;
1224
bootloader[6] = KERNEL_LOAD_ADDR;
1225
memcpy(phys_ram_base, bootloader, sizeof(bootloader));
1226
set_kernel_args(ram_size, initrd_size, kernel_cmdline);
1229
QEMUMachine integratorcp_machine = {
1231
"ARM Integrator/CP",
510
pl110_init(ds, 0xc0000000, pic, 22, 0);
512
arm_load_kernel(ram_size, kernel_filename, kernel_cmdline,
513
initrd_filename, 0x113);
516
static void integratorcp926_init(int ram_size, int vga_ram_size,
517
int boot_device, DisplayState *ds, const char **fd_filename, int snapshot,
518
const char *kernel_filename, const char *kernel_cmdline,
519
const char *initrd_filename)
521
integratorcp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
522
snapshot, kernel_filename, kernel_cmdline,
523
initrd_filename, ARM_CPUID_ARM926);
526
static void integratorcp1026_init(int ram_size, int vga_ram_size,
527
int boot_device, DisplayState *ds, const char **fd_filename, int snapshot,
528
const char *kernel_filename, const char *kernel_cmdline,
529
const char *initrd_filename)
531
integratorcp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
532
snapshot, kernel_filename, kernel_cmdline,
533
initrd_filename, ARM_CPUID_ARM1026);
536
QEMUMachine integratorcp926_machine = {
538
"ARM Integrator/CP (ARM926EJ-S)",
539
integratorcp926_init,
542
QEMUMachine integratorcp1026_machine = {
544
"ARM Integrator/CP (ARM1026EJ-S)",
545
integratorcp1026_init,
added
removed
hw/integratorcp.c
