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- Committer: Bazaar Package Importer
- Author(s): Eduard Bloch
- Date: 2004-09-06 18:17:31 UTC
- Revision ID: james.westby@ubuntu.com-20040906181731-si44puez4f5pzd8s
Tags: upstream-2.9.9
Import upstream version 2.9.9
- files added:
- drivers
- modem
- patches
- scripts
- scripts/debian
- scripts/mandrake
- scripts/suse
added
removed
patches/alsa-linux-2.6.0.patch
1
diff -Nru linux-2.6.0_orig/include/sound/ac97_codec.h linux-2.6.0/include/sound/ac97_codec.h
2
--- linux-2.6.0_orig/include/sound/ac97_codec.h 2003-12-28 22:18:44.000000000 +0200
3
+++ linux-2.6.0/include/sound/ac97_codec.h 2003-12-28 22:29:43.000000000 +0200
4
@@ -180,6 +180,24 @@
5
#define AC97_MEA_PRG 0x4000 /* HADC power down (high) */
6
#define AC97_MEA_PRH 0x8000 /* HDAC power down (high) */
7
8
+/* modem gpio status defines */
9
+#define AC97_GPIO_LINE1_OH 0x0001 /* Off Hook Line1 */
10
+#define AC97_GPIO_LINE1_RI 0x0002 /* Ring Detect Line1 */
11
+#define AC97_GPIO_LINE1_CID 0x0004 /* Caller ID path enable Line1 */
12
+#define AC97_GPIO_LINE1_LCS 0x0008 /* Loop Current Sense Line1 */
13
+#define AC97_GPIO_LINE1_PULSE 0x0010 /* Opt./ Pulse Dial Line1 (out) */
14
+#define AC97_GPIO_LINE1_HL1R 0x0020 /* Opt./ Handset to Line1 relay control (out) */
15
+#define AC97_GPIO_LINE1_HOHD 0x0040 /* Opt./ Handset off hook detect Line1 (in) */
16
+#define AC97_GPIO_LINE12_AC 0x0080 /* Opt./ Int.bit 1 / Line1/2 AC (out) */
17
+#define AC97_GPIO_LINE12_DC 0x0100 /* Opt./ Int.bit 2 / Line1/2 DC (out) */
18
+#define AC97_GPIO_LINE12_RS 0x0200 /* Opt./ Int.bit 3 / Line1/2 RS (out) */
19
+#define AC97_GPIO_LINE2_OH 0x0400 /* Off Hook Line2 */
20
+#define AC97_GPIO_LINE2_RI 0x0800 /* Ring Detect Line2 */
21
+#define AC97_GPIO_LINE2_CID 0x1000 /* Caller ID path enable Line2 */
22
+#define AC97_GPIO_LINE2_LCS 0x2000 /* Loop Current Sense Line2 */
23
+#define AC97_GPIO_LINE2_PULSE 0x4000 /* Opt./ Pulse Dial Line2 (out) */
24
+#define AC97_GPIO_LINE2_HL1R 0x8000 /* Opt./ Handset to Line2 relay control (out) */
25
+
26
/* specific - SigmaTel */
27
#define AC97_SIGMATEL_ANALOG 0x6c /* Analog Special */
28
#define AC97_SIGMATEL_DAC2INVERT 0x6e
29
diff -Nru linux-2.6.0_orig/sound/pci/ac97/ac97_codec.c linux-2.6.0/sound/pci/ac97/ac97_codec.c
30
--- linux-2.6.0_orig/sound/pci/ac97/ac97_codec.c 2003-12-28 22:18:44.000000000 +0200
31
+++ linux-2.6.0/sound/pci/ac97/ac97_codec.c 2003-12-28 22:29:43.000000000 +0200
32
@@ -143,7 +143,7 @@
33
{ 0x4e534331, 0xffffffff, "LM4549", NULL, NULL },
34
{ 0x4e534350, 0xffffffff, "LM4550", NULL, NULL },
35
{ 0x50534304, 0xffffffff, "UCB1400", NULL, NULL },
36
-{ 0x53494c20, 0xffffffe0, "Si3036/8", NULL, NULL },
37
+{ 0x53494c20, 0xffffffe0, "Si3036/8", NULL, mpatch_si3036 },
38
{ 0x54524102, 0xffffffff, "TR28022", NULL, NULL },
39
{ 0x54524106, 0xffffffff, "TR28026", NULL, NULL },
40
{ 0x54524108, 0xffffffff, "TR28028", patch_tritech_tr28028, NULL }, // added by xin jin [07/09/99]
41
@@ -1492,6 +1492,12 @@
42
static int snd_ac97_modem_build(snd_card_t * card, ac97_t * ac97)
43
{
44
/* TODO */
45
+ //printk("AC97_GPIO_CFG = %x\n",snd_ac97_read(ac97,AC97_GPIO_CFG));
46
+ snd_ac97_write(ac97, AC97_GPIO_CFG, 0xffff & ~(AC97_GPIO_LINE1_OH));
47
+ snd_ac97_write(ac97, AC97_GPIO_POLARITY, 0xffff & ~(AC97_GPIO_LINE1_OH));
48
+ snd_ac97_write(ac97, AC97_GPIO_STICKY, 0xffff);
49
+ snd_ac97_write(ac97, AC97_GPIO_WAKEUP, 0x0);
50
+ snd_ac97_write(ac97, AC97_MISC_AFE, 0x0);
51
return 0;
52
}
53
54
diff -Nru linux-2.6.0_orig/sound/pci/ac97/ac97_patch.c linux-2.6.0/sound/pci/ac97/ac97_patch.c
55
--- linux-2.6.0_orig/sound/pci/ac97/ac97_patch.c 2003-12-28 22:18:44.000000000 +0200
56
+++ linux-2.6.0/sound/pci/ac97/ac97_patch.c 2003-12-28 22:29:43.000000000 +0200
57
@@ -1099,3 +1099,14 @@
58
ac97->build_ops = &patch_vt1616_ops;
59
return 0;
60
}
61
+
62
+/* Si3036/8 specific registers */
63
+#define AC97_SI3036_CHIP_ID 0x5a
64
+
65
+int mpatch_si3036(ac97_t * ac97)
66
+{
67
+ //printk("mpatch_si3036: chip id = %x\n", snd_ac97_read(ac97, 0x5a));
68
+ snd_ac97_write_cache(ac97, 0x5c, 0xf210 );
69
+ snd_ac97_write_cache(ac97, 0x68, 0);
70
+ return 0;
71
+}
72
diff -Nru linux-2.6.0_orig/sound/pci/ac97/ac97_patch.h linux-2.6.0/sound/pci/ac97/ac97_patch.h
73
--- linux-2.6.0_orig/sound/pci/ac97/ac97_patch.h 2003-12-28 22:18:44.000000000 +0200
74
+++ linux-2.6.0/sound/pci/ac97/ac97_patch.h 2003-12-28 22:29:43.000000000 +0200
75
@@ -47,3 +47,5 @@
76
int patch_cm9738(ac97_t * ac97);
77
int patch_cm9739(ac97_t * ac97);
78
int patch_vt1616(ac97_t * ac97);
79
+int mpatch_si3036(ac97_t * ac97);
80
+
81
diff -Nru linux-2.6.0_orig/sound/pci/intel8x0m.c linux-2.6.0/sound/pci/intel8x0m.c
82
--- linux-2.6.0_orig/sound/pci/intel8x0m.c 1970-01-01 02:00:00.000000000 +0200
83
+++ linux-2.6.0/sound/pci/intel8x0m.c 2003-12-28 22:30:09.000000000 +0200
84
@@ -0,0 +1,1488 @@
85
+/*
86
+ * ALSA modem driver for Intel ICH (i8x0) chipsets
87
+ *
88
+ * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
89
+ *
90
+ * This is modified (by Sasha Khapyorsky <sashak@smlink.com>) version
91
+ * of ALSA ICH sound driver intel8x0.c .
92
+ *
93
+ *
94
+ * This program is free software; you can redistribute it and/or modify
95
+ * it under the terms of the GNU General Public License as published by
96
+ * the Free Software Foundation; either version 2 of the License, or
97
+ * (at your option) any later version.
98
+ *
99
+ * This program is distributed in the hope that it will be useful,
100
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
101
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
102
+ * GNU General Public License for more details.
103
+ *
104
+ * You should have received a copy of the GNU General Public License
105
+ * along with this program; if not, write to the Free Software
106
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
107
+ *
108
+ */
109
+
110
+#include <sound/driver.h>
111
+#include <asm/io.h>
112
+#include <linux/delay.h>
113
+#include <linux/interrupt.h>
114
+#include <linux/init.h>
115
+#include <linux/pci.h>
116
+#include <linux/slab.h>
117
+#include <linux/gameport.h>
118
+#include <sound/core.h>
119
+#include <sound/pcm.h>
120
+#include <sound/ac97_codec.h>
121
+#include <sound/info.h>
122
+#include <sound/mpu401.h>
123
+#define SNDRV_GET_ID
124
+#include <sound/initval.h>
125
+
126
+MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
127
+MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440 modem");
128
+MODULE_LICENSE("GPL");
129
+MODULE_CLASSES("{sound}");
130
+MODULE_DEVICES("{{Intel,82801AA-ICH},"
131
+ "{Intel,82901AB-ICH0},"
132
+ "{Intel,82801BA-ICH2},"
133
+ "{Intel,82801CA-ICH3},"
134
+ "{Intel,82801DB-ICH4},"
135
+ "{Intel,ICH5},"
136
+ "{Intel,MX440}}");
137
+
138
+
139
+static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
140
+static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
141
+static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
142
+static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
143
+
144
+MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
145
+MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
146
+MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
147
+MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
148
+MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
149
+MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
150
+MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
151
+MODULE_PARM_DESC(enable, "Enable Intel i8x0 modemcard.");
152
+MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
153
+MODULE_PARM(ac97_clock, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
154
+MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
155
+MODULE_PARM_SYNTAX(ac97_clock, SNDRV_ENABLED ",default:0");
156
+
157
+/*
158
+ * Direct registers
159
+ */
160
+
161
+#ifndef PCI_DEVICE_ID_INTEL_82801_6
162
+#define PCI_DEVICE_ID_INTEL_82801_6 0x2416
163
+#endif
164
+#ifndef PCI_DEVICE_ID_INTEL_82901_6
165
+#define PCI_DEVICE_ID_INTEL_82901_6 0x2426
166
+#endif
167
+#ifndef PCI_DEVICE_ID_INTEL_82801BA_6
168
+#define PCI_DEVICE_ID_INTEL_82801BA_6 0x2446
169
+#endif
170
+#ifndef PCI_DEVICE_ID_INTEL_440MX_6
171
+#define PCI_DEVICE_ID_INTEL_440MX_6 0x7196
172
+#endif
173
+#ifndef PCI_DEVICE_ID_INTEL_ICH3_6
174
+#define PCI_DEVICE_ID_INTEL_ICH3_6 0x2486
175
+#endif
176
+#ifndef PCI_DEVICE_ID_INTEL_ICH4_6
177
+#define PCI_DEVICE_ID_INTEL_ICH4_6 0x24c6
178
+#endif
179
+#ifndef PCI_DEVICE_ID_INTEL_ICH5_6
180
+#define PCI_DEVICE_ID_INTEL_ICH5_6 0x24d6
181
+#endif
182
+#ifndef PCI_DEVICE_ID_SI_7013
183
+#define PCI_DEVICE_ID_SI_7013 0x7013
184
+#endif
185
+#if 0
186
+#ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
187
+#define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
188
+#endif
189
+#ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
190
+#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
191
+#endif
192
+#ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
193
+#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
194
+#endif
195
+#endif
196
+
197
+enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
198
+
199
+#define ICHREG(x) ICH_REG_##x
200
+
201
+#define DEFINE_REGSET(name,base) \
202
+enum { \
203
+ ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
204
+ ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
205
+ ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
206
+ ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
207
+ ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
208
+ ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
209
+ ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
210
+};
211
+
212
+/* busmaster blocks */
213
+DEFINE_REGSET(OFF, 0); /* offset */
214
+
215
+/* values for each busmaster block */
216
+
217
+/* LVI */
218
+#define ICH_REG_LVI_MASK 0x1f
219
+
220
+/* SR */
221
+#define ICH_FIFOE 0x10 /* FIFO error */
222
+#define ICH_BCIS 0x08 /* buffer completion interrupt status */
223
+#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
224
+#define ICH_CELV 0x02 /* current equals last valid */
225
+#define ICH_DCH 0x01 /* DMA controller halted */
226
+
227
+/* PIV */
228
+#define ICH_REG_PIV_MASK 0x1f /* mask */
229
+
230
+/* CR */
231
+#define ICH_IOCE 0x10 /* interrupt on completion enable */
232
+#define ICH_FEIE 0x08 /* fifo error interrupt enable */
233
+#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
234
+#define ICH_RESETREGS 0x02 /* reset busmaster registers */
235
+#define ICH_STARTBM 0x01 /* start busmaster operation */
236
+
237
+
238
+/* global block */
239
+#define ICH_REG_GLOB_CNT 0x3c /* dword - global control */
240
+#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
241
+#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
242
+#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
243
+#define ICH_ACLINK 0x00000008 /* AClink shut off */
244
+#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
245
+#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
246
+#define ICH_GIE 0x00000001 /* GPI interrupt enable */
247
+#define ICH_REG_GLOB_STA 0x40 /* dword - global status */
248
+#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
249
+#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
250
+#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
251
+#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
252
+#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
253
+#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
254
+#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
255
+#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
256
+#define ICH_MD3 0x00020000 /* modem power down semaphore */
257
+#define ICH_AD3 0x00010000 /* audio power down semaphore */
258
+#define ICH_RCS 0x00008000 /* read completion status */
259
+#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
260
+#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
261
+#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
262
+#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
263
+#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
264
+#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
265
+#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
266
+#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
267
+#define ICH_POINT 0x00000040 /* playback interrupt */
268
+#define ICH_PIINT 0x00000020 /* capture interrupt */
269
+#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
270
+#define ICH_MOINT 0x00000004 /* modem playback interrupt */
271
+#define ICH_MIINT 0x00000002 /* modem capture interrupt */
272
+#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
273
+#define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */
274
+#define ICH_CAS 0x01 /* codec access semaphore */
275
+
276
+#define ICH_MAX_FRAGS 32 /* max hw frags */
277
+
278
+
279
+/*
280
+ *
281
+ */
282
+
283
+enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
284
+enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
285
+
286
+#define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
287
+
288
+typedef struct {
289
+ unsigned int ichd; /* ich device number */
290
+ unsigned long reg_offset; /* offset to bmaddr */
291
+ u32 *bdbar; /* CPU address (32bit) */
292
+ unsigned int bdbar_addr; /* PCI bus address (32bit) */
293
+ snd_pcm_substream_t *substream;
294
+ unsigned int physbuf; /* physical address (32bit) */
295
+ unsigned int size;
296
+ unsigned int fragsize;
297
+ unsigned int fragsize1;
298
+ unsigned int position;
299
+ int frags;
300
+ int lvi;
301
+ int lvi_frag;
302
+ int civ;
303
+ int ack;
304
+ int ack_reload;
305
+ unsigned int ack_bit;
306
+ unsigned int roff_sr;
307
+ unsigned int roff_picb;
308
+ unsigned int int_sta_mask; /* interrupt status mask */
309
+ unsigned int ali_slot; /* ALI DMA slot */
310
+ ac97_t *ac97;
311
+} ichdev_t;
312
+
313
+typedef struct _snd_intel8x0m intel8x0_t;
314
+#define chip_t intel8x0_t
315
+
316
+struct _snd_intel8x0m {
317
+ unsigned int device_type;
318
+ char ac97_name[64];
319
+ char ctrl_name[64];
320
+
321
+ int irq;
322
+
323
+ unsigned int mmio;
324
+ unsigned long addr;
325
+ unsigned long remap_addr;
326
+ struct resource *res;
327
+ unsigned int bm_mmio;
328
+ unsigned long bmaddr;
329
+ unsigned long remap_bmaddr;
330
+ struct resource *res_bm;
331
+
332
+ struct pci_dev *pci;
333
+ snd_card_t *card;
334
+
335
+ int pcm_devs;
336
+ snd_pcm_t *pcm[2];
337
+ ichdev_t ichd[2];
338
+
339
+ int in_ac97_init: 1;
340
+
341
+ ac97_t *ac97[3];
342
+
343
+ spinlock_t reg_lock;
344
+ spinlock_t ac97_lock;
345
+
346
+ u32 bdbars_count;
347
+ u32 *bdbars;
348
+ dma_addr_t bdbars_addr;
349
+ u32 int_sta_reg; /* interrupt status register */
350
+ u32 int_sta_mask; /* interrupt status mask */
351
+ unsigned int pcm_pos_shift;
352
+
353
+#ifdef CONFIG_PM
354
+ int in_suspend;
355
+#endif
356
+};
357
+
358
+static struct pci_device_id snd_intel8x0m_ids[] = {
359
+ { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
360
+ { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
361
+ { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
362
+ { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
363
+ { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */
364
+ { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */
365
+ { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
366
+ { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
367
+#if 0
368
+ /* TODO: support needed */
369
+ { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7013 */
370
+ { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
371
+ { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
372
+ { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
373
+ { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
374
+ { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
375
+#endif
376
+ { 0, }
377
+};
378
+
379
+MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
380
+
381
+/*
382
+ * Lowlevel I/O - busmaster
383
+ */
384
+
385
+static u8 igetbyte(intel8x0_t *chip, u32 offset)
386
+{
387
+ if (chip->bm_mmio)
388
+ return readb(chip->remap_bmaddr + offset);
389
+ else
390
+ return inb(chip->bmaddr + offset);
391
+}
392
+
393
+static u16 igetword(intel8x0_t *chip, u32 offset)
394
+{
395
+ if (chip->bm_mmio)
396
+ return readw(chip->remap_bmaddr + offset);
397
+ else
398
+ return inw(chip->bmaddr + offset);
399
+}
400
+
401
+static u32 igetdword(intel8x0_t *chip, u32 offset)
402
+{
403
+ if (chip->bm_mmio)
404
+ return readl(chip->remap_bmaddr + offset);
405
+ else
406
+ return inl(chip->bmaddr + offset);
407
+}
408
+
409
+static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
410
+{
411
+ if (chip->bm_mmio)
412
+ writeb(val, chip->remap_bmaddr + offset);
413
+ else
414
+ outb(val, chip->bmaddr + offset);
415
+}
416
+
417
+static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
418
+{
419
+ if (chip->bm_mmio)
420
+ writel(val, chip->remap_bmaddr + offset);
421
+ else
422
+ outl(val, chip->bmaddr + offset);
423
+}
424
+
425
+/*
426
+ * Lowlevel I/O - AC'97 registers
427
+ */
428
+
429
+static u16 iagetword(intel8x0_t *chip, u32 offset)
430
+{
431
+ if (chip->mmio)
432
+ return readw(chip->remap_addr + offset);
433
+ else
434
+ return inw(chip->addr + offset);
435
+}
436
+
437
+static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
438
+{
439
+ if (chip->mmio)
440
+ writew(val, chip->remap_addr + offset);
441
+ else
442
+ outw(val, chip->addr + offset);
443
+}
444
+
445
+/*
446
+ * Basic I/O
447
+ */
448
+
449
+/*
450
+ * access to AC97 codec via normal i/o (for ICH and SIS7013)
451
+ */
452
+
453
+/* return the GLOB_STA bit for the corresponding codec */
454
+static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
455
+{
456
+ static unsigned int codec_bit[3] = {
457
+ ICH_PCR, ICH_SCR, ICH_TCR
458
+ };
459
+ snd_assert(codec < 3, return ICH_PCR);
460
+ return codec_bit[codec];
461
+}
462
+
463
+static int snd_intel8x0m_codec_semaphore(intel8x0_t *chip, unsigned int codec)
464
+{
465
+ int time;
466
+
467
+ if (codec > 1)
468
+ return -EIO;
469
+ codec = get_ich_codec_bit(chip, codec);
470
+
471
+ /* codec ready ? */
472
+ if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
473
+ return -EIO;
474
+
475
+ /* Anyone holding a semaphore for 1 msec should be shot... */
476
+ time = 100;
477
+ do {
478
+ if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
479
+ return 0;
480
+ udelay(10);
481
+ } while (time--);
482
+
483
+ /* access to some forbidden (non existant) ac97 registers will not
484
+ * reset the semaphore. So even if you don't get the semaphore, still
485
+ * continue the access. We don't need the semaphore anyway. */
486
+ snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
487
+ igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
488
+ iagetword(chip, 0); /* clear semaphore flag */
489
+ /* I don't care about the semaphore */
490
+ return -EBUSY;
491
+}
492
+
493
+static void snd_intel8x0_codec_write(ac97_t *ac97,
494
+ unsigned short reg,
495
+ unsigned short val)
496
+{
497
+ intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
498
+
499
+ spin_lock(&chip->ac97_lock);
500
+ if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
501
+ if (! chip->in_ac97_init)
502
+ snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
503
+ }
504
+ iaputword(chip, reg + ac97->num * 0x80, val);
505
+ spin_unlock(&chip->ac97_lock);
506
+}
507
+
508
+static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
509
+ unsigned short reg)
510
+{
511
+ intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return ~0);
512
+ unsigned short res;
513
+ unsigned int tmp;
514
+
515
+ spin_lock(&chip->ac97_lock);
516
+ if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
517
+ if (! chip->in_ac97_init)
518
+ snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
519
+ res = 0xffff;
520
+ } else {
521
+ res = iagetword(chip, reg + ac97->num * 0x80);
522
+ if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
523
+ /* reset RCS and preserve other R/WC bits */
524
+ iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
525
+ if (! chip->in_ac97_init)
526
+ snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
527
+ res = 0xffff;
528
+ }
529
+ }
530
+ spin_unlock(&chip->ac97_lock);
531
+ return res;
532
+}
533
+
534
+
535
+/*
536
+ * DMA I/O
537
+ */
538
+static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
539
+{
540
+ int idx;
541
+ u32 *bdbar = ichdev->bdbar;
542
+ unsigned long port = ichdev->reg_offset;
543
+
544
+ iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
545
+ if (ichdev->size == ichdev->fragsize) {
546
+ ichdev->ack_reload = ichdev->ack = 2;
547
+ ichdev->fragsize1 = ichdev->fragsize >> 1;
548
+ for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
549
+ bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
550
+ bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
551
+ ichdev->fragsize1 >> chip->pcm_pos_shift);
552
+ bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
553
+ bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
554
+ ichdev->fragsize1 >> chip->pcm_pos_shift);
555
+ }
556
+ ichdev->frags = 2;
557
+ } else {
558
+ ichdev->ack_reload = ichdev->ack = 1;
559
+ ichdev->fragsize1 = ichdev->fragsize;
560
+ for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
561
+ bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
562
+ bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
563
+ ichdev->fragsize >> chip->pcm_pos_shift);
564
+ // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
565
+ }
566
+ ichdev->frags = ichdev->size / ichdev->fragsize;
567
+ }
568
+ iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
569
+ ichdev->civ = 0;
570
+ iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
571
+ ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
572
+ ichdev->position = 0;
573
+#if 0
574
+ printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
575
+ ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
576
+#endif
577
+ /* clear interrupts */
578
+ iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
579
+}
580
+
581
+/*
582
+ * Interrupt handler
583
+ */
584
+
585
+static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
586
+{
587
+ unsigned long port = ichdev->reg_offset;
588
+ int civ, i, step;
589
+ int ack = 0;
590
+
591
+ civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
592
+ if (civ == ichdev->civ) {
593
+ // snd_printd("civ same %d\n", civ);
594
+ step = 1;
595
+ ichdev->civ++;
596
+ ichdev->civ &= ICH_REG_LVI_MASK;
597
+ } else {
598
+ step = civ - ichdev->civ;
599
+ if (step < 0)
600
+ step += ICH_REG_LVI_MASK + 1;
601
+ // if (step != 1)
602
+ // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
603
+ ichdev->civ = civ;
604
+ }
605
+
606
+ ichdev->position += step * ichdev->fragsize1;
607
+ ichdev->position %= ichdev->size;
608
+ ichdev->lvi += step;
609
+ ichdev->lvi &= ICH_REG_LVI_MASK;
610
+ iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
611
+ for (i = 0; i < step; i++) {
612
+ ichdev->lvi_frag++;
613
+ ichdev->lvi_frag %= ichdev->frags;
614
+ ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
615
+ // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
616
+ if (--ichdev->ack == 0) {
617
+ ichdev->ack = ichdev->ack_reload;
618
+ ack = 1;
619
+ }
620
+ }
621
+ if (ack && ichdev->substream) {
622
+ spin_unlock(&chip->reg_lock);
623
+ snd_pcm_period_elapsed(ichdev->substream);
624
+ spin_lock(&chip->reg_lock);
625
+ }
626
+ iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
627
+}
628
+
629
+static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
630
+{
631
+ intel8x0_t *chip = snd_magic_cast(intel8x0_t, dev_id, return IRQ_NONE);
632
+ ichdev_t *ichdev;
633
+ unsigned int status;
634
+ unsigned int i;
635
+
636
+ spin_lock(&chip->reg_lock);
637
+ status = igetdword(chip, chip->int_sta_reg);
638
+ if ((status & chip->int_sta_mask) == 0) {
639
+ if (status)
640
+ iputdword(chip, chip->int_sta_reg, status);
641
+ spin_unlock(&chip->reg_lock);
642
+ return IRQ_NONE;
643
+ }
644
+
645
+ for (i = 0; i < chip->bdbars_count; i++) {
646
+ ichdev = &chip->ichd[i];
647
+ if (status & ichdev->int_sta_mask)
648
+ snd_intel8x0_update(chip, ichdev);
649
+ }
650
+
651
+ /* ack them */
652
+ iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
653
+ spin_unlock(&chip->reg_lock);
654
+
655
+ return IRQ_HANDLED;
656
+}
657
+
658
+/*
659
+ * PCM part
660
+ */
661
+
662
+static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
663
+{
664
+ intel8x0_t *chip = snd_pcm_substream_chip(substream);
665
+ ichdev_t *ichdev = get_ichdev(substream);
666
+ unsigned char val = 0;
667
+ unsigned long port = ichdev->reg_offset;
668
+
669
+ switch (cmd) {
670
+ case SNDRV_PCM_TRIGGER_START:
671
+ case SNDRV_PCM_TRIGGER_RESUME:
672
+ val = ICH_IOCE | ICH_STARTBM;
673
+ break;
674
+ case SNDRV_PCM_TRIGGER_STOP:
675
+ case SNDRV_PCM_TRIGGER_SUSPEND:
676
+ val = 0;
677
+ break;
678
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
679
+ val = ICH_IOCE;
680
+ break;
681
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
682
+ val = ICH_IOCE | ICH_STARTBM;
683
+ break;
684
+ default:
685
+ return -EINVAL;
686
+ }
687
+ iputbyte(chip, port + ICH_REG_OFF_CR, val);
688
+ if (cmd == SNDRV_PCM_TRIGGER_STOP) {
689
+ /* wait until DMA stopped */
690
+ while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
691
+ /* reset whole DMA things */
692
+ iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
693
+ }
694
+ return 0;
695
+}
696
+
697
+static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
698
+ snd_pcm_hw_params_t * hw_params)
699
+{
700
+ return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
701
+}
702
+
703
+static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
704
+{
705
+ return snd_pcm_lib_free_pages(substream);
706
+}
707
+
708
+static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
709
+{
710
+ intel8x0_t *chip = snd_pcm_substream_chip(substream);
711
+ ichdev_t *ichdev = get_ichdev(substream);
712
+ size_t ptr1, ptr;
713
+
714
+ ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
715
+ if (ptr1 != 0)
716
+ ptr = ichdev->fragsize1 - ptr1;
717
+ else
718
+ ptr = 0;
719
+ ptr += ichdev->position;
720
+ if (ptr >= ichdev->size)
721
+ return 0;
722
+ return bytes_to_frames(substream->runtime, ptr);
723
+}
724
+
725
+static int snd_intel8x0m_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
726
+{
727
+ ichdev_t *ichdev = get_ichdev(substream);
728
+ /* hook off/on on start/stop */
729
+ /* TODO: move it to ac97 controls */
730
+ switch (cmd) {
731
+ case SNDRV_PCM_TRIGGER_START:
732
+ snd_ac97_update_bits(ichdev->ac97, AC97_GPIO_STATUS,
733
+ AC97_GPIO_LINE1_OH, AC97_GPIO_LINE1_OH);
734
+ break;
735
+ case SNDRV_PCM_TRIGGER_STOP:
736
+ snd_ac97_update_bits(ichdev->ac97, AC97_GPIO_STATUS,
737
+ AC97_GPIO_LINE1_OH, ~AC97_GPIO_LINE1_OH);
738
+ break;
739
+ default:
740
+ return -EINVAL;
741
+ }
742
+ return snd_intel8x0_pcm_trigger(substream,cmd);
743
+}
744
+
745
+static int snd_intel8x0m_pcm_prepare(snd_pcm_substream_t * substream)
746
+{
747
+ intel8x0_t *chip = snd_pcm_substream_chip(substream);
748
+ snd_pcm_runtime_t *runtime = substream->runtime;
749
+ ichdev_t *ichdev = get_ichdev(substream);
750
+
751
+ ichdev->physbuf = runtime->dma_addr;
752
+ ichdev->size = snd_pcm_lib_buffer_bytes(substream);
753
+ ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
754
+ snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
755
+ snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
756
+ snd_intel8x0_setup_periods(chip, ichdev);
757
+ return 0;
758
+}
759
+
760
+static snd_pcm_hardware_t snd_intel8x0m_stream =
761
+{
762
+ .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
763
+ SNDRV_PCM_INFO_BLOCK_TRANSFER |
764
+ SNDRV_PCM_INFO_MMAP_VALID |
765
+ SNDRV_PCM_INFO_PAUSE |
766
+ SNDRV_PCM_INFO_RESUME),
767
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
768
+ .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
769
+ .rate_min = 8000,
770
+ .rate_max = 16000,
771
+ .channels_min = 1,
772
+ .channels_max = 1,
773
+ .buffer_bytes_max = 32 * 1024,
774
+ .period_bytes_min = 32,
775
+ .period_bytes_max = 32 * 1024,
776
+ .periods_min = 1,
777
+ .periods_max = 1024,
778
+ .fifo_size = 0,
779
+};
780
+
781
+
782
+static int snd_intel8x0m_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
783
+{
784
+ static unsigned int rates[] = { 8000, 9600, 12000, 16000 };
785
+ static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
786
+ .count = ARRAY_SIZE(rates),
787
+ .list = rates,
788
+ .mask = 0,
789
+ };
790
+ snd_pcm_runtime_t *runtime = substream->runtime;
791
+ int err;
792
+
793
+ ichdev->substream = substream;
794
+ runtime->hw = snd_intel8x0m_stream;
795
+ err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
796
+ if ( err < 0 )
797
+ return err;
798
+ runtime->private_data = ichdev;
799
+ return 0;
800
+}
801
+
802
+static int snd_intel8x0m_playback_open(snd_pcm_substream_t * substream)
803
+{
804
+ intel8x0_t *chip = snd_pcm_substream_chip(substream);
805
+
806
+ return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
807
+}
808
+
809
+static int snd_intel8x0m_playback_close(snd_pcm_substream_t * substream)
810
+{
811
+ intel8x0_t *chip = snd_pcm_substream_chip(substream);
812
+
813
+ chip->ichd[ICHD_MDMOUT].substream = NULL;
814
+ return 0;
815
+}
816
+
817
+static int snd_intel8x0m_capture_open(snd_pcm_substream_t * substream)
818
+{
819
+ intel8x0_t *chip = snd_pcm_substream_chip(substream);
820
+
821
+ return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
822
+}
823
+
824
+static int snd_intel8x0m_capture_close(snd_pcm_substream_t * substream)
825
+{
826
+ intel8x0_t *chip = snd_pcm_substream_chip(substream);
827
+
828
+ chip->ichd[ICHD_MDMIN].substream = NULL;
829
+ return 0;
830
+}
831
+
832
+
833
+static snd_pcm_ops_t snd_intel8x0m_playback_ops = {
834
+ .open = snd_intel8x0m_playback_open,
835
+ .close = snd_intel8x0m_playback_close,
836
+ .ioctl = snd_pcm_lib_ioctl,
837
+ .hw_params = snd_intel8x0_hw_params,
838
+ .hw_free = snd_intel8x0_hw_free,
839
+ .prepare = snd_intel8x0m_pcm_prepare,
840
+ .trigger = snd_intel8x0m_pcm_trigger,
841
+ .pointer = snd_intel8x0_pcm_pointer,
842
+};
843
+
844
+static snd_pcm_ops_t snd_intel8x0m_capture_ops = {
845
+ .open = snd_intel8x0m_capture_open,
846
+ .close = snd_intel8x0m_capture_close,
847
+ .ioctl = snd_pcm_lib_ioctl,
848
+ .hw_params = snd_intel8x0_hw_params,
849
+ .hw_free = snd_intel8x0_hw_free,
850
+ .prepare = snd_intel8x0m_pcm_prepare,
851
+ .trigger = snd_intel8x0m_pcm_trigger,
852
+ .pointer = snd_intel8x0_pcm_pointer,
853
+};
854
+
855
+
856
+struct ich_pcm_table {
857
+ char *suffix;
858
+ snd_pcm_ops_t *playback_ops;
859
+ snd_pcm_ops_t *capture_ops;
860
+ size_t prealloc_size;
861
+ size_t prealloc_max_size;
862
+ int ac97_idx;
863
+};
864
+
865
+static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
866
+{
867
+ snd_pcm_t *pcm;
868
+ int err;
869
+ char name[32];
870
+
871
+ if (rec->suffix)
872
+ sprintf(name, "Intel ICH - %s", rec->suffix);
873
+ else
874
+ strcpy(name, "Intel ICH");
875
+ err = snd_pcm_new(chip->card, name, device,
876
+ rec->playback_ops ? 1 : 0,
877
+ rec->capture_ops ? 1 : 0, &pcm);
878
+ if (err < 0)
879
+ return err;
880
+
881
+ if (rec->playback_ops)
882
+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
883
+ if (rec->capture_ops)
884
+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
885
+
886
+ pcm->private_data = chip;
887
+ pcm->info_flags = 0;
888
+ if (rec->suffix)
889
+ sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
890
+ else
891
+ strcpy(pcm->name, chip->card->shortname);
892
+ chip->pcm[device] = pcm;
893
+
894
+ snd_pcm_lib_preallocate_pci_pages_for_all(chip->pci, pcm, rec->prealloc_size,
895
+ rec->prealloc_max_size);
896
+
897
+ return 0;
898
+}
899
+
900
+static struct ich_pcm_table intel_pcms[] __devinitdata = {
901
+ {
902
+ .suffix = "Modem",
903
+ .playback_ops = &snd_intel8x0m_playback_ops,
904
+ .capture_ops = &snd_intel8x0m_capture_ops,
905
+ .prealloc_size = 4 * 1024,
906
+ .prealloc_max_size = 16 * 1024,
907
+ },
908
+};
909
+
910
+static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
911
+{
912
+ int i, tblsize, device, err;
913
+ struct ich_pcm_table *tbl, *rec;
914
+
915
+#if 1
916
+ tbl = intel_pcms;
917
+ tblsize = 1;
918
+#else
919
+ switch (chip->device_type) {
920
+ case DEVICE_NFORCE:
921
+ tbl = nforce_pcms;
922
+ tblsize = ARRAY_SIZE(nforce_pcms);
923
+ break;
924
+ case DEVICE_ALI:
925
+ tbl = ali_pcms;
926
+ tblsize = ARRAY_SIZE(ali_pcms);
927
+ break;
928
+ default:
929
+ tbl = intel_pcms;
930
+ tblsize = 2;
931
+ break;
932
+ }
933
+#endif
934
+ device = 0;
935
+ for (i = 0; i < tblsize; i++) {
936
+ rec = tbl + i;
937
+ if (i > 0 && rec->ac97_idx) {
938
+ /* activate PCM only when associated AC'97 codec */
939
+ if (! chip->ichd[rec->ac97_idx].ac97)
940
+ continue;
941
+ }
942
+ err = snd_intel8x0_pcm1(chip, device, rec);
943
+ if (err < 0)
944
+ return err;
945
+ device++;
946
+ }
947
+
948
+ chip->pcm_devs = device;
949
+ return 0;
950
+}
951
+
952
+
953
+/*
954
+ * Mixer part
955
+ */
956
+
957
+static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
958
+{
959
+ intel8x0_t *chip = snd_magic_cast(intel8x0_t, ac97->private_data, return);
960
+ chip->ac97[ac97->num] = NULL;
961
+}
962
+
963
+
964
+static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock)
965
+{
966
+ ac97_t ac97, *x97;
967
+ int err;
968
+ unsigned int i;
969
+ unsigned int glob_sta = 0;
970
+
971
+ chip->in_ac97_init = 1;
972
+ memset(&ac97, 0, sizeof(ac97));
973
+ ac97.private_data = chip;
974
+ ac97.private_free = snd_intel8x0_mixer_free_ac97;
975
+ if (ac97_clock >= 8000 && ac97_clock <= 48000)
976
+ ac97.clock = ac97_clock;
977
+ else
978
+ ac97.clock = 48000;
979
+
980
+ glob_sta = igetdword(chip, ICHREG(GLOB_STA));
981
+ ac97.write = snd_intel8x0_codec_write;
982
+ ac97.read = snd_intel8x0_codec_read;
983
+ ac97.pci = chip->pci;
984
+
985
+ i = glob_sta & ICH_SCR ? 1 : 0;
986
+ ac97.num = i;
987
+ if ((err = snd_ac97_modem(chip->card, &ac97, &x97)) < 0) {
988
+ snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
989
+ goto __err;
990
+ }
991
+ chip->ac97[i] = x97;
992
+ if(ac97_is_modem(x97)) {
993
+ chip->ichd[ICHD_MDMIN].ac97 = x97;
994
+ chip->ichd[ICHD_MDMOUT].ac97 = x97;
995
+ }
996
+ chip->in_ac97_init = 0;
997
+ return 0;
998
+
999
+ __err:
1000
+ /* clear the cold-reset bit for the next chance */
1001
+ if (chip->device_type != DEVICE_ALI)
1002
+ iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
1003
+ return err;
1004
+}
1005
+
1006
+
1007
+/*
1008
+ *
1009
+ */
1010
+
1011
+#define do_delay(chip) do {\
1012
+ set_current_state(TASK_UNINTERRUPTIBLE);\
1013
+ schedule_timeout(1);\
1014
+} while (0)
1015
+
1016
+static int snd_intel8x0m_ich_chip_init(intel8x0_t *chip, int probing)
1017
+{
1018
+ unsigned long end_time;
1019
+ unsigned int cnt, status, nstatus;
1020
+
1021
+ /* put logic to right state */
1022
+ /* first clear status bits */
1023
+ status = ICH_RCS | ICH_MIINT | ICH_MOINT;
1024
+ cnt = igetdword(chip, ICHREG(GLOB_STA));
1025
+ iputdword(chip, ICHREG(GLOB_STA), cnt & status);
1026
+
1027
+ /* ACLink on, 2 channels */
1028
+ cnt = igetdword(chip, ICHREG(GLOB_CNT));
1029
+ cnt &= ~(ICH_ACLINK);
1030
+ /* finish cold or do warm reset */
1031
+ cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
1032
+ iputdword(chip, ICHREG(GLOB_CNT), cnt);
1033
+ end_time = (jiffies + (HZ / 4)) + 1;
1034
+ do {
1035
+ if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
1036
+ goto __ok;
1037
+ do_delay(chip);
1038
+ } while (time_after_eq(end_time, jiffies));
1039
+ snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
1040
+ return -EIO;
1041
+
1042
+ __ok:
1043
+ if (probing) {
1044
+ /* wait for any codec ready status.
1045
+ * Once it becomes ready it should remain ready
1046
+ * as long as we do not disable the ac97 link.
1047
+ */
1048
+ end_time = jiffies + HZ;
1049
+ do {
1050
+ status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
1051
+ if (status)
1052
+ break;
1053
+ do_delay(chip);
1054
+ } while (time_after_eq(end_time, jiffies));
1055
+ if (! status) {
1056
+ /* no codec is found */
1057
+ snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
1058
+ return -EIO;
1059
+ }
1060
+
1061
+ /* up to two codecs (modem cannot be tertiary with ICH4) */
1062
+ nstatus = ICH_PCR | ICH_SCR;
1063
+
1064
+ /* wait for other codecs ready status. */
1065
+ end_time = jiffies + HZ / 4;
1066
+ while (status != nstatus && time_after_eq(end_time, jiffies)) {
1067
+ do_delay(chip);
1068
+ status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
1069
+ }
1070
+
1071
+ } else {
1072
+ /* resume phase */
1073
+ int i;
1074
+ status = 0;
1075
+ for (i = 0; i < 3; i++)
1076
+ if (chip->ac97[i])
1077
+ status |= get_ich_codec_bit(chip, i);
1078
+ /* wait until all the probed codecs are ready */
1079
+ end_time = jiffies + HZ;
1080
+ do {
1081
+ nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
1082
+ if (status == nstatus)
1083
+ break;
1084
+ do_delay(chip);
1085
+ } while (time_after_eq(end_time, jiffies));
1086
+ }
1087
+
1088
+ return 0;
1089
+}
1090
+
1091
+static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
1092
+{
1093
+ unsigned int i;
1094
+ int err;
1095
+
1096
+ if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
1097
+ return err;
1098
+ iagetword(chip, 0); /* clear semaphore flag */
1099
+
1100
+ /* disable interrupts */
1101
+ for (i = 0; i < chip->bdbars_count; i++)
1102
+ iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1103
+ /* reset channels */
1104
+ for (i = 0; i < chip->bdbars_count; i++)
1105
+ iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1106
+ /* initialize Buffer Descriptor Lists */
1107
+ for (i = 0; i < chip->bdbars_count; i++)
1108
+ iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
1109
+ return 0;
1110
+}
1111
+
1112
+static int snd_intel8x0_free(intel8x0_t *chip)
1113
+{
1114
+ unsigned int i;
1115
+
1116
+ if (chip->irq < 0)
1117
+ goto __hw_end;
1118
+ /* disable interrupts */
1119
+ for (i = 0; i < chip->bdbars_count; i++)
1120
+ iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1121
+ /* reset channels */
1122
+ for (i = 0; i < chip->bdbars_count; i++)
1123
+ iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1124
+ /* --- */
1125
+ synchronize_irq(chip->irq);
1126
+ __hw_end:
1127
+ if (chip->bdbars)
1128
+ snd_free_pci_pages(chip->pci, chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, chip->bdbars, chip->bdbars_addr);
1129
+ if (chip->remap_addr)
1130
+ iounmap((void *) chip->remap_addr);
1131
+ if (chip->remap_bmaddr)
1132
+ iounmap((void *) chip->remap_bmaddr);
1133
+ if (chip->res) {
1134
+ release_resource(chip->res);
1135
+ kfree_nocheck(chip->res);
1136
+ }
1137
+ if (chip->res_bm) {
1138
+ release_resource(chip->res_bm);
1139
+ kfree_nocheck(chip->res_bm);
1140
+ }
1141
+ if (chip->irq >= 0)
1142
+ free_irq(chip->irq, (void *)chip);
1143
+ snd_magic_kfree(chip);
1144
+ return 0;
1145
+}
1146
+
1147
+#ifdef CONFIG_PM
1148
+/*
1149
+ * power management
1150
+ */
1151
+static void intel8x0_suspend(intel8x0_t *chip)
1152
+{
1153
+ snd_card_t *card = chip->card;
1154
+ int i;
1155
+
1156
+ if (chip->in_suspend ||
1157
+ card->power_state == SNDRV_CTL_POWER_D3hot)
1158
+ return;
1159
+
1160
+ chip->in_suspend = 1;
1161
+ for (i = 0; i < chip->pcm_devs; i++)
1162
+ snd_pcm_suspend_all(chip->pcm[i]);
1163
+ snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1164
+}
1165
+
1166
+static void intel8x0_resume(intel8x0_t *chip)
1167
+{
1168
+ snd_card_t *card = chip->card;
1169
+ int i;
1170
+
1171
+ if (! chip->in_suspend ||
1172
+ card->power_state == SNDRV_CTL_POWER_D0)
1173
+ return;
1174
+
1175
+ pci_enable_device(chip->pci);
1176
+ pci_set_master(chip->pci);
1177
+ snd_intel8x0_chip_init(chip, 0);
1178
+ for (i = 0; i < 3; i++)
1179
+ if (chip->ac97[i])
1180
+ snd_ac97_resume(chip->ac97[i]);
1181
+
1182
+ chip->in_suspend = 0;
1183
+ snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1184
+}
1185
+
1186
+static int snd_intel8x0m_suspend(struct pci_dev *dev, u32 state)
1187
+{
1188
+ intel8x0_t *chip = snd_magic_cast(intel8x0_t, pci_get_drvdata(dev), return -ENXIO);
1189
+ intel8x0_suspend(chip);
1190
+ return 0;
1191
+}
1192
+static int snd_intel8x0m_resume(struct pci_dev *dev)
1193
+{
1194
+ intel8x0_t *chip = snd_magic_cast(intel8x0_t, pci_get_drvdata(dev), return -ENXIO);
1195
+ intel8x0_resume(chip);
1196
+ return 0;
1197
+}
1198
+
1199
+/* callback */
1200
+static int snd_intel8x0_set_power_state(snd_card_t *card, unsigned int power_state)
1201
+{
1202
+ intel8x0_t *chip = snd_magic_cast(intel8x0_t, card->power_state_private_data, return -ENXIO);
1203
+ switch (power_state) {
1204
+ case SNDRV_CTL_POWER_D0:
1205
+ case SNDRV_CTL_POWER_D1:
1206
+ case SNDRV_CTL_POWER_D2:
1207
+ intel8x0_resume(chip);
1208
+ break;
1209
+ case SNDRV_CTL_POWER_D3hot:
1210
+ case SNDRV_CTL_POWER_D3cold:
1211
+ intel8x0_suspend(chip);
1212
+ break;
1213
+ default:
1214
+ return -EINVAL;
1215
+ }
1216
+ return 0;
1217
+}
1218
+
1219
+#endif /* CONFIG_PM */
1220
+
1221
+static void snd_intel8x0m_proc_read(snd_info_entry_t * entry,
1222
+ snd_info_buffer_t * buffer)
1223
+{
1224
+ intel8x0_t *chip = snd_magic_cast(intel8x0_t, entry->private_data, return);
1225
+ unsigned int tmp;
1226
+
1227
+ snd_iprintf(buffer, "Intel8x0m\n\n");
1228
+ if (chip->device_type == DEVICE_ALI)
1229
+ return;
1230
+ tmp = igetdword(chip, ICHREG(GLOB_STA));
1231
+ snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
1232
+ snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
1233
+ snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
1234
+ tmp & ICH_PCR ? " primary" : "",
1235
+ tmp & ICH_SCR ? " secondary" : "",
1236
+ tmp & ICH_TCR ? " tertiary" : "",
1237
+ (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1238
+}
1239
+
1240
+static void __devinit snd_intel8x0m_proc_init(intel8x0_t * chip)
1241
+{
1242
+ snd_info_entry_t *entry;
1243
+
1244
+ if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
1245
+ snd_info_set_text_ops(entry, chip, snd_intel8x0m_proc_read);
1246
+}
1247
+
1248
+static int snd_intel8x0_dev_free(snd_device_t *device)
1249
+{
1250
+ intel8x0_t *chip = snd_magic_cast(intel8x0_t, device->device_data, return -ENXIO);
1251
+ return snd_intel8x0_free(chip);
1252
+}
1253
+
1254
+struct ich_reg_info {
1255
+ unsigned int int_sta_mask;
1256
+ unsigned int offset;
1257
+};
1258
+
1259
+static int __devinit snd_intel8x0m_create(snd_card_t * card,
1260
+ struct pci_dev *pci,
1261
+ unsigned long device_type,
1262
+ intel8x0_t ** r_intel8x0)
1263
+{
1264
+ intel8x0_t *chip;
1265
+ int err;
1266
+ unsigned int i;
1267
+ unsigned int int_sta_masks;
1268
+ ichdev_t *ichdev;
1269
+ static snd_device_ops_t ops = {
1270
+ .dev_free = snd_intel8x0_dev_free,
1271
+ };
1272
+ static struct ich_reg_info intel_regs[2] = {
1273
+ { ICH_MIINT, 0 },
1274
+ { ICH_MOINT, 0x10 },
1275
+ };
1276
+ struct ich_reg_info *tbl;
1277
+
1278
+ *r_intel8x0 = NULL;
1279
+
1280
+ if ((err = pci_enable_device(pci)) < 0)
1281
+ return err;
1282
+
1283
+ chip = snd_magic_kcalloc(intel8x0_t, 0, GFP_KERNEL);
1284
+ if (chip == NULL)
1285
+ return -ENOMEM;
1286
+ spin_lock_init(&chip->reg_lock);
1287
+ spin_lock_init(&chip->ac97_lock);
1288
+ chip->device_type = device_type;
1289
+ chip->card = card;
1290
+ chip->pci = pci;
1291
+ chip->irq = -1;
1292
+ snd_intel8x0m_proc_init(chip);
1293
+ sprintf(chip->ac97_name, "%s - AC'97", card->shortname);
1294
+ sprintf(chip->ctrl_name, "%s - Controller", card->shortname);
1295
+ if (device_type == DEVICE_ALI) {
1296
+ /* ALI5455 has no ac97 region */
1297
+ chip->bmaddr = pci_resource_start(pci, 0);
1298
+ if ((chip->res_bm = request_region(chip->bmaddr, 256, chip->ctrl_name)) == NULL) {
1299
+ snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 256 - 1);
1300
+ snd_intel8x0_free(chip);
1301
+ return -EBUSY;
1302
+ }
1303
+ goto port_inited;
1304
+ }
1305
+
1306
+ if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
1307
+ chip->mmio = 1;
1308
+ chip->addr = pci_resource_start(pci, 2);
1309
+ if ((chip->res = request_mem_region(chip->addr, 512, chip->ac97_name)) == NULL) {
1310
+ snd_printk("unable to grab I/O memory 0x%lx-0x%lx\n", chip->addr, chip->addr + 512 - 1);
1311
+ snd_intel8x0_free(chip);
1312
+ return -EBUSY;
1313
+ }
1314
+ chip->remap_addr = (unsigned long) ioremap_nocache(chip->addr, 512);
1315
+ if (chip->remap_addr == 0) {
1316
+ snd_printk("AC'97 space ioremap problem\n");
1317
+ snd_intel8x0_free(chip);
1318
+ return -EIO;
1319
+ }
1320
+ } else {
1321
+ chip->addr = pci_resource_start(pci, 0);
1322
+ if ((chip->res = request_region(chip->addr, 256, chip->ac97_name)) == NULL) {
1323
+ snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->addr, chip->addr + 256 - 1);
1324
+ snd_intel8x0_free(chip);
1325
+ return -EBUSY;
1326
+ }
1327
+ }
1328
+ if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
1329
+ chip->bm_mmio = 1;
1330
+ chip->bmaddr = pci_resource_start(pci, 3);
1331
+ if ((chip->res_bm = request_mem_region(chip->bmaddr, 256, chip->ctrl_name)) == NULL) {
1332
+ snd_printk("unable to grab I/O memory 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 512 - 1);
1333
+ snd_intel8x0_free(chip);
1334
+ return -EBUSY;
1335
+ }
1336
+ chip->remap_bmaddr = (unsigned long) ioremap_nocache(chip->bmaddr, 256);
1337
+ if (chip->remap_bmaddr == 0) {
1338
+ snd_printk("Controller space ioremap problem\n");
1339
+ snd_intel8x0_free(chip);
1340
+ return -EIO;
1341
+ }
1342
+ } else {
1343
+ chip->bmaddr = pci_resource_start(pci, 1);
1344
+ if ((chip->res_bm = request_region(chip->bmaddr, 128, chip->ctrl_name)) == NULL) {
1345
+ snd_printk("unable to grab ports 0x%lx-0x%lx\n", chip->bmaddr, chip->bmaddr + 128 - 1);
1346
+ snd_intel8x0_free(chip);
1347
+ return -EBUSY;
1348
+ }
1349
+ }
1350
+
1351
+ port_inited:
1352
+ if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
1353
+ snd_printk("unable to grab IRQ %d\n", pci->irq);
1354
+ snd_intel8x0_free(chip);
1355
+ return -EBUSY;
1356
+ }
1357
+ chip->irq = pci->irq;
1358
+ pci_set_master(pci);
1359
+ synchronize_irq(chip->irq);
1360
+
1361
+ /* initialize offsets */
1362
+ chip->bdbars_count = 2;
1363
+ tbl = intel_regs;
1364
+
1365
+ for (i = 0; i < chip->bdbars_count; i++) {
1366
+ ichdev = &chip->ichd[i];
1367
+ ichdev->ichd = i;
1368
+ ichdev->reg_offset = tbl[i].offset;
1369
+ ichdev->int_sta_mask = tbl[i].int_sta_mask;
1370
+ if (device_type == DEVICE_SIS) {
1371
+ /* SiS 7013 swaps the registers */
1372
+ ichdev->roff_sr = ICH_REG_OFF_PICB;
1373
+ ichdev->roff_picb = ICH_REG_OFF_SR;
1374
+ } else {
1375
+ ichdev->roff_sr = ICH_REG_OFF_SR;
1376
+ ichdev->roff_picb = ICH_REG_OFF_PICB;
1377
+ }
1378
+ if (device_type == DEVICE_ALI)
1379
+ ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1380
+ }
1381
+ /* SIS7013 handles the pcm data in bytes, others are in words */
1382
+ chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1383
+
1384
+ /* allocate buffer descriptor lists */
1385
+ /* the start of each lists must be aligned to 8 bytes */
1386
+ chip->bdbars = (u32 *)snd_malloc_pci_pages(pci, chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, &chip->bdbars_addr);
1387
+ if (chip->bdbars == NULL) {
1388
+ snd_intel8x0_free(chip);
1389
+ return -ENOMEM;
1390
+ }
1391
+ /* tables must be aligned to 8 bytes here, but the kernel pages
1392
+ are much bigger, so we don't care (on i386) */
1393
+ int_sta_masks = 0;
1394
+ for (i = 0; i < chip->bdbars_count; i++) {
1395
+ ichdev = &chip->ichd[i];
1396
+ ichdev->bdbar = chip->bdbars + (i * ICH_MAX_FRAGS * 2);
1397
+ ichdev->bdbar_addr = chip->bdbars_addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1398
+ int_sta_masks |= ichdev->int_sta_mask;
1399
+ }
1400
+ chip->int_sta_reg = ICH_REG_GLOB_STA;
1401
+ chip->int_sta_mask = int_sta_masks;
1402
+
1403
+ if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
1404
+ snd_intel8x0_free(chip);
1405
+ return err;
1406
+ }
1407
+
1408
+#ifdef CONFIG_PM
1409
+ card->set_power_state = snd_intel8x0_set_power_state;
1410
+ card->power_state_private_data = chip;
1411
+#endif
1412
+
1413
+ if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1414
+ snd_intel8x0_free(chip);
1415
+ return err;
1416
+ }
1417
+
1418
+ *r_intel8x0 = chip;
1419
+ return 0;
1420
+}
1421
+
1422
+static struct shortname_table {
1423
+ unsigned int id;
1424
+ const char *s;
1425
+} shortnames[] __devinitdata = {
1426
+ { PCI_DEVICE_ID_INTEL_82801_6, "Intel 82801AA-ICH" },
1427
+ { PCI_DEVICE_ID_INTEL_82901_6, "Intel 82901AB-ICH0" },
1428
+ { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1429
+ { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1430
+ { PCI_DEVICE_ID_INTEL_ICH3_6, "Intel 82801CA-ICH3" },
1431
+ { PCI_DEVICE_ID_INTEL_ICH4_6, "Intel 82801DB-ICH4" },
1432
+ { PCI_DEVICE_ID_INTEL_ICH5_6, "Intel ICH5" },
1433
+ { 0x7446, "AMD AMD768" },
1434
+#if 0
1435
+ { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1436
+ { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
1437
+ { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
1438
+ { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
1439
+ { 0x5455, "ALi M5455" },
1440
+ { 0x746d, "AMD AMD8111" },
1441
+#endif
1442
+ { 0, 0 },
1443
+};
1444
+
1445
+static int __devinit snd_intel8x0m_probe(struct pci_dev *pci,
1446
+ const struct pci_device_id *pci_id)
1447
+{
1448
+ static int dev;
1449
+ snd_card_t *card;
1450
+ intel8x0_t *chip;
1451
+ int err;
1452
+ struct shortname_table *name;
1453
+
1454
+ if (dev >= SNDRV_CARDS)
1455
+ return -ENODEV;
1456
+ if (!enable[dev]) {
1457
+ dev++;
1458
+ return -ENOENT;
1459
+ }
1460
+
1461
+ card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1462
+ if (card == NULL)
1463
+ return -ENOMEM;
1464
+
1465
+ switch (pci_id->driver_data) {
1466
+ case DEVICE_NFORCE:
1467
+ strcpy(card->driver, "NFORCE");
1468
+ break;
1469
+ default:
1470
+ strcpy(card->driver, "ICH");
1471
+ break;
1472
+ }
1473
+
1474
+ strcpy(card->shortname, "Intel ICH");
1475
+ for (name = shortnames; name->id; name++) {
1476
+ if (pci->device == name->id) {
1477
+ strcpy(card->shortname, name->s);
1478
+ break;
1479
+ }
1480
+ }
1481
+ strcat(card->shortname," Modem");
1482
+
1483
+ if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1484
+ snd_card_free(card);
1485
+ return err;
1486
+ }
1487
+
1488
+ if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev])) < 0) {
1489
+ snd_card_free(card);
1490
+ return err;
1491
+ }
1492
+ if ((err = snd_intel8x0_pcm(chip)) < 0) {
1493
+ snd_card_free(card);
1494
+ return err;
1495
+ }
1496
+
1497
+ sprintf(card->longname, "%s at 0x%lx, irq %i",
1498
+ card->shortname, chip->addr, chip->irq);
1499
+
1500
+ if ((err = snd_card_register(card)) < 0) {
1501
+ snd_card_free(card);
1502
+ return err;
1503
+ }
1504
+ pci_set_drvdata(pci, chip);
1505
+ dev++;
1506
+ return 0;
1507
+}
1508
+
1509
+static void __devexit snd_intel8x0m_remove(struct pci_dev *pci)
1510
+{
1511
+ intel8x0_t *chip = snd_magic_cast(intel8x0_t, pci_get_drvdata(pci), return);
1512
+ if (chip)
1513
+ snd_card_free(chip->card);
1514
+ pci_set_drvdata(pci, NULL);
1515
+}
1516
+
1517
+static struct pci_driver driver = {
1518
+ .name = "Intel ICH Modem",
1519
+ .id_table = snd_intel8x0m_ids,
1520
+ .probe = snd_intel8x0m_probe,
1521
+ .remove = __devexit_p(snd_intel8x0m_remove),
1522
+#ifdef CONFIG_PM
1523
+ .suspend = snd_intel8x0m_suspend,
1524
+ .resume = snd_intel8x0m_resume,
1525
+#endif
1526
+};
1527
+
1528
+
1529
+static int __init alsa_card_intel8x0m_init(void)
1530
+{
1531
+ int err;
1532
+
1533
+ if ((err = pci_module_init(&driver)) < 0) {
1534
+#ifdef MODULE
1535
+ printk(KERN_ERR "Intel ICH modemcard not found or device busy\n");
1536
+#endif
1537
+ return err;
1538
+ }
1539
+
1540
+ return 0;
1541
+}
1542
+
1543
+static void __exit alsa_card_intel8x0m_exit(void)
1544
+{
1545
+ pci_unregister_driver(&driver);
1546
+}
1547
+
1548
+module_init(alsa_card_intel8x0m_init)
1549
+module_exit(alsa_card_intel8x0m_exit)
1550
+
1551
+#ifndef MODULE
1552
+
1553
+/* format is: snd-intel8x0=enable,index,id,ac97_clock,mpu_port,joystick */
1554
+
1555
+static int __init alsa_card_intel8x0m_setup(char *str)
1556
+{
1557
+ static unsigned __initdata nr_dev = 0;
1558
+
1559
+ if (nr_dev >= SNDRV_CARDS)
1560
+ return 0;
1561
+ (void)(get_option(&str,&enable[nr_dev]) == 2 &&
1562
+ get_option(&str,&index[nr_dev]) == 2 &&
1563
+ get_id(&str,&id[nr_dev]) == 2 &&
1564
+ get_option(&str,&ac97_clock[nr_dev]) == 2
1565
+ );
1566
+ nr_dev++;
1567
+ return 1;
1568
+}
1569
+
1570
+__setup("snd-intel8x0m=", alsa_card_intel8x0m_setup);
1571
+
1572
+#endif /* ifndef MODULE */
1573
diff -Nru linux-2.6.0_orig/sound/pci/Kconfig linux-2.6.0/sound/pci/Kconfig
1574
--- linux-2.6.0_orig/sound/pci/Kconfig 2003-12-28 22:18:44.000000000 +0200
1575
+++ linux-2.6.0/sound/pci/Kconfig 2003-12-28 22:29:43.000000000 +0200
1576
@@ -172,6 +172,13 @@
1577
Say 'Y' or 'M' to include support for Intel8x0 based soundcards,
1578
SiS 7012, AMD768/8111, NVidia NForce and ALi 5455 chips.
1579
1580
+config SND_INTEL8X0M
1581
+ tristate "Intel i8x0/MX440; AMD768/8111 modems (EXPERIMENTAL)"
1582
+ depends on SND && EXPERIMENTAL
1583
+ help
1584
+ Say 'Y' or 'M' to include support for Intel8x0 and AMD768/8111 based
1585
+ modems.
1586
+
1587
config SND_SONICVIBES
1588
tristate "S3 SonicVibes"
1589
depends on SND
1590
diff -Nru linux-2.6.0_orig/sound/pci/Makefile linux-2.6.0/sound/pci/Makefile
1591
--- linux-2.6.0_orig/sound/pci/Makefile 2003-12-28 22:18:44.000000000 +0200
1592
+++ linux-2.6.0/sound/pci/Makefile 2003-12-28 22:29:43.000000000 +0200
1593
@@ -13,6 +13,7 @@
1594
snd-es1968-objs := es1968.o
1595
snd-fm801-objs := fm801.o
1596
snd-intel8x0-objs := intel8x0.o
1597
+snd-intel8x0m-objs := intel8x0m.o
1598
snd-maestro3-objs := maestro3.o
1599
snd-rme32-objs := rme32.o
1600
snd-rme96-objs := rme96.o
1601
@@ -29,6 +30,7 @@
1602
obj-$(CONFIG_SND_ES1968) += snd-es1968.o
1603
obj-$(CONFIG_SND_FM801) += snd-fm801.o
1604
obj-$(CONFIG_SND_INTEL8X0) += snd-intel8x0.o
1605
+obj-$(CONFIG_SND_INTEL8X0M) += snd-intel8x0m.o
1606
obj-$(CONFIG_SND_MAESTRO3) += snd-maestro3.o
1607
obj-$(CONFIG_SND_RME32) += snd-rme32.o
1608
obj-$(CONFIG_SND_RME96) += snd-rme96.o
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