2
* Tiny Code Generator for QEMU
4
* Copyright (c) 2008 Fabrice Bellard
6
* Permission is hereby granted, free of charge, to any person obtaining a copy
7
* of this software and associated documentation files (the "Software"), to deal
8
* in the Software without restriction, including without limitation the rights
9
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
* copies of the Software, and to permit persons to whom the Software is
11
* furnished to do so, subject to the following conditions:
13
* The above copyright notice and this permission notice shall be included in
14
* all copies or substantial portions of the Software.
16
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
36
int __op_param1, __op_param2, __op_param3;
37
#if defined(__sparc__) || defined(__arm__)
38
void __op_gen_label1(){}
39
void __op_gen_label2(){}
40
void __op_gen_label3(){}
42
int __op_gen_label1, __op_gen_label2, __op_gen_label3;
44
int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
48
static inline void flush_icache_range(unsigned long start, unsigned long stop)
51
#elif defined(__ia64__)
52
static inline void flush_icache_range(unsigned long start, unsigned long stop)
54
while (start < stop) {
55
asm volatile ("fc %0" :: "r"(start));
58
asm volatile (";;sync.i;;srlz.i;;");
60
#elif defined(__powerpc__)
62
#define MIN_CACHE_LINE_SIZE 8 /* conservative value */
64
static inline void flush_icache_range(unsigned long start, unsigned long stop)
68
start &= ~(MIN_CACHE_LINE_SIZE - 1);
69
stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
71
for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
72
asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
74
asm volatile ("sync" : : : "memory");
75
for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
76
asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
78
asm volatile ("sync" : : : "memory");
79
asm volatile ("isync" : : : "memory");
81
#elif defined(__alpha__)
82
static inline void flush_icache_range(unsigned long start, unsigned long stop)
86
#elif defined(__sparc__)
87
static inline void flush_icache_range(unsigned long start, unsigned long stop)
91
p = start & ~(8UL - 1UL);
92
stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
94
for (; p < stop; p += 8)
95
__asm__ __volatile__("flush\t%0" : : "r" (p));
97
#elif defined(__arm__)
98
static inline void flush_icache_range(unsigned long start, unsigned long stop)
100
register unsigned long _beg __asm ("a1") = start;
101
register unsigned long _end __asm ("a2") = stop;
102
register unsigned long _flg __asm ("a3") = 0;
103
__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
105
#elif defined(__mc68000)
107
# include <asm/cachectl.h>
108
static inline void flush_icache_range(unsigned long start, unsigned long stop)
110
cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
112
#elif defined(__mips__)
114
#include <sys/cachectl.h>
115
static inline void flush_icache_range(unsigned long start, unsigned long stop)
117
_flush_cache ((void *)start, stop - start, BCACHE);
120
#error unsupported CPU
125
register int gp asm("$29");
127
static inline void immediate_ldah(void *p, int val) {
129
long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff;
135
static inline void immediate_lda(void *dest, int val) {
136
*(uint16_t *) dest = val;
138
void fix_bsr(void *p, int offset) {
140
*dest &= ~((1 << 21) - 1);
141
*dest |= (offset >> 2) & ((1 << 21) - 1);
144
#endif /* __alpha__ */
148
#define ARM_LDR_TABLE_SIZE 1024
150
typedef struct LDREntry {
156
static LDREntry arm_ldr_table[1024];
157
static uint32_t arm_data_table[ARM_LDR_TABLE_SIZE];
159
extern char exec_loop;
161
static inline void arm_reloc_pc24(uint32_t *ptr, uint32_t insn, int val)
163
*ptr = (insn & ~0xffffff) | ((insn + ((val - (int)ptr) >> 2)) & 0xffffff);
166
static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
167
LDREntry *ldr_start, LDREntry *ldr_end,
168
uint32_t *data_start, uint32_t *data_end,
173
int offset, data_size, target;
178
data_size = (data_end - data_start) << 2;
181
/* generate branch to skip the data */
184
target = (long)gen_code_ptr + data_size + 4;
185
arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);
190
data_ptr = gen_code_ptr;
191
memcpy(gen_code_ptr, data_start, data_size);
192
gen_code_ptr += data_size;
194
/* patch the ldr to point to the data */
195
for(le = ldr_start; le < ldr_end; le++) {
196
ptr = (uint32_t *)le->ptr;
197
offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) +
198
(unsigned long)data_ptr -
199
(unsigned long)ptr - 8;
201
fprintf(stderr, "Negative constant pool offset\n");
207
if (offset >= 4096) {
208
fprintf(stderr, "Bad ldr offset\n");
214
if (offset >= 1024 ) {
215
fprintf(stderr, "Bad ldc offset\n");
221
if (offset >= 1024 ) {
222
fprintf(stderr, "Bad add offset\n");
227
fprintf(stderr, "Bad pc relative fixup\n");
233
insn |= offset | 0x00800000;
236
insn |= (offset >> 2) | 0x00800000;
239
insn |= (offset >> 2) | 0xf00;
251
/* Patch instruction with "val" where "mask" has 1 bits. */
252
static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val)
254
uint64_t m0, m1, v0, v1, b0, b1, *b = (uint64_t *) (insn_addr & -16);
255
# define insn_mask ((1UL << 41) - 1)
258
b0 = b[0]; b1 = b[1];
259
shift = 5 + 41 * (insn_addr % 16); /* 5 template, 3 x 41-bit insns */
261
m1 = mask << (shift - 64);
262
v1 = val << (shift - 64);
264
m0 = mask << shift; m1 = mask >> (64 - shift);
265
v0 = val << shift; v1 = val >> (64 - shift);
266
b[0] = (b0 & ~m0) | (v0 & m0);
268
b[1] = (b1 & ~m1) | (v1 & m1);
271
static inline void ia64_patch_imm60 (uint64_t insn_addr, uint64_t val)
273
ia64_patch(insn_addr,
275
( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */
276
| ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */));
277
ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18);
280
static inline void ia64_imm64 (void *insn, uint64_t val)
282
/* Ignore the slot number of the relocation; GCC and Intel
283
toolchains differed for some time on whether IMM64 relocs are
284
against slot 1 (Intel) or slot 2 (GCC). */
285
uint64_t insn_addr = (uint64_t) insn & ~3UL;
287
ia64_patch(insn_addr + 2,
289
( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */
290
| ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */
291
| ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */
292
| ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */
293
| ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */)
295
ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22);
298
static inline void ia64_imm60b (void *insn, uint64_t val)
300
/* Ignore the slot number of the relocation; GCC and Intel
301
toolchains differed for some time on whether IMM64 relocs are
302
against slot 1 (Intel) or slot 2 (GCC). */
303
uint64_t insn_addr = (uint64_t) insn & ~3UL;
305
if (val + ((uint64_t) 1 << 59) >= (1UL << 60))
306
fprintf(stderr, "%s: value %ld out of IMM60 range\n",
307
__FUNCTION__, (int64_t) val);
308
ia64_patch_imm60(insn_addr + 2, val);
311
static inline void ia64_imm22 (void *insn, uint64_t val)
313
if (val + (1 << 21) >= (1 << 22))
314
fprintf(stderr, "%s: value %li out of IMM22 range\n",
315
__FUNCTION__, (int64_t)val);
316
ia64_patch((uint64_t) insn, 0x01fffcfe000UL,
317
( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
318
| ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */
319
| ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */
320
| ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */));
323
/* Like ia64_imm22(), but also clear bits 20-21. For addl, this has
324
the effect of turning "addl rX=imm22,rY" into "addl
326
static inline void ia64_imm22_r0 (void *insn, uint64_t val)
328
if (val + (1 << 21) >= (1 << 22))
329
fprintf(stderr, "%s: value %li out of IMM22 range\n",
330
__FUNCTION__, (int64_t)val);
331
ia64_patch((uint64_t) insn, 0x01fffcfe000UL | (0x3UL << 20),
332
( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */
333
| ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */
334
| ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */
335
| ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */));
338
static inline void ia64_imm21b (void *insn, uint64_t val)
340
if (val + (1 << 20) >= (1 << 21))
341
fprintf(stderr, "%s: value %li out of IMM21b range\n",
342
__FUNCTION__, (int64_t)val);
343
ia64_patch((uint64_t) insn, 0x11ffffe000UL,
344
( ((val & 0x100000UL) << 16) /* bit 20 -> 36 */
345
| ((val & 0x0fffffUL) << 13) /* bit 0 -> 13 */));
348
static inline void ia64_nop_b (void *insn)
350
ia64_patch((uint64_t) insn, (1UL << 41) - 1, 2UL << 37);
353
static inline void ia64_ldxmov(void *insn, uint64_t val)
355
if (val + (1 << 21) < (1 << 22))
356
ia64_patch((uint64_t) insn, 0x1fff80fe000UL, 8UL << 37);
359
static inline int ia64_patch_ltoff(void *insn, uint64_t val,
362
if (relaxable && (val + (1 << 21) < (1 << 22))) {
363
ia64_imm22_r0(insn, val);
370
struct ia64_fixup *next;
371
void *addr; /* address that needs to be patched */
375
#define IA64_PLT(insn, plt_index) \
377
struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \
378
fixup->next = plt_fixes; \
380
fixup->addr = (insn); \
381
fixup->value = (plt_index); \
382
plt_offset[(plt_index)] = 1; \
385
#define IA64_LTOFF(insn, val, relaxable) \
387
if (ia64_patch_ltoff(insn, val, relaxable)) { \
388
struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \
389
fixup->next = ltoff_fixes; \
390
ltoff_fixes = fixup; \
391
fixup->addr = (insn); \
392
fixup->value = (val); \
396
static inline void ia64_apply_fixes (uint8_t **gen_code_pp,
397
struct ia64_fixup *ltoff_fixes,
399
struct ia64_fixup *plt_fixes,
401
unsigned long *plt_target,
402
unsigned int *plt_offset)
404
static const uint8_t plt_bundle[] = {
405
0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; movl r1=GP */
406
0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x60,
408
0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */
409
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0
411
uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start;
413
struct ia64_fixup *fixup;
414
unsigned int offset = 0;
422
plt_start = gen_code_ptr;
424
for (i = 0; i < num_plts; ++i) {
426
plt_offset[i] = offset;
427
offset += sizeof(plt_bundle);
429
fdesc = (struct fdesc *) plt_target[i];
430
memcpy(gen_code_ptr, plt_bundle, sizeof(plt_bundle));
431
ia64_imm64 (gen_code_ptr + 0x02, fdesc->gp);
432
ia64_imm60b(gen_code_ptr + 0x12,
433
(fdesc->ip - (long) (gen_code_ptr + 0x10)) >> 4);
434
gen_code_ptr += sizeof(plt_bundle);
438
for (fixup = plt_fixes; fixup; fixup = fixup->next)
439
ia64_imm21b(fixup->addr,
440
((long) plt_start + plt_offset[fixup->value]
441
- ((long) fixup->addr & ~0xf)) >> 4);
444
got_start = gen_code_ptr;
446
/* First, create the GOT: */
447
for (fixup = ltoff_fixes; fixup; fixup = fixup->next) {
448
/* first check if we already have this value in the GOT: */
449
for (vp = (uint64_t *) got_start; vp < (uint64_t *) gen_code_ptr; ++vp)
450
if (*vp == fixup->value)
452
if (vp == (uint64_t *) gen_code_ptr) {
453
/* Nope, we need to put the value in the GOT: */
457
ia64_imm22(fixup->addr, (long) vp - gp);
459
/* Keep code ptr aligned. */
460
if ((long) gen_code_ptr & 15)
462
*gen_code_pp = gen_code_ptr;
467
const TCGArg *dyngen_op(TCGContext *s, int opc, const TCGArg *opparam_ptr)
469
uint8_t *gen_code_ptr;
471
gen_code_ptr = s->code_ptr;
474
/* op.h is dynamically generated by dyngen.c from op.c */
480
s->code_ptr = gen_code_ptr;