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* ARM AMBA Generic/Distributed Interrupt Controller
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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* This code is licenced under the GPL.
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/* TODO: Some variants of this controller can handle multiple CPUs.
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Currently only single CPU operation is implemented. */
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#define DPRINTF(fmt, args...) \
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do { printf("arm_gic: " fmt , ##args); } while (0)
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#define DPRINTF(fmt, args...) do {} while(0)
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/* Distributed interrupt controller. */
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static const uint8_t gic_id[] =
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{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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typedef struct gic_irq_state
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unsigned model:1; /* 0 = 1:N, 1 = N:N */
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unsigned trigger:1; /* nonzero = edge triggered. */
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#define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1
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#define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0
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#define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
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#define GIC_SET_PENDING(irq) s->irq_state[irq].pending = 1
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#define GIC_CLEAR_PENDING(irq) s->irq_state[irq].pending = 0
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#define GIC_TEST_PENDING(irq) s->irq_state[irq].pending
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#define GIC_SET_ACTIVE(irq) s->irq_state[irq].active = 1
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#define GIC_CLEAR_ACTIVE(irq) s->irq_state[irq].active = 0
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#define GIC_TEST_ACTIVE(irq) s->irq_state[irq].active
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#define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
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#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
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#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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#define GIC_SET_LEVEL(irq) s->irq_state[irq].level = 1
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#define GIC_CLEAR_LEVEL(irq) s->irq_state[irq].level = 0
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#define GIC_TEST_LEVEL(irq) s->irq_state[irq].level
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#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
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#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
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#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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typedef struct gic_state
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arm_pic_handler handler;
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gic_irq_state irq_state[GIC_NIRQ];
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int irq_target[GIC_NIRQ];
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int priority[GIC_NIRQ];
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int last_active[GIC_NIRQ];
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/* TODO: Many places that call this routine could be optimized. */
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/* Update interrupt status after enabled or pending bits have been changed. */
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static void gic_update(gic_state *s)
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s->current_pending = 1023;
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if (!s->enabled || !s->cpu_enabled) {
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pic_set_irq_new(s->parent, s->parent_irq, 0);
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for (irq = 0; irq < 96; irq++) {
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if (GIC_TEST_ENABLED(irq) && GIC_TEST_PENDING(irq)) {
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if (s->priority[irq] < best_prio) {
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best_prio = s->priority[irq];
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if (best_prio > s->priority_mask) {
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pic_set_irq_new(s->parent, s->parent_irq, 0);
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s->current_pending = best_irq;
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if (best_prio < s->running_priority) {
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DPRINTF("Raised pending IRQ %d\n", best_irq);
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pic_set_irq_new(s->parent, s->parent_irq, 1);
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static void gic_set_irq(void *opaque, int irq, int level)
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gic_state *s = (gic_state *)opaque;
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/* The first external input line is internal interrupt 32. */
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if (level == GIC_TEST_LEVEL(irq))
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if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
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DPRINTF("Set %d pending\n", irq);
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GIC_SET_PENDING(irq);
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GIC_CLEAR_LEVEL(irq);
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static void gic_set_running_irq(gic_state *s, int irq)
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s->running_irq = irq;
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s->running_priority = 0x100;
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s->running_priority = s->priority[irq];
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static uint32_t gic_acknowledge_irq(gic_state *s)
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new_irq = s->current_pending;
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if (new_irq == 1023 || s->priority[new_irq] >= s->running_priority) {
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DPRINTF("ACK no pending IRQ\n");
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pic_set_irq_new(s->parent, s->parent_irq, 0);
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s->last_active[new_irq] = s->running_irq;
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/* For level triggered interrupts we clear the pending bit while
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the interrupt is active. */
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GIC_CLEAR_PENDING(new_irq);
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gic_set_running_irq(s, new_irq);
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DPRINTF("ACK %d\n", new_irq);
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static void gic_complete_irq(gic_state * s, int irq)
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DPRINTF("EOI %d\n", irq);
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if (s->running_irq == 1023)
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return; /* No active IRQ. */
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/* Mark level triggered interrupts as pending if they are still
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if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq)
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&& GIC_TEST_LEVEL(irq)) {
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GIC_SET_PENDING(irq);
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if (irq != s->running_irq) {
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/* Complete an IRQ that is not currently running. */
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int tmp = s->running_irq;
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while (s->last_active[tmp] != 1023) {
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if (s->last_active[tmp] == irq) {
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s->last_active[tmp] = s->last_active[irq];
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tmp = s->last_active[tmp];
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/* Complete the current running IRQ. */
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gic_set_running_irq(s, s->last_active[s->running_irq]);
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static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
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gic_state *s = (gic_state *)opaque;
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offset -= s->base + 0x1000;
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if (offset < 0x100) {
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return (GIC_NIRQ / 32) - 1;
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} else if (offset < 0x200) {
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/* Interrupt Set/Clear Enable. */
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irq = (offset - 0x100) * 8;
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irq = (offset - 0x180) * 8;
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for (i = 0; i < 8; i++) {
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if (GIC_TEST_ENABLED(irq + i)) {
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} else if (offset < 0x300) {
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/* Interrupt Set/Clear Pending. */
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irq = (offset - 0x200) * 8;
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irq = (offset - 0x280) * 8;
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for (i = 0; i < 8; i++) {
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if (GIC_TEST_PENDING(irq + i)) {
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} else if (offset < 0x400) {
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/* Interrupt Active. */
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irq = (offset - 0x300) * 8;
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for (i = 0; i < 8; i++) {
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if (GIC_TEST_ACTIVE(irq + i)) {
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} else if (offset < 0x800) {
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/* Interrupt Priority. */
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irq = offset - 0x400;
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res = s->priority[irq];
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} else if (offset < 0xc00) {
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/* Interrupt CPU Target. */
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irq = offset - 0x800;
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res = s->irq_target[irq];
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} else if (offset < 0xf00) {
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/* Interrupt Configuration. */
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irq = (offset - 0xc00) * 2;
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for (i = 0; i < 4; i++) {
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if (GIC_TEST_MODEL(irq + i))
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res |= (1 << (i * 2));
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if (GIC_TEST_TRIGGER(irq + i))
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res |= (2 << (i * 2));
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} else if (offset < 0xfe0) {
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} else /* offset >= 0xfe0 */ {
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res = gic_id[(offset - 0xfe0) >> 2];
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cpu_abort (cpu_single_env, "gic_dist_readb: Bad offset %x\n", offset);
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static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
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val = gic_dist_readb(opaque, offset);
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val |= gic_dist_readb(opaque, offset + 1) << 8;
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static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
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val = gic_dist_readw(opaque, offset);
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val |= gic_dist_readw(opaque, offset + 2) << 16;
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static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
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gic_state *s = (gic_state *)opaque;
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offset -= s->base + 0x1000;
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if (offset < 0x100) {
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s->enabled = (value & 1);
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DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
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} else if (offset < 4) {
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} else if (offset < 0x180) {
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/* Interrupt Set Enable. */
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irq = (offset - 0x100) * 8;
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for (i = 0; i < 8; i++) {
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if (value & (1 << i)) {
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if (!GIC_TEST_ENABLED(irq + i))
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DPRINTF("Enabled IRQ %d\n", irq + i);
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GIC_SET_ENABLED(irq + i);
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/* If a raised level triggered IRQ enabled then mark
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if (GIC_TEST_LEVEL(irq + i) && !GIC_TEST_TRIGGER(irq + i))
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GIC_SET_PENDING(irq + i);
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} else if (offset < 0x200) {
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/* Interrupt Clear Enable. */
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irq = (offset - 0x180) * 8;
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for (i = 0; i < 8; i++) {
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if (value & (1 << i)) {
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if (GIC_TEST_ENABLED(irq + i))
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DPRINTF("Disabled IRQ %d\n", irq + i);
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GIC_CLEAR_ENABLED(irq + i);
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} else if (offset < 0x280) {
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/* Interrupt Set Pending. */
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irq = (offset - 0x200) * 8;
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for (i = 0; i < 8; i++) {
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if (value & (1 << i)) {
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GIC_SET_PENDING(irq + i);
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} else if (offset < 0x300) {
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/* Interrupt Clear Pending. */
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irq = (offset - 0x280) * 8;
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for (i = 0; i < 8; i++) {
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if (value & (1 << i)) {
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GIC_CLEAR_PENDING(irq + i);
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} else if (offset < 0x400) {
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/* Interrupt Active. */
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} else if (offset < 0x800) {
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/* Interrupt Priority. */
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irq = offset - 0x400;
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s->priority[irq] = value;
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} else if (offset < 0xc00) {
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/* Interrupt CPU Target. */
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irq = offset - 0x800;
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s->irq_target[irq] = value;
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} else if (offset < 0xf00) {
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/* Interrupt Configuration. */
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irq = (offset - 0xc00) * 4;
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for (i = 0; i < 4; i++) {
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if (value & (1 << (i * 2))) {
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GIC_SET_MODEL(irq + i);
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GIC_CLEAR_MODEL(irq + i);
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if (value & (2 << (i * 2))) {
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GIC_SET_TRIGGER(irq + i);
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GIC_CLEAR_TRIGGER(irq + i);
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/* 0xf00 is only handled for word writes. */
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cpu_abort (cpu_single_env, "gic_dist_writeb: Bad offset %x\n", offset);
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static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
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gic_state *s = (gic_state *)opaque;
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if (offset - s->base == 0xf00) {
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GIC_SET_PENDING(value & 0x3ff);
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gic_dist_writeb(opaque, offset, value & 0xff);
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gic_dist_writeb(opaque, offset + 1, value >> 8);
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static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
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gic_dist_writew(opaque, offset, value & 0xffff);
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gic_dist_writew(opaque, offset + 2, value >> 16);
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static CPUReadMemoryFunc *gic_dist_readfn[] = {
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static CPUWriteMemoryFunc *gic_dist_writefn[] = {
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static uint32_t gic_cpu_read(void *opaque, target_phys_addr_t offset)
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gic_state *s = (gic_state *)opaque;
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case 0x00: /* Control */
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return s->cpu_enabled;
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case 0x04: /* Priority mask */
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return s->priority_mask;
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case 0x08: /* Binary Point */
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/* ??? Not implemented. */
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case 0x0c: /* Acknowledge */
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return gic_acknowledge_irq(s);
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case 0x14: /* Runing Priority */
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return s->running_priority;
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case 0x18: /* Highest Pending Interrupt */
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return s->current_pending;
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cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
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static void gic_cpu_write(void *opaque, target_phys_addr_t offset,
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gic_state *s = (gic_state *)opaque;
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case 0x00: /* Control */
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s->cpu_enabled = (value & 1);
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DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis");
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case 0x04: /* Priority mask */
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s->priority_mask = (value & 0x3ff);
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case 0x08: /* Binary Point */
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/* ??? Not implemented. */
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case 0x10: /* End Of Interrupt */
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return gic_complete_irq(s, value & 0x3ff);
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cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
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static CPUReadMemoryFunc *gic_cpu_readfn[] = {
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static CPUWriteMemoryFunc *gic_cpu_writefn[] = {
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static void gic_reset(gic_state *s)
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memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
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s->priority_mask = 0xf0;
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s->current_pending = 1023;
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s->running_irq = 1023;
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s->running_priority = 0x100;
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for (i = 0; i < 15; i++) {
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void *arm_gic_init(uint32_t base, void *parent, int parent_irq)
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s = (gic_state *)qemu_mallocz(sizeof(gic_state));
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s->handler = gic_set_irq;
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s->parent_irq = parent_irq;
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if (base != 0xffffffff) {
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iomemtype = cpu_register_io_memory(0, gic_cpu_readfn,
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cpu_register_physical_memory(base, 0x00000fff, iomemtype);
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iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
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gic_dist_writefn, s);
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cpu_register_physical_memory(base + 0x1000, 0x00000fff, iomemtype);
added
removed
hw/arm_gic.c
