3796
3796
\begin{table}[htbp]
3798
\begin{tabular}{lcccccc}\toprule
3799
Scheme & $1$ & $2$ & $3$ & $4$ & $5$ & $6$ \\\cmidrule{2-7}
3800
Huffman Code & \multicolumn{6}{c}{Coding Mode} \\\midrule
3801
\bin{0} & $3$ & $3$ & $3$ & $3$ & $0$ & $0$ \\
3802
\bin{10} & $4$ & $4$ & $2$ & $2$ & $3$ & $5$ \\
3803
\bin{110} & $2$ & $0$ & $4$ & $0$ & $4$ & $3$ \\
3804
\bin{1110} & $0$ & $2$ & $0$ & $4$ & $2$ & $4$ \\
3805
\bin{11110} & $1$ & $1$ & $1$ & $1$ & $1$ & $2$ \\
3806
\bin{111110} & $5$ & $5$ & $5$ & $5$ & $5$ & $1$ \\
3807
\bin{1111110} & $6$ & $6$ & $6$ & $6$ & $6$ & $6$ \\
3808
\bin{1111111} & $7$ & $7$ & $7$ & $7$ & $7$ & $7$ \\
3798
\begin{tabular}{lccccccc}\toprule
3799
Scheme & $1$ & $2$ & $3$ & $4$ & $5$ & $6$ & $7$ \\\cmidrule{2-7}
3800
Huffman Code & \multicolumn{6}{c}{Coding Mode} & \locvar{\mi} \\\midrule
3801
\bin{0} & $3$ & $3$ & $3$ & $3$ & $0$ & $0$ & $0$ \\
3802
\bin{10} & $4$ & $4$ & $2$ & $2$ & $3$ & $5$ & $1$ \\
3803
\bin{110} & $2$ & $0$ & $4$ & $0$ & $4$ & $3$ & $2$ \\
3804
\bin{1110} & $0$ & $2$ & $0$ & $4$ & $2$ & $4$ & $3$ \\
3805
\bin{11110} & $1$ & $1$ & $1$ & $1$ & $1$ & $2$ & $4$ \\
3806
\bin{111110} & $5$ & $5$ & $5$ & $5$ & $5$ & $1$ & $5$ \\
3807
\bin{1111110} & $6$ & $6$ & $6$ & $6$ & $6$ & $6$ & $6$ \\
3808
\bin{1111111} & $7$ & $7$ & $7$ & $7$ & $7$ & $7$ & $7$ \\
3809
3809
\bottomrule\end{tabular}
3811
\caption{Coding Modes}
3811
\caption{Macro Block Mode Schemes}
3812
3812
\label{tab:mode-codes}
3856
3856
$\locvar{MALPHABET}[\locvar{\mi}]$, where \locvar{\mi} is the index of the
3857
3857
Huffman code decoded.
3859
Otherwise, if no luma-plane blocks in the macro block are coded, read a 3-bit
3860
unsigned integer as $\bitvar{MBMODES}[\locvar{\mbi}]$.
3859
Otherwise, read a 3-bit unsigned integer as $\bitvar{MBMODES}[\locvar{\mbi}]$.
3861
3860
\end{enumerate}
3863
Otherwise, assign $\bitvar{MBMODE}[\locvar{\mbi}]$ the value 0 (INTER\_NOMV).
3862
Otherwise, if no luma-plane blocks in the macro block are coded, assign
3863
$\bitvar{MBMODES}[\locvar{\mbi}]$ the value 0 (INTER\_NOMV).
3864
3864
\end{enumerate}
3865
3865
\end{enumerate}
3866
3866
\end{enumerate}
4138
4138
Thus, \locvar{A} is the index in coded order of the block in the lower left,
4139
4139
\locvar{B} the lower right, \locvar{C} the upper left, and \locvar{D} the
4140
4140
upper right. % TODO: as shown in Figure~REF.
4142
If $\bitvar{BCODED}[\locvar{A}]$ is non-zero, decode a single motion vector
4143
into \locvar{MVX} and \locvar{MVY} using the procedure described in
4144
Section~\ref{sub:mv-decode}.
4146
Otherwise, assign \locvar{MVX} and \locvar{MVY} both the value zero.
4148
Assign $\bitvar{MVECTS}[\locvar{A}]$ the value $(\locvar{MVX},\locvar{MVY})$.
4150
If $\bitvar{BCODED}[\locvar{B}]$ is non-zero, decode a single motion vector
4151
into \locvar{MVX} and \locvar{MVY} using the procedure described in
4152
Section~\ref{sub:mv-decode}.
4154
Otherwise, assign \locvar{MVX} and \locvar{MVY} both the value zero.
4156
Assign $\bitvar{MVECTS}[\locvar{B}]$ the value $(\locvar{MVX},\locvar{MVY})$.
4158
If $\bitvar{BCODED}[\locvar{C}]$ is non-zero, decode a single motion vector
4159
into \locvar{MVX} and \locvar{MVY} using the procedure described in
4160
Section~\ref{sub:mv-decode}.
4162
Otherwise, assign \locvar{MVX} and \locvar{MVY} both the value zero.
4164
Assign $\bitvar{MVECTS}[\locvar{C}]$ the value $(\locvar{MVX},\locvar{MVY})$.
4166
If $\bitvar{BCODED}[\locvar{D}]$ is non-zero, decode a single motion vector
4167
into \locvar{MVX} and \locvar{MVY} using the procedure described in
4168
Section~\ref{sub:mv-decode}.
4170
Otherwise, assign \locvar{MVX} and \locvar{MVY} both the value zero.
4172
Assign $\bitvar{MVECTS}[\locvar{D}]$ the value $(\locvar{MVX},\locvar{MVY})$.
4173
Note that \locvar{MVX} and \locvar{MVY} retain this last value.
4141
\item If $\bitvar{BCODED}[\locvar{A}]$ is non-zero:
4143
\item Decode a single motion vector into \locvar{MVX} and \locvar{MVY} using
4144
the procedure described in Section~\ref{sub:mv-decode}.
4145
\item Assign $\bitvar{MVECTS}[\locvar{A}]$ the value
4146
$(\locvar{MVX},\locvar{MVY})$.
4148
\item Otherwise, assign $\bitvar{MVECTS}[\locvar{A}]$ the value $(0,0)$.
4149
\item If $\bitvar{BCODED}[\locvar{B}]$ is non-zero:
4151
\item Decode a single motion vector into \locvar{MVX} and \locvar{MVY} using
4152
the procedure described in Section~\ref{sub:mv-decode}.
4153
\item Assign $\bitvar{MVECTS}[\locvar{B}]$ the value
4154
$(\locvar{MVX},\locvar{MVY})$.
4157
Otherwise assign $\bitvar{MVECTS}[\locvar{B}]$ the value $(0,0)$.
4158
\item If $\bitvar{BCODED}[\locvar{C}]$ is non-zero:
4160
\item Decode a single motion vector into \locvar{MVX} and \locvar{MVY} using
4161
the procedure described in Section~\ref{sub:mv-decode}.
4162
\item Assign $\bitvar{MVECTS}[\locvar{C}]$ the value
4163
$(\locvar{MVX},\locvar{MVY})$.
4165
\item Otherwise assign $\bitvar{MVECTS}[\locvar{C}]$ the value $(0,0)$.
4166
\item If $\bitvar{BCODED}[\locvar{D}]$ is non-zero:
4168
\item Decode a single motion vector into \locvar{MVX} and \locvar{MVY} using
4169
the procedure described in Section~\ref{sub:mv-decode}.
4170
\item Assign $\bitvar{MVECTS}[\locvar{D}]$ the value
4171
$(\locvar{MVX},\locvar{MVY})$.
4174
Otherwise, assign $\bitvar{MVECTS}[\locvar{D}]$ the value $(0,0)$.
4175
4176
If \bitvar{PF} is 0 (4:2:0):
4176
4177
\begin{enumerate}
4195
4196
If \bitvar{PF} is 2 (4:2:2):
4196
4197
\begin{enumerate}
4198
Let \locvar{E} and \locvar{F} be the indices in coded order of the top and
4199
bottom blocks in the macro block from the $C_b$ plane, respectively, and
4200
\locvar{G} and \locvar{H} be the indices in coded order of the top and bottom
4199
Let \locvar{E} and \locvar{F} be the indices in coded order of the bottom and
4200
top blocks in the macro block from the $C_b$ plane, respectively, and
4201
\locvar{G} and \locvar{H} be the indices in coded order of the bottom and top
4201
4202
blocks in the $C_r$ plane, respectively. %TODO: as shown in Figure~REF.
4203
4204
Assign $\bitvar{MVECTS}[\locvar{E}]$ and $\bitvar{MVECTS}[\locvar{G}]$ the
4205
4206
\begin{multline*}
4206
4207
(\round\left(\frac{
4207
\bitvar{MVECTS}[\locvar{A}]_x+\bitvar{MVECTS}[\locvar{B}]_x}{4}\right), \\
4208
\bitvar{MVECTS}[\locvar{A}]_x+\bitvar{MVECTS}[\locvar{B}]_x}{2}\right), \\
4208
4209
\round\left(\frac{
4209
\bitvar{MVECTS}[\locvar{A}]_y+\bitvar{MVECTS}[\locvar{B}]_y}{4}\right))
4210
\bitvar{MVECTS}[\locvar{A}]_y+\bitvar{MVECTS}[\locvar{B}]_y}{2}\right))
4210
4211
\end{multline*}
4212
4213
Assign $\bitvar{MVECTS}[\locvar{F}]$ and $\bitvar{MVECTS}[\locvar{H}]$ the
4214
4215
\begin{multline*}
4215
4216
(\round\left(\frac{
4216
\bitvar{MVECTS}[\locvar{C}]_x+\bitvar{MVECTS}[\locvar{D}]_x}{4}\right), \\
4217
\bitvar{MVECTS}[\locvar{C}]_x+\bitvar{MVECTS}[\locvar{D}]_x}{2}\right), \\
4217
4218
\round\left(\frac{
4218
\bitvar{MVECTS}[\locvar{C}]_y+\bitvar{MVECTS}[\locvar{D}]_y}{4}\right))
4219
\bitvar{MVECTS}[\locvar{C}]_y+\bitvar{MVECTS}[\locvar{D}]_y}{2}\right))
4219
4220
\end{multline*}
4220
4221
\end{enumerate}
6207
6212
All intermediate values are truncated to a 32-bit signed representation by
6208
6213
discarding any higher-order bits in their two's complement representation.
6209
The final output of each 1D transform is truncated to 16-bits in the same
6214
The final output of each 1D transform is truncated to a 16-bit signed value in
6211
6216
In practice, if the high word of a $16\times 16$ bit multiplication can be
6212
6217
obtained directly, 16 bits is sufficient for every calculation except scaling
6214
Here we specify truncating to 16 bits before the multiplication to simplify
6215
implementations using hardware or common SIMD instruction sets.
6219
Thus we truncate to 16 bits before that multiplication to allow an
6220
implementation entirely in 16-bit registers.
6221
Implementations using larger registers must sign-extend the 16-bit value to
6222
maintain compatibility.
6217
6224
Note that if 16-bit register are used, overflow in the additions and
6218
6225
subtractions should be handled using \textit{unsaturated} arithmetic.
6407
6414
Assign \locvar{R} the value $\locvar{T}[0]+\locvar{T}[7]$.
6409
Truncate \locvar{R} to a 16-bit representation by dropping any higher-order
6416
Truncate \locvar{R} to a 16-bit signed representation by dropping any
6412
6419
Assign $\bitvar{X}[0]$ the value \locvar{R}.
6414
6421
Assign \locvar{R} the value $\locvar{T}[1]+\locvar{T}[6]$.
6416
Truncate \locvar{R} to a 16-bit representation by dropping any higher-order
6423
Truncate \locvar{R} to a 16-bit signed representation by dropping any
6419
6426
Assign $\bitvar{X}[1]$ the value \locvar{R}.
6421
6428
Assign \locvar{R} the value $\locvar{T}[2]+\locvar{T}[5]$.
6423
Truncate \locvar{R} to a 16-bit representation by dropping any higher-order
6430
Truncate \locvar{R} to a 16-bit signed representation by dropping any
6426
6433
Assign $\bitvar{X}[2]$ the value \locvar{R}.
6428
6435
Assign \locvar{R} the value $\locvar{T}[3]+\locvar{T}[4]$.
6430
Truncate \locvar{R} to a 16-bit representation by dropping any higher-order
6437
Truncate \locvar{R} to a 16-bit signed representation by dropping any
6433
6440
Assign $\bitvar{X}[3]$ the value \locvar{R}.
6435
6442
Assign \locvar{R} the value $\locvar{T}[3]-\locvar{T}[4]$.
6437
Truncate \locvar{R} to a 16-bit representation by dropping any higher-order
6444
Truncate \locvar{R} to a 16-bit signed representation by dropping any
6440
6447
Assign $\bitvar{X}[4]$ the value \locvar{R}.
6442
6449
Assign \locvar{R} the value $\locvar{T}[2]-\locvar{T}[5]$.
6444
Truncate \locvar{R} to a 16-bit representation by dropping any higher-order
6451
Truncate \locvar{R} to a 16-bit signed representation by dropping any
6447
6454
Assign $\bitvar{X}[5]$ the value \locvar{R}.
6449
Assign \locvar{X} the value $\locvar{T}[1]-\locvar{T}[6]$.
6456
Assign \locvar{R} the value $\locvar{T}[1]-\locvar{T}[6]$.
6451
Truncate \locvar{R} to a 16-bit representation by dropping any higher-order
6458
Truncate \locvar{R} to a 16-bit signed representation by dropping any
6454
6461
Assign $\bitvar{X}[6]$ the value \locvar{R}.
6456
6463
Assign \locvar{R} the value $\locvar{T}[0]-\locvar{T}[7]$.
6458
Truncate \locvar{R} to a 16-bit representation by dropping any higher-order
6465
Truncate \locvar{R} to a 16-bit signed representation by dropping any
6461
6468
Assign $\bitvar{X}[7]$ the value \locvar{R}.
6462
6469
\end{enumerate}
added
removed
doc/spec/spec.tex
