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<!-- HEADER 9-4-4: Special Spice and Verilog Nodes -->
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<!-- COMMAND Tool/Simulation (Spice)/Set Generic Spice Template -->
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<!-- COMMAND Tool/Simulation (Spice)/Set Spice 2 Template -->
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<!-- COMMAND Tool/Simulation (Spice)/Set Spice 3 Template -->
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<!-- COMMAND Tool/Simulation (Spice)/Set HSpice Template -->
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<!-- COMMAND Tool/Simulation (Spice)/Set PSpice Template -->
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<!-- COMMAND Tool/Simulation (Spice)/Set GnuCap Template -->
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<!-- COMMAND Tool/Simulation (Spice)/Set SmartSpice Template -->
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<!-- COMMAND Tool/Simulation (Spice)/Set Assura CDL Template -->
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<!-- COMMAND Tool/Simulation (Spice)/Set Calibre Spice Template -->
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<!-- COMMAND Tool/Simulation (Verilog)/Set Verilog Template -->
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<!-- COMMAND Tools/Simulation (Spice)/Set Generic Spice Template -->
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<!-- COMMAND Tools/Simulation (Spice)/Set Spice 2 Template -->
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<!-- COMMAND Tools/Simulation (Spice)/Set Spice 3 Template -->
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<!-- COMMAND Tools/Simulation (Spice)/Set HSpice Template -->
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<!-- COMMAND Tools/Simulation (Spice)/Set PSpice Template -->
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<!-- COMMAND Tools/Simulation (Spice)/Set GnuCap Template -->
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<!-- COMMAND Tools/Simulation (Spice)/Set SmartSpice Template -->
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<!-- COMMAND Tools/Simulation (Spice)/Set Assura CDL Template -->
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<!-- COMMAND Tools/Simulation (Spice)/Set Calibre Spice Template -->
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<!-- COMMAND Tools/Simulation (Verilog)/Set Verilog Template -->
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<!-- COMMAND Tools/Simulation (Verilog)/Set Verilog Default Parameter -->
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For both Spice and Verilog, you can place special nodes in your circuit that augment the generated deck.
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Spice even has a predefined set of these nodes, available from the "Spice" entry in the component menu.
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Parameters are created with the <B>Cell Parameters...</B> command (in menu <B>Edit / Properties</B>).
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See <A HREF="chap06-08-05.html#chap06-08-05">Section 6-8-5</A> for more on parameters.</LI>
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<LI>At least one template. The template is the essential part of the Node because it describes exactly what Spice or Verilog will be emitted.
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The Spice template is created with the <B>Set Generic Spice Template</B> command (in menu <B>Tool / Simulation (Spice)</B>).
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The Spice template is created with the <B>Set Generic Spice Template</B> command (in menu <B>Tools / Simulation (Spice)</B>).
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If the template is specific to a particular version of Spice, use the appropriate template command
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(<B>Set Spice 2 Template</B>, <B>Set Spice 3 Template</B>, <B>Set HSpice Template</B>, <B>Set PSpice Template</B>,
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<B>Set GnuCap Template</B>, <B>Set SmartSpice Template</B>, <B>Set Assura CDL Template</B>, or
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<B>Set Calibre Spice Template</B>).
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You can also create a Verilog template by using the <B>Set Verilog Template</B> command (in menu <B>Tool / Simulation (Verilog)</B>).
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Note that a single cell can contain both Verilog and multiple Spice templates.
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You can also create a Verilog template by using the <B>Set Verilog Template</B> command (in menu <B>Tools / Simulation (Verilog)</B>).
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And can customize instances of the current cell (by prepending per-instance parameters)
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with <B>Set Verilog Default Parameter</B>.
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Note that a single cell can contain both Verilog and Spice templates.
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Once a template has been created, double-click on the text to edit it.</LI>
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