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- Committer: Bazaar Package Importer
- Author(s): Chris Lamb
- Date: 2008-07-06 20:26:53 UTC
- Revision ID: james.westby@ubuntu.com-20080706202653-e99oiii765j3a0qn
Tags: upstream-0.0.10~git+20080706+b1f3169
Import upstream version 0.0.10~git+20080706+b1f3169
- files added:
- man
- src
added
removed
src/nv_type.h
1
#ifndef __NV_STRUCT_H__
2
#define __NV_STRUCT_H__
3
4
#include "colormapst.h"
5
#include "vgaHW.h"
6
#include "xf86Cursor.h"
7
#include "xf86int10.h"
8
#include "exa.h"
9
#ifdef XF86DRI
10
#define _XF86DRI_SERVER_
11
#include "xf86drm.h"
12
#include "dri.h"
13
#include <stdbool.h>
14
#include <stdint.h>
15
#include "nouveau_drm.h"
16
#include "xf86Crtc.h"
17
#else
18
#error "This driver requires a DRI-enabled X server"
19
#endif
20
21
#include "nv_pcicompat.h"
22
23
#include "nouveau_local.h" /* needed for NOUVEAU_EXA_PIXMAPS */
24
25
#include "nouveau_crtc.h"
26
#include "nouveau_connector.h"
27
#include "nouveau_output.h"
28
29
#include "drmmode_display.h"
30
31
#define NV_ARCH_03 0x03
32
#define NV_ARCH_04 0x04
33
#define NV_ARCH_10 0x10
34
#define NV_ARCH_20 0x20
35
#define NV_ARCH_30 0x30
36
#define NV_ARCH_40 0x40
37
#define NV_ARCH_50 0x50
38
39
#define CHIPSET_NV03 0x0010
40
#define CHIPSET_NV04 0x0020
41
#define CHIPSET_NV10 0x0100
42
#define CHIPSET_NV11 0x0110
43
#define CHIPSET_NV15 0x0150
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#define CHIPSET_NV17 0x0170
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#define CHIPSET_NV18 0x0180
46
#define CHIPSET_NFORCE 0x01A0
47
#define CHIPSET_NFORCE2 0x01F0
48
#define CHIPSET_NV20 0x0200
49
#define CHIPSET_NV25 0x0250
50
#define CHIPSET_NV28 0x0280
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#define CHIPSET_NV30 0x0300
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#define CHIPSET_NV31 0x0310
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#define CHIPSET_NV34 0x0320
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#define CHIPSET_NV35 0x0330
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#define CHIPSET_NV36 0x0340
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#define CHIPSET_NV40 0x0040
57
#define CHIPSET_NV41 0x00C0
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#define CHIPSET_NV43 0x0140
59
#define CHIPSET_NV44 0x0160
60
#define CHIPSET_NV44A 0x0220
61
#define CHIPSET_NV45 0x0210
62
#define CHIPSET_NV50 0x0190
63
#define CHIPSET_NV84 0x0400
64
#define CHIPSET_MISC_BRIDGED 0x00F0
65
#define CHIPSET_G70 0x0090
66
#define CHIPSET_G71 0x0290
67
#define CHIPSET_G72 0x01D0
68
#define CHIPSET_G73 0x0390
69
// integrated GeForces (6100, 6150)
70
#define CHIPSET_C51 0x0240
71
// variant of C51, seems based on a G70 design
72
#define CHIPSET_C512 0x03D0
73
#define CHIPSET_G73_BRIDGED 0x02E0
74
75
76
#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
77
#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
78
#define SetBF(mask,value) ((value) << (0?mask))
79
#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
80
#define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
81
#define SetBit(n) (1<<(n))
82
#define Set8Bits(value) ((value)&0xff)
83
84
#define MAX_NUM_DCB_ENTRIES 16
85
86
#define LOC_ON_CHIP 0
87
88
struct dcb_entry {
89
int index;
90
uint8_t type;
91
uint8_t i2c_index;
92
uint8_t heads;
93
uint8_t bus;
94
uint8_t location;
95
uint8_t or;
96
bool duallink_possible;
97
union {
98
struct {
99
bool use_straps_for_mode;
100
bool use_power_scripts;
101
} lvdsconf;
102
};
103
};
104
105
typedef enum
106
{/* matches DCB types */
107
OUTPUT_NONE = 4,
108
OUTPUT_ANALOG = 0,
109
OUTPUT_TMDS = 2,
110
OUTPUT_LVDS = 3,
111
OUTPUT_TV = 1,
112
} NVOutputType;
113
114
/* NV50 */
115
typedef enum Head {
116
HEAD0 = 0,
117
HEAD1
118
} Head;
119
120
/* NV50 */
121
typedef enum ORNum {
122
DAC0 = 0,
123
DAC1 = 1,
124
DAC2 = 2,
125
SOR0 = 0,
126
SOR1 = 1
127
} ORNum;
128
129
enum scaling_modes {
130
SCALE_PANEL,
131
SCALE_FULLSCREEN,
132
SCALE_ASPECT,
133
SCALE_NOSCALE,
134
SCALE_INVALID
135
};
136
137
typedef struct _nv_crtc_reg
138
{
139
unsigned char MiscOutReg; /* */
140
uint8_t CRTC[0xff];
141
uint8_t CR58[0x10];
142
uint8_t Sequencer[5];
143
uint8_t Graphics[9];
144
uint8_t Attribute[21];
145
unsigned char DAC[768]; /* Internal Colorlookuptable */
146
uint32_t cursorConfig;
147
uint32_t crtcOwner;
148
uint32_t gpio;
149
uint32_t gpio_ext;
150
uint32_t unk830;
151
uint32_t unk834;
152
uint32_t unk850;
153
uint32_t head;
154
uint32_t config;
155
uint32_t fb_start;
156
157
/* These are former output regs, but are believed to be crtc related */
158
uint32_t general;
159
uint32_t debug_0;
160
uint32_t debug_1;
161
uint32_t debug_2;
162
uint32_t unk_a20;
163
uint32_t unk_a24;
164
uint32_t unk_a34;
165
uint32_t dither_regs[6];
166
uint32_t fp_horiz_regs[7];
167
uint32_t fp_vert_regs[7];
168
uint32_t nv10_cursync;
169
uint32_t fp_control;
170
uint32_t dither;
171
bool vpll_changed;
172
uint32_t vpll_a;
173
uint32_t vpll_b;
174
} NVCrtcRegRec, *NVCrtcRegPtr;
175
176
typedef struct _nv_output_reg
177
{
178
uint32_t output;
179
int head;
180
} NVOutputRegRec, *NVOutputRegPtr;
181
182
typedef struct _riva_hw_state
183
{
184
uint32_t bpp;
185
uint32_t width;
186
uint32_t height;
187
uint32_t interlace;
188
uint32_t repaint0;
189
uint32_t repaint1;
190
uint32_t screen;
191
uint32_t scale;
192
uint32_t dither;
193
uint32_t extra;
194
uint32_t fifo;
195
uint32_t pixel;
196
uint32_t horiz;
197
uint32_t arbitration0;
198
uint32_t arbitration1;
199
uint32_t pll;
200
uint32_t pllB;
201
uint32_t vpll;
202
uint32_t vpll2;
203
uint32_t vpllB;
204
uint32_t vpll2B;
205
uint32_t pllsel;
206
uint32_t sel_clk;
207
uint32_t reg580;
208
uint32_t general;
209
uint32_t crtcOwner;
210
uint32_t head;
211
uint32_t head2;
212
uint32_t cursorConfig;
213
uint32_t cursor0;
214
uint32_t cursor1;
215
uint32_t cursor2;
216
uint32_t timingH;
217
uint32_t timingV;
218
uint32_t displayV;
219
uint32_t crtcSync;
220
221
NVCrtcRegRec crtc_reg[2];
222
} RIVA_HW_STATE, *NVRegPtr;
223
224
typedef struct _NVCrtcPrivateRec {
225
int head;
226
uint8_t last_dpms;
227
#if NOUVEAU_EXA_PIXMAPS
228
struct nouveau_bo *shadow;
229
#else
230
ExaOffscreenArea *shadow;
231
#endif /* NOUVEAU_EXA_PIXMAPS */
232
int fp_users;
233
} NVCrtcPrivateRec, *NVCrtcPrivatePtr;
234
235
typedef enum {
236
OUTPUT_A = (1 << 0),
237
OUTPUT_B = (1 << 1),
238
OUTPUT_C = (1 << 2)
239
} ValidOutputResource;
240
241
typedef struct _NVOutputPrivateRec {
242
uint8_t last_dpms; /* pre-NV50 */
243
I2CBusPtr pDDCBus;
244
NVOutputType type;
245
struct dcb_entry *dcb;
246
uint32_t fpWidth;
247
uint32_t fpHeight;
248
DisplayModePtr native_mode;
249
uint8_t scaling_mode;
250
bool dithering;
251
NVOutputRegRec restore;
252
} NVOutputPrivateRec, *NVOutputPrivatePtr;
253
254
/* changing these requires matching changes to reg tables in nv_get_clock */
255
#define MAX_PLL_TYPES 4
256
enum pll_types {
257
NVPLL,
258
MPLL,
259
VPLL1,
260
VPLL2
261
};
262
263
struct pll_lims {
264
struct {
265
int minfreq;
266
int maxfreq;
267
int min_inputfreq;
268
int max_inputfreq;
269
270
uint8_t min_m;
271
uint8_t max_m;
272
uint8_t min_n;
273
uint8_t max_n;
274
} vco1, vco2;
275
276
uint8_t unk1c;
277
uint8_t max_log2p_bias;
278
uint8_t log2p_bias;
279
int refclk;
280
};
281
282
typedef struct {
283
uint8_t *data;
284
unsigned int length;
285
bool execute;
286
287
uint8_t major_version, chip_version;
288
uint8_t feature_byte;
289
290
uint32_t fmaxvco, fminvco;
291
292
uint32_t dactestval;
293
294
uint16_t init_script_tbls_ptr;
295
uint16_t extra_init_script_tbl_ptr;
296
uint16_t macro_index_tbl_ptr;
297
uint16_t macro_tbl_ptr;
298
uint16_t condition_tbl_ptr;
299
uint16_t io_condition_tbl_ptr;
300
uint16_t io_flag_condition_tbl_ptr;
301
uint16_t init_function_tbl_ptr;
302
303
uint16_t pll_limit_tbl_ptr;
304
uint16_t ram_restrict_tbl_ptr;
305
306
struct {
307
DisplayModePtr native_mode;
308
uint8_t *edid;
309
uint16_t lvdsmanufacturerpointer;
310
uint16_t xlated_entry;
311
bool power_off_for_reset;
312
bool reset_after_pclk_change;
313
bool dual_link;
314
bool link_c_increment;
315
bool if_is_24bit;
316
bool BITbit1;
317
int duallink_transition_clk;
318
/* lower nibble stores PEXTDEV_BOOT_0 strap
319
* upper nibble stores xlated display strap */
320
uint8_t strapping;
321
} fp;
322
323
struct {
324
uint16_t output0_script_ptr;
325
uint16_t output1_script_ptr;
326
} tmds;
327
328
struct {
329
uint16_t mem_init_tbl_ptr;
330
uint16_t sdr_seq_tbl_ptr;
331
uint16_t ddr_seq_tbl_ptr;
332
333
struct {
334
uint8_t crt, tv, panel;
335
} i2c_indices;
336
} legacy;
337
} bios_t;
338
339
enum LVDS_script {
340
/* Order *does* matter here */
341
LVDS_INIT = 1,
342
LVDS_RESET,
343
LVDS_BACKLIGHT_ON,
344
LVDS_BACKLIGHT_OFF,
345
LVDS_PANEL_ON,
346
LVDS_PANEL_OFF
347
};
348
349
typedef struct {
350
Bool vga_mode;
351
uint8_t depth; /* mode related */
352
uint8_t bpp; /* pitch related */
353
uint16_t x_res;
354
uint16_t y_res;
355
Bool enabled;
356
uint32_t fb_start;
357
} NVConsoleMode;
358
359
typedef struct _NVRec *NVPtr;
360
typedef struct _NVRec {
361
RIVA_HW_STATE SavedReg;
362
RIVA_HW_STATE ModeReg;
363
uint32_t saved_vga_font[4][16384];
364
uint32_t Architecture;
365
EntityInfoPtr pEnt;
366
#ifndef XSERVER_LIBPCIACCESS
367
pciVideoPtr PciInfo;
368
PCITAG PciTag;
369
#else
370
struct pci_device *PciInfo;
371
#endif /* XSERVER_LIBPCIACCESS */
372
int Chipset;
373
int NVArch;
374
Bool Primary;
375
CARD32 IOAddress;
376
377
/* VRAM physical address */
378
unsigned long VRAMPhysical;
379
/* Size of VRAM BAR */
380
unsigned long VRAMPhysicalSize;
381
/* Accesible VRAM size (by the GPU) */
382
unsigned long VRAMSize;
383
/* Accessible AGP size */
384
unsigned long AGPSize;
385
386
/* Various pinned memory regions */
387
struct nouveau_bo * FB;
388
//struct nouveau_bo * FB_old; /* for KMS */
389
struct nouveau_bo * shadow[2]; /* for easy acces by exa */
390
struct nouveau_bo * Cursor;
391
struct nouveau_bo * Cursor2;
392
struct nouveau_bo * CLUT0; /* NV50 only */
393
struct nouveau_bo * CLUT1; /* NV50 only */
394
struct nouveau_bo * GART;
395
396
bios_t VBIOS;
397
Bool NoAccel;
398
Bool HWCursor;
399
Bool FpScale;
400
Bool ShadowFB;
401
unsigned char * ShadowPtr;
402
int ShadowPitch;
403
CARD32 MinVClockFreqKHz;
404
CARD32 MaxVClockFreqKHz;
405
CARD32 CrystalFreqKHz;
406
CARD32 RamAmountKBytes;
407
408
volatile CARD32 *REGS;
409
volatile CARD32 *FB_BAR;
410
volatile CARD32 *PGRAPH;
411
volatile CARD32 *PRAMIN;
412
volatile CARD32 *CURSOR;
413
volatile CARD8 *PCIO0;
414
volatile CARD8 *PCIO1;
415
volatile CARD8 *PVIO0;
416
volatile CARD8 *PVIO1;
417
volatile CARD8 *PDIO0;
418
volatile CARD8 *PDIO1;
419
420
unsigned int SaveGeneration;
421
uint8_t cur_head;
422
ExaDriverPtr EXADriverPtr;
423
xf86CursorInfoPtr CursorInfoRec;
424
void (*PointerMoved)(int index, int x, int y);
425
ScreenBlockHandlerProcPtr BlockHandler;
426
CloseScreenProcPtr CloseScreen;
427
int Rotate;
428
/* Cursor */
429
CARD32 curFg, curBg;
430
CARD32 curImage[256];
431
/* I2C / DDC */
432
xf86Int10InfoPtr pInt10;
433
unsigned Int10Mode;
434
I2CBusPtr I2C;
435
void (*VideoTimerCallback)(ScrnInfoPtr, Time);
436
XF86VideoAdaptorPtr overlayAdaptor;
437
XF86VideoAdaptorPtr blitAdaptor;
438
XF86VideoAdaptorPtr textureAdaptor[2];
439
int videoKey;
440
int FlatPanel;
441
Bool FPDither;
442
int Mobile;
443
Bool Television;
444
int vtOWNER;
445
Bool crtc_active[2];
446
OptionInfoPtr Options;
447
Bool alphaCursor;
448
unsigned char DDCBase;
449
Bool twoHeads;
450
Bool twoStagePLL;
451
Bool fpScaler;
452
int fpWidth;
453
int fpHeight;
454
CARD32 fpSyncs;
455
Bool usePanelTweak;
456
int PanelTweak;
457
Bool LVDS;
458
459
Bool LockedUp;
460
461
CARD32 currentRop;
462
463
Bool WaitVSyncPossible;
464
Bool BlendingPossible;
465
Bool RandRRotation;
466
DRIInfoPtr pDRIInfo;
467
drmVersionPtr pLibDRMVersion;
468
drmVersionPtr pKernelDRMVersion;
469
470
Bool randr12_enable;
471
Bool kms_enable;
472
Bool new_restore;
473
474
I2CBusPtr pI2CBus[MAX_NUM_DCB_ENTRIES];
475
476
#ifdef XF86DRM_MODE
477
void *drmmode; /* for KMS */
478
#endif
479
480
struct {
481
int entries;
482
struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
483
unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
484
unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
485
} dcb_table;
486
487
NVConsoleMode console_mode[2];
488
489
nouveauCrtcPtr crtc[2];
490
nouveauOutputPtr output; /* this a linked list. */
491
/* Assume a connector can exist for each i2c bus. */
492
nouveauConnectorPtr connector[MAX_NUM_DCB_ENTRIES];
493
494
struct {
495
ORNum dac;
496
ORNum sor;
497
} i2cMap[4];
498
struct {
499
Bool present;
500
ORNum or;
501
} lvds;
502
503
/* DRM interface */
504
struct nouveau_device *dev;
505
506
/* GPU context */
507
struct nouveau_channel *chan;
508
struct nouveau_notifier *notify0;
509
struct nouveau_grobj *NvNull;
510
struct nouveau_grobj *NvContextSurfaces;
511
struct nouveau_grobj *NvContextBeta1;
512
struct nouveau_grobj *NvContextBeta4;
513
struct nouveau_grobj *NvImagePattern;
514
struct nouveau_grobj *NvRop;
515
struct nouveau_grobj *NvRectangle;
516
struct nouveau_grobj *NvImageBlit;
517
struct nouveau_grobj *NvScaledImage;
518
struct nouveau_grobj *NvClipRectangle;
519
struct nouveau_grobj *NvMemFormat;
520
struct nouveau_grobj *NvImageFromCpu;
521
struct nouveau_grobj *Nv2D;
522
struct nouveau_grobj *Nv3D;
523
524
} NVRec;
525
526
#define NVPTR(p) ((NVPtr)((p)->driverPrivate))
527
528
#define NVShowHideCursor(pScrn, show) do { \
529
NVPtr pNv = NVPTR(pScrn); \
530
nv_crtc_show_hide_cursor(pScrn, pNv->cur_head, show); \
531
} while(0)
532
533
#define NVLockUnlock(pScrn, lock) NVLockVgaCrtc(NVPTR(pScrn), NVPTR(pScrn)->cur_head, lock)
534
535
#define nvReadCurVGA(pNv, reg) NVReadVgaCrtc(pNv, pNv->cur_head, reg)
536
#define nvWriteCurVGA(pNv, reg, val) NVWriteVgaCrtc(pNv, pNv->cur_head, reg, val)
537
538
#define nvReadCurRAMDAC(pNv, reg) NVReadRAMDAC(pNv, pNv->cur_head, reg)
539
#define nvWriteCurRAMDAC(pNv, reg, val) NVWriteRAMDAC(pNv, pNv->cur_head, reg, val)
540
541
#define nvReadCurCRTC(pNv, reg) NVReadCRTC(pNv, pNv->cur_head, reg)
542
#define nvWriteCurCRTC(pNv, reg, val) NVWriteCRTC(pNv, pNv->cur_head, reg, val)
543
544
#define nvReadFB(pNv, reg) DDXMMIOW("nvReadFB: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
545
#define nvWriteFB(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteFB: reg %08x val %08x\n", reg, val))
546
547
#define nvReadGRAPH(pNv, reg) DDXMMIOW("nvReadGRAPH: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
548
#define nvWriteGRAPH(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteGRAPH: reg %08x val %08x\n", reg, val))
549
550
#define nvReadMC(pNv, reg) DDXMMIOW("nvReadMC: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
551
#define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteMC: reg %08x val %08x\n", reg, val))
552
553
#define nvReadME(pNv, reg) DDXMMIOW("nvReadME: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
554
#define nvWriteME(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteME: reg %08x val %08x\n", reg, val))
555
556
#define nvReadEXTDEV(pNv, reg) DDXMMIOW("nvReadEXTDEV: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
557
#define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteEXTDEV: reg %08x val %08x\n", reg, val))
558
559
#define nvReadTIMER(pNv, reg) DDXMMIOW("nvReadTIMER: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
560
#define nvWriteTIMER(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteTIMER: reg %08x val %08x\n", reg, val))
561
562
#define nvReadVIDEO(pNv, reg) DDXMMIOW("nvReadVIDEO: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
563
#define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteVIDEO: reg %08x val %08x\n", reg, val))
564
565
typedef struct _NVPortPrivRec {
566
short brightness;
567
short contrast;
568
short saturation;
569
short hue;
570
RegionRec clip;
571
CARD32 colorKey;
572
Bool autopaintColorKey;
573
Bool doubleBuffer;
574
CARD32 videoStatus;
575
int currentBuffer;
576
Time videoTime;
577
int overlayCRTC;
578
Bool grabbedByV4L;
579
Bool iturbt_709;
580
Bool blitter;
581
Bool texture;
582
Bool bicubic; /* only for texture adapter */
583
Bool SyncToVBlank;
584
struct nouveau_bo *video_mem;
585
int pitch;
586
int offset;
587
struct nouveau_bo *TT_mem_chunk[2];
588
int currentHostBuffer;
589
struct nouveau_notifier *DMANotifier[2];
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} NVPortPrivRec, *NVPortPrivPtr;
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#define GET_OVERLAY_PRIVATE(pNv) \
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(NVPortPrivPtr)((pNv)->overlayAdaptor->pPortPrivates[0].ptr)
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#define GET_BLIT_PRIVATE(pNv) \
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(NVPortPrivPtr)((pNv)->blitAdaptor->pPortPrivates[0].ptr)
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#define OFF_TIMER 0x01
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#define FREE_TIMER 0x02
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#define CLIENT_VIDEO_ON 0x04
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#define OFF_DELAY 500 /* milliseconds */
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#define FREE_DELAY 5000
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#define TIMER_MASK (OFF_TIMER | FREE_TIMER)
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#endif /* __NV_STRUCT_H__ */
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