1
2009-12-13 H.J. Lu <hongjiu.lu@intel.com>
3
* sysdeps/i386/i686/multiarch/strcspn.S Include <init-arch.h>
4
instead of <ifunc-defines.h>. Use bit_XXX and index_XXX to
5
check processor feature.
6
* sysdeps/i386/i686/multiarch/strlen.S: Likewise.
7
* sysdeps/i386/i686/multiarch/strspn.S: Likewise.
9
* sysdeps/x86_64/multiarch/init-arch.h (bit_SSE2): New.
10
(index_SSE2): Likewise.
12
diff --git a/sysdeps/i386/i686/multiarch/strcspn.S b/sysdeps/i386/i686/multiarch/strcspn.S
13
index 73e7eb4..b2310e4 100644
14
--- a/sysdeps/i386/i686/multiarch/strcspn.S
15
+++ b/sysdeps/i386/i686/multiarch/strcspn.S
17
#ifdef HAVE_SSE4_SUPPORT
20
-#include <ifunc-defines.h>
21
+#include <init-arch.h>
24
#define STRCSPN_SSE42 __strpbrk_sse42
25
@@ -64,7 +64,7 @@ ENTRY(STRCSPN)
27
call __init_cpu_features
28
1: leal STRCSPN_IA32@GOTOFF(%ebx), %eax
29
- testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features@GOTOFF(%ebx)
30
+ testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
32
leal STRCSPN_SSE42@GOTOFF(%ebx), %eax
34
@@ -80,7 +80,7 @@ ENTRY(STRCSPN)
36
call __init_cpu_features
37
1: leal STRCSPN_IA32, %eax
38
- testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features
39
+ testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
41
leal STRCSPN_SSE42, %eax
43
diff --git a/sysdeps/i386/i686/multiarch/strlen.S b/sysdeps/i386/i686/multiarch/strlen.S
44
index 0c1e864..9786add 100644
45
--- a/sysdeps/i386/i686/multiarch/strlen.S
46
+++ b/sysdeps/i386/i686/multiarch/strlen.S
51
-#include <ifunc-defines.h>
52
+#include <init-arch.h>
54
/* Define multiple versions only for the definition in libc and for the
55
DSO. In static binaries, we need strlen before the initialization
56
@@ -46,7 +46,7 @@ ENTRY(strlen)
58
call __init_cpu_features
59
1: leal __strlen_ia32@GOTOFF(%ebx), %eax
60
- testl $(1<<26), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET+__cpu_features@GOTOFF(%ebx)
61
+ testl $bit_SSE2, CPUID_OFFSET+index_SSE2+__cpu_features@GOTOFF(%ebx)
63
leal __strlen_sse2@GOTOFF(%ebx), %eax
65
diff --git a/sysdeps/i386/i686/multiarch/strspn.S b/sysdeps/i386/i686/multiarch/strspn.S
66
index f306d2d..7fe6f97 100644
67
--- a/sysdeps/i386/i686/multiarch/strspn.S
68
+++ b/sysdeps/i386/i686/multiarch/strspn.S
70
#ifdef HAVE_SSE4_SUPPORT
73
-#include <ifunc-defines.h>
74
+#include <init-arch.h>
76
/* Define multiple versions only for the definition in libc. */
78
@@ -49,7 +49,7 @@ ENTRY(strspn)
80
call __init_cpu_features
81
1: leal __strspn_ia32@GOTOFF(%ebx), %eax
82
- testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features@GOTOFF(%ebx)
83
+ testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
85
leal __strspn_sse42@GOTOFF(%ebx), %eax
87
@@ -65,7 +65,7 @@ ENTRY(strspn)
89
call __init_cpu_features
90
1: leal __strspn_ia32, %eax
91
- testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features
92
+ testl $index_SSE2, CPUID_OFFSET+index_SSE4_2+__cpu_features
94
leal __strspn_sse42, %eax
96
diff --git a/sysdeps/x86_64/multiarch/init-arch.h b/sysdeps/x86_64/multiarch/init-arch.h
97
index 9e8915f..0f8f77a 100644
98
--- a/sysdeps/x86_64/multiarch/init-arch.h
99
+++ b/sysdeps/x86_64/multiarch/init-arch.h
102
#include <ifunc-defines.h>
104
+#define bit_SSE2 (1 << 26)
105
#define bit_SSSE3 (1 << 9)
106
#define bit_SSE4_2 (1 << 20)
108
+#define index_SSE2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
109
#define index_SSSE3 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
110
#define index_SSE4_2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET