45
45
void rs600_gpu_init(struct radeon_device *rdev);
46
46
int rs600_mc_wait_for_idle(struct radeon_device *rdev);
48
int rs600_mc_init(struct radeon_device *rdev)
50
/* read back the MC value from the hw */
54
/* Setup GPU memory space */
55
tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
56
rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
57
rdev->mc.gtt_location = 0xffffffffUL;
58
r = radeon_mc_setup(rdev);
59
rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
65
/* hpd for digital panel detect/disconnect */
66
bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
69
bool connected = false;
73
tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
74
if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
78
tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
79
if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
88
void rs600_hpd_set_polarity(struct radeon_device *rdev,
89
enum radeon_hpd_id hpd)
92
bool connected = rs600_hpd_sense(rdev, hpd);
96
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
98
tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
100
tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
101
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
104
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
106
tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
108
tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
109
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
116
void rs600_hpd_init(struct radeon_device *rdev)
118
struct drm_device *dev = rdev->ddev;
119
struct drm_connector *connector;
121
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123
switch (radeon_connector->hpd.hpd) {
125
WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
126
S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
127
rdev->irq.hpd[0] = true;
130
WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
131
S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
132
rdev->irq.hpd[1] = true;
138
if (rdev->irq.installed)
142
void rs600_hpd_fini(struct radeon_device *rdev)
144
struct drm_device *dev = rdev->ddev;
145
struct drm_connector *connector;
147
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
148
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
149
switch (radeon_connector->hpd.hpd) {
151
WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
152
S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
153
rdev->irq.hpd[0] = false;
156
WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
157
S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
158
rdev->irq.hpd[1] = false;
100
218
WREG32(R_00004C_BUS_CNTL, tmp);
101
219
/* FIXME: setup default page */
102
220
WREG32_MC(R_000100_MC_PT0_CNTL,
103
(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
104
S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
221
(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
222
S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
105
224
for (i = 0; i < 19; i++) {
106
225
WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
107
S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
108
S_00016C_SYSTEM_ACCESS_MODE_MASK(
109
V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) |
110
S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
111
V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) |
112
S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) |
113
S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
114
S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1));
226
S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
227
S_00016C_SYSTEM_ACCESS_MODE_MASK(
228
V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
229
S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
230
V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
231
S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
232
S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
233
S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
117
/* System context map to GART space */
118
WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start);
119
WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end);
121
235
/* enable first context */
122
WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
123
WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
124
236
WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
125
S_000102_ENABLE_PAGE_TABLE(1) |
126
S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
237
S_000102_ENABLE_PAGE_TABLE(1) |
238
S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
127
240
/* disable all other contexts */
128
for (i = 1; i < 8; i++) {
241
for (i = 1; i < 8; i++)
129
242
WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
132
244
/* setup the page table */
133
245
WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
134
rdev->gart.table_addr);
246
rdev->gart.table_addr);
247
WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
248
WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
135
249
WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
251
/* System context maps to VRAM space */
252
WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
253
WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
137
255
/* enable page tables */
138
256
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
139
257
WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
147
265
void rs600_gart_disable(struct radeon_device *rdev)
151
270
/* FIXME: disable out of gart access */
152
271
WREG32_MC(R_000100_MC_PT0_CNTL, 0);
153
272
tmp = RREG32_MC(R_000009_MC_CNTL1);
154
273
WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
155
274
if (rdev->gart.table.vram.robj) {
156
radeon_object_kunmap(rdev->gart.table.vram.robj);
157
radeon_object_unpin(rdev->gart.table.vram.robj);
275
r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
277
radeon_bo_kunmap(rdev->gart.table.vram.robj);
278
radeon_bo_unpin(rdev->gart.table.vram.robj);
279
radeon_bo_unreserve(rdev->gart.table.vram.robj);
190
313
uint32_t tmp = 0;
191
314
uint32_t mode_int = 0;
315
u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
316
~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
317
u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
318
~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
320
if (!rdev->irq.installed) {
321
WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
322
WREG32(R_000040_GEN_INT_CNTL, 0);
193
325
if (rdev->irq.sw_int) {
194
326
tmp |= S_000040_SW_INT_EN(1);
199
331
if (rdev->irq.crtc_vblank_int[1]) {
200
332
mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
334
if (rdev->irq.hpd[0]) {
335
hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
337
if (rdev->irq.hpd[1]) {
338
hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
202
340
WREG32(R_000040_GEN_INT_CNTL, tmp);
203
341
WREG32(R_006540_DxMODE_INT_MASK, mode_int);
342
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
343
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
219
360
WREG32(R_006D34_D2MODE_VBLANK_STATUS,
220
361
S_006D34_D2MODE_VBLANK_ACK(1));
363
if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
364
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
365
tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
366
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
368
if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
369
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
370
tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
371
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
223
374
*r500_disp_int = 0;
252
404
while (status || r500_disp_int) {
253
405
/* SW interrupt */
254
if (G_000040_SW_INT_EN(status))
406
if (G_000044_SW_INT(status))
255
407
radeon_fence_process(rdev);
256
408
/* Vertical blank interrupts */
257
409
if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int))
258
410
drm_handle_vblank(rdev->ddev, 0);
259
411
if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int))
260
412
drm_handle_vblank(rdev->ddev, 1);
413
if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
414
queue_hotplug = true;
417
if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
418
queue_hotplug = true;
261
421
status = rs600_irq_ack(rdev, &r500_disp_int);
424
queue_work(rdev->wq, &rdev->hotplug_work);
263
425
if (rdev->msi_enabled) {
264
426
switch (rdev->family) {