170
174
idx, relocs_chunk->length_dw);
173
*cs_reloc = &p->relocs[0];
177
*cs_reloc = p->relocs;
174
178
(*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
175
179
(*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
184
* r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
185
* @parser: parser structure holding parsing context.
187
* Check next packet is relocation packet3, do bo validation and compute
188
* GPU offset using the provided start.
190
static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
192
struct radeon_cs_packet p3reloc;
195
r = r600_cs_packet_parse(p, &p3reloc, p->idx);
199
if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
180
206
* r600_cs_packet_next_vline() - parse userspace VLINE packet
181
207
* @parser: parser structure holding parsing context.
503
531
for (i = 0; i < pkt->count; i++) {
504
532
reg = start_reg + (4 * i);
534
/* This register were added late, there is userspace
535
* which does provide relocation for those but set
536
* 0 offset. In order to avoid breaking old userspace
537
* we detect this and set address to point to last
538
* CB_COLOR0_BASE, note that if userspace doesn't set
539
* CB_COLOR0_BASE before this register we will report
540
* error. Old userspace always set CB_COLOR0_BASE
541
* before any of this.
543
case R_0280E0_CB_COLOR0_FRAG:
544
case R_0280E4_CB_COLOR1_FRAG:
545
case R_0280E8_CB_COLOR2_FRAG:
546
case R_0280EC_CB_COLOR3_FRAG:
547
case R_0280F0_CB_COLOR4_FRAG:
548
case R_0280F4_CB_COLOR5_FRAG:
549
case R_0280F8_CB_COLOR6_FRAG:
550
case R_0280FC_CB_COLOR7_FRAG:
551
case R_0280C0_CB_COLOR0_TILE:
552
case R_0280C4_CB_COLOR1_TILE:
553
case R_0280C8_CB_COLOR2_TILE:
554
case R_0280CC_CB_COLOR3_TILE:
555
case R_0280D0_CB_COLOR4_TILE:
556
case R_0280D4_CB_COLOR5_TILE:
557
case R_0280D8_CB_COLOR6_TILE:
558
case R_0280DC_CB_COLOR7_TILE:
559
if (!r600_cs_packet_next_is_pkt3_nop(p)) {
560
if (!track->cb_color0_base_last) {
561
dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
564
ib[idx+1+i] = track->cb_color0_base_last;
565
printk_once(KERN_WARNING "radeon: You have old & broken userspace "
566
"please consider updating mesa & xf86-video-ati\n");
568
r = r600_cs_packet_next_reloc(p, &reloc);
570
dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
573
ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
506
576
case DB_DEPTH_BASE:
507
577
case DB_HTILE_DATA_BASE:
508
578
case CB_COLOR0_BASE:
579
r = r600_cs_packet_next_reloc(p, &reloc);
581
DRM_ERROR("bad SET_CONTEXT_REG "
585
ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
586
track->cb_color0_base_last = ib[idx+1+i];
509
588
case CB_COLOR1_BASE:
510
589
case CB_COLOR2_BASE:
511
590
case CB_COLOR3_BASE:
678
757
int r600_cs_parse(struct radeon_cs_parser *p)
680
759
struct radeon_cs_packet pkt;
760
struct r600_cs_track *track;
763
track = kzalloc(sizeof(*track), GFP_KERNEL);
684
766
r = r600_cs_packet_parse(p, &pkt, p->idx);