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- Committer: Bazaar Package Importer
- Author(s): Hakan Ardo
- Date: 2009-10-31 11:52:10 UTC
- mfrom: (1.1.8 upstream) (4.1.2 squeeze)
- Revision ID: james.westby@ubuntu.com-20091031115210-x0mlijnegkce86fk
Tags: 1:1.6.7-1
* New upstream relese (closes: #544030)
* Added lintian overrides (closes: #553265)
* Added lintian overrides (closes: #553265)
- files added:
- ChangeLog-2008
- avr/lib/avr25/ata6289
- avr/lib/avr25/attiny13a
- avr/lib/avr25/attiny87
- avr/lib/avr31/at43usb320
- avr/lib/avr4/at90pwm81
- avr/lib/avr5/at90scr100
- avr/lib/avr5/atmega128rfa1
- avr/lib/avr5/atmega16m1
- avr/lib/avr5/atmega16u4
- avr/lib/avr5/atmega32u6
- avr/lib/avr5/atmega64c1
- avr/lib/avr5/atmega64m1
- avr/lib/avr51/atmega128rfa1
- avr/lib/avrxmega2
- avr/lib/avrxmega2/atxmega16a4
- avr/lib/avrxmega2/atxmega16d4
- avr/lib/avrxmega2/atxmega32d4
- avr/lib/avrxmega3
- avr/lib/avrxmega3/atxmega32a4
- avr/lib/avrxmega4
- avr/lib/avrxmega4/atxmega64a3
- avr/lib/avrxmega4/atxmega64d3
- avr/lib/avrxmega6
- avr/lib/avrxmega6/atxmega128a3
- avr/lib/avrxmega6/atxmega128d3
- avr/lib/avrxmega6/atxmega192a3
- avr/lib/avrxmega6/atxmega256a3
- avr/lib/avrxmega6/atxmega256a3b
- avr/lib/avrxmega6/atxmega256d3
- files removed:
- autom4te.cache
- doc/LICENSE-Changes
- tests
- tests/simulate
- tests/simulate/avr
- tests/simulate/fplib
- tests/simulate/math
- tests/simulate/other
- tests/simulate/pmstring
- tests/simulate/printf
- tests/simulate/regression
- tests/simulate/scanf
- tests/simulate/stdlib
- tests/simulate/string
- xml
- files modified:
- AUTHORS
added
removed
include/avr/iox192a3.h
1
/* Copyright (c) 2009 Atmel Corporation
2
All rights reserved.
3
4
Redistribution and use in source and binary forms, with or without
5
modification, are permitted provided that the following conditions are met:
6
7
* Redistributions of source code must retain the above copyright
8
notice, this list of conditions and the following disclaimer.
9
10
* Redistributions in binary form must reproduce the above copyright
11
notice, this list of conditions and the following disclaimer in
12
the documentation and/or other materials provided with the
13
distribution.
14
15
* Neither the name of the copyright holders nor the names of
16
contributors may be used to endorse or promote products derived
17
from this software without specific prior written permission.
18
19
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
POSSIBILITY OF SUCH DAMAGE. */
30
31
/* $Id: iox192a3.h,v 1.1.2.2 2009/03/20 05:55:30 arcanum Exp $ */
32
33
/* avr/iox192a3.h - definitions for ATxmega192A3 */
34
35
/* This file should only be included from <avr/io.h>, never directly. */
36
37
#ifndef _AVR_IO_H_
38
# error "Include <avr/io.h> instead of this file."
39
#endif
40
41
#ifndef _AVR_IOXXX_H_
42
# define _AVR_IOXXX_H_ "iox192a3.h"
43
#else
44
# error "Attempt to include more than one <avr/ioXXX.h> file."
45
#endif
46
47
48
#ifndef _AVR_ATxmega192A3_H_
49
#define _AVR_ATxmega192A3_H_ 1
50
51
52
/* Ungrouped common registers */
53
#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
54
#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
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#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
56
#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
57
#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
58
#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
59
#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
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#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
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#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
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#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
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#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
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#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
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#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
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#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
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#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
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#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
69
70
#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
71
#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
72
#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
73
#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
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#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
75
#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
76
#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
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#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
78
#define SREG _SFR_MEM8(0x003F) /* Status Register */
79
80
81
/* C Language Only */
82
#if !defined (__ASSEMBLER__)
83
84
#include <stdint.h>
85
86
typedef volatile uint8_t register8_t;
87
typedef volatile uint16_t register16_t;
88
typedef volatile uint32_t register32_t;
89
90
91
#ifdef _WORDREGISTER
92
#undef _WORDREGISTER
93
#endif
94
#define _WORDREGISTER(regname) \
95
union \
96
{ \
97
register16_t regname; \
98
struct \
99
{ \
100
register8_t regname ## L; \
101
register8_t regname ## H; \
102
}; \
103
}
104
105
#ifdef _DWORDREGISTER
106
#undef _DWORDREGISTER
107
#endif
108
#define _DWORDREGISTER(regname) \
109
union \
110
{ \
111
register32_t regname; \
112
struct \
113
{ \
114
register8_t regname ## 0; \
115
register8_t regname ## 1; \
116
register8_t regname ## 2; \
117
register8_t regname ## 3; \
118
}; \
119
}
120
121
122
/*
123
==========================================================================
124
IO Module Structures
125
==========================================================================
126
*/
127
128
129
/*
130
--------------------------------------------------------------------------
131
XOCD - On-Chip Debug System
132
--------------------------------------------------------------------------
133
*/
134
135
/* On-Chip Debug System */
136
typedef struct OCD_struct
137
{
138
register8_t OCDR0; /* OCD Register 0 */
139
register8_t OCDR1; /* OCD Register 1 */
140
} OCD_t;
141
142
143
/* CCP signatures */
144
typedef enum CCP_enum
145
{
146
CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
147
CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
148
} CCP_t;
149
150
151
/*
152
--------------------------------------------------------------------------
153
CLK - Clock System
154
--------------------------------------------------------------------------
155
*/
156
157
/* Clock System */
158
typedef struct CLK_struct
159
{
160
register8_t CTRL; /* Control Register */
161
register8_t PSCTRL; /* Prescaler Control Register */
162
register8_t LOCK; /* Lock register */
163
register8_t RTCCTRL; /* RTC Control Register */
164
} CLK_t;
165
166
/*
167
--------------------------------------------------------------------------
168
CLK - Clock System
169
--------------------------------------------------------------------------
170
*/
171
172
/* Power Reduction */
173
typedef struct PR_struct
174
{
175
register8_t PRGEN; /* General Power Reduction */
176
register8_t PRPA; /* Power Reduction Port A */
177
register8_t PRPB; /* Power Reduction Port B */
178
register8_t PRPC; /* Power Reduction Port C */
179
register8_t PRPD; /* Power Reduction Port D */
180
register8_t PRPE; /* Power Reduction Port E */
181
register8_t PRPF; /* Power Reduction Port F */
182
} PR_t;
183
184
/* System Clock Selection */
185
typedef enum CLK_SCLKSEL_enum
186
{
187
CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */
188
CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */
189
CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */
190
CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
191
CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
192
} CLK_SCLKSEL_t;
193
194
/* Prescaler A Division Factor */
195
typedef enum CLK_PSADIV_enum
196
{
197
CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
198
CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
199
CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
200
CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
201
CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
202
CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
203
CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
204
CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
205
CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
206
CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
207
} CLK_PSADIV_t;
208
209
/* Prescaler B and C Division Factor */
210
typedef enum CLK_PSBCDIV_enum
211
{
212
CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
213
CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
214
CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
215
CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
216
} CLK_PSBCDIV_t;
217
218
/* RTC Clock Source */
219
typedef enum CLK_RTCSRC_enum
220
{
221
CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */
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CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */
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CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */
224
CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */
225
} CLK_RTCSRC_t;
226
227
228
/*
229
--------------------------------------------------------------------------
230
SLEEP - Sleep Controller
231
--------------------------------------------------------------------------
232
*/
233
234
/* Sleep Controller */
235
typedef struct SLEEP_struct
236
{
237
register8_t CTRL; /* Control Register */
238
} SLEEP_t;
239
240
/* Sleep Mode */
241
typedef enum SLEEP_SMODE_enum
242
{
243
SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
244
SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
245
SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
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SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
247
SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
248
} SLEEP_SMODE_t;
249
250
251
/*
252
--------------------------------------------------------------------------
253
OSC - Oscillator
254
--------------------------------------------------------------------------
255
*/
256
257
/* Oscillator */
258
typedef struct OSC_struct
259
{
260
register8_t CTRL; /* Control Register */
261
register8_t STATUS; /* Status Register */
262
register8_t XOSCCTRL; /* External Oscillator Control Register */
263
register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */
264
register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */
265
register8_t PLLCTRL; /* PLL Control REgister */
266
register8_t DFLLCTRL; /* DFLL Control Register */
267
} OSC_t;
268
269
/* Oscillator Frequency Range */
270
typedef enum OSC_FRQRANGE_enum
271
{
272
OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
273
OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
274
OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
275
OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
276
} OSC_FRQRANGE_t;
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278
/* External Oscillator Selection and Startup Time */
279
typedef enum OSC_XOSCSEL_enum
280
{
281
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
282
OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
283
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
284
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
285
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
286
} OSC_XOSCSEL_t;
287
288
/* PLL Clock Source */
289
typedef enum OSC_PLLSRC_enum
290
{
291
OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */
292
OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */
293
OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
294
} OSC_PLLSRC_t;
295
296
297
/*
298
--------------------------------------------------------------------------
299
DFLL - DFLL
300
--------------------------------------------------------------------------
301
*/
302
303
/* DFLL */
304
typedef struct DFLL_struct
305
{
306
register8_t CTRL; /* Control Register */
307
register8_t reserved_0x01;
308
register8_t CALA; /* Calibration Register A */
309
register8_t CALB; /* Calibration Register B */
310
register8_t COMP0; /* Oscillator Compare Register 0 */
311
register8_t COMP1; /* Oscillator Compare Register 1 */
312
register8_t COMP2; /* Oscillator Compare Register 2 */
313
register8_t reserved_0x07;
314
} DFLL_t;
315
316
317
/*
318
--------------------------------------------------------------------------
319
RST - Reset
320
--------------------------------------------------------------------------
321
*/
322
323
/* Reset */
324
typedef struct RST_struct
325
{
326
register8_t STATUS; /* Status Register */
327
register8_t CTRL; /* Control Register */
328
} RST_t;
329
330
331
/*
332
--------------------------------------------------------------------------
333
WDT - Watch-Dog Timer
334
--------------------------------------------------------------------------
335
*/
336
337
/* Watch-Dog Timer */
338
typedef struct WDT_struct
339
{
340
register8_t CTRL; /* Control */
341
register8_t WINCTRL; /* Windowed Mode Control */
342
register8_t STATUS; /* Status */
343
} WDT_t;
344
345
/* Period setting */
346
typedef enum WDT_PER_enum
347
{
348
WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
349
WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
350
WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
351
WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
352
WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */
353
WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */
354
WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */
355
WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
356
WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
357
WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
358
WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
359
} WDT_PER_t;
360
361
/* Closed window period */
362
typedef enum WDT_WPER_enum
363
{
364
WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
365
WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
366
WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
367
WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
368
WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */
369
WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */
370
WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */
371
WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
372
WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
373
WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
374
WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
375
} WDT_WPER_t;
376
377
378
/*
379
--------------------------------------------------------------------------
380
MCU - MCU Control
381
--------------------------------------------------------------------------
382
*/
383
384
/* MCU Control */
385
typedef struct MCU_struct
386
{
387
register8_t DEVID0; /* Device ID byte 0 */
388
register8_t DEVID1; /* Device ID byte 1 */
389
register8_t DEVID2; /* Device ID byte 2 */
390
register8_t REVID; /* Revision ID */
391
register8_t JTAGUID; /* JTAG User ID */
392
register8_t reserved_0x05;
393
register8_t MCUCR; /* MCU Control */
394
register8_t reserved_0x07;
395
register8_t EVSYSLOCK; /* Event System Lock */
396
register8_t AWEXLOCK; /* AWEX Lock */
397
register8_t reserved_0x0A;
398
register8_t reserved_0x0B;
399
} MCU_t;
400
401
402
/*
403
--------------------------------------------------------------------------
404
PMIC - Programmable Multi-level Interrupt Controller
405
--------------------------------------------------------------------------
406
*/
407
408
/* Programmable Multi-level Interrupt Controller */
409
typedef struct PMIC_struct
410
{
411
register8_t STATUS; /* Status Register */
412
register8_t INTPRI; /* Interrupt Priority */
413
register8_t CTRL; /* Control Register */
414
} PMIC_t;
415
416
417
/*
418
--------------------------------------------------------------------------
419
DMA - DMA Controller
420
--------------------------------------------------------------------------
421
*/
422
423
/* DMA Channel */
424
typedef struct DMA_CH_struct
425
{
426
register8_t CTRLA; /* Channel Control */
427
register8_t CTRLB; /* Channel Control */
428
register8_t ADDRCTRL; /* Address Control */
429
register8_t TRIGSRC; /* Channel Trigger Source */
430
_WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
431
register8_t REPCNT; /* Channel Repeat Count */
432
register8_t reserved_0x07;
433
register8_t SRCADDR0; /* Channel Source Address 0 */
434
register8_t SRCADDR1; /* Channel Source Address 1 */
435
register8_t SRCADDR2; /* Channel Source Address 2 */
436
register8_t reserved_0x0B;
437
register8_t DESTADDR0; /* Channel Destination Address 0 */
438
register8_t DESTADDR1; /* Channel Destination Address 1 */
439
register8_t DESTADDR2; /* Channel Destination Address 2 */
440
register8_t reserved_0x0F;
441
} DMA_CH_t;
442
443
/*
444
--------------------------------------------------------------------------
445
DMA - DMA Controller
446
--------------------------------------------------------------------------
447
*/
448
449
/* DMA Controller */
450
typedef struct DMA_struct
451
{
452
register8_t CTRL; /* Control */
453
register8_t reserved_0x01;
454
register8_t reserved_0x02;
455
register8_t INTFLAGS; /* Transfer Interrupt Status */
456
register8_t STATUS; /* Status */
457
register8_t reserved_0x05;
458
_WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
459
register8_t reserved_0x08;
460
register8_t reserved_0x09;
461
register8_t reserved_0x0A;
462
register8_t reserved_0x0B;
463
register8_t reserved_0x0C;
464
register8_t reserved_0x0D;
465
register8_t reserved_0x0E;
466
register8_t reserved_0x0F;
467
DMA_CH_t CH0; /* DMA Channel 0 */
468
DMA_CH_t CH1; /* DMA Channel 1 */
469
DMA_CH_t CH2; /* DMA Channel 2 */
470
DMA_CH_t CH3; /* DMA Channel 3 */
471
} DMA_t;
472
473
/* Burst mode */
474
typedef enum DMA_CH_BURSTLEN_enum
475
{
476
DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
477
DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
478
DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
479
DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
480
} DMA_CH_BURSTLEN_t;
481
482
/* Source address reload mode */
483
typedef enum DMA_CH_SRCRELOAD_enum
484
{
485
DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
486
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
487
DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
488
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
489
} DMA_CH_SRCRELOAD_t;
490
491
/* Source addressing mode */
492
typedef enum DMA_CH_SRCDIR_enum
493
{
494
DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
495
DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
496
DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
497
} DMA_CH_SRCDIR_t;
498
499
/* Destination adress reload mode */
500
typedef enum DMA_CH_DESTRELOAD_enum
501
{
502
DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
503
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
504
DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
505
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
506
} DMA_CH_DESTRELOAD_t;
507
508
/* Destination adressing mode */
509
typedef enum DMA_CH_DESTDIR_enum
510
{
511
DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
512
DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
513
DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
514
} DMA_CH_DESTDIR_t;
515
516
/* Transfer trigger source */
517
typedef enum DMA_CH_TRIGSRC_enum
518
{
519
DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
520
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
521
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
522
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
523
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
524
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
525
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
526
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
527
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
528
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
529
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
530
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
531
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
532
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
533
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
534
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
535
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
536
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
537
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
538
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
539
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
540
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
541
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
542
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
543
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
544
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
545
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
546
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
547
DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
548
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
549
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
550
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
551
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
552
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
553
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
554
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
555
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
556
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
557
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
558
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
559
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
560
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
561
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
562
DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
563
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
564
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
565
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
566
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
567
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
568
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
569
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
570
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
571
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
572
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
573
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
574
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
575
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
576
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
577
DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
578
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
579
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
580
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
581
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
582
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
583
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
584
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
585
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
586
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
587
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
588
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
589
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
590
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
591
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
592
DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
593
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
594
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
595
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
596
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
597
} DMA_CH_TRIGSRC_t;
598
599
/* Double buffering mode */
600
typedef enum DMA_DBUFMODE_enum
601
{
602
DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
603
DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
604
DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
605
DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
606
} DMA_DBUFMODE_t;
607
608
/* Priority mode */
609
typedef enum DMA_PRIMODE_enum
610
{
611
DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
612
DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
613
DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
614
DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
615
} DMA_PRIMODE_t;
616
617
/* Interrupt level */
618
typedef enum DMA_CH_ERRINTLVL_enum
619
{
620
DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
621
DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
622
DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
623
DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
624
} DMA_CH_ERRINTLVL_t;
625
626
/* Interrupt level */
627
typedef enum DMA_CH_TRNINTLVL_enum
628
{
629
DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
630
DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
631
DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
632
DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
633
} DMA_CH_TRNINTLVL_t;
634
635
636
/*
637
--------------------------------------------------------------------------
638
EVSYS - Event System
639
--------------------------------------------------------------------------
640
*/
641
642
/* Event System */
643
typedef struct EVSYS_struct
644
{
645
register8_t CH0MUX; /* Event Channel 0 Multiplexer */
646
register8_t CH1MUX; /* Event Channel 1 Multiplexer */
647
register8_t CH2MUX; /* Event Channel 2 Multiplexer */
648
register8_t CH3MUX; /* Event Channel 3 Multiplexer */
649
register8_t CH4MUX; /* Event Channel 4 Multiplexer */
650
register8_t CH5MUX; /* Event Channel 5 Multiplexer */
651
register8_t CH6MUX; /* Event Channel 6 Multiplexer */
652
register8_t CH7MUX; /* Event Channel 7 Multiplexer */
653
register8_t CH0CTRL; /* Channel 0 Control Register */
654
register8_t CH1CTRL; /* Channel 1 Control Register */
655
register8_t CH2CTRL; /* Channel 2 Control Register */
656
register8_t CH3CTRL; /* Channel 3 Control Register */
657
register8_t CH4CTRL; /* Channel 4 Control Register */
658
register8_t CH5CTRL; /* Channel 5 Control Register */
659
register8_t CH6CTRL; /* Channel 6 Control Register */
660
register8_t CH7CTRL; /* Channel 7 Control Register */
661
register8_t STROBE; /* Event Strobe */
662
register8_t DATA; /* Event Data */
663
} EVSYS_t;
664
665
/* Quadrature Decoder Index Recognition Mode */
666
typedef enum EVSYS_QDIRM_enum
667
{
668
EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
669
EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
670
EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
671
EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
672
} EVSYS_QDIRM_t;
673
674
/* Digital filter coefficient */
675
typedef enum EVSYS_DIGFILT_enum
676
{
677
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
678
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
679
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
680
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
681
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
682
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
683
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
684
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
685
} EVSYS_DIGFILT_t;
686
687
/* Event Channel multiplexer input selection */
688
typedef enum EVSYS_CHMUX_enum
689
{
690
EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
691
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
692
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
693
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
694
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
695
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
696
EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
697
EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
698
EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
699
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
700
EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
701
EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
702
EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
703
EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
704
EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
705
EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
706
EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
707
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
708
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
709
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
710
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
711
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
712
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
713
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
714
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
715
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
716
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
717
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
718
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
719
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
720
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
721
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
722
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
723
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
724
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
725
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
726
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
727
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
728
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
729
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
730
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
731
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
732
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
733
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
734
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
735
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
736
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
737
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
738
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
739
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
740
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
741
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
742
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
743
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
744
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
745
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
746
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
747
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
748
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
749
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
750
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
751
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
752
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
753
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
754
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
755
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
756
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
757
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
758
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
759
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
760
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
761
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
762
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
763
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
764
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
765
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
766
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
767
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
768
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
769
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
770
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
771
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
772
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
773
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
774
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
775
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
776
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
777
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
778
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
779
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
780
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
781
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
782
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
783
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
784
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
785
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
786
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
787
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
788
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
789
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
790
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
791
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
792
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
793
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
794
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
795
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
796
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
797
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
798
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
799
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
800
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
801
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
802
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
803
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
804
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
805
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
806
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
807
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
808
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
809
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
810
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
811
} EVSYS_CHMUX_t;
812
813
814
/*
815
--------------------------------------------------------------------------
816
NVM - Non Volatile Memory Controller
817
--------------------------------------------------------------------------
818
*/
819
820
/* Non-volatile Memory Controller */
821
typedef struct NVM_struct
822
{
823
register8_t ADDR0; /* Address Register 0 */
824
register8_t ADDR1; /* Address Register 1 */
825
register8_t ADDR2; /* Address Register 2 */
826
register8_t reserved_0x03;
827
register8_t DATA0; /* Data Register 0 */
828
register8_t DATA1; /* Data Register 1 */
829
register8_t DATA2; /* Data Register 2 */
830
register8_t reserved_0x07;
831
register8_t reserved_0x08;
832
register8_t reserved_0x09;
833
register8_t CMD; /* Command */
834
register8_t CTRLA; /* Control Register A */
835
register8_t CTRLB; /* Control Register B */
836
register8_t INTCTRL; /* Interrupt Control */
837
register8_t reserved_0x0E;
838
register8_t STATUS; /* Status */
839
register8_t LOCKBITS; /* Lock Bits */
840
} NVM_t;
841
842
/*
843
--------------------------------------------------------------------------
844
NVM - Non Volatile Memory Controller
845
--------------------------------------------------------------------------
846
*/
847
848
/* Lock Bits */
849
typedef struct NVM_LOCKBITS_struct
850
{
851
register8_t LOCKBITS; /* Lock Bits */
852
} NVM_LOCKBITS_t;
853
854
/*
855
--------------------------------------------------------------------------
856
NVM - Non Volatile Memory Controller
857
--------------------------------------------------------------------------
858
*/
859
860
/* Fuses */
861
typedef struct NVM_FUSES_struct
862
{
863
register8_t FUSEBYTE0; /* JTAG User ID */
864
register8_t FUSEBYTE1; /* Watchdog Configuration */
865
register8_t FUSEBYTE2; /* Reset Configuration */
866
register8_t reserved_0x03;
867
register8_t FUSEBYTE4; /* Start-up Configuration */
868
register8_t FUSEBYTE5; /* EESAVE and BOD Level */
869
} NVM_FUSES_t;
870
871
/*
872
--------------------------------------------------------------------------
873
NVM - Non Volatile Memory Controller
874
--------------------------------------------------------------------------
875
*/
876
877
/* Production Signatures */
878
typedef struct NVM_PROD_SIGNATURES_struct
879
{
880
register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */
881
register8_t reserved_0x01;
882
register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */
883
register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */
884
register8_t reserved_0x04;
885
register8_t reserved_0x05;
886
register8_t reserved_0x06;
887
register8_t reserved_0x07;
888
register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
889
register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
890
register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
891
register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
892
register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
893
register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
894
register8_t reserved_0x0E;
895
register8_t reserved_0x0F;
896
register8_t WAFNUM; /* Wafer Number */
897
register8_t reserved_0x11;
898
register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
899
register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
900
register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
901
register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
902
register8_t reserved_0x16;
903
register8_t reserved_0x17;
904
register8_t reserved_0x18;
905
register8_t reserved_0x19;
906
register8_t reserved_0x1A;
907
register8_t reserved_0x1B;
908
register8_t reserved_0x1C;
909
register8_t reserved_0x1D;
910
register8_t reserved_0x1E;
911
register8_t reserved_0x1F;
912
register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
913
register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
914
register8_t reserved_0x22;
915
register8_t reserved_0x23;
916
register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
917
register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
918
register8_t reserved_0x26;
919
register8_t reserved_0x27;
920
register8_t reserved_0x28;
921
register8_t reserved_0x29;
922
register8_t reserved_0x2A;
923
register8_t reserved_0x2B;
924
register8_t reserved_0x2C;
925
register8_t reserved_0x2D;
926
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
927
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
928
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
929
register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
930
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
931
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
932
register8_t reserved_0x34;
933
register8_t reserved_0x35;
934
register8_t reserved_0x36;
935
register8_t reserved_0x37;
936
register8_t reserved_0x38;
937
register8_t reserved_0x39;
938
register8_t reserved_0x3A;
939
register8_t reserved_0x3B;
940
register8_t reserved_0x3C;
941
register8_t reserved_0x3D;
942
register8_t reserved_0x3E;
943
} NVM_PROD_SIGNATURES_t;
944
945
/* NVM Command */
946
typedef enum NVM_CMD_enum
947
{
948
NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
949
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
950
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
951
NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
952
NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
953
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
954
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
955
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
956
NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
957
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
958
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
959
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
960
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
961
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
962
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
963
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
964
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
965
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
966
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
967
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
968
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
969
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
970
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
971
NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
972
NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
973
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */
974
} NVM_CMD_t;
975
976
/* SPM ready interrupt level */
977
typedef enum NVM_SPMLVL_enum
978
{
979
NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
980
NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
981
NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
982
NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
983
} NVM_SPMLVL_t;
984
985
/* EEPROM ready interrupt level */
986
typedef enum NVM_EELVL_enum
987
{
988
NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
989
NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
990
NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
991
NVM_EELVL_HI_gc = (0x03<<0), /* High level */
992
} NVM_EELVL_t;
993
994
/* Boot lock bits - boot setcion */
995
typedef enum NVM_BLBB_enum
996
{
997
NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
998
NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
999
NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
1000
NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
1001
} NVM_BLBB_t;
1002
1003
/* Boot lock bits - application section */
1004
typedef enum NVM_BLBA_enum
1005
{
1006
NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
1007
NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
1008
NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
1009
NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
1010
} NVM_BLBA_t;
1011
1012
/* Boot lock bits - application table section */
1013
typedef enum NVM_BLBAT_enum
1014
{
1015
NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
1016
NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
1017
NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
1018
NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
1019
} NVM_BLBAT_t;
1020
1021
/* Lock bits */
1022
typedef enum NVM_LB_enum
1023
{
1024
NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
1025
NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
1026
NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
1027
} NVM_LB_t;
1028
1029
/* Boot Loader Section Reset Vector */
1030
typedef enum BOOTRST_enum
1031
{
1032
BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
1033
BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
1034
} BOOTRST_t;
1035
1036
/* BOD operation */
1037
typedef enum BOD_enum
1038
{
1039
BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */
1040
BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */
1041
BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
1042
} BOD_t;
1043
1044
/* Watchdog (Window) Timeout Period */
1045
typedef enum WD_enum
1046
{
1047
WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
1048
WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
1049
WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
1050
WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
1051
WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
1052
WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
1053
WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
1054
WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
1055
WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
1056
WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
1057
WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
1058
} WD_t;
1059
1060
/* Start-up Time */
1061
typedef enum SUT_enum
1062
{
1063
SUT_0MS_gc = (0x03<<2), /* 0 ms */
1064
SUT_4MS_gc = (0x01<<2), /* 4 ms */
1065
SUT_64MS_gc = (0x00<<2), /* 64 ms */
1066
} SUT_t;
1067
1068
/* Brown Out Detection Voltage Level */
1069
typedef enum BODLVL_enum
1070
{
1071
BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
1072
BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */
1073
BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */
1074
BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */
1075
BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */
1076
BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */
1077
BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */
1078
} BODLVL_t;
1079
1080
1081
/*
1082
--------------------------------------------------------------------------
1083
AC - Analog Comparator
1084
--------------------------------------------------------------------------
1085
*/
1086
1087
/* Analog Comparator */
1088
typedef struct AC_struct
1089
{
1090
register8_t AC0CTRL; /* Comparator 0 Control */
1091
register8_t AC1CTRL; /* Comparator 1 Control */
1092
register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */
1093
register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */
1094
register8_t CTRLA; /* Control Register A */
1095
register8_t CTRLB; /* Control Register B */
1096
register8_t WINCTRL; /* Window Mode Control */
1097
register8_t STATUS; /* Status */
1098
} AC_t;
1099
1100
/* Interrupt mode */
1101
typedef enum AC_INTMODE_enum
1102
{
1103
AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
1104
AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
1105
AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
1106
} AC_INTMODE_t;
1107
1108
/* Interrupt level */
1109
typedef enum AC_INTLVL_enum
1110
{
1111
AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
1112
AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
1113
AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
1114
AC_INTLVL_HI_gc = (0x03<<4), /* High level */
1115
} AC_INTLVL_t;
1116
1117
/* Hysteresis mode selection */
1118
typedef enum AC_HYSMODE_enum
1119
{
1120
AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
1121
AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
1122
AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
1123
} AC_HYSMODE_t;
1124
1125
/* Positive input multiplexer selection */
1126
typedef enum AC_MUXPOS_enum
1127
{
1128
AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
1129
AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
1130
AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
1131
AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
1132
AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
1133
AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
1134
AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
1135
AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
1136
} AC_MUXPOS_t;
1137
1138
/* Negative input multiplexer selection */
1139
typedef enum AC_MUXNEG_enum
1140
{
1141
AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
1142
AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
1143
AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
1144
AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
1145
AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
1146
AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
1147
AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
1148
AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
1149
} AC_MUXNEG_t;
1150
1151
/* Windows interrupt mode */
1152
typedef enum AC_WINTMODE_enum
1153
{
1154
AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
1155
AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
1156
AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
1157
AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
1158
} AC_WINTMODE_t;
1159
1160
/* Window interrupt level */
1161
typedef enum AC_WINTLVL_enum
1162
{
1163
AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
1164
AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
1165
AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
1166
AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
1167
} AC_WINTLVL_t;
1168
1169
/* Window mode state */
1170
typedef enum AC_WSTATE_enum
1171
{
1172
AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
1173
AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
1174
AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
1175
} AC_WSTATE_t;
1176
1177
1178
/*
1179
--------------------------------------------------------------------------
1180
ADC - Analog/Digital Converter
1181
--------------------------------------------------------------------------
1182
*/
1183
1184
/* ADC Channel */
1185
typedef struct ADC_CH_struct
1186
{
1187
register8_t CTRL; /* Control Register */
1188
register8_t MUXCTRL; /* MUX Control */
1189
register8_t INTCTRL; /* Channel Interrupt Control */
1190
register8_t INTFLAGS; /* Interrupt Flags */
1191
_WORDREGISTER(RES); /* Channel Result */
1192
register8_t reserved_0x6;
1193
register8_t reserved_0x7;
1194
} ADC_CH_t;
1195
1196
/*
1197
--------------------------------------------------------------------------
1198
ADC - Analog/Digital Converter
1199
--------------------------------------------------------------------------
1200
*/
1201
1202
/* Analog-to-Digital Converter */
1203
typedef struct ADC_struct
1204
{
1205
register8_t CTRLA; /* Control Register A */
1206
register8_t CTRLB; /* Control Register B */
1207
register8_t REFCTRL; /* Reference Control */
1208
register8_t EVCTRL; /* Event Control */
1209
register8_t PRESCALER; /* Clock Prescaler */
1210
register8_t CALCTRL; /* Calibration Control Register */
1211
register8_t INTFLAGS; /* Interrupt Flags */
1212
register8_t reserved_0x07;
1213
register8_t reserved_0x08;
1214
register8_t reserved_0x09;
1215
register8_t reserved_0x0A;
1216
register8_t reserved_0x0B;
1217
_WORDREGISTER(CAL); /* Calibration Value */
1218
register8_t reserved_0x0E;
1219
register8_t reserved_0x0F;
1220
_WORDREGISTER(CH0RES); /* Channel 0 Result */
1221
_WORDREGISTER(CH1RES); /* Channel 1 Result */
1222
_WORDREGISTER(CH2RES); /* Channel 2 Result */
1223
_WORDREGISTER(CH3RES); /* Channel 3 Result */
1224
_WORDREGISTER(CMP); /* Compare Value */
1225
register8_t reserved_0x1A;
1226
register8_t reserved_0x1B;
1227
register8_t reserved_0x1C;
1228
register8_t reserved_0x1D;
1229
register8_t reserved_0x1E;
1230
register8_t reserved_0x1F;
1231
ADC_CH_t CH0; /* ADC Channel 0 */
1232
ADC_CH_t CH1; /* ADC Channel 1 */
1233
ADC_CH_t CH2; /* ADC Channel 2 */
1234
ADC_CH_t CH3; /* ADC Channel 3 */
1235
} ADC_t;
1236
1237
/* Positive input multiplexer selection */
1238
typedef enum ADC_CH_MUXPOS_enum
1239
{
1240
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
1241
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
1242
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
1243
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
1244
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
1245
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
1246
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
1247
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
1248
} ADC_CH_MUXPOS_t;
1249
1250
/* Internal input multiplexer selections */
1251
typedef enum ADC_CH_MUXINT_enum
1252
{
1253
ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
1254
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
1255
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
1256
ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
1257
} ADC_CH_MUXINT_t;
1258
1259
/* Negative input multiplexer selection */
1260
typedef enum ADC_CH_MUXNEG_enum
1261
{
1262
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
1263
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
1264
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
1265
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
1266
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */
1267
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */
1268
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */
1269
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */
1270
} ADC_CH_MUXNEG_t;
1271
1272
/* Input mode */
1273
typedef enum ADC_CH_INPUTMODE_enum
1274
{
1275
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
1276
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
1277
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
1278
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
1279
} ADC_CH_INPUTMODE_t;
1280
1281
/* Gain factor */
1282
typedef enum ADC_CH_GAIN_enum
1283
{
1284
ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
1285
ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
1286
ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
1287
ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
1288
ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
1289
ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
1290
ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
1291
} ADC_CH_GAIN_t;
1292
1293
/* Conversion result resolution */
1294
typedef enum ADC_RESOLUTION_enum
1295
{
1296
ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
1297
ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
1298
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
1299
} ADC_RESOLUTION_t;
1300
1301
/* Voltage reference selection */
1302
typedef enum ADC_REFSEL_enum
1303
{
1304
ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
1305
ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */
1306
ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
1307
ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
1308
} ADC_REFSEL_t;
1309
1310
/* Channel sweep selection */
1311
typedef enum ADC_SWEEP_enum
1312
{
1313
ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
1314
ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
1315
ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
1316
ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
1317
} ADC_SWEEP_t;
1318
1319
/* Event channel input selection */
1320
typedef enum ADC_EVSEL_enum
1321
{
1322
ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
1323
ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
1324
ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
1325
ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
1326
ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
1327
ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
1328
ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
1329
ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
1330
} ADC_EVSEL_t;
1331
1332
/* Event action selection */
1333
typedef enum ADC_EVACT_enum
1334
{
1335
ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
1336
ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
1337
ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
1338
ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
1339
ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
1340
ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
1341
ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
1342
} ADC_EVACT_t;
1343
1344
/* Interupt mode */
1345
typedef enum ADC_CH_INTMODE_enum
1346
{
1347
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
1348
ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
1349
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
1350
} ADC_CH_INTMODE_t;
1351
1352
/* Interrupt level */
1353
typedef enum ADC_CH_INTLVL_enum
1354
{
1355
ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
1356
ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
1357
ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
1358
ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
1359
} ADC_CH_INTLVL_t;
1360
1361
/* DMA request selection */
1362
typedef enum ADC_DMASEL_enum
1363
{
1364
ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
1365
ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
1366
ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
1367
ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
1368
} ADC_DMASEL_t;
1369
1370
/* Clock prescaler */
1371
typedef enum ADC_PRESCALER_enum
1372
{
1373
ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
1374
ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
1375
ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
1376
ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
1377
ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
1378
ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
1379
ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
1380
ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
1381
} ADC_PRESCALER_t;
1382
1383
1384
/*
1385
--------------------------------------------------------------------------
1386
DAC - Digital/Analog Converter
1387
--------------------------------------------------------------------------
1388
*/
1389
1390
/* Digital-to-Analog Converter */
1391
typedef struct DAC_struct
1392
{
1393
register8_t CTRLA; /* Control Register A */
1394
register8_t CTRLB; /* Control Register B */
1395
register8_t CTRLC; /* Control Register C */
1396
register8_t EVCTRL; /* Event Input Control */
1397
register8_t TIMCTRL; /* Timing Control */
1398
register8_t STATUS; /* Status */
1399
register8_t reserved_0x06;
1400
register8_t reserved_0x07;
1401
register8_t GAINCAL; /* Gain Calibration */
1402
register8_t OFFSETCAL; /* Offset Calibration */
1403
register8_t reserved_0x0A;
1404
register8_t reserved_0x0B;
1405
register8_t reserved_0x0C;
1406
register8_t reserved_0x0D;
1407
register8_t reserved_0x0E;
1408
register8_t reserved_0x0F;
1409
register8_t reserved_0x10;
1410
register8_t reserved_0x11;
1411
register8_t reserved_0x12;
1412
register8_t reserved_0x13;
1413
register8_t reserved_0x14;
1414
register8_t reserved_0x15;
1415
register8_t reserved_0x16;
1416
register8_t reserved_0x17;
1417
_WORDREGISTER(CH0DATA); /* Channel 0 Data */
1418
_WORDREGISTER(CH1DATA); /* Channel 1 Data */
1419
} DAC_t;
1420
1421
/* Output channel selection */
1422
typedef enum DAC_CHSEL_enum
1423
{
1424
DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */
1425
DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */
1426
} DAC_CHSEL_t;
1427
1428
/* Reference voltage selection */
1429
typedef enum DAC_REFSEL_enum
1430
{
1431
DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
1432
DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
1433
DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
1434
DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
1435
} DAC_REFSEL_t;
1436
1437
/* Event channel selection */
1438
typedef enum DAC_EVSEL_enum
1439
{
1440
DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
1441
DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
1442
DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
1443
DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
1444
DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
1445
DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
1446
DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
1447
DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
1448
} DAC_EVSEL_t;
1449
1450
/* Conversion interval */
1451
typedef enum DAC_CONINTVAL_enum
1452
{
1453
DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
1454
DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
1455
DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
1456
DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
1457
DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
1458
DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
1459
DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
1460
DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
1461
} DAC_CONINTVAL_t;
1462
1463
/* Refresh rate */
1464
typedef enum DAC_REFRESH_enum
1465
{
1466
DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
1467
DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
1468
DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
1469
DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
1470
DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
1471
DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
1472
DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
1473
DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
1474
DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */
1475
DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
1476
DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
1477
DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
1478
DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
1479
DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
1480
} DAC_REFRESH_t;
1481
1482
1483
/*
1484
--------------------------------------------------------------------------
1485
RTC - Real-Time Clounter
1486
--------------------------------------------------------------------------
1487
*/
1488
1489
/* Real-Time Counter */
1490
typedef struct RTC_struct
1491
{
1492
register8_t CTRL; /* Control Register */
1493
register8_t STATUS; /* Status Register */
1494
register8_t INTCTRL; /* Interrupt Control Register */
1495
register8_t INTFLAGS; /* Interrupt Flags */
1496
register8_t TEMP; /* Temporary register */
1497
register8_t reserved_0x05;
1498
register8_t reserved_0x06;
1499
register8_t reserved_0x07;
1500
_WORDREGISTER(CNT); /* Count Register */
1501
_WORDREGISTER(PER); /* Period Register */
1502
_WORDREGISTER(COMP); /* Compare Register */
1503
} RTC_t;
1504
1505
/* Prescaler Factor */
1506
typedef enum RTC_PRESCALER_enum
1507
{
1508
RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
1509
RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
1510
RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
1511
RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
1512
RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
1513
RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
1514
RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
1515
RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
1516
} RTC_PRESCALER_t;
1517
1518
/* Compare Interrupt level */
1519
typedef enum RTC_COMPINTLVL_enum
1520
{
1521
RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1522
RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
1523
RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1524
RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
1525
} RTC_COMPINTLVL_t;
1526
1527
/* Overflow Interrupt level */
1528
typedef enum RTC_OVFINTLVL_enum
1529
{
1530
RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1531
RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
1532
RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1533
RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
1534
} RTC_OVFINTLVL_t;
1535
1536
1537
/*
1538
--------------------------------------------------------------------------
1539
EBI - External Bus Interface
1540
--------------------------------------------------------------------------
1541
*/
1542
1543
/* EBI Chip Select Module */
1544
typedef struct EBI_CS_struct
1545
{
1546
register8_t CTRLA; /* Chip Select Control Register A */
1547
register8_t CTRLB; /* Chip Select Control Register B */
1548
_WORDREGISTER(BASEADDR); /* Chip Select Base Address */
1549
} EBI_CS_t;
1550
1551
/*
1552
--------------------------------------------------------------------------
1553
EBI - External Bus Interface
1554
--------------------------------------------------------------------------
1555
*/
1556
1557
/* External Bus Interface */
1558
typedef struct EBI_struct
1559
{
1560
register8_t CTRL; /* Control */
1561
register8_t SDRAMCTRLA; /* SDRAM Control Register A */
1562
register8_t reserved_0x02;
1563
register8_t reserved_0x03;
1564
_WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
1565
_WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
1566
register8_t SDRAMCTRLB; /* SDRAM Control Register B */
1567
register8_t SDRAMCTRLC; /* SDRAM Control Register C */
1568
register8_t reserved_0x0A;
1569
register8_t reserved_0x0B;
1570
register8_t reserved_0x0C;
1571
register8_t reserved_0x0D;
1572
register8_t reserved_0x0E;
1573
register8_t reserved_0x0F;
1574
EBI_CS_t CS0; /* Chip Select 0 */
1575
EBI_CS_t CS1; /* Chip Select 1 */
1576
EBI_CS_t CS2; /* Chip Select 2 */
1577
EBI_CS_t CS3; /* Chip Select 3 */
1578
} EBI_t;
1579
1580
/* Chip Select adress space */
1581
typedef enum EBI_CS_ASPACE_enum
1582
{
1583
EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
1584
EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
1585
EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
1586
EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
1587
EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
1588
EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
1589
EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
1590
EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
1591
EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
1592
EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
1593
EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
1594
EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
1595
EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
1596
EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
1597
EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
1598
EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
1599
EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
1600
} EBI_CS_ASPACE_t;
1601
1602
/* */
1603
typedef enum EBI_CS_SRWS_enum
1604
{
1605
EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
1606
EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
1607
EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
1608
EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
1609
EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
1610
EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
1611
EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
1612
EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
1613
} EBI_CS_SRWS_t;
1614
1615
/* Chip Select address mode */
1616
typedef enum EBI_CS_MODE_enum
1617
{
1618
EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
1619
EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
1620
EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
1621
EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
1622
} EBI_CS_MODE_t;
1623
1624
/* Chip Select SDRAM mode */
1625
typedef enum EBI_CS_SDMODE_enum
1626
{
1627
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
1628
EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
1629
} EBI_CS_SDMODE_t;
1630
1631
/* */
1632
typedef enum EBI_SDDATAW_enum
1633
{
1634
EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
1635
EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
1636
} EBI_SDDATAW_t;
1637
1638
/* */
1639
typedef enum EBI_LPCMODE_enum
1640
{
1641
EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
1642
EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
1643
} EBI_LPCMODE_t;
1644
1645
/* */
1646
typedef enum EBI_SRMODE_enum
1647
{
1648
EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
1649
EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
1650
EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
1651
EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
1652
} EBI_SRMODE_t;
1653
1654
/* */
1655
typedef enum EBI_IFMODE_enum
1656
{
1657
EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
1658
EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
1659
EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
1660
EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
1661
} EBI_IFMODE_t;
1662
1663
/* */
1664
typedef enum EBI_SDCOL_enum
1665
{
1666
EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
1667
EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
1668
EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
1669
EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
1670
} EBI_SDCOL_t;
1671
1672
/* */
1673
typedef enum EBI_MRDLY_enum
1674
{
1675
EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1676
EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1677
EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1678
EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1679
} EBI_MRDLY_t;
1680
1681
/* */
1682
typedef enum EBI_ROWCYCDLY_enum
1683
{
1684
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1685
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1686
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1687
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1688
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1689
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1690
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1691
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1692
} EBI_ROWCYCDLY_t;
1693
1694
/* */
1695
typedef enum EBI_RPDLY_enum
1696
{
1697
EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1698
EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1699
EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1700
EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1701
EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1702
EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1703
EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1704
EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1705
} EBI_RPDLY_t;
1706
1707
/* */
1708
typedef enum EBI_WRDLY_enum
1709
{
1710
EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1711
EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1712
EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1713
EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1714
} EBI_WRDLY_t;
1715
1716
/* */
1717
typedef enum EBI_ESRDLY_enum
1718
{
1719
EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1720
EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1721
EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1722
EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1723
EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1724
EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1725
EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1726
EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1727
} EBI_ESRDLY_t;
1728
1729
/* */
1730
typedef enum EBI_ROWCOLDLY_enum
1731
{
1732
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1733
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1734
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1735
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1736
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1737
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1738
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1739
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1740
} EBI_ROWCOLDLY_t;
1741
1742
1743
/*
1744
--------------------------------------------------------------------------
1745
TWI - Two-Wire Interface
1746
--------------------------------------------------------------------------
1747
*/
1748
1749
/* */
1750
typedef struct TWI_MASTER_struct
1751
{
1752
register8_t CTRLA; /* Control Register A */
1753
register8_t CTRLB; /* Control Register B */
1754
register8_t CTRLC; /* Control Register C */
1755
register8_t STATUS; /* Status Register */
1756
register8_t BAUD; /* Baurd Rate Control Register */
1757
register8_t ADDR; /* Address Register */
1758
register8_t DATA; /* Data Register */
1759
} TWI_MASTER_t;
1760
1761
/*
1762
--------------------------------------------------------------------------
1763
TWI - Two-Wire Interface
1764
--------------------------------------------------------------------------
1765
*/
1766
1767
/* */
1768
typedef struct TWI_SLAVE_struct
1769
{
1770
register8_t CTRLA; /* Control Register A */
1771
register8_t CTRLB; /* Control Register B */
1772
register8_t STATUS; /* Status Register */
1773
register8_t ADDR; /* Address Register */
1774
register8_t DATA; /* Data Register */
1775
register8_t ADDRMASK; /* Address Mask Register */
1776
} TWI_SLAVE_t;
1777
1778
/*
1779
--------------------------------------------------------------------------
1780
TWI - Two-Wire Interface
1781
--------------------------------------------------------------------------
1782
*/
1783
1784
/* Two-Wire Interface */
1785
typedef struct TWI_struct
1786
{
1787
register8_t CTRL; /* TWI Common Control Register */
1788
TWI_MASTER_t MASTER; /* TWI master module */
1789
TWI_SLAVE_t SLAVE; /* TWI slave module */
1790
} TWI_t;
1791
1792
/* Master Interrupt Level */
1793
typedef enum TWI_MASTER_INTLVL_enum
1794
{
1795
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1796
TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1797
TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1798
TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
1799
} TWI_MASTER_INTLVL_t;
1800
1801
/* Inactive Timeout */
1802
typedef enum TWI_MASTER_TIMEOUT_enum
1803
{
1804
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
1805
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
1806
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
1807
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
1808
} TWI_MASTER_TIMEOUT_t;
1809
1810
/* Master Command */
1811
typedef enum TWI_MASTER_CMD_enum
1812
{
1813
TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
1814
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
1815
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
1816
TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
1817
} TWI_MASTER_CMD_t;
1818
1819
/* Master Bus State */
1820
typedef enum TWI_MASTER_BUSSTATE_enum
1821
{
1822
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
1823
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
1824
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
1825
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
1826
} TWI_MASTER_BUSSTATE_t;
1827
1828
/* Slave Interrupt Level */
1829
typedef enum TWI_SLAVE_INTLVL_enum
1830
{
1831
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1832
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1833
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1834
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
1835
} TWI_SLAVE_INTLVL_t;
1836
1837
/* Slave Command */
1838
typedef enum TWI_SLAVE_CMD_enum
1839
{
1840
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
1841
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
1842
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
1843
} TWI_SLAVE_CMD_t;
1844
1845
1846
/*
1847
--------------------------------------------------------------------------
1848
PORT - Port Configuration
1849
--------------------------------------------------------------------------
1850
*/
1851
1852
/* I/O port Configuration */
1853
typedef struct PORTCFG_struct
1854
{
1855
register8_t MPCMASK; /* Multi-pin Configuration Mask */
1856
register8_t reserved_0x01;
1857
register8_t VPCTRLA; /* Virtual Port Control Register A */
1858
register8_t VPCTRLB; /* Virtual Port Control Register B */
1859
register8_t CLKEVOUT; /* Clock and Event Out Register */
1860
} PORTCFG_t;
1861
1862
/*
1863
--------------------------------------------------------------------------
1864
PORT - Port Configuration
1865
--------------------------------------------------------------------------
1866
*/
1867
1868
/* Virtual Port */
1869
typedef struct VPORT_struct
1870
{
1871
register8_t DIR; /* I/O Port Data Direction */
1872
register8_t OUT; /* I/O Port Output */
1873
register8_t IN; /* I/O Port Input */
1874
register8_t INTFLAGS; /* Interrupt Flag Register */
1875
} VPORT_t;
1876
1877
/*
1878
--------------------------------------------------------------------------
1879
PORT - Port Configuration
1880
--------------------------------------------------------------------------
1881
*/
1882
1883
/* I/O Ports */
1884
typedef struct PORT_struct
1885
{
1886
register8_t DIR; /* I/O Port Data Direction */
1887
register8_t DIRSET; /* I/O Port Data Direction Set */
1888
register8_t DIRCLR; /* I/O Port Data Direction Clear */
1889
register8_t DIRTGL; /* I/O Port Data Direction Toggle */
1890
register8_t OUT; /* I/O Port Output */
1891
register8_t OUTSET; /* I/O Port Output Set */
1892
register8_t OUTCLR; /* I/O Port Output Clear */
1893
register8_t OUTTGL; /* I/O Port Output Toggle */
1894
register8_t IN; /* I/O port Input */
1895
register8_t INTCTRL; /* Interrupt Control Register */
1896
register8_t INT0MASK; /* Port Interrupt 0 Mask */
1897
register8_t INT1MASK; /* Port Interrupt 1 Mask */
1898
register8_t INTFLAGS; /* Interrupt Flag Register */
1899
register8_t reserved_0x0D;
1900
register8_t reserved_0x0E;
1901
register8_t reserved_0x0F;
1902
register8_t PIN0CTRL; /* Pin 0 Control Register */
1903
register8_t PIN1CTRL; /* Pin 1 Control Register */
1904
register8_t PIN2CTRL; /* Pin 2 Control Register */
1905
register8_t PIN3CTRL; /* Pin 3 Control Register */
1906
register8_t PIN4CTRL; /* Pin 4 Control Register */
1907
register8_t PIN5CTRL; /* Pin 5 Control Register */
1908
register8_t PIN6CTRL; /* Pin 6 Control Register */
1909
register8_t PIN7CTRL; /* Pin 7 Control Register */
1910
} PORT_t;
1911
1912
/* Virtual Port 0 Mapping */
1913
typedef enum PORTCFG_VP0MAP_enum
1914
{
1915
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
1916
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
1917
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
1918
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
1919
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
1920
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
1921
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
1922
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
1923
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
1924
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
1925
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
1926
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
1927
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
1928
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
1929
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
1930
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
1931
} PORTCFG_VP0MAP_t;
1932
1933
/* Virtual Port 1 Mapping */
1934
typedef enum PORTCFG_VP1MAP_enum
1935
{
1936
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
1937
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
1938
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
1939
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
1940
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
1941
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
1942
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
1943
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
1944
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
1945
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
1946
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
1947
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
1948
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
1949
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
1950
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
1951
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
1952
} PORTCFG_VP1MAP_t;
1953
1954
/* Virtual Port 2 Mapping */
1955
typedef enum PORTCFG_VP2MAP_enum
1956
{
1957
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
1958
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
1959
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
1960
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
1961
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
1962
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
1963
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
1964
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
1965
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
1966
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
1967
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
1968
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
1969
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
1970
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
1971
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
1972
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
1973
} PORTCFG_VP2MAP_t;
1974
1975
/* Virtual Port 3 Mapping */
1976
typedef enum PORTCFG_VP3MAP_enum
1977
{
1978
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
1979
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
1980
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
1981
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
1982
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
1983
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
1984
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
1985
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
1986
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
1987
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
1988
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
1989
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
1990
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
1991
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
1992
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
1993
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
1994
} PORTCFG_VP3MAP_t;
1995
1996
/* Clock Output Port */
1997
typedef enum PORTCFG_CLKOUT_enum
1998
{
1999
PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */
2000
PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */
2001
PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */
2002
PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */
2003
} PORTCFG_CLKOUT_t;
2004
2005
/* Event Output Port */
2006
typedef enum PORTCFG_EVOUT_enum
2007
{
2008
PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
2009
PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
2010
PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
2011
PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
2012
} PORTCFG_EVOUT_t;
2013
2014
/* Port Interrupt 0 Level */
2015
typedef enum PORT_INT0LVL_enum
2016
{
2017
PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2018
PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
2019
PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
2020
PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
2021
} PORT_INT0LVL_t;
2022
2023
/* Port Interrupt 1 Level */
2024
typedef enum PORT_INT1LVL_enum
2025
{
2026
PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2027
PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
2028
PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
2029
PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
2030
} PORT_INT1LVL_t;
2031
2032
/* Output/Pull Configuration */
2033
typedef enum PORT_OPC_enum
2034
{
2035
PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
2036
PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
2037
PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
2038
PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
2039
PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
2040
PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
2041
PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
2042
PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
2043
} PORT_OPC_t;
2044
2045
/* Input/Sense Configuration */
2046
typedef enum PORT_ISC_enum
2047
{
2048
PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
2049
PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
2050
PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
2051
PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
2052
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
2053
} PORT_ISC_t;
2054
2055
2056
/*
2057
--------------------------------------------------------------------------
2058
TC - 16-bit Timer/Counter With PWM
2059
--------------------------------------------------------------------------
2060
*/
2061
2062
/* 16-bit Timer/Counter 0 */
2063
typedef struct TC0_struct
2064
{
2065
register8_t CTRLA; /* Control Register A */
2066
register8_t CTRLB; /* Control Register B */
2067
register8_t CTRLC; /* Control register C */
2068
register8_t CTRLD; /* Control Register D */
2069
register8_t CTRLE; /* Control Register E */
2070
register8_t reserved_0x05;
2071
register8_t INTCTRLA; /* Interrupt Control Register A */
2072
register8_t INTCTRLB; /* Interrupt Control Register B */
2073
register8_t CTRLFCLR; /* Control Register F Clear */
2074
register8_t CTRLFSET; /* Control Register F Set */
2075
register8_t CTRLGCLR; /* Control Register G Clear */
2076
register8_t CTRLGSET; /* Control Register G Set */
2077
register8_t INTFLAGS; /* Interrupt Flag Register */
2078
register8_t reserved_0x0D;
2079
register8_t reserved_0x0E;
2080
register8_t TEMP; /* Temporary Register For 16-bit Access */
2081
register8_t reserved_0x10;
2082
register8_t reserved_0x11;
2083
register8_t reserved_0x12;
2084
register8_t reserved_0x13;
2085
register8_t reserved_0x14;
2086
register8_t reserved_0x15;
2087
register8_t reserved_0x16;
2088
register8_t reserved_0x17;
2089
register8_t reserved_0x18;
2090
register8_t reserved_0x19;
2091
register8_t reserved_0x1A;
2092
register8_t reserved_0x1B;
2093
register8_t reserved_0x1C;
2094
register8_t reserved_0x1D;
2095
register8_t reserved_0x1E;
2096
register8_t reserved_0x1F;
2097
_WORDREGISTER(CNT); /* Count */
2098
register8_t reserved_0x22;
2099
register8_t reserved_0x23;
2100
register8_t reserved_0x24;
2101
register8_t reserved_0x25;
2102
_WORDREGISTER(PER); /* Period */
2103
_WORDREGISTER(CCA); /* Compare or Capture A */
2104
_WORDREGISTER(CCB); /* Compare or Capture B */
2105
_WORDREGISTER(CCC); /* Compare or Capture C */
2106
_WORDREGISTER(CCD); /* Compare or Capture D */
2107
register8_t reserved_0x30;
2108
register8_t reserved_0x31;
2109
register8_t reserved_0x32;
2110
register8_t reserved_0x33;
2111
register8_t reserved_0x34;
2112
register8_t reserved_0x35;
2113
_WORDREGISTER(PERBUF); /* Period Buffer */
2114
_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
2115
_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
2116
_WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
2117
_WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
2118
} TC0_t;
2119
2120
/*
2121
--------------------------------------------------------------------------
2122
TC - 16-bit Timer/Counter With PWM
2123
--------------------------------------------------------------------------
2124
*/
2125
2126
/* 16-bit Timer/Counter 1 */
2127
typedef struct TC1_struct
2128
{
2129
register8_t CTRLA; /* Control Register A */
2130
register8_t CTRLB; /* Control Register B */
2131
register8_t CTRLC; /* Control register C */
2132
register8_t CTRLD; /* Control Register D */
2133
register8_t CTRLE; /* Control Register E */
2134
register8_t reserved_0x05;
2135
register8_t INTCTRLA; /* Interrupt Control Register A */
2136
register8_t INTCTRLB; /* Interrupt Control Register B */
2137
register8_t CTRLFCLR; /* Control Register F Clear */
2138
register8_t CTRLFSET; /* Control Register F Set */
2139
register8_t CTRLGCLR; /* Control Register G Clear */
2140
register8_t CTRLGSET; /* Control Register G Set */
2141
register8_t INTFLAGS; /* Interrupt Flag Register */
2142
register8_t reserved_0x0D;
2143
register8_t reserved_0x0E;
2144
register8_t TEMP; /* Temporary Register For 16-bit Access */
2145
register8_t reserved_0x10;
2146
register8_t reserved_0x11;
2147
register8_t reserved_0x12;
2148
register8_t reserved_0x13;
2149
register8_t reserved_0x14;
2150
register8_t reserved_0x15;
2151
register8_t reserved_0x16;
2152
register8_t reserved_0x17;
2153
register8_t reserved_0x18;
2154
register8_t reserved_0x19;
2155
register8_t reserved_0x1A;
2156
register8_t reserved_0x1B;
2157
register8_t reserved_0x1C;
2158
register8_t reserved_0x1D;
2159
register8_t reserved_0x1E;
2160
register8_t reserved_0x1F;
2161
_WORDREGISTER(CNT); /* Count */
2162
register8_t reserved_0x22;
2163
register8_t reserved_0x23;
2164
register8_t reserved_0x24;
2165
register8_t reserved_0x25;
2166
_WORDREGISTER(PER); /* Period */
2167
_WORDREGISTER(CCA); /* Compare or Capture A */
2168
_WORDREGISTER(CCB); /* Compare or Capture B */
2169
register8_t reserved_0x2C;
2170
register8_t reserved_0x2D;
2171
register8_t reserved_0x2E;
2172
register8_t reserved_0x2F;
2173
register8_t reserved_0x30;
2174
register8_t reserved_0x31;
2175
register8_t reserved_0x32;
2176
register8_t reserved_0x33;
2177
register8_t reserved_0x34;
2178
register8_t reserved_0x35;
2179
_WORDREGISTER(PERBUF); /* Period Buffer */
2180
_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
2181
_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
2182
} TC1_t;
2183
2184
/*
2185
--------------------------------------------------------------------------
2186
TC - 16-bit Timer/Counter With PWM
2187
--------------------------------------------------------------------------
2188
*/
2189
2190
/* Advanced Waveform Extension */
2191
typedef struct AWEX_struct
2192
{
2193
register8_t CTRL; /* Control Register */
2194
register8_t reserved_0x01;
2195
register8_t FDEVMASK; /* Fault Detection Event Mask */
2196
register8_t FDCTRL; /* Fault Detection Control Register */
2197
register8_t STATUS; /* Status Register */
2198
register8_t reserved_0x05;
2199
register8_t DTBOTH; /* Dead Time Both Sides */
2200
register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
2201
register8_t DTLS; /* Dead Time Low Side */
2202
register8_t DTHS; /* Dead Time High Side */
2203
register8_t DTLSBUF; /* Dead Time Low Side Buffer */
2204
register8_t DTHSBUF; /* Dead Time High Side Buffer */
2205
register8_t OUTOVEN; /* Output Override Enable */
2206
} AWEX_t;
2207
2208
/*
2209
--------------------------------------------------------------------------
2210
TC - 16-bit Timer/Counter With PWM
2211
--------------------------------------------------------------------------
2212
*/
2213
2214
/* High-Resolution Extension */
2215
typedef struct HIRES_struct
2216
{
2217
register8_t CTRL; /* Control Register */
2218
} HIRES_t;
2219
2220
/* Clock Selection */
2221
typedef enum TC_CLKSEL_enum
2222
{
2223
TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
2224
TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
2225
TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
2226
TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
2227
TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
2228
TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
2229
TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
2230
TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
2231
TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
2232
TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
2233
TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
2234
TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
2235
TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
2236
TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
2237
TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
2238
TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
2239
} TC_CLKSEL_t;
2240
2241
/* Waveform Generation Mode */
2242
typedef enum TC_WGMODE_enum
2243
{
2244
TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
2245
TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
2246
TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
2247
TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
2248
TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
2249
TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
2250
} TC_WGMODE_t;
2251
2252
/* Event Action */
2253
typedef enum TC_EVACT_enum
2254
{
2255
TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
2256
TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
2257
TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
2258
TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
2259
TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
2260
TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */
2261
TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
2262
} TC_EVACT_t;
2263
2264
/* Event Selection */
2265
typedef enum TC_EVSEL_enum
2266
{
2267
TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
2268
TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
2269
TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
2270
TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
2271
TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
2272
TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
2273
TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
2274
TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
2275
TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
2276
} TC_EVSEL_t;
2277
2278
/* Error Interrupt Level */
2279
typedef enum TC_ERRINTLVL_enum
2280
{
2281
TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2282
TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
2283
TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2284
TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
2285
} TC_ERRINTLVL_t;
2286
2287
/* Overflow Interrupt Level */
2288
typedef enum TC_OVFINTLVL_enum
2289
{
2290
TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2291
TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
2292
TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2293
TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
2294
} TC_OVFINTLVL_t;
2295
2296
/* Compare or Capture D Interrupt Level */
2297
typedef enum TC_CCDINTLVL_enum
2298
{
2299
TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
2300
TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
2301
TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
2302
TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
2303
} TC_CCDINTLVL_t;
2304
2305
/* Compare or Capture C Interrupt Level */
2306
typedef enum TC_CCCINTLVL_enum
2307
{
2308
TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
2309
TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
2310
TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
2311
TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
2312
} TC_CCCINTLVL_t;
2313
2314
/* Compare or Capture B Interrupt Level */
2315
typedef enum TC_CCBINTLVL_enum
2316
{
2317
TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2318
TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
2319
TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2320
TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
2321
} TC_CCBINTLVL_t;
2322
2323
/* Compare or Capture A Interrupt Level */
2324
typedef enum TC_CCAINTLVL_enum
2325
{
2326
TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2327
TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
2328
TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2329
TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
2330
} TC_CCAINTLVL_t;
2331
2332
/* Timer/Counter Command */
2333
typedef enum TC_CMD_enum
2334
{
2335
TC_CMD_NONE_gc = (0x00<<2), /* No Command */
2336
TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
2337
TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
2338
TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
2339
} TC_CMD_t;
2340
2341
/* Fault Detect Action */
2342
typedef enum AWEX_FDACT_enum
2343
{
2344
AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
2345
AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
2346
AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
2347
} AWEX_FDACT_t;
2348
2349
/* High Resolution Enable */
2350
typedef enum HIRES_HREN_enum
2351
{
2352
HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
2353
HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
2354
HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
2355
HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
2356
} HIRES_HREN_t;
2357
2358
2359
/*
2360
--------------------------------------------------------------------------
2361
USART - Universal Asynchronous Receiver-Transmitter
2362
--------------------------------------------------------------------------
2363
*/
2364
2365
/* Universal Synchronous/Asynchronous Receiver/Transmitter */
2366
typedef struct USART_struct
2367
{
2368
register8_t DATA; /* Data Register */
2369
register8_t STATUS; /* Status Register */
2370
register8_t reserved_0x02;
2371
register8_t CTRLA; /* Control Register A */
2372
register8_t CTRLB; /* Control Register B */
2373
register8_t CTRLC; /* Control Register C */
2374
register8_t BAUDCTRLA; /* Baud Rate Control Register A */
2375
register8_t BAUDCTRLB; /* Baud Rate Control Register B */
2376
} USART_t;
2377
2378
/* Receive Complete Interrupt level */
2379
typedef enum USART_RXCINTLVL_enum
2380
{
2381
USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
2382
USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
2383
USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
2384
USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
2385
} USART_RXCINTLVL_t;
2386
2387
/* Transmit Complete Interrupt level */
2388
typedef enum USART_TXCINTLVL_enum
2389
{
2390
USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2391
USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
2392
USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2393
USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
2394
} USART_TXCINTLVL_t;
2395
2396
/* Data Register Empty Interrupt level */
2397
typedef enum USART_DREINTLVL_enum
2398
{
2399
USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2400
USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
2401
USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2402
USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
2403
} USART_DREINTLVL_t;
2404
2405
/* Character Size */
2406
typedef enum USART_CHSIZE_enum
2407
{
2408
USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
2409
USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
2410
USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
2411
USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
2412
USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
2413
} USART_CHSIZE_t;
2414
2415
/* Communication Mode */
2416
typedef enum USART_CMODE_enum
2417
{
2418
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
2419
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
2420
USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
2421
USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
2422
} USART_CMODE_t;
2423
2424
/* Parity Mode */
2425
typedef enum USART_PMODE_enum
2426
{
2427
USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
2428
USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
2429
USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
2430
} USART_PMODE_t;
2431
2432
2433
/*
2434
--------------------------------------------------------------------------
2435
SPI - Serial Peripheral Interface
2436
--------------------------------------------------------------------------
2437
*/
2438
2439
/* Serial Peripheral Interface */
2440
typedef struct SPI_struct
2441
{
2442
register8_t CTRL; /* Control Register */
2443
register8_t INTCTRL; /* Interrupt Control Register */
2444
register8_t STATUS; /* Status Register */
2445
register8_t DATA; /* Data Register */
2446
} SPI_t;
2447
2448
/* SPI Mode */
2449
typedef enum SPI_MODE_enum
2450
{
2451
SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
2452
SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
2453
SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
2454
SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
2455
} SPI_MODE_t;
2456
2457
/* Prescaler setting */
2458
typedef enum SPI_PRESCALER_enum
2459
{
2460
SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
2461
SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
2462
SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
2463
SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
2464
} SPI_PRESCALER_t;
2465
2466
/* Interrupt level */
2467
typedef enum SPI_INTLVL_enum
2468
{
2469
SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2470
SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
2471
SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
2472
SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
2473
} SPI_INTLVL_t;
2474
2475
2476
/*
2477
--------------------------------------------------------------------------
2478
IRCOM - IR Communication Module
2479
--------------------------------------------------------------------------
2480
*/
2481
2482
/* IR Communication Module */
2483
typedef struct IRCOM_struct
2484
{
2485
register8_t CTRL; /* Control Register */
2486
register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
2487
register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
2488
} IRCOM_t;
2489
2490
/* Event channel selection */
2491
typedef enum IRDA_EVSEL_enum
2492
{
2493
IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
2494
IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
2495
IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
2496
IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
2497
IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
2498
IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
2499
IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
2500
IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
2501
IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
2502
} IRDA_EVSEL_t;
2503
2504
2505
/*
2506
--------------------------------------------------------------------------
2507
AES - AES Module
2508
--------------------------------------------------------------------------
2509
*/
2510
2511
/* AES Module */
2512
typedef struct AES_struct
2513
{
2514
register8_t CTRL; /* AES Control Register */
2515
register8_t STATUS; /* AES Status Register */
2516
register8_t STATE; /* AES State Register */
2517
register8_t KEY; /* AES Key Register */
2518
register8_t INTCTRL; /* AES Interrupt Control Register */
2519
} AES_t;
2520
2521
/* Interrupt level */
2522
typedef enum AES_INTLVL_enum
2523
{
2524
AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2525
AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
2526
AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
2527
AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
2528
} AES_INTLVL_t;
2529
2530
2531
2532
/*
2533
==========================================================================
2534
IO Module Instances. Mapped to memory.
2535
==========================================================================
2536
*/
2537
2538
#define GPIO (*(GPIO_t *) 0x0000) /* General Purpose IO Registers */
2539
#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
2540
#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
2541
#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
2542
#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
2543
#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
2544
#define CPU (*(CPU_t *) 0x0030) /* CPU Registers */
2545
#define CLK (*(CLK_t *) 0x0040) /* Clock System */
2546
#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
2547
#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
2548
#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
2549
#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
2550
#define PR (*(PR_t *) 0x0070) /* Power Reduction */
2551
#define RST (*(RST_t *) 0x0078) /* Reset Controller */
2552
#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
2553
#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
2554
#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
2555
#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
2556
#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */
2557
#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
2558
#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
2559
#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
2560
#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
2561
#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */
2562
#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */
2563
#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
2564
#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */
2565
#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
2566
#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
2567
#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */
2568
#define PORTA (*(PORT_t *) 0x0600) /* Port A */
2569
#define PORTB (*(PORT_t *) 0x0620) /* Port B */
2570
#define PORTC (*(PORT_t *) 0x0640) /* Port C */
2571
#define PORTD (*(PORT_t *) 0x0660) /* Port D */
2572
#define PORTE (*(PORT_t *) 0x0680) /* Port E */
2573
#define PORTF (*(PORT_t *) 0x06A0) /* Port F */
2574
#define PORTR (*(PORT_t *) 0x07E0) /* Port R */
2575
#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
2576
#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
2577
#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
2578
#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
2579
#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
2580
#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */
2581
#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
2582
#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
2583
#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
2584
#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */
2585
#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */
2586
#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
2587
#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */
2588
#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
2589
#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
2590
#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */
2591
#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */
2592
#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */
2593
#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
2594
#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */
2595
#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */
2596
#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */
2597
#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */
2598
#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */
2599
#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */
2600
#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */
2601
2602
2603
#endif /* !defined (__ASSEMBLER__) */
2604
2605
2606
/* ========== Flattened fully qualified IO register names ========== */
2607
2608
/* GPIO - General Purpose IO Registers */
2609
#define GPIO_GPIO0 _SFR_MEM8(0x0000)
2610
#define GPIO_GPIO1 _SFR_MEM8(0x0001)
2611
#define GPIO_GPIO2 _SFR_MEM8(0x0002)
2612
#define GPIO_GPIO3 _SFR_MEM8(0x0003)
2613
#define GPIO_GPIO4 _SFR_MEM8(0x0004)
2614
#define GPIO_GPIO5 _SFR_MEM8(0x0005)
2615
#define GPIO_GPIO6 _SFR_MEM8(0x0006)
2616
#define GPIO_GPIO7 _SFR_MEM8(0x0007)
2617
#define GPIO_GPIO8 _SFR_MEM8(0x0008)
2618
#define GPIO_GPIO9 _SFR_MEM8(0x0009)
2619
#define GPIO_GPIOA _SFR_MEM8(0x000A)
2620
#define GPIO_GPIOB _SFR_MEM8(0x000B)
2621
#define GPIO_GPIOC _SFR_MEM8(0x000C)
2622
#define GPIO_GPIOD _SFR_MEM8(0x000D)
2623
#define GPIO_GPIOE _SFR_MEM8(0x000E)
2624
#define GPIO_GPIOF _SFR_MEM8(0x000F)
2625
2626
/* VPORT0 - Virtual Port 0 */
2627
#define VPORT0_DIR _SFR_MEM8(0x0010)
2628
#define VPORT0_OUT _SFR_MEM8(0x0011)
2629
#define VPORT0_IN _SFR_MEM8(0x0012)
2630
#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
2631
2632
/* VPORT1 - Virtual Port 1 */
2633
#define VPORT1_DIR _SFR_MEM8(0x0014)
2634
#define VPORT1_OUT _SFR_MEM8(0x0015)
2635
#define VPORT1_IN _SFR_MEM8(0x0016)
2636
#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
2637
2638
/* VPORT2 - Virtual Port 2 */
2639
#define VPORT2_DIR _SFR_MEM8(0x0018)
2640
#define VPORT2_OUT _SFR_MEM8(0x0019)
2641
#define VPORT2_IN _SFR_MEM8(0x001A)
2642
#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
2643
2644
/* VPORT3 - Virtual Port 3 */
2645
#define VPORT3_DIR _SFR_MEM8(0x001C)
2646
#define VPORT3_OUT _SFR_MEM8(0x001D)
2647
#define VPORT3_IN _SFR_MEM8(0x001E)
2648
#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
2649
2650
/* OCD - On-Chip Debug System */
2651
#define OCD_OCDR0 _SFR_MEM8(0x002E)
2652
#define OCD_OCDR1 _SFR_MEM8(0x002F)
2653
2654
/* CPU - CPU Registers */
2655
#define CPU_CCP _SFR_MEM8(0x0034)
2656
#define CPU_RAMPD _SFR_MEM8(0x0038)
2657
#define CPU_RAMPX _SFR_MEM8(0x0039)
2658
#define CPU_RAMPY _SFR_MEM8(0x003A)
2659
#define CPU_RAMPZ _SFR_MEM8(0x003B)
2660
#define CPU_EIND _SFR_MEM8(0x003C)
2661
#define CPU_SPL _SFR_MEM8(0x003D)
2662
#define CPU_SPH _SFR_MEM8(0x003E)
2663
#define CPU_SREG _SFR_MEM8(0x003F)
2664
2665
/* CLK - Clock System */
2666
#define CLK_CTRL _SFR_MEM8(0x0040)
2667
#define CLK_PSCTRL _SFR_MEM8(0x0041)
2668
#define CLK_LOCK _SFR_MEM8(0x0042)
2669
#define CLK_RTCCTRL _SFR_MEM8(0x0043)
2670
2671
/* SLEEP - Sleep Controller */
2672
#define SLEEP_CTRL _SFR_MEM8(0x0048)
2673
2674
/* OSC - Oscillator Control */
2675
#define OSC_CTRL _SFR_MEM8(0x0050)
2676
#define OSC_STATUS _SFR_MEM8(0x0051)
2677
#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
2678
#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
2679
#define OSC_RC32KCAL _SFR_MEM8(0x0054)
2680
#define OSC_PLLCTRL _SFR_MEM8(0x0055)
2681
#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
2682
2683
/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
2684
#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
2685
#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
2686
#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
2687
#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
2688
#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
2689
#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
2690
2691
/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
2692
#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
2693
#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
2694
#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
2695
#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
2696
#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
2697
#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
2698
2699
/* PR - Power Reduction */
2700
#define PR_PRGEN _SFR_MEM8(0x0070)
2701
#define PR_PRPA _SFR_MEM8(0x0071)
2702
#define PR_PRPB _SFR_MEM8(0x0072)
2703
#define PR_PRPC _SFR_MEM8(0x0073)
2704
#define PR_PRPD _SFR_MEM8(0x0074)
2705
#define PR_PRPE _SFR_MEM8(0x0075)
2706
#define PR_PRPF _SFR_MEM8(0x0076)
2707
2708
/* RST - Reset Controller */
2709
#define RST_STATUS _SFR_MEM8(0x0078)
2710
#define RST_CTRL _SFR_MEM8(0x0079)
2711
2712
/* WDT - Watch-Dog Timer */
2713
#define WDT_CTRL _SFR_MEM8(0x0080)
2714
#define WDT_WINCTRL _SFR_MEM8(0x0081)
2715
#define WDT_STATUS _SFR_MEM8(0x0082)
2716
2717
/* MCU - MCU Control */
2718
#define MCU_DEVID0 _SFR_MEM8(0x0090)
2719
#define MCU_DEVID1 _SFR_MEM8(0x0091)
2720
#define MCU_DEVID2 _SFR_MEM8(0x0092)
2721
#define MCU_REVID _SFR_MEM8(0x0093)
2722
#define MCU_JTAGUID _SFR_MEM8(0x0094)
2723
#define MCU_MCUCR _SFR_MEM8(0x0096)
2724
#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
2725
#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
2726
2727
/* PMIC - Programmable Interrupt Controller */
2728
#define PMIC_STATUS _SFR_MEM8(0x00A0)
2729
#define PMIC_INTPRI _SFR_MEM8(0x00A1)
2730
#define PMIC_CTRL _SFR_MEM8(0x00A2)
2731
2732
/* PORTCFG - Port Configuration */
2733
#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
2734
#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
2735
#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
2736
#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
2737
2738
/* AES - AES Crypto Module */
2739
#define AES_CTRL _SFR_MEM8(0x00C0)
2740
#define AES_STATUS _SFR_MEM8(0x00C1)
2741
#define AES_STATE _SFR_MEM8(0x00C2)
2742
#define AES_KEY _SFR_MEM8(0x00C3)
2743
#define AES_INTCTRL _SFR_MEM8(0x00C4)
2744
2745
/* DMA - DMA Controller */
2746
#define DMA_CTRL _SFR_MEM8(0x0100)
2747
#define DMA_INTFLAGS _SFR_MEM8(0x0103)
2748
#define DMA_STATUS _SFR_MEM8(0x0104)
2749
#define DMA_TEMP _SFR_MEM16(0x0106)
2750
#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
2751
#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
2752
#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
2753
#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
2754
#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
2755
#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
2756
#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
2757
#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
2758
#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
2759
#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
2760
#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
2761
#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
2762
#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
2763
#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
2764
#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
2765
#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
2766
#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
2767
#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
2768
#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
2769
#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
2770
#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
2771
#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
2772
#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
2773
#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
2774
#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
2775
#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
2776
#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
2777
#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
2778
#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
2779
#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
2780
#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
2781
#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
2782
#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
2783
#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
2784
#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
2785
#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
2786
#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
2787
#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
2788
#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
2789
#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
2790
#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
2791
#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
2792
#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
2793
#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
2794
#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
2795
#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
2796
#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
2797
#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
2798
2799
/* EVSYS - Event System */
2800
#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
2801
#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
2802
#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
2803
#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
2804
#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
2805
#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
2806
#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
2807
#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
2808
#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
2809
#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
2810
#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
2811
#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
2812
#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
2813
#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
2814
#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
2815
#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
2816
#define EVSYS_STROBE _SFR_MEM8(0x0190)
2817
#define EVSYS_DATA _SFR_MEM8(0x0191)
2818
2819
/* NVM - Non Volatile Memory Controller */
2820
#define NVM_ADDR0 _SFR_MEM8(0x01C0)
2821
#define NVM_ADDR1 _SFR_MEM8(0x01C1)
2822
#define NVM_ADDR2 _SFR_MEM8(0x01C2)
2823
#define NVM_DATA0 _SFR_MEM8(0x01C4)
2824
#define NVM_DATA1 _SFR_MEM8(0x01C5)
2825
#define NVM_DATA2 _SFR_MEM8(0x01C6)
2826
#define NVM_CMD _SFR_MEM8(0x01CA)
2827
#define NVM_CTRLA _SFR_MEM8(0x01CB)
2828
#define NVM_CTRLB _SFR_MEM8(0x01CC)
2829
#define NVM_INTCTRL _SFR_MEM8(0x01CD)
2830
#define NVM_STATUS _SFR_MEM8(0x01CF)
2831
#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
2832
2833
/* ADCA - Analog to Digital Converter A */
2834
#define ADCA_CTRLA _SFR_MEM8(0x0200)
2835
#define ADCA_CTRLB _SFR_MEM8(0x0201)
2836
#define ADCA_REFCTRL _SFR_MEM8(0x0202)
2837
#define ADCA_EVCTRL _SFR_MEM8(0x0203)
2838
#define ADCA_PRESCALER _SFR_MEM8(0x0204)
2839
#define ADCA_CALCTRL _SFR_MEM8(0x0205)
2840
#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
2841
#define ADCA_CAL _SFR_MEM16(0x020C)
2842
#define ADCA_CH0RES _SFR_MEM16(0x0210)
2843
#define ADCA_CH1RES _SFR_MEM16(0x0212)
2844
#define ADCA_CH2RES _SFR_MEM16(0x0214)
2845
#define ADCA_CH3RES _SFR_MEM16(0x0216)
2846
#define ADCA_CMP _SFR_MEM16(0x0218)
2847
#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
2848
#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
2849
#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
2850
#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
2851
#define ADCA_CH0_RES _SFR_MEM16(0x0224)
2852
#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
2853
#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
2854
#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
2855
#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
2856
#define ADCA_CH1_RES _SFR_MEM16(0x022C)
2857
#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
2858
#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
2859
#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
2860
#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
2861
#define ADCA_CH2_RES _SFR_MEM16(0x0234)
2862
#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
2863
#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
2864
#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
2865
#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
2866
#define ADCA_CH3_RES _SFR_MEM16(0x023C)
2867
2868
/* ADCB - Analog to Digital Converter B */
2869
#define ADCB_CTRLA _SFR_MEM8(0x0240)
2870
#define ADCB_CTRLB _SFR_MEM8(0x0241)
2871
#define ADCB_REFCTRL _SFR_MEM8(0x0242)
2872
#define ADCB_EVCTRL _SFR_MEM8(0x0243)
2873
#define ADCB_PRESCALER _SFR_MEM8(0x0244)
2874
#define ADCB_CALCTRL _SFR_MEM8(0x0245)
2875
#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
2876
#define ADCB_CAL _SFR_MEM16(0x024C)
2877
#define ADCB_CH0RES _SFR_MEM16(0x0250)
2878
#define ADCB_CH1RES _SFR_MEM16(0x0252)
2879
#define ADCB_CH2RES _SFR_MEM16(0x0254)
2880
#define ADCB_CH3RES _SFR_MEM16(0x0256)
2881
#define ADCB_CMP _SFR_MEM16(0x0258)
2882
#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
2883
#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
2884
#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
2885
#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
2886
#define ADCB_CH0_RES _SFR_MEM16(0x0264)
2887
#define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
2888
#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
2889
#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
2890
#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
2891
#define ADCB_CH1_RES _SFR_MEM16(0x026C)
2892
#define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
2893
#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
2894
#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
2895
#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
2896
#define ADCB_CH2_RES _SFR_MEM16(0x0274)
2897
#define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
2898
#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
2899
#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
2900
#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
2901
#define ADCB_CH3_RES _SFR_MEM16(0x027C)
2902
2903
/* DACB - Digital to Analog Converter B */
2904
#define DACB_CTRLA _SFR_MEM8(0x0320)
2905
#define DACB_CTRLB _SFR_MEM8(0x0321)
2906
#define DACB_CTRLC _SFR_MEM8(0x0322)
2907
#define DACB_EVCTRL _SFR_MEM8(0x0323)
2908
#define DACB_TIMCTRL _SFR_MEM8(0x0324)
2909
#define DACB_STATUS _SFR_MEM8(0x0325)
2910
#define DACB_GAINCAL _SFR_MEM8(0x0328)
2911
#define DACB_OFFSETCAL _SFR_MEM8(0x0329)
2912
#define DACB_CH0DATA _SFR_MEM16(0x0338)
2913
#define DACB_CH1DATA _SFR_MEM16(0x033A)
2914
2915
/* ACA - Analog Comparator A */
2916
#define ACA_AC0CTRL _SFR_MEM8(0x0380)
2917
#define ACA_AC1CTRL _SFR_MEM8(0x0381)
2918
#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
2919
#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
2920
#define ACA_CTRLA _SFR_MEM8(0x0384)
2921
#define ACA_CTRLB _SFR_MEM8(0x0385)
2922
#define ACA_WINCTRL _SFR_MEM8(0x0386)
2923
#define ACA_STATUS _SFR_MEM8(0x0387)
2924
2925
/* ACB - Analog Comparator B */
2926
#define ACB_AC0CTRL _SFR_MEM8(0x0390)
2927
#define ACB_AC1CTRL _SFR_MEM8(0x0391)
2928
#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
2929
#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
2930
#define ACB_CTRLA _SFR_MEM8(0x0394)
2931
#define ACB_CTRLB _SFR_MEM8(0x0395)
2932
#define ACB_WINCTRL _SFR_MEM8(0x0396)
2933
#define ACB_STATUS _SFR_MEM8(0x0397)
2934
2935
/* RTC - Real-Time Counter */
2936
#define RTC_CTRL _SFR_MEM8(0x0400)
2937
#define RTC_STATUS _SFR_MEM8(0x0401)
2938
#define RTC_INTCTRL _SFR_MEM8(0x0402)
2939
#define RTC_INTFLAGS _SFR_MEM8(0x0403)
2940
#define RTC_TEMP _SFR_MEM8(0x0404)
2941
#define RTC_CNT _SFR_MEM16(0x0408)
2942
#define RTC_PER _SFR_MEM16(0x040A)
2943
#define RTC_COMP _SFR_MEM16(0x040C)
2944
2945
/* TWIC - Two-Wire Interface C */
2946
#define TWIC_CTRL _SFR_MEM8(0x0480)
2947
#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
2948
#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
2949
#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
2950
#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
2951
#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
2952
#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
2953
#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
2954
#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
2955
#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
2956
#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
2957
#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
2958
#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
2959
#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
2960
2961
/* TWIE - Two-Wire Interface E */
2962
#define TWIE_CTRL _SFR_MEM8(0x04A0)
2963
#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
2964
#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
2965
#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
2966
#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
2967
#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
2968
#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
2969
#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
2970
#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
2971
#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
2972
#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
2973
#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
2974
#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
2975
#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
2976
2977
/* PORTA - Port A */
2978
#define PORTA_DIR _SFR_MEM8(0x0600)
2979
#define PORTA_DIRSET _SFR_MEM8(0x0601)
2980
#define PORTA_DIRCLR _SFR_MEM8(0x0602)
2981
#define PORTA_DIRTGL _SFR_MEM8(0x0603)
2982
#define PORTA_OUT _SFR_MEM8(0x0604)
2983
#define PORTA_OUTSET _SFR_MEM8(0x0605)
2984
#define PORTA_OUTCLR _SFR_MEM8(0x0606)
2985
#define PORTA_OUTTGL _SFR_MEM8(0x0607)
2986
#define PORTA_IN _SFR_MEM8(0x0608)
2987
#define PORTA_INTCTRL _SFR_MEM8(0x0609)
2988
#define PORTA_INT0MASK _SFR_MEM8(0x060A)
2989
#define PORTA_INT1MASK _SFR_MEM8(0x060B)
2990
#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
2991
#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
2992
#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
2993
#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
2994
#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
2995
#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
2996
#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
2997
#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
2998
#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
2999
3000
/* PORTB - Port B */
3001
#define PORTB_DIR _SFR_MEM8(0x0620)
3002
#define PORTB_DIRSET _SFR_MEM8(0x0621)
3003
#define PORTB_DIRCLR _SFR_MEM8(0x0622)
3004
#define PORTB_DIRTGL _SFR_MEM8(0x0623)
3005
#define PORTB_OUT _SFR_MEM8(0x0624)
3006
#define PORTB_OUTSET _SFR_MEM8(0x0625)
3007
#define PORTB_OUTCLR _SFR_MEM8(0x0626)
3008
#define PORTB_OUTTGL _SFR_MEM8(0x0627)
3009
#define PORTB_IN _SFR_MEM8(0x0628)
3010
#define PORTB_INTCTRL _SFR_MEM8(0x0629)
3011
#define PORTB_INT0MASK _SFR_MEM8(0x062A)
3012
#define PORTB_INT1MASK _SFR_MEM8(0x062B)
3013
#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
3014
#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
3015
#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
3016
#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
3017
#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
3018
#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
3019
#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
3020
#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
3021
#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
3022
3023
/* PORTC - Port C */
3024
#define PORTC_DIR _SFR_MEM8(0x0640)
3025
#define PORTC_DIRSET _SFR_MEM8(0x0641)
3026
#define PORTC_DIRCLR _SFR_MEM8(0x0642)
3027
#define PORTC_DIRTGL _SFR_MEM8(0x0643)
3028
#define PORTC_OUT _SFR_MEM8(0x0644)
3029
#define PORTC_OUTSET _SFR_MEM8(0x0645)
3030
#define PORTC_OUTCLR _SFR_MEM8(0x0646)
3031
#define PORTC_OUTTGL _SFR_MEM8(0x0647)
3032
#define PORTC_IN _SFR_MEM8(0x0648)
3033
#define PORTC_INTCTRL _SFR_MEM8(0x0649)
3034
#define PORTC_INT0MASK _SFR_MEM8(0x064A)
3035
#define PORTC_INT1MASK _SFR_MEM8(0x064B)
3036
#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
3037
#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
3038
#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
3039
#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
3040
#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
3041
#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
3042
#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
3043
#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
3044
#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
3045
3046
/* PORTD - Port D */
3047
#define PORTD_DIR _SFR_MEM8(0x0660)
3048
#define PORTD_DIRSET _SFR_MEM8(0x0661)
3049
#define PORTD_DIRCLR _SFR_MEM8(0x0662)
3050
#define PORTD_DIRTGL _SFR_MEM8(0x0663)
3051
#define PORTD_OUT _SFR_MEM8(0x0664)
3052
#define PORTD_OUTSET _SFR_MEM8(0x0665)
3053
#define PORTD_OUTCLR _SFR_MEM8(0x0666)
3054
#define PORTD_OUTTGL _SFR_MEM8(0x0667)
3055
#define PORTD_IN _SFR_MEM8(0x0668)
3056
#define PORTD_INTCTRL _SFR_MEM8(0x0669)
3057
#define PORTD_INT0MASK _SFR_MEM8(0x066A)
3058
#define PORTD_INT1MASK _SFR_MEM8(0x066B)
3059
#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
3060
#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
3061
#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
3062
#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
3063
#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
3064
#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
3065
#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
3066
#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
3067
#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
3068
3069
/* PORTE - Port E */
3070
#define PORTE_DIR _SFR_MEM8(0x0680)
3071
#define PORTE_DIRSET _SFR_MEM8(0x0681)
3072
#define PORTE_DIRCLR _SFR_MEM8(0x0682)
3073
#define PORTE_DIRTGL _SFR_MEM8(0x0683)
3074
#define PORTE_OUT _SFR_MEM8(0x0684)
3075
#define PORTE_OUTSET _SFR_MEM8(0x0685)
3076
#define PORTE_OUTCLR _SFR_MEM8(0x0686)
3077
#define PORTE_OUTTGL _SFR_MEM8(0x0687)
3078
#define PORTE_IN _SFR_MEM8(0x0688)
3079
#define PORTE_INTCTRL _SFR_MEM8(0x0689)
3080
#define PORTE_INT0MASK _SFR_MEM8(0x068A)
3081
#define PORTE_INT1MASK _SFR_MEM8(0x068B)
3082
#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
3083
#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
3084
#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
3085
#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
3086
#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
3087
#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
3088
#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
3089
#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
3090
#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
3091
3092
/* PORTF - Port F */
3093
#define PORTF_DIR _SFR_MEM8(0x06A0)
3094
#define PORTF_DIRSET _SFR_MEM8(0x06A1)
3095
#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
3096
#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
3097
#define PORTF_OUT _SFR_MEM8(0x06A4)
3098
#define PORTF_OUTSET _SFR_MEM8(0x06A5)
3099
#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
3100
#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
3101
#define PORTF_IN _SFR_MEM8(0x06A8)
3102
#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
3103
#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
3104
#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
3105
#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
3106
#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
3107
#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
3108
#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
3109
#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
3110
#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
3111
#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
3112
#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
3113
#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
3114
3115
/* PORTR - Port R */
3116
#define PORTR_DIR _SFR_MEM8(0x07E0)
3117
#define PORTR_DIRSET _SFR_MEM8(0x07E1)
3118
#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
3119
#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
3120
#define PORTR_OUT _SFR_MEM8(0x07E4)
3121
#define PORTR_OUTSET _SFR_MEM8(0x07E5)
3122
#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
3123
#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
3124
#define PORTR_IN _SFR_MEM8(0x07E8)
3125
#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
3126
#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
3127
#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
3128
#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
3129
#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
3130
#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
3131
#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
3132
#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
3133
#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
3134
#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
3135
#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
3136
#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
3137
3138
/* TCC0 - Timer/Counter C0 */
3139
#define TCC0_CTRLA _SFR_MEM8(0x0800)
3140
#define TCC0_CTRLB _SFR_MEM8(0x0801)
3141
#define TCC0_CTRLC _SFR_MEM8(0x0802)
3142
#define TCC0_CTRLD _SFR_MEM8(0x0803)
3143
#define TCC0_CTRLE _SFR_MEM8(0x0804)
3144
#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
3145
#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
3146
#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
3147
#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
3148
#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
3149
#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
3150
#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
3151
#define TCC0_TEMP _SFR_MEM8(0x080F)
3152
#define TCC0_CNT _SFR_MEM16(0x0820)
3153
#define TCC0_PER _SFR_MEM16(0x0826)
3154
#define TCC0_CCA _SFR_MEM16(0x0828)
3155
#define TCC0_CCB _SFR_MEM16(0x082A)
3156
#define TCC0_CCC _SFR_MEM16(0x082C)
3157
#define TCC0_CCD _SFR_MEM16(0x082E)
3158
#define TCC0_PERBUF _SFR_MEM16(0x0836)
3159
#define TCC0_CCABUF _SFR_MEM16(0x0838)
3160
#define TCC0_CCBBUF _SFR_MEM16(0x083A)
3161
#define TCC0_CCCBUF _SFR_MEM16(0x083C)
3162
#define TCC0_CCDBUF _SFR_MEM16(0x083E)
3163
3164
/* TCC1 - Timer/Counter C1 */
3165
#define TCC1_CTRLA _SFR_MEM8(0x0840)
3166
#define TCC1_CTRLB _SFR_MEM8(0x0841)
3167
#define TCC1_CTRLC _SFR_MEM8(0x0842)
3168
#define TCC1_CTRLD _SFR_MEM8(0x0843)
3169
#define TCC1_CTRLE _SFR_MEM8(0x0844)
3170
#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
3171
#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
3172
#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
3173
#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
3174
#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
3175
#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
3176
#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
3177
#define TCC1_TEMP _SFR_MEM8(0x084F)
3178
#define TCC1_CNT _SFR_MEM16(0x0860)
3179
#define TCC1_PER _SFR_MEM16(0x0866)
3180
#define TCC1_CCA _SFR_MEM16(0x0868)
3181
#define TCC1_CCB _SFR_MEM16(0x086A)
3182
#define TCC1_PERBUF _SFR_MEM16(0x0876)
3183
#define TCC1_CCABUF _SFR_MEM16(0x0878)
3184
#define TCC1_CCBBUF _SFR_MEM16(0x087A)
3185
3186
/* AWEXC - Advanced Waveform Extension C */
3187
#define AWEXC_CTRL _SFR_MEM8(0x0880)
3188
#define AWEXC_FDEVMASK _SFR_MEM8(0x0882)
3189
#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
3190
#define AWEXC_STATUS _SFR_MEM8(0x0884)
3191
#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
3192
#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
3193
#define AWEXC_DTLS _SFR_MEM8(0x0888)
3194
#define AWEXC_DTHS _SFR_MEM8(0x0889)
3195
#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
3196
#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
3197
#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
3198
3199
/* HIRESC - High-Resolution Extension C */
3200
#define HIRESC_CTRL _SFR_MEM8(0x0890)
3201
3202
/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
3203
#define USARTC0_DATA _SFR_MEM8(0x08A0)
3204
#define USARTC0_STATUS _SFR_MEM8(0x08A1)
3205
#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
3206
#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
3207
#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
3208
#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
3209
#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
3210
3211
/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
3212
#define USARTC1_DATA _SFR_MEM8(0x08B0)
3213
#define USARTC1_STATUS _SFR_MEM8(0x08B1)
3214
#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
3215
#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
3216
#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
3217
#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
3218
#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
3219
3220
/* SPIC - Serial Peripheral Interface C */
3221
#define SPIC_CTRL _SFR_MEM8(0x08C0)
3222
#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
3223
#define SPIC_STATUS _SFR_MEM8(0x08C2)
3224
#define SPIC_DATA _SFR_MEM8(0x08C3)
3225
3226
/* IRCOM - IR Communication Module */
3227
#define IRCOM_CTRL _SFR_MEM8(0x08F8)
3228
#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
3229
#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
3230
3231
/* TCD0 - Timer/Counter D0 */
3232
#define TCD0_CTRLA _SFR_MEM8(0x0900)
3233
#define TCD0_CTRLB _SFR_MEM8(0x0901)
3234
#define TCD0_CTRLC _SFR_MEM8(0x0902)
3235
#define TCD0_CTRLD _SFR_MEM8(0x0903)
3236
#define TCD0_CTRLE _SFR_MEM8(0x0904)
3237
#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
3238
#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
3239
#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
3240
#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
3241
#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
3242
#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
3243
#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
3244
#define TCD0_TEMP _SFR_MEM8(0x090F)
3245
#define TCD0_CNT _SFR_MEM16(0x0920)
3246
#define TCD0_PER _SFR_MEM16(0x0926)
3247
#define TCD0_CCA _SFR_MEM16(0x0928)
3248
#define TCD0_CCB _SFR_MEM16(0x092A)
3249
#define TCD0_CCC _SFR_MEM16(0x092C)
3250
#define TCD0_CCD _SFR_MEM16(0x092E)
3251
#define TCD0_PERBUF _SFR_MEM16(0x0936)
3252
#define TCD0_CCABUF _SFR_MEM16(0x0938)
3253
#define TCD0_CCBBUF _SFR_MEM16(0x093A)
3254
#define TCD0_CCCBUF _SFR_MEM16(0x093C)
3255
#define TCD0_CCDBUF _SFR_MEM16(0x093E)
3256
3257
/* TCD1 - Timer/Counter D1 */
3258
#define TCD1_CTRLA _SFR_MEM8(0x0940)
3259
#define TCD1_CTRLB _SFR_MEM8(0x0941)
3260
#define TCD1_CTRLC _SFR_MEM8(0x0942)
3261
#define TCD1_CTRLD _SFR_MEM8(0x0943)
3262
#define TCD1_CTRLE _SFR_MEM8(0x0944)
3263
#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
3264
#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
3265
#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
3266
#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
3267
#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
3268
#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
3269
#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
3270
#define TCD1_TEMP _SFR_MEM8(0x094F)
3271
#define TCD1_CNT _SFR_MEM16(0x0960)
3272
#define TCD1_PER _SFR_MEM16(0x0966)
3273
#define TCD1_CCA _SFR_MEM16(0x0968)
3274
#define TCD1_CCB _SFR_MEM16(0x096A)
3275
#define TCD1_PERBUF _SFR_MEM16(0x0976)
3276
#define TCD1_CCABUF _SFR_MEM16(0x0978)
3277
#define TCD1_CCBBUF _SFR_MEM16(0x097A)
3278
3279
/* HIRESD - High-Resolution Extension D */
3280
#define HIRESD_CTRL _SFR_MEM8(0x0990)
3281
3282
/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
3283
#define USARTD0_DATA _SFR_MEM8(0x09A0)
3284
#define USARTD0_STATUS _SFR_MEM8(0x09A1)
3285
#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
3286
#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
3287
#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
3288
#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
3289
#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
3290
3291
/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
3292
#define USARTD1_DATA _SFR_MEM8(0x09B0)
3293
#define USARTD1_STATUS _SFR_MEM8(0x09B1)
3294
#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
3295
#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
3296
#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
3297
#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
3298
#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
3299
3300
/* SPID - Serial Peripheral Interface D */
3301
#define SPID_CTRL _SFR_MEM8(0x09C0)
3302
#define SPID_INTCTRL _SFR_MEM8(0x09C1)
3303
#define SPID_STATUS _SFR_MEM8(0x09C2)
3304
#define SPID_DATA _SFR_MEM8(0x09C3)
3305
3306
/* TCE0 - Timer/Counter E0 */
3307
#define TCE0_CTRLA _SFR_MEM8(0x0A00)
3308
#define TCE0_CTRLB _SFR_MEM8(0x0A01)
3309
#define TCE0_CTRLC _SFR_MEM8(0x0A02)
3310
#define TCE0_CTRLD _SFR_MEM8(0x0A03)
3311
#define TCE0_CTRLE _SFR_MEM8(0x0A04)
3312
#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
3313
#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
3314
#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
3315
#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
3316
#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
3317
#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
3318
#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
3319
#define TCE0_TEMP _SFR_MEM8(0x0A0F)
3320
#define TCE0_CNT _SFR_MEM16(0x0A20)
3321
#define TCE0_PER _SFR_MEM16(0x0A26)
3322
#define TCE0_CCA _SFR_MEM16(0x0A28)
3323
#define TCE0_CCB _SFR_MEM16(0x0A2A)
3324
#define TCE0_CCC _SFR_MEM16(0x0A2C)
3325
#define TCE0_CCD _SFR_MEM16(0x0A2E)
3326
#define TCE0_PERBUF _SFR_MEM16(0x0A36)
3327
#define TCE0_CCABUF _SFR_MEM16(0x0A38)
3328
#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
3329
#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
3330
#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
3331
3332
/* TCE1 - Timer/Counter E1 */
3333
#define TCE1_CTRLA _SFR_MEM8(0x0A40)
3334
#define TCE1_CTRLB _SFR_MEM8(0x0A41)
3335
#define TCE1_CTRLC _SFR_MEM8(0x0A42)
3336
#define TCE1_CTRLD _SFR_MEM8(0x0A43)
3337
#define TCE1_CTRLE _SFR_MEM8(0x0A44)
3338
#define TCE1_INTCTRLA _SFR_MEM8(0x0A46)
3339
#define TCE1_INTCTRLB _SFR_MEM8(0x0A47)
3340
#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48)
3341
#define TCE1_CTRLFSET _SFR_MEM8(0x0A49)
3342
#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A)
3343
#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B)
3344
#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C)
3345
#define TCE1_TEMP _SFR_MEM8(0x0A4F)
3346
#define TCE1_CNT _SFR_MEM16(0x0A60)
3347
#define TCE1_PER _SFR_MEM16(0x0A66)
3348
#define TCE1_CCA _SFR_MEM16(0x0A68)
3349
#define TCE1_CCB _SFR_MEM16(0x0A6A)
3350
#define TCE1_PERBUF _SFR_MEM16(0x0A76)
3351
#define TCE1_CCABUF _SFR_MEM16(0x0A78)
3352
#define TCE1_CCBBUF _SFR_MEM16(0x0A7A)
3353
3354
/* AWEXE - Advanced Waveform Extension E */
3355
#define AWEXE_CTRL _SFR_MEM8(0x0A80)
3356
#define AWEXE_FDEVMASK _SFR_MEM8(0x0A82)
3357
#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
3358
#define AWEXE_STATUS _SFR_MEM8(0x0A84)
3359
#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
3360
#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
3361
#define AWEXE_DTLS _SFR_MEM8(0x0A88)
3362
#define AWEXE_DTHS _SFR_MEM8(0x0A89)
3363
#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
3364
#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
3365
#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
3366
3367
/* HIRESE - High-Resolution Extension E */
3368
#define HIRESE_CTRL _SFR_MEM8(0x0A90)
3369
3370
/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
3371
#define USARTE0_DATA _SFR_MEM8(0x0AA0)
3372
#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
3373
#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
3374
#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
3375
#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
3376
#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
3377
#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
3378
3379
/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
3380
#define USARTE1_DATA _SFR_MEM8(0x0AB0)
3381
#define USARTE1_STATUS _SFR_MEM8(0x0AB1)
3382
#define USARTE1_CTRLA _SFR_MEM8(0x0AB3)
3383
#define USARTE1_CTRLB _SFR_MEM8(0x0AB4)
3384
#define USARTE1_CTRLC _SFR_MEM8(0x0AB5)
3385
#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6)
3386
#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7)
3387
3388
/* SPIE - Serial Peripheral Interface E */
3389
#define SPIE_CTRL _SFR_MEM8(0x0AC0)
3390
#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
3391
#define SPIE_STATUS _SFR_MEM8(0x0AC2)
3392
#define SPIE_DATA _SFR_MEM8(0x0AC3)
3393
3394
/* TCF0 - Timer/Counter F0 */
3395
#define TCF0_CTRLA _SFR_MEM8(0x0B00)
3396
#define TCF0_CTRLB _SFR_MEM8(0x0B01)
3397
#define TCF0_CTRLC _SFR_MEM8(0x0B02)
3398
#define TCF0_CTRLD _SFR_MEM8(0x0B03)
3399
#define TCF0_CTRLE _SFR_MEM8(0x0B04)
3400
#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
3401
#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
3402
#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
3403
#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
3404
#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
3405
#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
3406
#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
3407
#define TCF0_TEMP _SFR_MEM8(0x0B0F)
3408
#define TCF0_CNT _SFR_MEM16(0x0B20)
3409
#define TCF0_PER _SFR_MEM16(0x0B26)
3410
#define TCF0_CCA _SFR_MEM16(0x0B28)
3411
#define TCF0_CCB _SFR_MEM16(0x0B2A)
3412
#define TCF0_CCC _SFR_MEM16(0x0B2C)
3413
#define TCF0_CCD _SFR_MEM16(0x0B2E)
3414
#define TCF0_PERBUF _SFR_MEM16(0x0B36)
3415
#define TCF0_CCABUF _SFR_MEM16(0x0B38)
3416
#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
3417
#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
3418
#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
3419
3420
/* HIRESF - High-Resolution Extension F */
3421
#define HIRESF_CTRL _SFR_MEM8(0x0B90)
3422
3423
/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
3424
#define USARTF0_DATA _SFR_MEM8(0x0BA0)
3425
#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
3426
#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
3427
#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
3428
#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
3429
#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
3430
#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
3431
3432
/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
3433
#define USARTF1_DATA _SFR_MEM8(0x0BB0)
3434
#define USARTF1_STATUS _SFR_MEM8(0x0BB1)
3435
#define USARTF1_CTRLA _SFR_MEM8(0x0BB3)
3436
#define USARTF1_CTRLB _SFR_MEM8(0x0BB4)
3437
#define USARTF1_CTRLC _SFR_MEM8(0x0BB5)
3438
#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6)
3439
#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7)
3440
3441
/* SPIF - Serial Peripheral Interface F */
3442
#define SPIF_CTRL _SFR_MEM8(0x0BC0)
3443
#define SPIF_INTCTRL _SFR_MEM8(0x0BC1)
3444
#define SPIF_STATUS _SFR_MEM8(0x0BC2)
3445
#define SPIF_DATA _SFR_MEM8(0x0BC3)
3446
3447
3448
3449
/*================== Bitfield Definitions ================== */
3450
3451
/* XOCD - On-Chip Debug System */
3452
/* OCD.OCDR1 bit masks and bit positions */
3453
#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
3454
#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
3455
3456
3457
/* CPU - CPU */
3458
/* CPU.CCP bit masks and bit positions */
3459
#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
3460
#define CPU_CCP_gp 0 /* CCP signature group position. */
3461
#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
3462
#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
3463
#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
3464
#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
3465
#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
3466
#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
3467
#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
3468
#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
3469
#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
3470
#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
3471
#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
3472
#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
3473
#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
3474
#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
3475
#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
3476
#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
3477
3478
3479
/* CPU.SREG bit masks and bit positions */
3480
#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
3481
#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
3482
3483
#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
3484
#define CPU_T_bp 6 /* Transfer Bit bit position. */
3485
3486
#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
3487
#define CPU_H_bp 5 /* Half Carry Flag bit position. */
3488
3489
#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
3490
#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
3491
3492
#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
3493
#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
3494
3495
#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
3496
#define CPU_N_bp 2 /* Negative Flag bit position. */
3497
3498
#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
3499
#define CPU_Z_bp 1 /* Zero Flag bit position. */
3500
3501
#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
3502
#define CPU_C_bp 0 /* Carry Flag bit position. */
3503
3504
3505
/* CLK - Clock System */
3506
/* CLK.CTRL bit masks and bit positions */
3507
#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
3508
#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
3509
#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
3510
#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
3511
#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
3512
#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
3513
#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
3514
#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
3515
3516
3517
/* CLK.PSCTRL bit masks and bit positions */
3518
#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
3519
#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
3520
#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
3521
#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
3522
#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
3523
#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
3524
#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
3525
#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
3526
#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
3527
#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
3528
#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
3529
#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
3530
3531
#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
3532
#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
3533
#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
3534
#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
3535
#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
3536
#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
3537
3538
3539
/* CLK.LOCK bit masks and bit positions */
3540
#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
3541
#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
3542
3543
3544
/* CLK.RTCCTRL bit masks and bit positions */
3545
#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
3546
#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
3547
#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
3548
#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
3549
#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
3550
#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
3551
#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
3552
#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
3553
3554
#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
3555
#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */
3556
3557
3558
/* PR.PRGEN bit masks and bit positions */
3559
#define PR_AES_bm 0x10 /* AES bit mask. */
3560
#define PR_AES_bp 4 /* AES bit position. */
3561
3562
#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
3563
#define PR_EBI_bp 3 /* External Bus Interface bit position. */
3564
3565
#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
3566
#define PR_RTC_bp 2 /* Real-time Counter bit position. */
3567
3568
#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
3569
#define PR_EVSYS_bp 1 /* Event System bit position. */
3570
3571
#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
3572
#define PR_DMA_bp 0 /* DMA-Controller bit position. */
3573
3574
3575
/* PR.PRPA bit masks and bit positions */
3576
#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
3577
#define PR_DAC_bp 2 /* Port A DAC bit position. */
3578
3579
#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
3580
#define PR_ADC_bp 1 /* Port A ADC bit position. */
3581
3582
#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
3583
#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
3584
3585
3586
/* PR.PRPB bit masks and bit positions */
3587
/* PR_DAC_bm Predefined. */
3588
/* PR_DAC_bp Predefined. */
3589
3590
/* PR_ADC_bm Predefined. */
3591
/* PR_ADC_bp Predefined. */
3592
3593
/* PR_AC_bm Predefined. */
3594
/* PR_AC_bp Predefined. */
3595
3596
3597
/* PR.PRPC bit masks and bit positions */
3598
#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
3599
#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
3600
3601
#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
3602
#define PR_USART1_bp 5 /* Port C USART1 bit position. */
3603
3604
#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
3605
#define PR_USART0_bp 4 /* Port C USART0 bit position. */
3606
3607
#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
3608
#define PR_SPI_bp 3 /* Port C SPI bit position. */
3609
3610
#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
3611
#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
3612
3613
#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
3614
#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
3615
3616
#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
3617
#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
3618
3619
3620
/* PR.PRPD bit masks and bit positions */
3621
/* PR_TWI_bm Predefined. */
3622
/* PR_TWI_bp Predefined. */
3623
3624
/* PR_USART1_bm Predefined. */
3625
/* PR_USART1_bp Predefined. */
3626
3627
/* PR_USART0_bm Predefined. */
3628
/* PR_USART0_bp Predefined. */
3629
3630
/* PR_SPI_bm Predefined. */
3631
/* PR_SPI_bp Predefined. */
3632
3633
/* PR_HIRES_bm Predefined. */
3634
/* PR_HIRES_bp Predefined. */
3635
3636
/* PR_TC1_bm Predefined. */
3637
/* PR_TC1_bp Predefined. */
3638
3639
/* PR_TC0_bm Predefined. */
3640
/* PR_TC0_bp Predefined. */
3641
3642
3643
/* PR.PRPE bit masks and bit positions */
3644
/* PR_TWI_bm Predefined. */
3645
/* PR_TWI_bp Predefined. */
3646
3647
/* PR_USART1_bm Predefined. */
3648
/* PR_USART1_bp Predefined. */
3649
3650
/* PR_USART0_bm Predefined. */
3651
/* PR_USART0_bp Predefined. */
3652
3653
/* PR_SPI_bm Predefined. */
3654
/* PR_SPI_bp Predefined. */
3655
3656
/* PR_HIRES_bm Predefined. */
3657
/* PR_HIRES_bp Predefined. */
3658
3659
/* PR_TC1_bm Predefined. */
3660
/* PR_TC1_bp Predefined. */
3661
3662
/* PR_TC0_bm Predefined. */
3663
/* PR_TC0_bp Predefined. */
3664
3665
3666
/* PR.PRPF bit masks and bit positions */
3667
/* PR_TWI_bm Predefined. */
3668
/* PR_TWI_bp Predefined. */
3669
3670
/* PR_USART1_bm Predefined. */
3671
/* PR_USART1_bp Predefined. */
3672
3673
/* PR_USART0_bm Predefined. */
3674
/* PR_USART0_bp Predefined. */
3675
3676
/* PR_SPI_bm Predefined. */
3677
/* PR_SPI_bp Predefined. */
3678
3679
/* PR_HIRES_bm Predefined. */
3680
/* PR_HIRES_bp Predefined. */
3681
3682
/* PR_TC1_bm Predefined. */
3683
/* PR_TC1_bp Predefined. */
3684
3685
/* PR_TC0_bm Predefined. */
3686
/* PR_TC0_bp Predefined. */
3687
3688
3689
/* SLEEP - Sleep Controller */
3690
/* SLEEP.CTRL bit masks and bit positions */
3691
#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
3692
#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
3693
#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
3694
#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
3695
#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
3696
#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
3697
#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
3698
#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
3699
3700
#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
3701
#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
3702
3703
3704
/* OSC - Oscillator */
3705
/* OSC.CTRL bit masks and bit positions */
3706
#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
3707
#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
3708
3709
#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
3710
#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
3711
3712
#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */
3713
#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */
3714
3715
#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */
3716
#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */
3717
3718
#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */
3719
#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */
3720
3721
3722
/* OSC.STATUS bit masks and bit positions */
3723
#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
3724
#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
3725
3726
#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
3727
#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
3728
3729
#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */
3730
#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */
3731
3732
#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */
3733
#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */
3734
3735
#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */
3736
#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */
3737
3738
3739
/* OSC.XOSCCTRL bit masks and bit positions */
3740
#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
3741
#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
3742
#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
3743
#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
3744
#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
3745
#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
3746
3747
#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */
3748
#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */
3749
3750
#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
3751
#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
3752
#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
3753
#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
3754
#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
3755
#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
3756
#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
3757
#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
3758
#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
3759
#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
3760
3761
3762
/* OSC.XOSCFAIL bit masks and bit positions */
3763
#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */
3764
#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */
3765
3766
#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */
3767
#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */
3768
3769
3770
/* OSC.PLLCTRL bit masks and bit positions */
3771
#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
3772
#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
3773
#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
3774
#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
3775
#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
3776
#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
3777
3778
#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
3779
#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
3780
#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
3781
#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
3782
#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
3783
#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
3784
#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
3785
#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
3786
#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
3787
#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
3788
#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
3789
#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
3790
3791
3792
/* OSC.DFLLCTRL bit masks and bit positions */
3793
#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */
3794
#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */
3795
3796
#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */
3797
#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */
3798
3799
3800
/* DFLL - DFLL */
3801
/* DFLL.CTRL bit masks and bit positions */
3802
#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
3803
#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
3804
3805
3806
/* DFLL.CALA bit masks and bit positions */
3807
#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */
3808
#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */
3809
#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */
3810
#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */
3811
#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */
3812
#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */
3813
#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */
3814
#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */
3815
#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */
3816
#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */
3817
#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */
3818
#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */
3819
#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */
3820
#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */
3821
#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */
3822
#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */
3823
3824
3825
/* DFLL.CALB bit masks and bit positions */
3826
#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */
3827
#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */
3828
#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */
3829
#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */
3830
#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */
3831
#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */
3832
#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */
3833
#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */
3834
#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */
3835
#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */
3836
#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */
3837
#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */
3838
#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */
3839
#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */
3840
3841
3842
/* RST - Reset */
3843
/* RST.STATUS bit masks and bit positions */
3844
#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
3845
#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
3846
3847
#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
3848
#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
3849
3850
#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
3851
#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
3852
3853
#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
3854
#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
3855
3856
#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
3857
#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
3858
3859
#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
3860
#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
3861
3862
#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
3863
#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
3864
3865
3866
/* RST.CTRL bit masks and bit positions */
3867
#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
3868
#define RST_SWRST_bp 0 /* Software Reset bit position. */
3869
3870
3871
/* WDT - Watch-Dog Timer */
3872
/* WDT.CTRL bit masks and bit positions */
3873
#define WDT_PER_gm 0x3C /* Period group mask. */
3874
#define WDT_PER_gp 2 /* Period group position. */
3875
#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
3876
#define WDT_PER0_bp 2 /* Period bit 0 position. */
3877
#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
3878
#define WDT_PER1_bp 3 /* Period bit 1 position. */
3879
#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
3880
#define WDT_PER2_bp 4 /* Period bit 2 position. */
3881
#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
3882
#define WDT_PER3_bp 5 /* Period bit 3 position. */
3883
3884
#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
3885
#define WDT_ENABLE_bp 1 /* Enable bit position. */
3886
3887
#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
3888
#define WDT_CEN_bp 0 /* Change Enable bit position. */
3889
3890
3891
/* WDT.WINCTRL bit masks and bit positions */
3892
#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
3893
#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
3894
#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
3895
#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
3896
#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
3897
#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
3898
#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
3899
#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
3900
#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
3901
#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
3902
3903
#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
3904
#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
3905
3906
#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
3907
#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
3908
3909
3910
/* WDT.STATUS bit masks and bit positions */
3911
#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
3912
#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
3913
3914
3915
/* MCU - MCU Control */
3916
/* MCU.MCUCR bit masks and bit positions */
3917
#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
3918
#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
3919
3920
3921
/* MCU.EVSYSLOCK bit masks and bit positions */
3922
#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
3923
#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
3924
3925
#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
3926
#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
3927
3928
3929
/* MCU.AWEXLOCK bit masks and bit positions */
3930
#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
3931
#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
3932
3933
#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
3934
#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
3935
3936
3937
/* PMIC - Programmable Multi-level Interrupt Controller */
3938
/* PMIC.STATUS bit masks and bit positions */
3939
#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
3940
#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
3941
3942
#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
3943
#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
3944
3945
#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
3946
#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
3947
3948
#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
3949
#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
3950
3951
3952
/* PMIC.CTRL bit masks and bit positions */
3953
#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
3954
#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
3955
3956
#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
3957
#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
3958
3959
#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
3960
#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
3961
3962
#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
3963
#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
3964
3965
#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
3966
#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
3967
3968
3969
/* DMA - DMA Controller */
3970
/* DMA_CH.CTRLA bit masks and bit positions */
3971
#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
3972
#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
3973
3974
#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
3975
#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
3976
3977
#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
3978
#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
3979
3980
#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
3981
#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
3982
3983
#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
3984
#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
3985
3986
#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
3987
#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
3988
#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
3989
#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
3990
#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
3991
#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
3992
3993
3994
/* DMA_CH.CTRLB bit masks and bit positions */
3995
#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
3996
#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
3997
3998
#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
3999
#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
4000
4001
#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
4002
#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
4003
4004
#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
4005
#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
4006
4007
#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
4008
#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
4009
#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
4010
#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
4011
#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
4012
#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
4013
4014
#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
4015
#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
4016
#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
4017
#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
4018
#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
4019
#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
4020
4021
4022
/* DMA_CH.ADDRCTRL bit masks and bit positions */
4023
#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
4024
#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
4025
#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
4026
#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
4027
#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
4028
#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
4029
4030
#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
4031
#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
4032
#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
4033
#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
4034
#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
4035
#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
4036
4037
#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
4038
#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
4039
#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
4040
#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
4041
#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
4042
#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
4043
4044
#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
4045
#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
4046
#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
4047
#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
4048
#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
4049
#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
4050
4051
4052
/* DMA_CH.TRIGSRC bit masks and bit positions */
4053
#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
4054
#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
4055
#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
4056
#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
4057
#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
4058
#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
4059
#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
4060
#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
4061
#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
4062
#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
4063
#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
4064
#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
4065
#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
4066
#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
4067
#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
4068
#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
4069
#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
4070
#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
4071
4072
4073
/* DMA.CTRL bit masks and bit positions */
4074
#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
4075
#define DMA_ENABLE_bp 7 /* Enable bit position. */
4076
4077
#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
4078
#define DMA_RESET_bp 6 /* Software Reset bit position. */
4079
4080
#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
4081
#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
4082
#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
4083
#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
4084
#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
4085
#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
4086
4087
#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
4088
#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
4089
#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
4090
#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
4091
#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
4092
#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
4093
4094
4095
/* DMA.INTFLAGS bit masks and bit positions */
4096
#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
4097
#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
4098
4099
#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
4100
#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
4101
4102
#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
4103
#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
4104
4105
#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
4106
#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
4107
4108
#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
4109
#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
4110
4111
#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
4112
#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
4113
4114
#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
4115
#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
4116
4117
#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
4118
#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
4119
4120
4121
/* DMA.STATUS bit masks and bit positions */
4122
#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
4123
#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
4124
4125
#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
4126
#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
4127
4128
#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
4129
#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
4130
4131
#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
4132
#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
4133
4134
#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
4135
#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
4136
4137
#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
4138
#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
4139
4140
#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
4141
#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
4142
4143
#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
4144
#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
4145
4146
4147
/* EVSYS - Event System */
4148
/* EVSYS.CH0MUX bit masks and bit positions */
4149
#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
4150
#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
4151
#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
4152
#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
4153
#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
4154
#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
4155
#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
4156
#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
4157
#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
4158
#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
4159
#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
4160
#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
4161
#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
4162
#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
4163
#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
4164
#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
4165
#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
4166
#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
4167
4168
4169
/* EVSYS.CH1MUX bit masks and bit positions */
4170
/* EVSYS_CHMUX_gm Predefined. */
4171
/* EVSYS_CHMUX_gp Predefined. */
4172
/* EVSYS_CHMUX0_bm Predefined. */
4173
/* EVSYS_CHMUX0_bp Predefined. */
4174
/* EVSYS_CHMUX1_bm Predefined. */
4175
/* EVSYS_CHMUX1_bp Predefined. */
4176
/* EVSYS_CHMUX2_bm Predefined. */
4177
/* EVSYS_CHMUX2_bp Predefined. */
4178
/* EVSYS_CHMUX3_bm Predefined. */
4179
/* EVSYS_CHMUX3_bp Predefined. */
4180
/* EVSYS_CHMUX4_bm Predefined. */
4181
/* EVSYS_CHMUX4_bp Predefined. */
4182
/* EVSYS_CHMUX5_bm Predefined. */
4183
/* EVSYS_CHMUX5_bp Predefined. */
4184
/* EVSYS_CHMUX6_bm Predefined. */
4185
/* EVSYS_CHMUX6_bp Predefined. */
4186
/* EVSYS_CHMUX7_bm Predefined. */
4187
/* EVSYS_CHMUX7_bp Predefined. */
4188
4189
4190
/* EVSYS.CH2MUX bit masks and bit positions */
4191
/* EVSYS_CHMUX_gm Predefined. */
4192
/* EVSYS_CHMUX_gp Predefined. */
4193
/* EVSYS_CHMUX0_bm Predefined. */
4194
/* EVSYS_CHMUX0_bp Predefined. */
4195
/* EVSYS_CHMUX1_bm Predefined. */
4196
/* EVSYS_CHMUX1_bp Predefined. */
4197
/* EVSYS_CHMUX2_bm Predefined. */
4198
/* EVSYS_CHMUX2_bp Predefined. */
4199
/* EVSYS_CHMUX3_bm Predefined. */
4200
/* EVSYS_CHMUX3_bp Predefined. */
4201
/* EVSYS_CHMUX4_bm Predefined. */
4202
/* EVSYS_CHMUX4_bp Predefined. */
4203
/* EVSYS_CHMUX5_bm Predefined. */
4204
/* EVSYS_CHMUX5_bp Predefined. */
4205
/* EVSYS_CHMUX6_bm Predefined. */
4206
/* EVSYS_CHMUX6_bp Predefined. */
4207
/* EVSYS_CHMUX7_bm Predefined. */
4208
/* EVSYS_CHMUX7_bp Predefined. */
4209
4210
4211
/* EVSYS.CH3MUX bit masks and bit positions */
4212
/* EVSYS_CHMUX_gm Predefined. */
4213
/* EVSYS_CHMUX_gp Predefined. */
4214
/* EVSYS_CHMUX0_bm Predefined. */
4215
/* EVSYS_CHMUX0_bp Predefined. */
4216
/* EVSYS_CHMUX1_bm Predefined. */
4217
/* EVSYS_CHMUX1_bp Predefined. */
4218
/* EVSYS_CHMUX2_bm Predefined. */
4219
/* EVSYS_CHMUX2_bp Predefined. */
4220
/* EVSYS_CHMUX3_bm Predefined. */
4221
/* EVSYS_CHMUX3_bp Predefined. */
4222
/* EVSYS_CHMUX4_bm Predefined. */
4223
/* EVSYS_CHMUX4_bp Predefined. */
4224
/* EVSYS_CHMUX5_bm Predefined. */
4225
/* EVSYS_CHMUX5_bp Predefined. */
4226
/* EVSYS_CHMUX6_bm Predefined. */
4227
/* EVSYS_CHMUX6_bp Predefined. */
4228
/* EVSYS_CHMUX7_bm Predefined. */
4229
/* EVSYS_CHMUX7_bp Predefined. */
4230
4231
4232
/* EVSYS.CH4MUX bit masks and bit positions */
4233
/* EVSYS_CHMUX_gm Predefined. */
4234
/* EVSYS_CHMUX_gp Predefined. */
4235
/* EVSYS_CHMUX0_bm Predefined. */
4236
/* EVSYS_CHMUX0_bp Predefined. */
4237
/* EVSYS_CHMUX1_bm Predefined. */
4238
/* EVSYS_CHMUX1_bp Predefined. */
4239
/* EVSYS_CHMUX2_bm Predefined. */
4240
/* EVSYS_CHMUX2_bp Predefined. */
4241
/* EVSYS_CHMUX3_bm Predefined. */
4242
/* EVSYS_CHMUX3_bp Predefined. */
4243
/* EVSYS_CHMUX4_bm Predefined. */
4244
/* EVSYS_CHMUX4_bp Predefined. */
4245
/* EVSYS_CHMUX5_bm Predefined. */
4246
/* EVSYS_CHMUX5_bp Predefined. */
4247
/* EVSYS_CHMUX6_bm Predefined. */
4248
/* EVSYS_CHMUX6_bp Predefined. */
4249
/* EVSYS_CHMUX7_bm Predefined. */
4250
/* EVSYS_CHMUX7_bp Predefined. */
4251
4252
4253
/* EVSYS.CH5MUX bit masks and bit positions */
4254
/* EVSYS_CHMUX_gm Predefined. */
4255
/* EVSYS_CHMUX_gp Predefined. */
4256
/* EVSYS_CHMUX0_bm Predefined. */
4257
/* EVSYS_CHMUX0_bp Predefined. */
4258
/* EVSYS_CHMUX1_bm Predefined. */
4259
/* EVSYS_CHMUX1_bp Predefined. */
4260
/* EVSYS_CHMUX2_bm Predefined. */
4261
/* EVSYS_CHMUX2_bp Predefined. */
4262
/* EVSYS_CHMUX3_bm Predefined. */
4263
/* EVSYS_CHMUX3_bp Predefined. */
4264
/* EVSYS_CHMUX4_bm Predefined. */
4265
/* EVSYS_CHMUX4_bp Predefined. */
4266
/* EVSYS_CHMUX5_bm Predefined. */
4267
/* EVSYS_CHMUX5_bp Predefined. */
4268
/* EVSYS_CHMUX6_bm Predefined. */
4269
/* EVSYS_CHMUX6_bp Predefined. */
4270
/* EVSYS_CHMUX7_bm Predefined. */
4271
/* EVSYS_CHMUX7_bp Predefined. */
4272
4273
4274
/* EVSYS.CH6MUX bit masks and bit positions */
4275
/* EVSYS_CHMUX_gm Predefined. */
4276
/* EVSYS_CHMUX_gp Predefined. */
4277
/* EVSYS_CHMUX0_bm Predefined. */
4278
/* EVSYS_CHMUX0_bp Predefined. */
4279
/* EVSYS_CHMUX1_bm Predefined. */
4280
/* EVSYS_CHMUX1_bp Predefined. */
4281
/* EVSYS_CHMUX2_bm Predefined. */
4282
/* EVSYS_CHMUX2_bp Predefined. */
4283
/* EVSYS_CHMUX3_bm Predefined. */
4284
/* EVSYS_CHMUX3_bp Predefined. */
4285
/* EVSYS_CHMUX4_bm Predefined. */
4286
/* EVSYS_CHMUX4_bp Predefined. */
4287
/* EVSYS_CHMUX5_bm Predefined. */
4288
/* EVSYS_CHMUX5_bp Predefined. */
4289
/* EVSYS_CHMUX6_bm Predefined. */
4290
/* EVSYS_CHMUX6_bp Predefined. */
4291
/* EVSYS_CHMUX7_bm Predefined. */
4292
/* EVSYS_CHMUX7_bp Predefined. */
4293
4294
4295
/* EVSYS.CH7MUX bit masks and bit positions */
4296
/* EVSYS_CHMUX_gm Predefined. */
4297
/* EVSYS_CHMUX_gp Predefined. */
4298
/* EVSYS_CHMUX0_bm Predefined. */
4299
/* EVSYS_CHMUX0_bp Predefined. */
4300
/* EVSYS_CHMUX1_bm Predefined. */
4301
/* EVSYS_CHMUX1_bp Predefined. */
4302
/* EVSYS_CHMUX2_bm Predefined. */
4303
/* EVSYS_CHMUX2_bp Predefined. */
4304
/* EVSYS_CHMUX3_bm Predefined. */
4305
/* EVSYS_CHMUX3_bp Predefined. */
4306
/* EVSYS_CHMUX4_bm Predefined. */
4307
/* EVSYS_CHMUX4_bp Predefined. */
4308
/* EVSYS_CHMUX5_bm Predefined. */
4309
/* EVSYS_CHMUX5_bp Predefined. */
4310
/* EVSYS_CHMUX6_bm Predefined. */
4311
/* EVSYS_CHMUX6_bp Predefined. */
4312
/* EVSYS_CHMUX7_bm Predefined. */
4313
/* EVSYS_CHMUX7_bp Predefined. */
4314
4315
4316
/* EVSYS.CH0CTRL bit masks and bit positions */
4317
#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
4318
#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
4319
#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
4320
#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
4321
#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
4322
#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
4323
4324
#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
4325
#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
4326
4327
#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
4328
#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
4329
4330
#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
4331
#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
4332
#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
4333
#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
4334
#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
4335
#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
4336
#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
4337
#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
4338
4339
4340
/* EVSYS.CH1CTRL bit masks and bit positions */
4341
/* EVSYS_DIGFILT_gm Predefined. */
4342
/* EVSYS_DIGFILT_gp Predefined. */
4343
/* EVSYS_DIGFILT0_bm Predefined. */
4344
/* EVSYS_DIGFILT0_bp Predefined. */
4345
/* EVSYS_DIGFILT1_bm Predefined. */
4346
/* EVSYS_DIGFILT1_bp Predefined. */
4347
/* EVSYS_DIGFILT2_bm Predefined. */
4348
/* EVSYS_DIGFILT2_bp Predefined. */
4349
4350
4351
/* EVSYS.CH2CTRL bit masks and bit positions */
4352
/* EVSYS_QDIRM_gm Predefined. */
4353
/* EVSYS_QDIRM_gp Predefined. */
4354
/* EVSYS_QDIRM0_bm Predefined. */
4355
/* EVSYS_QDIRM0_bp Predefined. */
4356
/* EVSYS_QDIRM1_bm Predefined. */
4357
/* EVSYS_QDIRM1_bp Predefined. */
4358
4359
/* EVSYS_QDIEN_bm Predefined. */
4360
/* EVSYS_QDIEN_bp Predefined. */
4361
4362
/* EVSYS_QDEN_bm Predefined. */
4363
/* EVSYS_QDEN_bp Predefined. */
4364
4365
/* EVSYS_DIGFILT_gm Predefined. */
4366
/* EVSYS_DIGFILT_gp Predefined. */
4367
/* EVSYS_DIGFILT0_bm Predefined. */
4368
/* EVSYS_DIGFILT0_bp Predefined. */
4369
/* EVSYS_DIGFILT1_bm Predefined. */
4370
/* EVSYS_DIGFILT1_bp Predefined. */
4371
/* EVSYS_DIGFILT2_bm Predefined. */
4372
/* EVSYS_DIGFILT2_bp Predefined. */
4373
4374
4375
/* EVSYS.CH3CTRL bit masks and bit positions */
4376
/* EVSYS_DIGFILT_gm Predefined. */
4377
/* EVSYS_DIGFILT_gp Predefined. */
4378
/* EVSYS_DIGFILT0_bm Predefined. */
4379
/* EVSYS_DIGFILT0_bp Predefined. */
4380
/* EVSYS_DIGFILT1_bm Predefined. */
4381
/* EVSYS_DIGFILT1_bp Predefined. */
4382
/* EVSYS_DIGFILT2_bm Predefined. */
4383
/* EVSYS_DIGFILT2_bp Predefined. */
4384
4385
4386
/* EVSYS.CH4CTRL bit masks and bit positions */
4387
/* EVSYS_QDIRM_gm Predefined. */
4388
/* EVSYS_QDIRM_gp Predefined. */
4389
/* EVSYS_QDIRM0_bm Predefined. */
4390
/* EVSYS_QDIRM0_bp Predefined. */
4391
/* EVSYS_QDIRM1_bm Predefined. */
4392
/* EVSYS_QDIRM1_bp Predefined. */
4393
4394
/* EVSYS_QDIEN_bm Predefined. */
4395
/* EVSYS_QDIEN_bp Predefined. */
4396
4397
/* EVSYS_QDEN_bm Predefined. */
4398
/* EVSYS_QDEN_bp Predefined. */
4399
4400
/* EVSYS_DIGFILT_gm Predefined. */
4401
/* EVSYS_DIGFILT_gp Predefined. */
4402
/* EVSYS_DIGFILT0_bm Predefined. */
4403
/* EVSYS_DIGFILT0_bp Predefined. */
4404
/* EVSYS_DIGFILT1_bm Predefined. */
4405
/* EVSYS_DIGFILT1_bp Predefined. */
4406
/* EVSYS_DIGFILT2_bm Predefined. */
4407
/* EVSYS_DIGFILT2_bp Predefined. */
4408
4409
4410
/* EVSYS.CH5CTRL bit masks and bit positions */
4411
/* EVSYS_DIGFILT_gm Predefined. */
4412
/* EVSYS_DIGFILT_gp Predefined. */
4413
/* EVSYS_DIGFILT0_bm Predefined. */
4414
/* EVSYS_DIGFILT0_bp Predefined. */
4415
/* EVSYS_DIGFILT1_bm Predefined. */
4416
/* EVSYS_DIGFILT1_bp Predefined. */
4417
/* EVSYS_DIGFILT2_bm Predefined. */
4418
/* EVSYS_DIGFILT2_bp Predefined. */
4419
4420
4421
/* EVSYS.CH6CTRL bit masks and bit positions */
4422
/* EVSYS_DIGFILT_gm Predefined. */
4423
/* EVSYS_DIGFILT_gp Predefined. */
4424
/* EVSYS_DIGFILT0_bm Predefined. */
4425
/* EVSYS_DIGFILT0_bp Predefined. */
4426
/* EVSYS_DIGFILT1_bm Predefined. */
4427
/* EVSYS_DIGFILT1_bp Predefined. */
4428
/* EVSYS_DIGFILT2_bm Predefined. */
4429
/* EVSYS_DIGFILT2_bp Predefined. */
4430
4431
4432
/* EVSYS.CH7CTRL bit masks and bit positions */
4433
/* EVSYS_DIGFILT_gm Predefined. */
4434
/* EVSYS_DIGFILT_gp Predefined. */
4435
/* EVSYS_DIGFILT0_bm Predefined. */
4436
/* EVSYS_DIGFILT0_bp Predefined. */
4437
/* EVSYS_DIGFILT1_bm Predefined. */
4438
/* EVSYS_DIGFILT1_bp Predefined. */
4439
/* EVSYS_DIGFILT2_bm Predefined. */
4440
/* EVSYS_DIGFILT2_bp Predefined. */
4441
4442
4443
/* NVM - Non Volatile Memory Controller */
4444
/* NVM.CMD bit masks and bit positions */
4445
#define NVM_CMD_gm 0xFF /* Command group mask. */
4446
#define NVM_CMD_gp 0 /* Command group position. */
4447
#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
4448
#define NVM_CMD0_bp 0 /* Command bit 0 position. */
4449
#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
4450
#define NVM_CMD1_bp 1 /* Command bit 1 position. */
4451
#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
4452
#define NVM_CMD2_bp 2 /* Command bit 2 position. */
4453
#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
4454
#define NVM_CMD3_bp 3 /* Command bit 3 position. */
4455
#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
4456
#define NVM_CMD4_bp 4 /* Command bit 4 position. */
4457
#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
4458
#define NVM_CMD5_bp 5 /* Command bit 5 position. */
4459
#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
4460
#define NVM_CMD6_bp 6 /* Command bit 6 position. */
4461
#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */
4462
#define NVM_CMD7_bp 7 /* Command bit 7 position. */
4463
4464
4465
/* NVM.CTRLA bit masks and bit positions */
4466
#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
4467
#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
4468
4469
4470
/* NVM.CTRLB bit masks and bit positions */
4471
#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
4472
#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
4473
4474
#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
4475
#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
4476
4477
#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
4478
#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
4479
4480
#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
4481
#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
4482
4483
4484
/* NVM.INTCTRL bit masks and bit positions */
4485
#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
4486
#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
4487
#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
4488
#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
4489
#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
4490
#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
4491
4492
#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
4493
#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
4494
#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
4495
#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
4496
#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
4497
#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
4498
4499
4500
/* NVM.STATUS bit masks and bit positions */
4501
#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
4502
#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
4503
4504
#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
4505
#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
4506
4507
#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
4508
#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
4509
4510
#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
4511
#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
4512
4513
4514
/* NVM.LOCKBITS bit masks and bit positions */
4515
#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
4516
#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
4517
#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
4518
#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
4519
#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
4520
#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
4521
4522
#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
4523
#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
4524
#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
4525
#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
4526
#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
4527
#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
4528
4529
#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
4530
#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
4531
#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
4532
#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
4533
#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
4534
#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
4535
4536
#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
4537
#define NVM_LB_gp 0 /* Lock Bits group position. */
4538
#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
4539
#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
4540
#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
4541
#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
4542
4543
4544
/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
4545
#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
4546
#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
4547
#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
4548
#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
4549
#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
4550
#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
4551
4552
#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
4553
#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
4554
#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
4555
#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
4556
#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
4557
#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
4558
4559
#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
4560
#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
4561
#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
4562
#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
4563
#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
4564
#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
4565
4566
#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
4567
#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
4568
#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
4569
#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
4570
#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
4571
#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
4572
4573
4574
/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
4575
#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
4576
#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
4577
#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
4578
#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
4579
#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
4580
#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
4581
#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
4582
#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
4583
#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
4584
#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
4585
#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
4586
#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
4587
#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
4588
#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
4589
#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
4590
#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
4591
#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
4592
#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
4593
4594
4595
/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
4596
#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
4597
#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
4598
#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
4599
#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
4600
#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
4601
#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
4602
#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
4603
#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
4604
#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
4605
#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
4606
4607
#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
4608
#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
4609
#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
4610
#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
4611
#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
4612
#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
4613
#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
4614
#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
4615
#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
4616
#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
4617
4618
4619
/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
4620
#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */
4621
#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */
4622
4623
#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
4624
#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
4625
4626
#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
4627
#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
4628
#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
4629
#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
4630
#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
4631
#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
4632
4633
4634
/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
4635
#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
4636
#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
4637
#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
4638
#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
4639
#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
4640
#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
4641
4642
#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
4643
#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
4644
4645
#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
4646
#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
4647
4648
4649
/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
4650
#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
4651
#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
4652
#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
4653
#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
4654
#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
4655
#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
4656
4657
#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
4658
#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
4659
4660
#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
4661
#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
4662
#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
4663
#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
4664
#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
4665
#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
4666
#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
4667
#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
4668
4669
4670
/* AC - Analog Comparator */
4671
/* AC.AC0CTRL bit masks and bit positions */
4672
#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
4673
#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
4674
#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
4675
#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
4676
#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
4677
#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
4678
4679
#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
4680
#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
4681
#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
4682
#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
4683
#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
4684
#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
4685
4686
#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
4687
#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
4688
4689
#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
4690
#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
4691
#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
4692
#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
4693
#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
4694
#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
4695
4696
#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
4697
#define AC_ENABLE_bp 0 /* Enable bit position. */
4698
4699
4700
/* AC.AC1CTRL bit masks and bit positions */
4701
/* AC_INTMODE_gm Predefined. */
4702
/* AC_INTMODE_gp Predefined. */
4703
/* AC_INTMODE0_bm Predefined. */
4704
/* AC_INTMODE0_bp Predefined. */
4705
/* AC_INTMODE1_bm Predefined. */
4706
/* AC_INTMODE1_bp Predefined. */
4707
4708
/* AC_INTLVL_gm Predefined. */
4709
/* AC_INTLVL_gp Predefined. */
4710
/* AC_INTLVL0_bm Predefined. */
4711
/* AC_INTLVL0_bp Predefined. */
4712
/* AC_INTLVL1_bm Predefined. */
4713
/* AC_INTLVL1_bp Predefined. */
4714
4715
/* AC_HSMODE_bm Predefined. */
4716
/* AC_HSMODE_bp Predefined. */
4717
4718
/* AC_HYSMODE_gm Predefined. */
4719
/* AC_HYSMODE_gp Predefined. */
4720
/* AC_HYSMODE0_bm Predefined. */
4721
/* AC_HYSMODE0_bp Predefined. */
4722
/* AC_HYSMODE1_bm Predefined. */
4723
/* AC_HYSMODE1_bp Predefined. */
4724
4725
/* AC_ENABLE_bm Predefined. */
4726
/* AC_ENABLE_bp Predefined. */
4727
4728
4729
/* AC.AC0MUXCTRL bit masks and bit positions */
4730
#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
4731
#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
4732
#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
4733
#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
4734
#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
4735
#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
4736
#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
4737
#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
4738
4739
#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
4740
#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
4741
#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
4742
#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
4743
#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
4744
#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
4745
#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
4746
#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
4747
4748
4749
/* AC.AC1MUXCTRL bit masks and bit positions */
4750
/* AC_MUXPOS_gm Predefined. */
4751
/* AC_MUXPOS_gp Predefined. */
4752
/* AC_MUXPOS0_bm Predefined. */
4753
/* AC_MUXPOS0_bp Predefined. */
4754
/* AC_MUXPOS1_bm Predefined. */
4755
/* AC_MUXPOS1_bp Predefined. */
4756
/* AC_MUXPOS2_bm Predefined. */
4757
/* AC_MUXPOS2_bp Predefined. */
4758
4759
/* AC_MUXNEG_gm Predefined. */
4760
/* AC_MUXNEG_gp Predefined. */
4761
/* AC_MUXNEG0_bm Predefined. */
4762
/* AC_MUXNEG0_bp Predefined. */
4763
/* AC_MUXNEG1_bm Predefined. */
4764
/* AC_MUXNEG1_bp Predefined. */
4765
/* AC_MUXNEG2_bm Predefined. */
4766
/* AC_MUXNEG2_bp Predefined. */
4767
4768
4769
/* AC.CTRLA bit masks and bit positions */
4770
#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */
4771
#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */
4772
4773
4774
/* AC.CTRLB bit masks and bit positions */
4775
#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
4776
#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
4777
#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
4778
#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
4779
#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
4780
#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
4781
#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
4782
#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
4783
#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
4784
#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
4785
#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
4786
#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
4787
#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
4788
#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
4789
4790
4791
/* AC.WINCTRL bit masks and bit positions */
4792
#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
4793
#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
4794
4795
#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
4796
#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
4797
#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
4798
#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
4799
#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
4800
#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
4801
4802
#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
4803
#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
4804
#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
4805
#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
4806
#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
4807
#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
4808
4809
4810
/* AC.STATUS bit masks and bit positions */
4811
#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
4812
#define AC_WSTATE_gp 6 /* Window Mode State group position. */
4813
#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
4814
#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
4815
#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
4816
#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
4817
4818
#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */
4819
#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */
4820
4821
#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */
4822
#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */
4823
4824
#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
4825
#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
4826
4827
#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */
4828
#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */
4829
4830
#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */
4831
#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */
4832
4833
4834
/* ADC - Analog/Digital Converter */
4835
/* ADC_CH.CTRL bit masks and bit positions */
4836
#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
4837
#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
4838
4839
#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */
4840
#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */
4841
#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */
4842
#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */
4843
#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */
4844
#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */
4845
#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */
4846
#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */
4847
4848
#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
4849
#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
4850
#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
4851
#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
4852
#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
4853
#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
4854
4855
4856
/* ADC_CH.MUXCTRL bit masks and bit positions */
4857
#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */
4858
#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */
4859
#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */
4860
#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */
4861
#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */
4862
#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */
4863
#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */
4864
#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */
4865
#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */
4866
#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */
4867
4868
#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */
4869
#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */
4870
#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */
4871
#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */
4872
#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */
4873
#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */
4874
#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */
4875
#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */
4876
#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */
4877
#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */
4878
4879
#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */
4880
#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */
4881
#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */
4882
#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */
4883
#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */
4884
#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */
4885
4886
4887
/* ADC_CH.INTCTRL bit masks and bit positions */
4888
#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
4889
#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
4890
#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
4891
#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
4892
#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
4893
#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
4894
4895
#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
4896
#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
4897
#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
4898
#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
4899
#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
4900
#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
4901
4902
4903
/* ADC_CH.INTFLAGS bit masks and bit positions */
4904
#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
4905
#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
4906
4907
4908
/* ADC.CTRLA bit masks and bit positions */
4909
#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
4910
#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
4911
#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
4912
#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
4913
#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
4914
#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
4915
4916
#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
4917
#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
4918
4919
#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
4920
#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
4921
4922
#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
4923
#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
4924
4925
#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
4926
#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
4927
4928
#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
4929
#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
4930
4931
#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
4932
#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
4933
4934
4935
/* ADC.CTRLB bit masks and bit positions */
4936
#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
4937
#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
4938
4939
#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
4940
#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
4941
4942
#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
4943
#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
4944
#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
4945
#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
4946
#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
4947
#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
4948
4949
4950
/* ADC.REFCTRL bit masks and bit positions */
4951
#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */
4952
#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
4953
#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
4954
#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
4955
#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
4956
#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
4957
4958
#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
4959
#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
4960
4961
#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
4962
#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
4963
4964
4965
/* ADC.EVCTRL bit masks and bit positions */
4966
#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
4967
#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
4968
#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
4969
#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
4970
#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
4971
#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
4972
4973
#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
4974
#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
4975
#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
4976
#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
4977
#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
4978
#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
4979
#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
4980
#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
4981
4982
#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
4983
#define ADC_EVACT_gp 0 /* Event Action Select group position. */
4984
#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
4985
#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
4986
#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
4987
#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
4988
#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
4989
#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
4990
4991
4992
/* ADC.PRESCALER bit masks and bit positions */
4993
#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
4994
#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
4995
#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
4996
#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
4997
#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
4998
#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
4999
#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
5000
#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
5001
5002
5003
/* ADC.CALCTRL bit masks and bit positions */
5004
#define ADC_CAL_bm 0x01 /* ADC Calibration Start bit mask. */
5005
#define ADC_CAL_bp 0 /* ADC Calibration Start bit position. */
5006
5007
5008
/* ADC.INTFLAGS bit masks and bit positions */
5009
#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
5010
#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
5011
5012
#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
5013
#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
5014
5015
#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
5016
#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
5017
5018
#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
5019
#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
5020
5021
5022
/* DAC - Digital/Analog Converter */
5023
/* DAC.CTRLA bit masks and bit positions */
5024
#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
5025
#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
5026
5027
#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
5028
#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
5029
5030
#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
5031
#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
5032
5033
#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
5034
#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
5035
5036
#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
5037
#define DAC_ENABLE_bp 0 /* Enable bit position. */
5038
5039
5040
/* DAC.CTRLB bit masks and bit positions */
5041
#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
5042
#define DAC_CHSEL_gp 5 /* Channel Select group position. */
5043
#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
5044
#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
5045
#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
5046
#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
5047
5048
#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
5049
#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
5050
5051
#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
5052
#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
5053
5054
5055
/* DAC.CTRLC bit masks and bit positions */
5056
#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
5057
#define DAC_REFSEL_gp 3 /* Reference Select group position. */
5058
#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
5059
#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
5060
#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
5061
#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
5062
5063
#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
5064
#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
5065
5066
5067
/* DAC.EVCTRL bit masks and bit positions */
5068
#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
5069
#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
5070
#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
5071
#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
5072
#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
5073
#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
5074
#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
5075
#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
5076
5077
5078
/* DAC.TIMCTRL bit masks and bit positions */
5079
#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
5080
#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
5081
#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
5082
#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
5083
#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
5084
#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
5085
#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
5086
#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
5087
5088
#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
5089
#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
5090
#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
5091
#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
5092
#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
5093
#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
5094
#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
5095
#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
5096
#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
5097
#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
5098
5099
5100
/* DAC.STATUS bit masks and bit positions */
5101
#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
5102
#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
5103
5104
#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
5105
#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
5106
5107
5108
/* RTC - Real-Time Clounter */
5109
/* RTC.CTRL bit masks and bit positions */
5110
#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
5111
#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
5112
#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
5113
#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
5114
#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
5115
#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
5116
#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
5117
#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
5118
5119
5120
/* RTC.STATUS bit masks and bit positions */
5121
#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
5122
#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
5123
5124
5125
/* RTC.INTCTRL bit masks and bit positions */
5126
#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
5127
#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
5128
#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
5129
#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
5130
#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
5131
#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
5132
5133
#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
5134
#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
5135
#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
5136
#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
5137
#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
5138
#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
5139
5140
5141
/* RTC.INTFLAGS bit masks and bit positions */
5142
#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
5143
#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
5144
5145
#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
5146
#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
5147
5148
5149
/* EBI - External Bus Interface */
5150
/* EBI_CS.CTRLA bit masks and bit positions */
5151
#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
5152
#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
5153
#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
5154
#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
5155
#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
5156
#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
5157
#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
5158
#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
5159
#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
5160
#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
5161
#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
5162
#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
5163
5164
#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
5165
#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
5166
#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */
5167
#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
5168
#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
5169
#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
5170
5171
5172
/* EBI_CS.CTRLB bit masks and bit positions */
5173
#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
5174
#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
5175
#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */
5176
#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
5177
#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */
5178
#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
5179
#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */
5180
#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */
5181
5182
#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
5183
#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */
5184
5185
#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
5186
#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */
5187
5188
#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
5189
#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
5190
#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */
5191
#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
5192
#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
5193
#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
5194
5195
5196
/* EBI.CTRL bit masks and bit positions */
5197
#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
5198
#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
5199
#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */
5200
#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
5201
#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */
5202
#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */
5203
5204
#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
5205
#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
5206
#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */
5207
#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
5208
#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */
5209
#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */
5210
5211
#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
5212
#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
5213
#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */
5214
#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
5215
#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */
5216
#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */
5217
5218
#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
5219
#define EBI_IFMODE_gp 0 /* Interface Mode group position. */
5220
#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */
5221
#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
5222
#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
5223
#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
5224
5225
5226
/* EBI.SDRAMCTRLA bit masks and bit positions */
5227
#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
5228
#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
5229
5230
#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
5231
#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */
5232
5233
#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
5234
#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
5235
#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */
5236
#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
5237
#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
5238
#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
5239
5240
5241
/* EBI.SDRAMCTRLB bit masks and bit positions */
5242
#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
5243
#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
5244
#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */
5245
#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
5246
#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */
5247
#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */
5248
5249
#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
5250
#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
5251
#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */
5252
#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
5253
#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */
5254
#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
5255
#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */
5256
#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */
5257
5258
#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
5259
#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
5260
#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
5261
#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
5262
#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
5263
#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
5264
#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
5265
#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
5266
5267
5268
/* EBI.SDRAMCTRLC bit masks and bit positions */
5269
#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
5270
#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
5271
#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */
5272
#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
5273
#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */
5274
#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */
5275
5276
#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
5277
#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
5278
#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
5279
#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
5280
#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
5281
#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
5282
#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
5283
#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
5284
5285
#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
5286
#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
5287
#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */
5288
#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
5289
#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */
5290
#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
5291
#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
5292
#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
5293
5294
5295
/* TWI - Two-Wire Interface */
5296
/* TWI_MASTER.CTRLA bit masks and bit positions */
5297
#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
5298
#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
5299
#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
5300
#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
5301
#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
5302
#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
5303
5304
#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
5305
#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
5306
5307
#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
5308
#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
5309
5310
#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
5311
#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
5312
5313
5314
/* TWI_MASTER.CTRLB bit masks and bit positions */
5315
#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
5316
#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
5317
#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
5318
#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
5319
#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
5320
#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
5321
5322
#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
5323
#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
5324
5325
#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
5326
#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
5327
5328
5329
/* TWI_MASTER.CTRLC bit masks and bit positions */
5330
#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
5331
#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
5332
5333
#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
5334
#define TWI_MASTER_CMD_gp 0 /* Command group position. */
5335
#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
5336
#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
5337
#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
5338
#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
5339
5340
5341
/* TWI_MASTER.STATUS bit masks and bit positions */
5342
#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
5343
#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
5344
5345
#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
5346
#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
5347
5348
#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
5349
#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
5350
5351
#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
5352
#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
5353
5354
#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
5355
#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
5356
5357
#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
5358
#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
5359
5360
#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
5361
#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
5362
#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
5363
#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
5364
#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
5365
#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
5366
5367
5368
/* TWI_SLAVE.CTRLA bit masks and bit positions */
5369
#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
5370
#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
5371
#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
5372
#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
5373
#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
5374
#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
5375
5376
#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
5377
#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
5378
5379
#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
5380
#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
5381
5382
#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
5383
#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
5384
5385
#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
5386
#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
5387
5388
#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
5389
#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
5390
5391
#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
5392
#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
5393
5394
5395
/* TWI_SLAVE.CTRLB bit masks and bit positions */
5396
#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
5397
#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
5398
5399
#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
5400
#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
5401
#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
5402
#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
5403
#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
5404
#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
5405
5406
5407
/* TWI_SLAVE.STATUS bit masks and bit positions */
5408
#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
5409
#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
5410
5411
#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
5412
#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
5413
5414
#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
5415
#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
5416
5417
#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
5418
#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
5419
5420
#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
5421
#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
5422
5423
#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
5424
#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
5425
5426
#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
5427
#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
5428
5429
#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
5430
#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
5431
5432
5433
/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
5434
#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
5435
#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
5436
#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
5437
#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
5438
#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
5439
#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
5440
#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
5441
#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
5442
#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
5443
#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
5444
#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
5445
#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
5446
#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
5447
#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
5448
#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
5449
#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
5450
5451
#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
5452
#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
5453
5454
5455
/* TWI.CTRL bit masks and bit positions */
5456
#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
5457
#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
5458
5459
#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
5460
#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
5461
5462
5463
/* PORT - Port Configuration */
5464
/* PORTCFG.VPCTRLA bit masks and bit positions */
5465
#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
5466
#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
5467
#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
5468
#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
5469
#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
5470
#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
5471
#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
5472
#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
5473
#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
5474
#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
5475
5476
#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
5477
#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
5478
#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
5479
#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
5480
#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
5481
#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
5482
#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
5483
#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
5484
#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
5485
#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
5486
5487
5488
/* PORTCFG.VPCTRLB bit masks and bit positions */
5489
#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
5490
#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
5491
#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
5492
#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
5493
#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
5494
#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
5495
#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
5496
#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
5497
#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
5498
#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
5499
5500
#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
5501
#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
5502
#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
5503
#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
5504
#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
5505
#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
5506
#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
5507
#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
5508
#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
5509
#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
5510
5511
5512
/* PORTCFG.CLKEVOUT bit masks and bit positions */
5513
#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
5514
#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
5515
#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
5516
#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
5517
#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
5518
#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
5519
5520
#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
5521
#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
5522
#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
5523
#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
5524
#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
5525
#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
5526
5527
5528
/* VPORT.INTFLAGS bit masks and bit positions */
5529
#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
5530
#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
5531
5532
#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
5533
#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
5534
5535
5536
/* PORT.INTCTRL bit masks and bit positions */
5537
#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
5538
#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
5539
#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
5540
#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
5541
#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
5542
#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
5543
5544
#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
5545
#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
5546
#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
5547
#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
5548
#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
5549
#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
5550
5551
5552
/* PORT.INTFLAGS bit masks and bit positions */
5553
#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
5554
#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
5555
5556
#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
5557
#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
5558
5559
5560
/* PORT.PIN0CTRL bit masks and bit positions */
5561
#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
5562
#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
5563
5564
#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
5565
#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
5566
5567
#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
5568
#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
5569
#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
5570
#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
5571
#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
5572
#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
5573
#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
5574
#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
5575
5576
#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
5577
#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
5578
#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
5579
#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
5580
#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
5581
#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
5582
#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
5583
#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
5584
5585
5586
/* PORT.PIN1CTRL bit masks and bit positions */
5587
/* PORT_SRLEN_bm Predefined. */
5588
/* PORT_SRLEN_bp Predefined. */
5589
5590
/* PORT_INVEN_bm Predefined. */
5591
/* PORT_INVEN_bp Predefined. */
5592
5593
/* PORT_OPC_gm Predefined. */
5594
/* PORT_OPC_gp Predefined. */
5595
/* PORT_OPC0_bm Predefined. */
5596
/* PORT_OPC0_bp Predefined. */
5597
/* PORT_OPC1_bm Predefined. */
5598
/* PORT_OPC1_bp Predefined. */
5599
/* PORT_OPC2_bm Predefined. */
5600
/* PORT_OPC2_bp Predefined. */
5601
5602
/* PORT_ISC_gm Predefined. */
5603
/* PORT_ISC_gp Predefined. */
5604
/* PORT_ISC0_bm Predefined. */
5605
/* PORT_ISC0_bp Predefined. */
5606
/* PORT_ISC1_bm Predefined. */
5607
/* PORT_ISC1_bp Predefined. */
5608
/* PORT_ISC2_bm Predefined. */
5609
/* PORT_ISC2_bp Predefined. */
5610
5611
5612
/* PORT.PIN2CTRL bit masks and bit positions */
5613
/* PORT_SRLEN_bm Predefined. */
5614
/* PORT_SRLEN_bp Predefined. */
5615
5616
/* PORT_INVEN_bm Predefined. */
5617
/* PORT_INVEN_bp Predefined. */
5618
5619
/* PORT_OPC_gm Predefined. */
5620
/* PORT_OPC_gp Predefined. */
5621
/* PORT_OPC0_bm Predefined. */
5622
/* PORT_OPC0_bp Predefined. */
5623
/* PORT_OPC1_bm Predefined. */
5624
/* PORT_OPC1_bp Predefined. */
5625
/* PORT_OPC2_bm Predefined. */
5626
/* PORT_OPC2_bp Predefined. */
5627
5628
/* PORT_ISC_gm Predefined. */
5629
/* PORT_ISC_gp Predefined. */
5630
/* PORT_ISC0_bm Predefined. */
5631
/* PORT_ISC0_bp Predefined. */
5632
/* PORT_ISC1_bm Predefined. */
5633
/* PORT_ISC1_bp Predefined. */
5634
/* PORT_ISC2_bm Predefined. */
5635
/* PORT_ISC2_bp Predefined. */
5636
5637
5638
/* PORT.PIN3CTRL bit masks and bit positions */
5639
/* PORT_SRLEN_bm Predefined. */
5640
/* PORT_SRLEN_bp Predefined. */
5641
5642
/* PORT_INVEN_bm Predefined. */
5643
/* PORT_INVEN_bp Predefined. */
5644
5645
/* PORT_OPC_gm Predefined. */
5646
/* PORT_OPC_gp Predefined. */
5647
/* PORT_OPC0_bm Predefined. */
5648
/* PORT_OPC0_bp Predefined. */
5649
/* PORT_OPC1_bm Predefined. */
5650
/* PORT_OPC1_bp Predefined. */
5651
/* PORT_OPC2_bm Predefined. */
5652
/* PORT_OPC2_bp Predefined. */
5653
5654
/* PORT_ISC_gm Predefined. */
5655
/* PORT_ISC_gp Predefined. */
5656
/* PORT_ISC0_bm Predefined. */
5657
/* PORT_ISC0_bp Predefined. */
5658
/* PORT_ISC1_bm Predefined. */
5659
/* PORT_ISC1_bp Predefined. */
5660
/* PORT_ISC2_bm Predefined. */
5661
/* PORT_ISC2_bp Predefined. */
5662
5663
5664
/* PORT.PIN4CTRL bit masks and bit positions */
5665
/* PORT_SRLEN_bm Predefined. */
5666
/* PORT_SRLEN_bp Predefined. */
5667
5668
/* PORT_INVEN_bm Predefined. */
5669
/* PORT_INVEN_bp Predefined. */
5670
5671
/* PORT_OPC_gm Predefined. */
5672
/* PORT_OPC_gp Predefined. */
5673
/* PORT_OPC0_bm Predefined. */
5674
/* PORT_OPC0_bp Predefined. */
5675
/* PORT_OPC1_bm Predefined. */
5676
/* PORT_OPC1_bp Predefined. */
5677
/* PORT_OPC2_bm Predefined. */
5678
/* PORT_OPC2_bp Predefined. */
5679
5680
/* PORT_ISC_gm Predefined. */
5681
/* PORT_ISC_gp Predefined. */
5682
/* PORT_ISC0_bm Predefined. */
5683
/* PORT_ISC0_bp Predefined. */
5684
/* PORT_ISC1_bm Predefined. */
5685
/* PORT_ISC1_bp Predefined. */
5686
/* PORT_ISC2_bm Predefined. */
5687
/* PORT_ISC2_bp Predefined. */
5688
5689
5690
/* PORT.PIN5CTRL bit masks and bit positions */
5691
/* PORT_SRLEN_bm Predefined. */
5692
/* PORT_SRLEN_bp Predefined. */
5693
5694
/* PORT_INVEN_bm Predefined. */
5695
/* PORT_INVEN_bp Predefined. */
5696
5697
/* PORT_OPC_gm Predefined. */
5698
/* PORT_OPC_gp Predefined. */
5699
/* PORT_OPC0_bm Predefined. */
5700
/* PORT_OPC0_bp Predefined. */
5701
/* PORT_OPC1_bm Predefined. */
5702
/* PORT_OPC1_bp Predefined. */
5703
/* PORT_OPC2_bm Predefined. */
5704
/* PORT_OPC2_bp Predefined. */
5705
5706
/* PORT_ISC_gm Predefined. */
5707
/* PORT_ISC_gp Predefined. */
5708
/* PORT_ISC0_bm Predefined. */
5709
/* PORT_ISC0_bp Predefined. */
5710
/* PORT_ISC1_bm Predefined. */
5711
/* PORT_ISC1_bp Predefined. */
5712
/* PORT_ISC2_bm Predefined. */
5713
/* PORT_ISC2_bp Predefined. */
5714
5715
5716
/* PORT.PIN6CTRL bit masks and bit positions */
5717
/* PORT_SRLEN_bm Predefined. */
5718
/* PORT_SRLEN_bp Predefined. */
5719
5720
/* PORT_INVEN_bm Predefined. */
5721
/* PORT_INVEN_bp Predefined. */
5722
5723
/* PORT_OPC_gm Predefined. */
5724
/* PORT_OPC_gp Predefined. */
5725
/* PORT_OPC0_bm Predefined. */
5726
/* PORT_OPC0_bp Predefined. */
5727
/* PORT_OPC1_bm Predefined. */
5728
/* PORT_OPC1_bp Predefined. */
5729
/* PORT_OPC2_bm Predefined. */
5730
/* PORT_OPC2_bp Predefined. */
5731
5732
/* PORT_ISC_gm Predefined. */
5733
/* PORT_ISC_gp Predefined. */
5734
/* PORT_ISC0_bm Predefined. */
5735
/* PORT_ISC0_bp Predefined. */
5736
/* PORT_ISC1_bm Predefined. */
5737
/* PORT_ISC1_bp Predefined. */
5738
/* PORT_ISC2_bm Predefined. */
5739
/* PORT_ISC2_bp Predefined. */
5740
5741
5742
/* PORT.PIN7CTRL bit masks and bit positions */
5743
/* PORT_SRLEN_bm Predefined. */
5744
/* PORT_SRLEN_bp Predefined. */
5745
5746
/* PORT_INVEN_bm Predefined. */
5747
/* PORT_INVEN_bp Predefined. */
5748
5749
/* PORT_OPC_gm Predefined. */
5750
/* PORT_OPC_gp Predefined. */
5751
/* PORT_OPC0_bm Predefined. */
5752
/* PORT_OPC0_bp Predefined. */
5753
/* PORT_OPC1_bm Predefined. */
5754
/* PORT_OPC1_bp Predefined. */
5755
/* PORT_OPC2_bm Predefined. */
5756
/* PORT_OPC2_bp Predefined. */
5757
5758
/* PORT_ISC_gm Predefined. */
5759
/* PORT_ISC_gp Predefined. */
5760
/* PORT_ISC0_bm Predefined. */
5761
/* PORT_ISC0_bp Predefined. */
5762
/* PORT_ISC1_bm Predefined. */
5763
/* PORT_ISC1_bp Predefined. */
5764
/* PORT_ISC2_bm Predefined. */
5765
/* PORT_ISC2_bp Predefined. */
5766
5767
5768
/* TC - 16-bit Timer/Counter With PWM */
5769
/* TC0.CTRLA bit masks and bit positions */
5770
#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
5771
#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
5772
#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
5773
#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
5774
#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
5775
#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
5776
#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
5777
#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
5778
#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
5779
#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
5780
5781
5782
/* TC0.CTRLB bit masks and bit positions */
5783
#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
5784
#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
5785
5786
#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
5787
#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
5788
5789
#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
5790
#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
5791
5792
#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
5793
#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
5794
5795
#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
5796
#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
5797
#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
5798
#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
5799
#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
5800
#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
5801
#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
5802
#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
5803
5804
5805
/* TC0.CTRLC bit masks and bit positions */
5806
#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
5807
#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
5808
5809
#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
5810
#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
5811
5812
#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
5813
#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
5814
5815
#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
5816
#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
5817
5818
5819
/* TC0.CTRLD bit masks and bit positions */
5820
#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
5821
#define TC0_EVACT_gp 5 /* Event Action group position. */
5822
#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
5823
#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
5824
#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
5825
#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
5826
#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
5827
#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
5828
5829
#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
5830
#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
5831
5832
#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
5833
#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
5834
#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
5835
#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
5836
#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
5837
#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
5838
#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
5839
#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
5840
#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
5841
#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
5842
5843
5844
/* TC0.CTRLE bit masks and bit positions */
5845
#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */
5846
#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */
5847
5848
#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
5849
#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
5850
5851
5852
/* TC0.INTCTRLA bit masks and bit positions */
5853
#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
5854
#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
5855
#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
5856
#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
5857
#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
5858
#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
5859
5860
#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
5861
#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
5862
#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
5863
#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
5864
#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
5865
#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
5866
5867
5868
/* TC0.INTCTRLB bit masks and bit positions */
5869
#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
5870
#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
5871
#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
5872
#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
5873
#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
5874
#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
5875
5876
#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
5877
#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
5878
#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
5879
#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
5880
#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
5881
#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
5882
5883
#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
5884
#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
5885
#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
5886
#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
5887
#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
5888
#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
5889
5890
#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
5891
#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
5892
#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
5893
#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
5894
#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
5895
#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
5896
5897
5898
/* TC0.CTRLFCLR bit masks and bit positions */
5899
#define TC0_CMD_gm 0x0C /* Command group mask. */
5900
#define TC0_CMD_gp 2 /* Command group position. */
5901
#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
5902
#define TC0_CMD0_bp 2 /* Command bit 0 position. */
5903
#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
5904
#define TC0_CMD1_bp 3 /* Command bit 1 position. */
5905
5906
#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
5907
#define TC0_LUPD_bp 1 /* Lock Update bit position. */
5908
5909
#define TC0_DIR_bm 0x01 /* Direction bit mask. */
5910
#define TC0_DIR_bp 0 /* Direction bit position. */
5911
5912
5913
/* TC0.CTRLFSET bit masks and bit positions */
5914
/* TC0_CMD_gm Predefined. */
5915
/* TC0_CMD_gp Predefined. */
5916
/* TC0_CMD0_bm Predefined. */
5917
/* TC0_CMD0_bp Predefined. */
5918
/* TC0_CMD1_bm Predefined. */
5919
/* TC0_CMD1_bp Predefined. */
5920
5921
/* TC0_LUPD_bm Predefined. */
5922
/* TC0_LUPD_bp Predefined. */
5923
5924
/* TC0_DIR_bm Predefined. */
5925
/* TC0_DIR_bp Predefined. */
5926
5927
5928
/* TC0.CTRLGCLR bit masks and bit positions */
5929
#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
5930
#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
5931
5932
#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
5933
#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
5934
5935
#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
5936
#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
5937
5938
#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
5939
#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
5940
5941
#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
5942
#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
5943
5944
5945
/* TC0.CTRLGSET bit masks and bit positions */
5946
/* TC0_CCDBV_bm Predefined. */
5947
/* TC0_CCDBV_bp Predefined. */
5948
5949
/* TC0_CCCBV_bm Predefined. */
5950
/* TC0_CCCBV_bp Predefined. */
5951
5952
/* TC0_CCBBV_bm Predefined. */
5953
/* TC0_CCBBV_bp Predefined. */
5954
5955
/* TC0_CCABV_bm Predefined. */
5956
/* TC0_CCABV_bp Predefined. */
5957
5958
/* TC0_PERBV_bm Predefined. */
5959
/* TC0_PERBV_bp Predefined. */
5960
5961
5962
/* TC0.INTFLAGS bit masks and bit positions */
5963
#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
5964
#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
5965
5966
#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
5967
#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
5968
5969
#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
5970
#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
5971
5972
#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
5973
#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
5974
5975
#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
5976
#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
5977
5978
#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
5979
#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
5980
5981
5982
/* TC1.CTRLA bit masks and bit positions */
5983
#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
5984
#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
5985
#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
5986
#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
5987
#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
5988
#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
5989
#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
5990
#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
5991
#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
5992
#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
5993
5994
5995
/* TC1.CTRLB bit masks and bit positions */
5996
#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
5997
#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
5998
5999
#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
6000
#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
6001
6002
#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
6003
#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
6004
#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
6005
#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
6006
#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
6007
#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
6008
#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
6009
#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
6010
6011
6012
/* TC1.CTRLC bit masks and bit positions */
6013
#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
6014
#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
6015
6016
#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
6017
#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
6018
6019
6020
/* TC1.CTRLD bit masks and bit positions */
6021
#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
6022
#define TC1_EVACT_gp 5 /* Event Action group position. */
6023
#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
6024
#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
6025
#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
6026
#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
6027
#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
6028
#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
6029
6030
#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
6031
#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
6032
6033
#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
6034
#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
6035
#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
6036
#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
6037
#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
6038
#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
6039
#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
6040
#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
6041
#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
6042
#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
6043
6044
6045
/* TC1.CTRLE bit masks and bit positions */
6046
#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */
6047
#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */
6048
6049
#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
6050
#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
6051
6052
6053
/* TC1.INTCTRLA bit masks and bit positions */
6054
#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
6055
#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
6056
#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
6057
#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
6058
#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
6059
#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
6060
6061
#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
6062
#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
6063
#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
6064
#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
6065
#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
6066
#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
6067
6068
6069
/* TC1.INTCTRLB bit masks and bit positions */
6070
#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
6071
#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
6072
#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
6073
#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
6074
#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
6075
#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
6076
6077
#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
6078
#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
6079
#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
6080
#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
6081
#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
6082
#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
6083
6084
6085
/* TC1.CTRLFCLR bit masks and bit positions */
6086
#define TC1_CMD_gm 0x0C /* Command group mask. */
6087
#define TC1_CMD_gp 2 /* Command group position. */
6088
#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
6089
#define TC1_CMD0_bp 2 /* Command bit 0 position. */
6090
#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
6091
#define TC1_CMD1_bp 3 /* Command bit 1 position. */
6092
6093
#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
6094
#define TC1_LUPD_bp 1 /* Lock Update bit position. */
6095
6096
#define TC1_DIR_bm 0x01 /* Direction bit mask. */
6097
#define TC1_DIR_bp 0 /* Direction bit position. */
6098
6099
6100
/* TC1.CTRLFSET bit masks and bit positions */
6101
/* TC1_CMD_gm Predefined. */
6102
/* TC1_CMD_gp Predefined. */
6103
/* TC1_CMD0_bm Predefined. */
6104
/* TC1_CMD0_bp Predefined. */
6105
/* TC1_CMD1_bm Predefined. */
6106
/* TC1_CMD1_bp Predefined. */
6107
6108
/* TC1_LUPD_bm Predefined. */
6109
/* TC1_LUPD_bp Predefined. */
6110
6111
/* TC1_DIR_bm Predefined. */
6112
/* TC1_DIR_bp Predefined. */
6113
6114
6115
/* TC1.CTRLGCLR bit masks and bit positions */
6116
#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
6117
#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
6118
6119
#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
6120
#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
6121
6122
#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
6123
#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
6124
6125
6126
/* TC1.CTRLGSET bit masks and bit positions */
6127
/* TC1_CCBBV_bm Predefined. */
6128
/* TC1_CCBBV_bp Predefined. */
6129
6130
/* TC1_CCABV_bm Predefined. */
6131
/* TC1_CCABV_bp Predefined. */
6132
6133
/* TC1_PERBV_bm Predefined. */
6134
/* TC1_PERBV_bp Predefined. */
6135
6136
6137
/* TC1.INTFLAGS bit masks and bit positions */
6138
#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
6139
#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
6140
6141
#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
6142
#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
6143
6144
#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
6145
#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
6146
6147
#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
6148
#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
6149
6150
6151
/* AWEX.CTRL bit masks and bit positions */
6152
#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
6153
#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
6154
6155
#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
6156
#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
6157
6158
#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
6159
#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
6160
6161
#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
6162
#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
6163
6164
#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
6165
#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
6166
6167
#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
6168
#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
6169
6170
6171
/* AWEX.FDCTRL bit masks and bit positions */
6172
#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
6173
#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
6174
6175
#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
6176
#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
6177
6178
#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
6179
#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
6180
#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
6181
#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
6182
#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
6183
#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
6184
6185
6186
/* AWEX.STATUS bit masks and bit positions */
6187
#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
6188
#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
6189
6190
#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
6191
#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
6192
6193
#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
6194
#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
6195
6196
6197
/* HIRES.CTRL bit masks and bit positions */
6198
#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
6199
#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
6200
#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
6201
#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
6202
#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
6203
#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
6204
6205
6206
/* USART - Universal Asynchronous Receiver-Transmitter */
6207
/* USART.STATUS bit masks and bit positions */
6208
#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
6209
#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
6210
6211
#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
6212
#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
6213
6214
#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
6215
#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
6216
6217
#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
6218
#define USART_FERR_bp 4 /* Frame Error bit position. */
6219
6220
#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
6221
#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
6222
6223
#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
6224
#define USART_PERR_bp 2 /* Parity Error bit position. */
6225
6226
#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
6227
#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
6228
6229
6230
/* USART.CTRLA bit masks and bit positions */
6231
#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
6232
#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
6233
#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
6234
#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
6235
#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
6236
#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
6237
6238
#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
6239
#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
6240
#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
6241
#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
6242
#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
6243
#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
6244
6245
#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
6246
#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
6247
#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
6248
#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
6249
#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
6250
#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
6251
6252
6253
/* USART.CTRLB bit masks and bit positions */
6254
#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
6255
#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
6256
6257
#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
6258
#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
6259
6260
#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
6261
#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
6262
6263
#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
6264
#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
6265
6266
#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
6267
#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
6268
6269
6270
/* USART.CTRLC bit masks and bit positions */
6271
#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
6272
#define USART_CMODE_gp 6 /* Communication Mode group position. */
6273
#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
6274
#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
6275
#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
6276
#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
6277
6278
#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
6279
#define USART_PMODE_gp 4 /* Parity Mode group position. */
6280
#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
6281
#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
6282
#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
6283
#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
6284
6285
#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
6286
#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
6287
6288
#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
6289
#define USART_CHSIZE_gp 0 /* Character Size group position. */
6290
#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
6291
#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
6292
#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
6293
#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
6294
#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
6295
#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
6296
6297
6298
/* USART.BAUDCTRLA bit masks and bit positions */
6299
#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
6300
#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
6301
#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
6302
#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
6303
#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
6304
#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
6305
#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
6306
#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
6307
#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
6308
#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
6309
#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
6310
#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
6311
#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
6312
#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
6313
#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
6314
#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
6315
#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
6316
#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
6317
6318
6319
/* USART.BAUDCTRLB bit masks and bit positions */
6320
#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
6321
#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
6322
#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
6323
#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
6324
#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
6325
#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
6326
#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
6327
#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
6328
#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
6329
#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
6330
6331
/* USART_BSEL_gm Predefined. */
6332
/* USART_BSEL_gp Predefined. */
6333
/* USART_BSEL0_bm Predefined. */
6334
/* USART_BSEL0_bp Predefined. */
6335
/* USART_BSEL1_bm Predefined. */
6336
/* USART_BSEL1_bp Predefined. */
6337
/* USART_BSEL2_bm Predefined. */
6338
/* USART_BSEL2_bp Predefined. */
6339
/* USART_BSEL3_bm Predefined. */
6340
/* USART_BSEL3_bp Predefined. */
6341
6342
6343
/* SPI - Serial Peripheral Interface */
6344
/* SPI.CTRL bit masks and bit positions */
6345
#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
6346
#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
6347
6348
#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
6349
#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
6350
6351
#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
6352
#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
6353
6354
#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
6355
#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
6356
6357
#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
6358
#define SPI_MODE_gp 2 /* SPI Mode group position. */
6359
#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
6360
#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
6361
#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
6362
#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
6363
6364
#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
6365
#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
6366
#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
6367
#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
6368
#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
6369
#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
6370
6371
6372
/* SPI.INTCTRL bit masks and bit positions */
6373
#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
6374
#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
6375
#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
6376
#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
6377
#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
6378
#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
6379
6380
6381
/* SPI.STATUS bit masks and bit positions */
6382
#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
6383
#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
6384
6385
#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
6386
#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
6387
6388
6389
/* IRCOM - IR Communication Module */
6390
/* IRCOM.CTRL bit masks and bit positions */
6391
#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
6392
#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
6393
#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
6394
#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
6395
#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
6396
#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
6397
#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
6398
#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
6399
#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
6400
#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
6401
6402
6403
/* AES - AES Module */
6404
/* AES.CTRL bit masks and bit positions */
6405
#define AES_START_bm 0x80 /* Start/Run bit mask. */
6406
#define AES_START_bp 7 /* Start/Run bit position. */
6407
6408
#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
6409
#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
6410
6411
#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
6412
#define AES_RESET_bp 5 /* AES Software Reset bit position. */
6413
6414
#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
6415
#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
6416
6417
#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
6418
#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
6419
6420
6421
/* AES.STATUS bit masks and bit positions */
6422
#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
6423
#define AES_ERROR_bp 7 /* AES Error bit position. */
6424
6425
#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
6426
#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
6427
6428
6429
/* AES.INTCTRL bit masks and bit positions */
6430
#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
6431
#define AES_INTLVL_gp 0 /* Interrupt level group position. */
6432
#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
6433
#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
6434
#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
6435
#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
6436
6437
6438
6439
// Generic Port Pins
6440
6441
#define PIN0_bm 0x01
6442
#define PIN0_bp 0
6443
#define PIN1_bm 0x02
6444
#define PIN1_bp 1
6445
#define PIN2_bm 0x04
6446
#define PIN2_bp 2
6447
#define PIN3_bm 0x08
6448
#define PIN3_bp 3
6449
#define PIN4_bm 0x10
6450
#define PIN4_bp 4
6451
#define PIN5_bm 0x20
6452
#define PIN5_bp 5
6453
#define PIN6_bm 0x40
6454
#define PIN6_bp 6
6455
#define PIN7_bm 0x80
6456
#define PIN7_bp 7
6457
6458
6459
/* ========== Interrupt Vector Definitions ========== */
6460
/* Vector 0 is the reset vector */
6461
6462
/* OSC interrupt vectors */
6463
#define OSC_XOSCF_vect_num 1
6464
#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */
6465
6466
/* PORTC interrupt vectors */
6467
#define PORTC_INT0_vect_num 2
6468
#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
6469
#define PORTC_INT1_vect_num 3
6470
#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
6471
6472
/* PORTR interrupt vectors */
6473
#define PORTR_INT0_vect_num 4
6474
#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
6475
#define PORTR_INT1_vect_num 5
6476
#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
6477
6478
/* DMA interrupt vectors */
6479
#define DMA_CH0_vect_num 6
6480
#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
6481
#define DMA_CH1_vect_num 7
6482
#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
6483
#define DMA_CH2_vect_num 8
6484
#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
6485
#define DMA_CH3_vect_num 9
6486
#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
6487
6488
/* RTC interrupt vectors */
6489
#define RTC_OVF_vect_num 10
6490
#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
6491
#define RTC_COMP_vect_num 11
6492
#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
6493
6494
/* TWIC interrupt vectors */
6495
#define TWIC_TWIS_vect_num 12
6496
#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
6497
#define TWIC_TWIM_vect_num 13
6498
#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
6499
6500
/* TCC0 interrupt vectors */
6501
#define TCC0_OVF_vect_num 14
6502
#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
6503
#define TCC0_ERR_vect_num 15
6504
#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
6505
#define TCC0_CCA_vect_num 16
6506
#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
6507
#define TCC0_CCB_vect_num 17
6508
#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
6509
#define TCC0_CCC_vect_num 18
6510
#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
6511
#define TCC0_CCD_vect_num 19
6512
#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
6513
6514
/* TCC1 interrupt vectors */
6515
#define TCC1_OVF_vect_num 20
6516
#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
6517
#define TCC1_ERR_vect_num 21
6518
#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
6519
#define TCC1_CCA_vect_num 22
6520
#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
6521
#define TCC1_CCB_vect_num 23
6522
#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
6523
6524
/* SPIC interrupt vectors */
6525
#define SPIC_INT_vect_num 24
6526
#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
6527
6528
/* USARTC0 interrupt vectors */
6529
#define USARTC0_RXC_vect_num 25
6530
#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
6531
#define USARTC0_DRE_vect_num 26
6532
#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
6533
#define USARTC0_TXC_vect_num 27
6534
#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
6535
6536
/* USARTC1 interrupt vectors */
6537
#define USARTC1_RXC_vect_num 28
6538
#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
6539
#define USARTC1_DRE_vect_num 29
6540
#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
6541
#define USARTC1_TXC_vect_num 30
6542
#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
6543
6544
/* AES interrupt vectors */
6545
#define AES_INT_vect_num 31
6546
#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
6547
6548
/* NVM interrupt vectors */
6549
#define NVM_EE_vect_num 32
6550
#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
6551
#define NVM_SPM_vect_num 33
6552
#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
6553
6554
/* PORTB interrupt vectors */
6555
#define PORTB_INT0_vect_num 34
6556
#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
6557
#define PORTB_INT1_vect_num 35
6558
#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
6559
6560
/* ACB interrupt vectors */
6561
#define ACB_AC0_vect_num 36
6562
#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */
6563
#define ACB_AC1_vect_num 37
6564
#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */
6565
#define ACB_ACW_vect_num 38
6566
#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */
6567
6568
/* ADCB interrupt vectors */
6569
#define ADCB_CH0_vect_num 39
6570
#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */
6571
#define ADCB_CH1_vect_num 40
6572
#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */
6573
#define ADCB_CH2_vect_num 41
6574
#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */
6575
#define ADCB_CH3_vect_num 42
6576
#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */
6577
6578
/* PORTE interrupt vectors */
6579
#define PORTE_INT0_vect_num 43
6580
#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
6581
#define PORTE_INT1_vect_num 44
6582
#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
6583
6584
/* TWIE interrupt vectors */
6585
#define TWIE_TWIS_vect_num 45
6586
#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
6587
#define TWIE_TWIM_vect_num 46
6588
#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
6589
6590
/* TCE0 interrupt vectors */
6591
#define TCE0_OVF_vect_num 47
6592
#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
6593
#define TCE0_ERR_vect_num 48
6594
#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
6595
#define TCE0_CCA_vect_num 49
6596
#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
6597
#define TCE0_CCB_vect_num 50
6598
#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
6599
#define TCE0_CCC_vect_num 51
6600
#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
6601
#define TCE0_CCD_vect_num 52
6602
#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
6603
6604
/* TCE1 interrupt vectors */
6605
#define TCE1_OVF_vect_num 53
6606
#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
6607
#define TCE1_ERR_vect_num 54
6608
#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */
6609
#define TCE1_CCA_vect_num 55
6610
#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */
6611
#define TCE1_CCB_vect_num 56
6612
#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */
6613
6614
/* SPIE interrupt vectors */
6615
#define SPIE_INT_vect_num 57
6616
#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */
6617
6618
/* USARTE0 interrupt vectors */
6619
#define USARTE0_RXC_vect_num 58
6620
#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
6621
#define USARTE0_DRE_vect_num 59
6622
#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
6623
#define USARTE0_TXC_vect_num 60
6624
#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
6625
6626
/* USARTE1 interrupt vectors */
6627
#define USARTE1_RXC_vect_num 61
6628
#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */
6629
#define USARTE1_DRE_vect_num 62
6630
#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */
6631
#define USARTE1_TXC_vect_num 63
6632
#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */
6633
6634
/* PORTD interrupt vectors */
6635
#define PORTD_INT0_vect_num 64
6636
#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
6637
#define PORTD_INT1_vect_num 65
6638
#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
6639
6640
/* PORTA interrupt vectors */
6641
#define PORTA_INT0_vect_num 66
6642
#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
6643
#define PORTA_INT1_vect_num 67
6644
#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
6645
6646
/* ACA interrupt vectors */
6647
#define ACA_AC0_vect_num 68
6648
#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
6649
#define ACA_AC1_vect_num 69
6650
#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
6651
#define ACA_ACW_vect_num 70
6652
#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
6653
6654
/* ADCA interrupt vectors */
6655
#define ADCA_CH0_vect_num 71
6656
#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
6657
#define ADCA_CH1_vect_num 72
6658
#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
6659
#define ADCA_CH2_vect_num 73
6660
#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
6661
#define ADCA_CH3_vect_num 74
6662
#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
6663
6664
/* TCD0 interrupt vectors */
6665
#define TCD0_OVF_vect_num 77
6666
#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
6667
#define TCD0_ERR_vect_num 78
6668
#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
6669
#define TCD0_CCA_vect_num 79
6670
#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
6671
#define TCD0_CCB_vect_num 80
6672
#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
6673
#define TCD0_CCC_vect_num 81
6674
#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
6675
#define TCD0_CCD_vect_num 82
6676
#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
6677
6678
/* TCD1 interrupt vectors */
6679
#define TCD1_OVF_vect_num 83
6680
#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
6681
#define TCD1_ERR_vect_num 84
6682
#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
6683
#define TCD1_CCA_vect_num 85
6684
#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
6685
#define TCD1_CCB_vect_num 86
6686
#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
6687
6688
/* SPID interrupt vectors */
6689
#define SPID_INT_vect_num 87
6690
#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
6691
6692
/* USARTD0 interrupt vectors */
6693
#define USARTD0_RXC_vect_num 88
6694
#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
6695
#define USARTD0_DRE_vect_num 89
6696
#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
6697
#define USARTD0_TXC_vect_num 90
6698
#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
6699
6700
/* USARTD1 interrupt vectors */
6701
#define USARTD1_RXC_vect_num 91
6702
#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
6703
#define USARTD1_DRE_vect_num 92
6704
#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
6705
#define USARTD1_TXC_vect_num 93
6706
#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
6707
6708
/* PORTF interrupt vectors */
6709
#define PORTF_INT0_vect_num 104
6710
#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
6711
#define PORTF_INT1_vect_num 105
6712
#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
6713
6714
/* TCF0 interrupt vectors */
6715
#define TCF0_OVF_vect_num 108
6716
#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
6717
#define TCF0_ERR_vect_num 109
6718
#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
6719
#define TCF0_CCA_vect_num 110
6720
#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
6721
#define TCF0_CCB_vect_num 111
6722
#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
6723
#define TCF0_CCC_vect_num 112
6724
#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
6725
#define TCF0_CCD_vect_num 113
6726
#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
6727
6728
/* USARTF0 interrupt vectors */
6729
#define USARTF0_RXC_vect_num 119
6730
#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */
6731
#define USARTF0_DRE_vect_num 120
6732
#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */
6733
#define USARTF0_TXC_vect_num 121
6734
#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */
6735
6736
6737
#define _VECTOR_SIZE 4 /* Size of individual vector. */
6738
#define _VECTORS_SIZE (122 * _VECTOR_SIZE)
6739
6740
6741
/* ========== Constants ========== */
6742
6743
#define PROGMEM_START (0x0000)
6744
#define PROGMEM_SIZE (204800)
6745
#define PROGMEM_PAGE_SIZE (512)
6746
#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
6747
6748
#define APP_SECTION_START (0x0000)
6749
#define APP_SECTION_SIZE (196608)
6750
#define APP_SECTION_PAGE_SIZE (512)
6751
#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
6752
6753
#define APPTABLE_SECTION_START (0x2E000)
6754
#define APPTABLE_SECTION_SIZE (8192)
6755
#define APPTABLE_SECTION_PAGE_SIZE (512)
6756
#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
6757
6758
#define BOOT_SECTION_START (0x30000)
6759
#define BOOT_SECTION_SIZE (8192)
6760
#define BOOT_SECTION_PAGE_SIZE (512)
6761
#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
6762
6763
#define DATAMEM_START (0x0000)
6764
#define DATAMEM_SIZE (16777216)
6765
#define DATAMEM_PAGE_SIZE (0)
6766
#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
6767
6768
#define IO_START (0x0000)
6769
#define IO_SIZE (4096)
6770
#define IO_PAGE_SIZE (0)
6771
#define IO_END (IO_START + IO_SIZE - 1)
6772
6773
#define MAPPED_EEPROM_START (0x1000)
6774
#define MAPPED_EEPROM_SIZE (4096)
6775
#define MAPPED_EEPROM_PAGE_SIZE (0)
6776
#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
6777
6778
#define INTERNAL_SRAM_START (0x2000)
6779
#define INTERNAL_SRAM_SIZE (16384)
6780
#define INTERNAL_SRAM_PAGE_SIZE (0)
6781
#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
6782
6783
#define EEPROM_START (0x0000)
6784
#define EEPROM_SIZE (4096)
6785
#define EEPROM_PAGE_SIZE (32)
6786
#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
6787
6788
#define FUSE_START (0x0000)
6789
#define FUSE_SIZE (6)
6790
#define FUSE_PAGE_SIZE (0)
6791
#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
6792
6793
#define LOCKBIT_START (0x0000)
6794
#define LOCKBIT_SIZE (1)
6795
#define LOCKBIT_PAGE_SIZE (0)
6796
#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
6797
6798
#define SIGNATURES_START (0x0000)
6799
#define SIGNATURES_SIZE (3)
6800
#define SIGNATURES_PAGE_SIZE (0)
6801
#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
6802
6803
#define USER_SIGNATURES_START (0x0000)
6804
#define USER_SIGNATURES_SIZE (512)
6805
#define USER_SIGNATURES_PAGE_SIZE (0)
6806
#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
6807
6808
#define PROD_SIGNATURES_START (0x0000)
6809
#define PROD_SIGNATURES_SIZE (52)
6810
#define PROD_SIGNATURES_PAGE_SIZE (0)
6811
#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
6812
6813
#define FLASHEND PROGMEM_END
6814
#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
6815
#define RAMSTART INTERNAL_SRAM_START
6816
#define RAMSIZE INTERNAL_SRAM_SIZE
6817
#define RAMEND INTERNAL_SRAM_END
6818
#define XRAMSTART EXTERNAL_SRAM_START
6819
#define XRAMSIZE EXTERNAL_SRAM_SIZE
6820
#define XRAMEND INTERNAL_SRAM_END
6821
#define E2END EEPROM_END
6822
#define E2PAGESIZE EEPROM_PAGE_SIZE
6823
6824
6825
/* ========== Fuses ========== */
6826
#define FUSE_MEMORY_SIZE 6
6827
6828
/* Fuse Byte 0 */
6829
#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
6830
#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
6831
#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
6832
#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
6833
#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
6834
#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
6835
#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
6836
#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
6837
#define FUSE0_DEFAULT (0xFF)
6838
6839
/* Fuse Byte 1 */
6840
#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
6841
#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
6842
#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
6843
#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
6844
#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
6845
#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
6846
#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
6847
#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
6848
#define FUSE1_DEFAULT (0xFF)
6849
6850
/* Fuse Byte 2 */
6851
#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
6852
#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
6853
#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
6854
#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
6855
#define FUSE2_DEFAULT (0xFF)
6856
6857
/* Fuse Byte 3 Reserved */
6858
6859
/* Fuse Byte 4 */
6860
#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
6861
#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
6862
#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
6863
#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
6864
#define FUSE4_DEFAULT (0xFF)
6865
6866
/* Fuse Byte 5 */
6867
#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
6868
#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
6869
#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
6870
#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
6871
#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
6872
#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
6873
#define FUSE5_DEFAULT (0xFF)
6874
6875
6876
/* ========== Lock Bits ========== */
6877
#define __LOCK_BITS_EXIST
6878
#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
6879
#define __BOOT_LOCK_APPLICATION_BITS_EXIST
6880
#define __BOOT_LOCK_BOOT_BITS_EXIST
6881
6882
6883
/* ========== Signature ========== */
6884
#define SIGNATURE_0 0x1E
6885
#define SIGNATURE_1 0x97
6886
#define SIGNATURE_2 0x44
6887
6888
6889
#endif /* _AVR_ATxmega192A3_H_ */
6890
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