33
34
static cl::opt<int> IfCvtFnStart("ifcvt-fn-start", cl::init(-1), cl::Hidden);
34
35
static cl::opt<int> IfCvtFnStop("ifcvt-fn-stop", cl::init(-1), cl::Hidden);
35
36
static cl::opt<int> IfCvtLimit("ifcvt-limit", cl::init(-1), cl::Hidden);
36
static cl::opt<bool> DisableSimple("disable-ifcvt-simple",
37
static cl::opt<bool> DisableSimple("disable-ifcvt-simple",
37
38
cl::init(false), cl::Hidden);
38
static cl::opt<bool> DisableSimpleF("disable-ifcvt-simple-false",
39
static cl::opt<bool> DisableSimpleF("disable-ifcvt-simple-false",
39
40
cl::init(false), cl::Hidden);
40
static cl::opt<bool> DisableTriangle("disable-ifcvt-triangle",
41
static cl::opt<bool> DisableTriangle("disable-ifcvt-triangle",
41
42
cl::init(false), cl::Hidden);
42
static cl::opt<bool> DisableTriangleR("disable-ifcvt-triangle-rev",
43
cl::init(false), cl::Hidden);
44
static cl::opt<bool> DisableTriangleF("disable-ifcvt-triangle-false",
45
cl::init(false), cl::Hidden);
46
static cl::opt<bool> DisableTriangleFR("disable-ifcvt-triangle-false-rev",
43
static cl::opt<bool> DisableTriangleR("disable-ifcvt-triangle-rev",
44
cl::init(false), cl::Hidden);
45
static cl::opt<bool> DisableTriangleF("disable-ifcvt-triangle-false",
46
cl::init(false), cl::Hidden);
47
static cl::opt<bool> DisableTriangleFR("disable-ifcvt-triangle-false-rev",
47
48
cl::init(false), cl::Hidden);
48
static cl::opt<bool> DisableDiamond("disable-ifcvt-diamond",
49
static cl::opt<bool> DisableDiamond("disable-ifcvt-diamond",
49
50
cl::init(false), cl::Hidden);
51
static cl::opt<bool> IfCvtBranchFold("ifcvt-branch-fold",
52
cl::init(true), cl::Hidden);
51
54
STATISTIC(NumSimple, "Number of simple if-conversions performed");
52
55
STATISTIC(NumSimpleFalse, "Number of simple (F) if-conversions performed");
167
171
std::vector<IfcvtToken*> &Tokens);
168
172
bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl<MachineOperand> &Cond,
169
173
bool isTriangle = false, bool RevBranch = false);
170
bool AnalyzeBlocks(MachineFunction &MF,
171
std::vector<IfcvtToken*> &Tokens);
174
void AnalyzeBlocks(MachineFunction &MF, std::vector<IfcvtToken*> &Tokens);
172
175
void InvalidatePreds(MachineBasicBlock *BB);
173
176
void RemoveExtraEdges(BBInfo &BBI);
174
177
bool IfConvertSimple(BBInfo &BBI, IfcvtKind Kind);
177
180
unsigned NumDups1, unsigned NumDups2);
178
181
void PredicateBlock(BBInfo &BBI,
179
182
MachineBasicBlock::iterator E,
180
SmallVectorImpl<MachineOperand> &Cond);
183
SmallVectorImpl<MachineOperand> &Cond,
184
SmallSet<unsigned, 4> &Redefs);
181
185
void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
182
186
SmallVectorImpl<MachineOperand> &Cond,
187
SmallSet<unsigned, 4> &Redefs,
183
188
bool IgnoreBr = false);
184
void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI);
186
bool MeetIfcvtSizeLimit(unsigned Size) const {
187
return Size > 0 && Size <= TLI->getIfCvtBlockSizeLimit();
189
void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges = true);
191
bool MeetIfcvtSizeLimit(MachineBasicBlock &BB, unsigned Size) const {
192
return Size > 0 && TII->isProfitableToIfCvt(BB, Size);
195
bool MeetIfcvtSizeLimit(MachineBasicBlock &TBB, unsigned TSize,
196
MachineBasicBlock &FBB, unsigned FSize) const {
197
return TSize > 0 && FSize > 0 &&
198
TII->isProfitableToIfCvt(TBB, TSize, FBB, FSize);
190
201
// blockAlwaysFallThrough - Block ends without a terminator.
219
230
char IfConverter::ID = 0;
222
static RegisterPass<IfConverter>
223
X("if-converter", "If Converter");
233
INITIALIZE_PASS(IfConverter, "if-converter", "If Converter", false, false);
225
235
FunctionPass *llvm::createIfConverterPass() { return new IfConverter(); }
227
237
bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
228
238
TLI = MF.getTarget().getTargetLowering();
229
239
TII = MF.getTarget().getInstrInfo();
240
TRI = MF.getTarget().getRegisterInfo();
230
241
if (!TII) return false;
243
// Tail merge tend to expose more if-conversion opportunities.
244
BranchFolder BF(true);
245
bool BFChange = BF.OptimizeFunction(MF, TII,
246
MF.getTarget().getRegisterInfo(),
247
getAnalysisIfAvailable<MachineModuleInfo>());
232
249
DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'"
233
250
<< MF.getFunction()->getName() << "\'");
387
407
/// ReverseBranchCondition - Reverse the condition of the end of the block
388
408
/// branch. Swap block's 'true' and 'false' successors.
389
409
bool IfConverter::ReverseBranchCondition(BBInfo &BBI) {
410
DebugLoc dl; // FIXME: this is nowhere
390
411
if (!TII->ReverseBranchCondition(BBI.BrCond)) {
391
412
TII->RemoveBranch(*BBI.BB);
392
TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond);
413
TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
393
414
std::swap(BBI.TrueBB, BBI.FalseBB);
431
452
/// ValidTriangle - Returns true if the 'true' and 'false' blocks (along
432
453
/// with their common predecessor) forms a valid triangle shape for ifcvt.
433
454
/// If 'FalseBranch' is true, it checks if 'true' block's false branch
434
/// branches to the false branch rather than the other way around. It also
455
/// branches to the 'false' block rather than the other way around. It also
435
456
/// returns the number of instructions that the ifcvt would need to duplicate
436
457
/// if performed in 'Dups'.
437
458
bool IfConverter::ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI,
515
536
MachineBasicBlock::iterator TI = TrueBBI.BB->begin();
516
537
MachineBasicBlock::iterator FI = FalseBBI.BB->begin();
517
while (TI != TrueBBI.BB->end() && FI != FalseBBI.BB->end()) {
538
MachineBasicBlock::iterator TIE = TrueBBI.BB->end();
539
MachineBasicBlock::iterator FIE = FalseBBI.BB->end();
540
// Skip dbg_value instructions
541
while (TI != TIE && TI->isDebugValue())
543
while (FI != FIE && FI->isDebugValue())
545
while (TI != TIE && FI != FIE) {
546
// Skip dbg_value instructions. These do not count.
547
if (TI->isDebugValue()) {
548
while (TI != TIE && TI->isDebugValue())
553
if (FI->isDebugValue()) {
554
while (FI != FIE && FI->isDebugValue())
518
559
if (!TI->isIdenticalTo(FI))
525
566
TI = firstNonBranchInst(TrueBBI.BB, TII);
526
567
FI = firstNonBranchInst(FalseBBI.BB, TII);
527
while (TI != TrueBBI.BB->begin() && FI != FalseBBI.BB->begin()) {
568
MachineBasicBlock::iterator TIB = TrueBBI.BB->begin();
569
MachineBasicBlock::iterator FIB = FalseBBI.BB->begin();
570
// Skip dbg_value instructions at end of the bb's.
571
while (TI != TIB && TI->isDebugValue())
573
while (FI != FIB && FI->isDebugValue())
575
while (TI != TIB && FI != FIB) {
576
// Skip dbg_value instructions. These do not count.
577
if (TI->isDebugValue()) {
578
while (TI != TIB && TI->isDebugValue())
583
if (FI->isDebugValue()) {
584
while (FI != FIB && FI->isDebugValue())
528
589
if (!TI->isIdenticalTo(FI))
702
766
bool FNeedSub = FalseBBI.Predicate.size() > 0;
703
767
bool Enqueued = false;
704
768
if (CanRevCond && ValidDiamond(TrueBBI, FalseBBI, Dups, Dups2) &&
705
MeetIfcvtSizeLimit(TrueBBI.NonPredSize - (Dups + Dups2)) &&
706
MeetIfcvtSizeLimit(FalseBBI.NonPredSize - (Dups + Dups2)) &&
769
MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize - (Dups + Dups2),
770
*FalseBBI.BB, FalseBBI.NonPredSize - (Dups + Dups2)) &&
707
771
FeasibilityAnalysis(TrueBBI, BBI.BrCond) &&
708
772
FeasibilityAnalysis(FalseBBI, RevCond)) {
732
796
Tokens.push_back(new IfcvtToken(BBI, ICTriangle, TNeedSub, Dups));
736
800
if (ValidTriangle(TrueBBI, FalseBBI, true, Dups) &&
737
MeetIfcvtSizeLimit(TrueBBI.NonPredSize) &&
801
MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize) &&
738
802
FeasibilityAnalysis(TrueBBI, BBI.BrCond, true, true)) {
739
803
Tokens.push_back(new IfcvtToken(BBI, ICTriangleRev, TNeedSub, Dups));
743
807
if (ValidSimple(TrueBBI, Dups) &&
744
MeetIfcvtSizeLimit(TrueBBI.NonPredSize) &&
808
MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize) &&
745
809
FeasibilityAnalysis(TrueBBI, BBI.BrCond)) {
746
810
// Simple (split, no rejoin):
750
814
// | TBB---> exit
753
817
Tokens.push_back(new IfcvtToken(BBI, ICSimple, TNeedSub, Dups));
757
821
if (CanRevCond) {
758
822
// Try the other path...
759
823
if (ValidTriangle(FalseBBI, TrueBBI, false, Dups) &&
760
MeetIfcvtSizeLimit(FalseBBI.NonPredSize) &&
824
MeetIfcvtSizeLimit(*FalseBBI.BB, FalseBBI.NonPredSize) &&
761
825
FeasibilityAnalysis(FalseBBI, RevCond, true)) {
762
826
Tokens.push_back(new IfcvtToken(BBI, ICTriangleFalse, FNeedSub, Dups));
766
830
if (ValidTriangle(FalseBBI, TrueBBI, true, Dups) &&
767
MeetIfcvtSizeLimit(FalseBBI.NonPredSize) &&
831
MeetIfcvtSizeLimit(*FalseBBI.BB, FalseBBI.NonPredSize) &&
768
832
FeasibilityAnalysis(FalseBBI, RevCond, true, true)) {
769
833
Tokens.push_back(new IfcvtToken(BBI, ICTriangleFRev, FNeedSub, Dups));
773
837
if (ValidSimple(FalseBBI, Dups) &&
774
MeetIfcvtSizeLimit(FalseBBI.NonPredSize) &&
838
MeetIfcvtSizeLimit(*FalseBBI.BB, FalseBBI.NonPredSize) &&
775
839
FeasibilityAnalysis(FalseBBI, RevCond)) {
776
840
Tokens.push_back(new IfcvtToken(BBI, ICSimpleFalse, FNeedSub, Dups));
787
851
/// AnalyzeBlocks - Analyze all blocks and find entries for all if-conversion
788
/// candidates. It returns true if any CFG restructuring is done to expose more
789
/// if-conversion opportunities.
790
bool IfConverter::AnalyzeBlocks(MachineFunction &MF,
853
void IfConverter::AnalyzeBlocks(MachineFunction &MF,
791
854
std::vector<IfcvtToken*> &Tokens) {
793
855
std::set<MachineBasicBlock*> Visited;
794
856
for (unsigned i = 0, e = Roots.size(); i != e; ++i) {
795
857
for (idf_ext_iterator<MachineBasicBlock*> I=idf_ext_begin(Roots[i],Visited),
802
864
// Sort to favor more complex ifcvt scheme.
803
865
std::stable_sort(Tokens.begin(), Tokens.end(), IfcvtTokenCmp);
808
868
/// canFallThroughTo - Returns true either if ToBB is the next block after BB or
809
869
/// that all the intervening blocks are empty (given BB can fall through to its
811
871
static bool canFallThroughTo(MachineBasicBlock *BB, MachineBasicBlock *ToBB) {
812
MachineFunction::iterator I = BB;
872
MachineFunction::iterator PI = BB;
873
MachineFunction::iterator I = llvm::next(PI);
813
874
MachineFunction::iterator TI = ToBB;
814
875
MachineFunction::iterator E = BB->getParent()->end();
816
if (I == E || !I->empty())
877
// Check isSuccessor to avoid case where the next block is empty, but
878
// it's not a successor.
879
if (I == E || !I->empty() || !PI->isSuccessor(I))
837
902
static void InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB,
838
903
const TargetInstrInfo *TII) {
904
DebugLoc dl; // FIXME: this is nowhere
839
905
SmallVector<MachineOperand, 0> NoCond;
840
TII->InsertBranch(*BB, ToBB, NULL, NoCond);
906
TII->InsertBranch(*BB, ToBB, NULL, NoCond, dl);
843
909
/// RemoveExtraEdges - Remove true / false edges if either / both are no longer
849
915
BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
918
/// InitPredRedefs / UpdatePredRedefs - Defs by predicated instructions are
919
/// modeled as read + write (sort like two-address instructions). These
920
/// routines track register liveness and add implicit uses to if-converted
921
/// instructions to conform to the model.
922
static void InitPredRedefs(MachineBasicBlock *BB, SmallSet<unsigned,4> &Redefs,
923
const TargetRegisterInfo *TRI) {
924
for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
925
E = BB->livein_end(); I != E; ++I) {
928
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
930
Redefs.insert(*Subreg);
934
static void UpdatePredRedefs(MachineInstr *MI, SmallSet<unsigned,4> &Redefs,
935
const TargetRegisterInfo *TRI,
936
bool AddImpUse = false) {
937
SmallVector<unsigned, 4> Defs;
938
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
939
const MachineOperand &MO = MI->getOperand(i);
942
unsigned Reg = MO.getReg();
947
else if (MO.isKill()) {
949
for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
953
for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
954
unsigned Reg = Defs[i];
955
if (Redefs.count(Reg)) {
957
// Treat predicated update as read + write.
958
MI->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
959
true/*IsImp*/,false/*IsKill*/));
962
for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
968
static void UpdatePredRedefs(MachineBasicBlock::iterator I,
969
MachineBasicBlock::iterator E,
970
SmallSet<unsigned,4> &Redefs,
971
const TargetRegisterInfo *TRI) {
973
UpdatePredRedefs(I, Redefs, TRI);
852
978
/// IfConvertSimple - If convert a simple (split, no rejoin) sub-CFG.
854
980
bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) {
873
999
if (TII->ReverseBranchCondition(Cond))
874
1000
assert(false && "Unable to reverse branch condition!");
1002
// Initialize liveins to the first BB. These are potentiall redefined by
1003
// predicated instructions.
1004
SmallSet<unsigned, 4> Redefs;
1005
InitPredRedefs(CvtBBI->BB, Redefs, TRI);
1006
InitPredRedefs(NextBBI->BB, Redefs, TRI);
876
1008
if (CvtBBI->BB->pred_size() > 1) {
877
1009
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
878
1010
// Copy instructions in the true block, predicate them, and add them to
879
1011
// the entry block.
880
CopyAndPredicateBlock(BBI, *CvtBBI, Cond);
1012
CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs);
882
PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond);
1014
PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond, Redefs);
884
1016
// Merge converted block into entry block.
885
1017
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
1093
// Initialize liveins to the first BB. These are potentially redefined by
1094
// predicated instructions.
1095
SmallSet<unsigned, 4> Redefs;
1096
InitPredRedefs(CvtBBI->BB, Redefs, TRI);
1097
InitPredRedefs(NextBBI->BB, Redefs, TRI);
960
1099
bool HasEarlyExit = CvtBBI->FalseBB != NULL;
961
bool DupBB = CvtBBI->BB->pred_size() > 1;
1100
if (CvtBBI->BB->pred_size() > 1) {
963
1101
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
964
1102
// Copy instructions in the true block, predicate them, and add them to
965
1103
// the entry block.
966
CopyAndPredicateBlock(BBI, *CvtBBI, Cond, true);
1104
CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs, true);
968
1106
// Predicate the 'true' block after removing its branch.
969
1107
CvtBBI->NonPredSize -= TII->RemoveBranch(*CvtBBI->BB);
970
PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond);
1108
PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond, Redefs);
972
1110
// Now merge the entry of the triangle with the true block.
973
1111
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
974
MergeBlocks(BBI, *CvtBBI);
1112
MergeBlocks(BBI, *CvtBBI, false);
977
1115
// If 'true' block has a 'false' successor, add an exit branch to it.
1047
// Merge the 'true' and 'false' blocks by copying the instructions
1048
// from the 'false' block to the 'true' block. That is, unless the true
1049
// block would clobber the predicate, in that case, do the opposite.
1185
// Put the predicated instructions from the 'true' block before the
1186
// instructions from the 'false' block, unless the true block would clobber
1187
// the predicate, in which case, do the opposite.
1050
1188
BBInfo *BBI1 = &TrueBBI;
1051
1189
BBInfo *BBI2 = &FalseBBI;
1052
1190
SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
1071
1209
// Remove the conditional branch from entry to the blocks.
1072
1210
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
1212
// Initialize liveins to the first BB. These are potentially redefined by
1213
// predicated instructions.
1214
SmallSet<unsigned, 4> Redefs;
1215
InitPredRedefs(BBI1->BB, Redefs, TRI);
1074
1217
// Remove the duplicated instructions at the beginnings of both paths.
1075
1218
MachineBasicBlock::iterator DI1 = BBI1->BB->begin();
1076
1219
MachineBasicBlock::iterator DI2 = BBI2->BB->begin();
1220
MachineBasicBlock::iterator DIE1 = BBI1->BB->end();
1221
MachineBasicBlock::iterator DIE2 = BBI2->BB->end();
1222
// Skip dbg_value instructions
1223
while (DI1 != DIE1 && DI1->isDebugValue())
1225
while (DI2 != DIE2 && DI2->isDebugValue())
1077
1227
BBI1->NonPredSize -= NumDups1;
1078
1228
BBI2->NonPredSize -= NumDups1;
1230
// Skip past the dups on each side separately since there may be
1231
// differing dbg_value entries.
1232
for (unsigned i = 0; i < NumDups1; ++DI1) {
1233
if (!DI1->isDebugValue())
1079
1236
while (NumDups1 != 0) {
1238
if (!DI2->isDebugValue())
1242
UpdatePredRedefs(BBI1->BB->begin(), DI1, Redefs, TRI);
1084
1243
BBI.BB->splice(BBI.BB->end(), BBI1->BB, BBI1->BB->begin(), DI1);
1085
1244
BBI2->BB->erase(BBI2->BB->begin(), DI2);
1087
1246
// Predicate the 'true' block after removing its branch.
1088
1247
BBI1->NonPredSize -= TII->RemoveBranch(*BBI1->BB);
1089
1248
DI1 = BBI1->BB->end();
1090
for (unsigned i = 0; i != NumDups2; ++i)
1249
for (unsigned i = 0; i != NumDups2; ) {
1250
// NumDups2 only counted non-dbg_value instructions, so this won't
1251
// run off the head of the list.
1252
assert (DI1 != BBI1->BB->begin());
1254
// skip dbg_value instructions
1255
if (!DI1->isDebugValue())
1092
1258
BBI1->BB->erase(DI1, BBI1->BB->end());
1093
PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1);
1259
PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1, Redefs);
1095
1261
// Predicate the 'false' block.
1096
1262
BBI2->NonPredSize -= TII->RemoveBranch(*BBI2->BB);
1097
1263
DI2 = BBI2->BB->end();
1098
1264
while (NumDups2 != 0) {
1265
// NumDups2 only counted non-dbg_value instructions, so this won't
1266
// run off the head of the list.
1267
assert (DI2 != BBI2->BB->begin());
1269
// skip dbg_value instructions
1270
if (!DI2->isDebugValue())
1102
PredicateBlock(*BBI2, DI2, *Cond2);
1273
PredicateBlock(*BBI2, DI2, *Cond2, Redefs);
1104
1275
// Merge the true block into the entry of the diamond.
1105
MergeBlocks(BBI, *BBI1);
1106
MergeBlocks(BBI, *BBI2);
1276
MergeBlocks(BBI, *BBI1, TailBB == 0);
1277
MergeBlocks(BBI, *BBI2, TailBB == 0);
1108
1279
// If the if-converted block falls through or unconditionally branches into
1109
1280
// the tail block, and the tail block does not have other predecessors, then
1111
1282
// tail, add a unconditional branch to it.
1113
1284
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
1114
if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
1115
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
1285
bool CanMergeTail = !TailBBI.HasFallThrough;
1286
// There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
1287
// check if there are any other predecessors besides those.
1288
unsigned NumPreds = TailBB->pred_size();
1290
CanMergeTail = false;
1291
else if (NumPreds == 1 && CanMergeTail) {
1292
MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
1293
if (*PI != BBI1->BB && *PI != BBI2->BB)
1294
CanMergeTail = false;
1116
1297
MergeBlocks(BBI, TailBBI);
1117
1298
TailBBI.IsDone = true;
1300
BBI.BB->addSuccessor(TailBB);
1119
1301
InsertUncondBranch(BBI.BB, TailBB, TII);
1120
1302
BBI.HasFallThrough = false;
1306
// RemoveExtraEdges won't work if the block has an unanalyzable branch,
1307
// which can happen here if TailBB is unanalyzable and is merged, so
1308
// explicitly remove BBI1 and BBI2 as successors.
1309
BBI.BB->removeSuccessor(BBI1->BB);
1310
BBI.BB->removeSuccessor(BBI2->BB);
1124
1311
RemoveExtraEdges(BBI);
1126
1313
// Update block info.
1135
1322
/// specified end with the specified condition.
1136
1323
void IfConverter::PredicateBlock(BBInfo &BBI,
1137
1324
MachineBasicBlock::iterator E,
1138
SmallVectorImpl<MachineOperand> &Cond) {
1325
SmallVectorImpl<MachineOperand> &Cond,
1326
SmallSet<unsigned, 4> &Redefs) {
1139
1327
for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) {
1140
if (TII->isPredicated(I))
1328
if (I->isDebugValue() || TII->isPredicated(I))
1142
1330
if (!TII->PredicateInstruction(I, Cond)) {
1152
1344
BBI.IsAnalyzed = false;
1153
1345
BBI.NonPredSize = 0;
1158
1350
/// CopyAndPredicateBlock - Copy and predicate instructions from source BB to
1159
1351
/// the destination block. Skip end of block branches if IgnoreBr is true.
1160
1352
void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
1161
1353
SmallVectorImpl<MachineOperand> &Cond,
1354
SmallSet<unsigned, 4> &Redefs,
1162
1355
bool IgnoreBr) {
1163
1356
MachineFunction &MF = *ToBBI.BB->getParent();
1165
1358
for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
1166
1359
E = FromBBI.BB->end(); I != E; ++I) {
1167
1360
const TargetInstrDesc &TID = I->getDesc();
1168
bool isPredicated = TII->isPredicated(I);
1169
1361
// Do not copy the end of the block branches.
1170
if (IgnoreBr && !isPredicated && TID.isBranch())
1362
if (IgnoreBr && TID.isBranch())
1173
1365
MachineInstr *MI = MF.CloneMachineInstr(I);
1174
1366
ToBBI.BB->insert(ToBBI.BB->end(), MI);
1175
1367
ToBBI.NonPredSize++;
1369
if (!TII->isPredicated(I) && !MI->isDebugValue()) {
1178
1370
if (!TII->PredicateInstruction(MI, Cond)) {
1180
1372
dbgs() << "Unable to predicate " << *I << "!\n";
1182
1374
llvm_unreachable(0);
1378
// If the predicated instruction now redefines a register as the result of
1379
// if-conversion, add an implicit kill.
1380
UpdatePredRedefs(MI, Redefs, TRI, true);
1186
std::vector<MachineBasicBlock *> Succs(FromBBI.BB->succ_begin(),
1187
FromBBI.BB->succ_end());
1188
MachineBasicBlock *NBB = getNextBlock(FromBBI.BB);
1189
MachineBasicBlock *FallThrough = FromBBI.HasFallThrough ? NBB : NULL;
1384
std::vector<MachineBasicBlock *> Succs(FromBBI.BB->succ_begin(),
1385
FromBBI.BB->succ_end());
1386
MachineBasicBlock *NBB = getNextBlock(FromBBI.BB);
1387
MachineBasicBlock *FallThrough = FromBBI.HasFallThrough ? NBB : NULL;
1191
for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1192
MachineBasicBlock *Succ = Succs[i];
1193
// Fallthrough edge can't be transferred.
1194
if (Succ == FallThrough)
1196
ToBBI.BB->addSuccessor(Succ);
1389
for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1390
MachineBasicBlock *Succ = Succs[i];
1391
// Fallthrough edge can't be transferred.
1392
if (Succ == FallThrough)
1394
ToBBI.BB->addSuccessor(Succ);
1199
1398
std::copy(FromBBI.Predicate.begin(), FromBBI.Predicate.end(),
1203
1402
ToBBI.ClobbersPred |= FromBBI.ClobbersPred;
1204
1403
ToBBI.IsAnalyzed = false;
1209
1408
/// MergeBlocks - Move all instructions from FromBB to the end of ToBB.
1211
void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI) {
1409
/// This will leave FromBB as an empty block, so remove all of its
1410
/// successor edges except for the fall-through edge. If AddEdges is true,
1411
/// i.e., when FromBBI's branch is being moved, add those successor edges to
1413
void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges) {
1212
1414
ToBBI.BB->splice(ToBBI.BB->end(),
1213
1415
FromBBI.BB, FromBBI.BB->begin(), FromBBI.BB->end());
1215
// Redirect all branches to FromBB to ToBB.
1216
std::vector<MachineBasicBlock *> Preds(FromBBI.BB->pred_begin(),
1217
FromBBI.BB->pred_end());
1218
for (unsigned i = 0, e = Preds.size(); i != e; ++i) {
1219
MachineBasicBlock *Pred = Preds[i];
1220
if (Pred == ToBBI.BB)
1222
Pred->ReplaceUsesOfBlockWith(FromBBI.BB, ToBBI.BB);
1225
1417
std::vector<MachineBasicBlock *> Succs(FromBBI.BB->succ_begin(),
1226
1418
FromBBI.BB->succ_end());
1227
1419
MachineBasicBlock *NBB = getNextBlock(FromBBI.BB);