25
25
* Following table maps 4 bit reset sample to CPU clock.
28
u32 dove_sar2cpu_clk[] = { 0, 0, 0, /* 0x0 -> 0x2 reserved */
29
1200000, 1067000, 933000,
32
0, 0, 0, 0, 0, 0}; /* 0x10->0x15 reserved */
67
27
u32 dove_sar2cpu_clk[] = { 0, 0, 0, 0, 0, /* 0->4 are reserved */