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- Committer: Bazaar Package Importer
- Author(s): Michael Casadevall
- Date: 2009-07-09 10:31:28 UTC
- Revision ID: james.westby@ubuntu.com-20090709103128-vygh81r4s0q2fyff
Tags: 2009.01-0ubuntu1
Initial release (LP: #398785)
- files added:
- debian
- debian/patches
added
removed
debian/patches/0013-ENGR00108473-Porting-i.MX51-3stack-TO2-support-to-V2.patch
1
From c878dfb5f2f2e034c279a5a422f8cbfbd4af8f08 Mon Sep 17 00:00:00 2001
2
From: Fred Fan <r01011@freescale.com>
3
Date: Wed, 25 Feb 2009 13:53:30 +0800
4
Subject: [PATCH] ENGR00108473 Porting i.MX51 3stack TO2 support to V2009.01
5
6
Support i.MX51 TO2.0 3stack board. And enable LAN9217 support.
7
NAND is not supported in this patch.
8
9
Signed-off-by: Fred Fan <r01011@freescale.com>
10
---
11
Makefile | 3 +
12
board/freescale/mx51_3stack/Makefile | 49 ++
13
board/freescale/mx51_3stack/board-mx51_3stack.h | 64 +++
14
board/freescale/mx51_3stack/config.mk | 1 +
15
board/freescale/mx51_3stack/flash_header.S | 113 ++++
16
board/freescale/mx51_3stack/lowlevel_init.S | 303 ++++++++++
17
board/freescale/mx51_3stack/mx51_3stack.c | 211 +++++++
18
board/freescale/mx51_3stack/u-boot.lds | 72 +++
19
cpu/arm_cortexa8/config.mk | 6 +-
20
cpu/arm_cortexa8/cpu.c | 5 +
21
cpu/arm_cortexa8/mx51/Makefile | 48 ++
22
cpu/arm_cortexa8/mx51/crm_regs.h | 669 +++++++++++++++++++++++
23
cpu/arm_cortexa8/mx51/generic.c | 182 ++++++
24
cpu/arm_cortexa8/mx51/interrupts.c | 113 ++++
25
cpu/arm_cortexa8/mx51/iomux.c | 199 +++++++
26
cpu/arm_cortexa8/mx51/mxc_nand_load.S | 167 ++++++
27
cpu/arm_cortexa8/mx51/serial.c | 226 ++++++++
28
cpu/arm_cortexa8/start.S | 4 +-
29
drivers/mtd/nand/Makefile | 1 +
30
drivers/net/smc911x.c | 9 +
31
include/asm-arm/arch-mx51/iomux.h | 240 ++++++++
32
include/asm-arm/arch-mx51/mx51.h | 423 ++++++++++++++
33
include/asm-arm/arch-mx51/mx51_pins.h | 370 +++++++++++++
34
include/asm-arm/arch-mx51/mxc_nand.h | 198 +++++++
35
include/configs/mx51_3stack.h | 191 +++++++
36
25 files changed, 3865 insertions(+), 2 deletions(-)
37
38
diff --git a/Makefile b/Makefile
39
index f02e9c3..1b5172d 100644
40
--- a/Makefile
41
+++ b/Makefile
42
@@ -2970,6 +2970,9 @@ mx31_3stack_config : unconfig
43
mx35_3stack_config : unconfig
44
@$(MKCONFIG) $(@:_config=) arm arm1136 mx35_3stack freescale mx35
45
46
+mx51_3stack_config : unconfig
47
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51_3stack freescale mx51
48
+
49
omap2420h4_config : unconfig
50
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
51
52
diff --git a/board/freescale/mx51_3stack/Makefile b/board/freescale/mx51_3stack/Makefile
53
new file mode 100644
54
index 0000000..f665a2d
55
--- /dev/null
56
+++ b/board/freescale/mx51_3stack/Makefile
57
@@ -0,0 +1,49 @@
58
+#
59
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
60
+#
61
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
62
+#
63
+# This program is free software; you can redistribute it and/or
64
+# modify it under the terms of the GNU General Public License as
65
+# published by the Free Software Foundation; either version 2 of
66
+# the License, or (at your option) any later version.
67
+#
68
+# This program is distributed in the hope that it will be useful,
69
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
70
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
71
+# GNU General Public License for more details.
72
+#
73
+# You should have received a copy of the GNU General Public License
74
+# along with this program; if not, write to the Free Software
75
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
76
+# MA 02111-1307 USA
77
+#
78
+
79
+include $(TOPDIR)/config.mk
80
+
81
+LIB = $(obj)lib$(BOARD).a
82
+
83
+COBJS := mx51_3stack.o
84
+SOBJS := lowlevel_init.o flash_header.o
85
+
86
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
87
+OBJS := $(addprefix $(obj),$(COBJS))
88
+SOBJS := $(addprefix $(obj),$(SOBJS))
89
+
90
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
91
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
92
+
93
+clean:
94
+ rm -f $(SOBJS) $(OBJS)
95
+
96
+distclean: clean
97
+ rm -f $(LIB) core *.bak .depend
98
+
99
+#########################################################################
100
+
101
+# defines $(obj).depend target
102
+include $(SRCTREE)/rules.mk
103
+
104
+sinclude $(obj).depend
105
+
106
+#########################################################################
107
diff --git a/board/freescale/mx51_3stack/board-mx51_3stack.h b/board/freescale/mx51_3stack/board-mx51_3stack.h
108
new file mode 100644
109
index 0000000..d7c30c1
110
--- /dev/null
111
+++ b/board/freescale/mx51_3stack/board-mx51_3stack.h
112
@@ -0,0 +1,64 @@
113
+/*
114
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
115
+ */
116
+
117
+/*
118
+ * The code contained herein is licensed under the GNU General Public
119
+ * License. You may obtain a copy of the GNU General Public License
120
+ * Version 2 or later at the following locations:
121
+ *
122
+ * http://www.opensource.org/licenses/gpl-license.html
123
+ * http://www.gnu.org/copyleft/gpl.html
124
+ */
125
+
126
+#ifndef __BOARD_FREESCALE_BOARD_MX51_3STACK_H__
127
+#define __BOARD_FREESCALE_BOARD_MX51_3STACK_H__
128
+
129
+/*!
130
+ * @defgroup BRDCFG_MX51 Board Configuration Options
131
+ * @ingroup MSL_MX51
132
+ */
133
+
134
+/*!
135
+ * @file mx51_3stack/board-mx51_3stack.h
136
+ *
137
+ * @brief This file contains all the board level configuration options.
138
+ *
139
+ * It currently hold the options defined for MX51 3Stack Platform.
140
+ *
141
+ * @ingroup BRDCFG_MX51
142
+ */
143
+
144
+/* CPLD offsets */
145
+#define PBC_LED_CTRL (0x20000)
146
+#define PBC_SB_STAT (0x20008)
147
+#define PBC_ID_AAAA (0x20040)
148
+#define PBC_ID_5555 (0x20048)
149
+#define PBC_VERSION (0x20050)
150
+#define PBC_ID_CAFE (0x20058)
151
+#define PBC_INT_STAT (0x20010)
152
+#define PBC_INT_MASK (0x20038)
153
+#define PBC_INT_REST (0x20020)
154
+#define PBC_SW_RESET (0x20060)
155
+
156
+/* LED switchs */
157
+#define LED_SWITCH_REG 0x00
158
+/* buttons */
159
+#define SWITCH_BUTTONS_REG 0x08
160
+/* status, interrupt */
161
+#define INTR_STATUS_REG 0x10
162
+#define INTR_MASK_REG 0x38
163
+#define INTR_RESET_REG 0x20
164
+/* magic word for debug CPLD */
165
+#define MAGIC_NUMBER1_REG 0x40
166
+#define MAGIC_NUMBER2_REG 0x48
167
+/* CPLD code version */
168
+#define CPLD_CODE_VER_REG 0x50
169
+/* magic word for debug CPLD */
170
+#define MAGIC_NUMBER3_REG 0x58
171
+/* module reset register*/
172
+#define MODULE_RESET_REG 0x60
173
+/* CPU ID and Personality ID */
174
+#define MCU_BOARD_ID_REG 0x68
175
+
176
+#endif /* __BOARD_FREESCALE_BOARD_MX51_3STACK_H__ */
177
diff --git a/board/freescale/mx51_3stack/config.mk b/board/freescale/mx51_3stack/config.mk
178
new file mode 100644
179
index 0000000..ce7369d
180
--- /dev/null
181
+++ b/board/freescale/mx51_3stack/config.mk
182
@@ -0,0 +1 @@
183
+TEXT_BASE = 0x97800000
184
diff --git a/board/freescale/mx51_3stack/flash_header.S b/board/freescale/mx51_3stack/flash_header.S
185
new file mode 100644
186
index 0000000..794ab6b
187
--- /dev/null
188
+++ b/board/freescale/mx51_3stack/flash_header.S
189
@@ -0,0 +1,113 @@
190
+/*
191
+ * Copyright 2009 Freescale Semiconductor, Inc.
192
+ *
193
+ * This program is free software; you can redistribute it and/or
194
+ * modify it under the terms of the GNU General Public License as
195
+ * published by the Free Software Foundation; either version 2 of
196
+ * the License, or (at your option) any later version.
197
+ *
198
+ * This program is distributed in the hope that it will be useful,
199
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
200
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
201
+ * GNU General Public License for more details.
202
+ *
203
+ * You should have received a copy of the GNU General Public License
204
+ * along with this program; if not, write to the Free Software
205
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
206
+ * MA 02111-1307 USA
207
+ */
208
+
209
+#include <config.h>
210
+#include <asm/arch/mx51.h>
211
+#include "board-mx51_3stack.h"
212
+
213
+#ifdef CONFIG_FLASH_HEADER
214
+#ifndef CONFIG_FLASH_HEADER_OFFSET
215
+# error "Must define the offset of flash header"
216
+#endif
217
+#define MXC_DCD_ITEM(i, type, addr, val) \
218
+dcd_node_##i: \
219
+ .word type ; \
220
+ .word addr ; \
221
+ .word val ; \
222
+
223
+.section ".text.flasheader", "x"
224
+ b _start
225
+ .org CONFIG_FLASH_HEADER_OFFSET
226
+app_code_jump_v: .word _start
227
+app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER
228
+app_code_csf: .word 0
229
+dcd_ptr_ptr: .word dcd_ptr
230
+super_root_key: .word 0
231
+dcd_ptr: .word dcd_array_start
232
+app_dest_ptr: .word TEXT_BASE
233
+dcd_array_start:
234
+magic: .word 0xB17219E9
235
+dcd_array_size: .word dcd_data_end - dcd_array_start - 8
236
+/* DCD */
237
+/* DDR2 IOMUX configuration */
238
+MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
239
+MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
240
+MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
241
+MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
242
+MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
243
+MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
244
+MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
245
+MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
246
+MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
247
+MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
248
+MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
249
+MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
250
+MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
251
+MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
252
+MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
253
+MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
254
+MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
255
+MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
256
+/* Set drive strength to MAX */
257
+MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6)
258
+MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6)
259
+MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6)
260
+MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6)
261
+/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
262
+/* CAS=3, BL=4 */
263
+MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
264
+MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
265
+MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
266
+MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
267
+MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
268
+/* Init DRAM on CS0 */
269
+MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
270
+MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
271
+MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
272
+MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
273
+MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
274
+MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
275
+MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
276
+MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
277
+MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
278
+MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
279
+MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
280
+MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
281
+/* Init DRAM on CS1 */
282
+MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
283
+MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
284
+MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
285
+MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
286
+MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
287
+MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
288
+MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
289
+MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
290
+MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
291
+MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
292
+MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
293
+MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
294
+MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
295
+MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
296
+MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
297
+MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
298
+MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
299
+dcd_data_end:
300
+image_len: .word 0x40000
301
+//image_len: .word _end - _start
302
+#endif
303
diff --git a/board/freescale/mx51_3stack/lowlevel_init.S b/board/freescale/mx51_3stack/lowlevel_init.S
304
new file mode 100644
305
index 0000000..fa15ddf
306
--- /dev/null
307
+++ b/board/freescale/mx51_3stack/lowlevel_init.S
308
@@ -0,0 +1,303 @@
309
+/*
310
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
311
+ *
312
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
313
+ *
314
+ * This program is free software; you can redistribute it and/or
315
+ * modify it under the terms of the GNU General Public License as
316
+ * published by the Free Software Foundation; either version 2 of
317
+ * the License, or (at your option) any later version.
318
+ *
319
+ * This program is distributed in the hope that it will be useful,
320
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
321
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
322
+ * GNU General Public License for more details.
323
+ *
324
+ * You should have received a copy of the GNU General Public License
325
+ * along with this program; if not, write to the Free Software
326
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
327
+ * MA 02111-1307 USA
328
+ */
329
+
330
+#include <config.h>
331
+#include <asm/arch/mx51.h>
332
+#include "board-mx51_3stack.h"
333
+
334
+/*
335
+ * return soc version
336
+ * 0x10: TO1
337
+ * 0x20: TO2
338
+ * 0x30: TO3
339
+ */
340
+.macro check_soc_version ret, tmp
341
+.endm
342
+
343
+/*
344
+ * L2CC Cache setup/invalidation/disable
345
+ */
346
+.macro init_l2cc
347
+ /* reconfigure L2 cache aux control reg */
348
+ ldr r0, =0x03C000C4
349
+ mcr p15, 1, r0, c9, c0, 2
350
+.endm /* init_l2cc */
351
+
352
+/* AIPS setup - Only setup MPROTx registers.
353
+ * The PACR default values are good.*/
354
+.macro init_aips
355
+ /*
356
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
357
+ * not forced to user-mode.
358
+ */
359
+ ldr r0, =AIPS1_BASE_ADDR
360
+ ldr r1, =0x77777777
361
+ str r1, [r0, #0x0]
362
+ str r1, [r0, #0x4]
363
+ ldr r0, =AIPS2_BASE_ADDR
364
+ str r1, [r0, #0x0]
365
+ str r1, [r0, #0x4]
366
+ /*
367
+ * Clear the on and off peripheral modules Supervisor Protect bit
368
+ * for SDMA to access them. Did not change the AIPS control registers
369
+ * (offset 0x20) access type
370
+ */
371
+.endm /* init_aips */
372
+
373
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
374
+.macro init_max
375
+.endm /* init_max */
376
+
377
+/* M4IF setup */
378
+.macro init_m4if
379
+ /* VPU and IPU given higher priority (0x4)
380
+ * IPU accesses with ID=0x1 given highest priority (=0xA)
381
+ */
382
+ ldr r0, =M4IF_BASE_ADDR
383
+ ldr r1, =0x00000a01
384
+ str r1, [r0, #0x48]
385
+ ldr r1, =0x00000404
386
+ str r1, [r0, #0x40]
387
+.endm /* init_m4if */
388
+
389
+/* To support 133MHz DDR */
390
+.macro init_drive_strength
391
+.endm /* init_drive_strength */
392
+
393
+/* CPLD on CS5 setup */
394
+.macro init_debug_board
395
+.endm /* init_debug_board */
396
+
397
+.macro setup_pll pll, freq
398
+ ldr r2, =\pll
399
+ ldr r1, =0x00001232
400
+ str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
401
+ mov r1, #0x2
402
+ str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
403
+
404
+ str r3, [r2, #PLL_DP_OP]
405
+ str r3, [r2, #PLL_DP_HFS_OP]
406
+
407
+ str r4, [r2, #PLL_DP_MFD]
408
+ str r4, [r2, #PLL_DP_HFS_MFD]
409
+
410
+ str r5, [r2, #PLL_DP_MFN]
411
+ str r5, [r2, #PLL_DP_HFS_MFN]
412
+
413
+ ldr r1, =0x00001232
414
+ str r1, [r2, #PLL_DP_CTL]
415
+1: ldr r1, [r2, #PLL_DP_CTL]
416
+ ands r1, r1, #0x1
417
+ beq 1b
418
+.endm
419
+
420
+.macro init_clock
421
+ ldr r0, =CCM_BASE_ADDR
422
+ mov r1, #0x00060000
423
+ str r1, [r0, #CLKCTL_CCDR]
424
+
425
+ /* Switch ARM to step clock */
426
+ mov r1, #0x4
427
+ str r1, [r0, #CLKCTL_CCSR]
428
+
429
+ mov r3, #DP_OP_800
430
+ mov r4, #DP_MFD_800
431
+ mov r5, #DP_MFN_800
432
+ setup_pll PLL1_BASE_ADDR
433
+ mov r3, #DP_OP_665
434
+ mov r4, #DP_MFD_665
435
+ mov r5, #DP_MFN_665
436
+ setup_pll PLL3_BASE_ADDR
437
+
438
+ /* Switch peripheral to PLL 3 */
439
+ ldr r1, =0x0000D3C0
440
+ str r1, [r0, #CLKCTL_CBCMR]
441
+ ldr r1, =0x033B9145
442
+ str r1, [r0, #CLKCTL_CBCDR]
443
+ mov r3, #DP_OP_665
444
+ mov r4, #DP_MFD_665
445
+ mov r5, #DP_MFN_665
446
+ setup_pll PLL2_BASE_ADDR
447
+
448
+ /* Switch peripheral to PLL2 */
449
+ ldr r1, =0x013B9145
450
+ str r1, [r0, #CLKCTL_CBCDR]
451
+ ldr r1, =0x0000E3C0
452
+ str r1, [r0, #CLKCTL_CBCMR]
453
+
454
+ mov r3, #DP_OP_216
455
+ mov r4, #DP_MFD_216
456
+ mov r5, #DP_MFN_216
457
+ setup_pll PLL3_BASE_ADDR
458
+
459
+ /* Set the platform clock dividers */
460
+ ldr r2, =ARM_BASE_ADDR
461
+ ldr r1, =0x00000725
462
+ str r1, [r2, #0x14]
463
+
464
+ /* Switch ARM back to PLL 1 */
465
+ mov r1, #0
466
+ str r1, [r0, #CLKCTL_CCSR]
467
+ str r1, [r0, #CLKCTL_CACRR]
468
+
469
+ /* Use lp_apm (24MHz) source for perclk */
470
+ mov r2, #0x48
471
+ ldr r2, [r0]
472
+ cmp r2, #0x10
473
+ ldrhs r1, =0x000020C2
474
+ ldrlo r1, =0x0000E3C2
475
+ str r1, [r0, #CLKCTL_CBCMR]
476
+ /* TO1.x emi = ahb, all perclk dividers are 1 since using 24MHz */
477
+ /* TO2.x ddr from PLL1, all perclk dividers are 1 since using 24MHz */
478
+ ldrhs r1, =0x59239100
479
+ ldrlo r1, =0x013D9100
480
+ strlo r1, [r0, #CLKCTL_CBCDR]
481
+
482
+ /* use PLL2 for UART source, get 66.5MHz */
483
+ ldr r1, =0xA5A2A020
484
+ str r1, [r0, #CLKCTL_CSCMR1]
485
+ ldr r1, =0x00C30321
486
+ str r1, [r0, #CLKCTL_CSCDR1]
487
+
488
+ /* make sure divider effective */
489
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
490
+ cmp r1, #0
491
+ bne 1b
492
+
493
+ mov r1, #0x0
494
+ str r1, [r0, #CLKCTL_CCDR]
495
+.endm
496
+
497
+.macro setup_wdog
498
+ ldr r0, =WDOG1_BASE_ADDR
499
+ mov r1, #0x30
500
+ strh r1, [r0]
501
+.endm
502
+
503
+.macro setup_sdram
504
+ ldr r0, =ESDCTL_BASE_ADDR
505
+ mov r2, #0x48
506
+ ldr r2, [r2]
507
+ cmp r2, #0x10
508
+ bhs 1f
509
+ /* Set CSD0 */
510
+ mov r1, #0x80000000
511
+ str r1, [r0, #ESDCTL_ESDCTL0]
512
+ /* Precharge command */
513
+ ldr r1, DDR_PERCHARGE_CMD
514
+ str r1, [r0, #ESDCTL_ESDSCR]
515
+ /* 2 refresh commands */
516
+ ldr r1, DDR_REFRESH_CMD
517
+ str r1, [r0, #ESDCTL_ESDSCR]
518
+ str r1, [r0, #ESDCTL_ESDSCR]
519
+ /* LMR with CAS=3 and BL=3 */
520
+ ldr r1, DDR_LMR1_W
521
+ str r1, [r0, #ESDCTL_ESDSCR]
522
+ /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
523
+ ldr r1, DDR_LMR_CMD
524
+ str r1, [r0, #ESDCTL_ESDCTL0]
525
+ /* Timing parameters */
526
+ ldr r1, DDR_TIMING_W
527
+ str r1, [r0, #ESDCTL_ESDCFG0]
528
+ /* MDDR enable, RLAT=2 */
529
+ ldr r1, DDR_MISC_W
530
+ str r1, [r0, #ESDCTL_ESDMISC]
531
+ /* Normal mode */
532
+ mov r1, #0x00000000
533
+ str r1, [r0, #ESDCTL_ESDSCR]
534
+1:
535
+.endm /* setup_sdram */
536
+
537
+.section ".text.init", "x"
538
+
539
+.globl lowlevel_init
540
+lowlevel_init:
541
+ /* Platform CHIP level init*/
542
+#ifdef TURN_OFF_IMPRECISE_ABORT
543
+ mrs r0, cpsr
544
+ bic r0, r0, #0x100
545
+ msr cpsr, r0
546
+#endif
547
+
548
+ mrc 15, 0, r1, c1, c0, 0
549
+
550
+#ifndef BRANCH_PREDICTION_ENABLE
551
+ mrc 15, 0, r0, c1, c0, 1
552
+ bic r0, r0, #7
553
+ mcr 15, 0, r0, c1, c0, 1
554
+#else
555
+ mrc 15, 0, r0, c1, c0, 1
556
+ orr r0, r0, #7
557
+ mcr 15, 0, r0, c1, c0, 1
558
+ orr r1, r1, #(1<<11)
559
+#endif
560
+
561
+#ifdef UNALIGNED_ACCESS_ENABLE
562
+ orr r1, r1, #(1<<22)
563
+#endif
564
+
565
+#ifdef LOW_INT_LATENCY_ENABLE
566
+ orr r1, r1, #(1<<21)
567
+#endif
568
+ mcr 15, 0, r1, c1, c0, 0
569
+
570
+ mov r0, #0
571
+#ifdef BRANCH_PREDICTION_ENABLE
572
+ mcr 15, 0, r0, c15, c2, 4
573
+#endif
574
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
575
+
576
+ init_l2cc
577
+
578
+ init_aips
579
+
580
+ setup_wdog
581
+
582
+ init_max
583
+
584
+ init_m4if
585
+
586
+ init_drive_strength
587
+
588
+ cmp pc, #PHYS_SDRAM_1
589
+ blo do_sdram_setup
590
+ cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
591
+ blo init_clock_start
592
+
593
+do_sdram_setup:
594
+ setup_sdram
595
+
596
+init_clock_start:
597
+ init_clock
598
+ init_debug_board
599
+ /*init_sdram*/
600
+
601
+ /* return from mxc_nand_load */
602
+ /* r12 saved upper lr*/
603
+ b mxc_nand_load
604
+
605
+/* Board level setting value */
606
+DDR_PERCHARGE_CMD: .word 0x04008008
607
+DDR_REFRESH_CMD: .word 0x00008010
608
+DDR_LMR1_W: .word 0x00338018
609
+DDR_LMR_CMD: .word 0xB2220000
610
+DDR_TIMING_W: .word 0xB02567A9
611
+DDR_MISC_W: .word 0x000A0104
612
diff --git a/board/freescale/mx51_3stack/mx51_3stack.c b/board/freescale/mx51_3stack/mx51_3stack.c
613
new file mode 100644
614
index 0000000..c7f93aa
615
--- /dev/null
616
+++ b/board/freescale/mx51_3stack/mx51_3stack.c
617
@@ -0,0 +1,211 @@
618
+/*
619
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
620
+ *
621
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
622
+ *
623
+ * See file CREDITS for list of people who contributed to this
624
+ * project.
625
+ *
626
+ * This program is free software; you can redistribute it and/or
627
+ * modify it under the terms of the GNU General Public License as
628
+ * published by the Free Software Foundation; either version 2 of
629
+ * the License, or (at your option) any later version.
630
+ *
631
+ * This program is distributed in the hope that it will be useful,
632
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
633
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
634
+ * GNU General Public License for more details.
635
+ *
636
+ * You should have received a copy of the GNU General Public License
637
+ * along with this program; if not, write to the Free Software
638
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
639
+ * MA 02111-1307 USA
640
+ */
641
+
642
+#include <common.h>
643
+#include <asm/io.h>
644
+#include <asm/errno.h>
645
+#include <asm/arch/mx51.h>
646
+#include <asm/arch/mx51_pins.h>
647
+#include <asm/arch/iomux.h>
648
+#include <i2c.h>
649
+#include "board-mx51_3stack.h"
650
+
651
+DECLARE_GLOBAL_DATA_PTR;
652
+
653
+static u32 system_rev;
654
+u32 mx51_io_base_addr;
655
+
656
+u32 get_board_rev(void)
657
+{
658
+ return system_rev;
659
+}
660
+
661
+static inline void setup_soc_rev(void)
662
+{
663
+ int reg;
664
+ reg = __REG(ROM_SI_REV);
665
+ switch (reg) {
666
+ case 0x02:
667
+ system_rev = 0x51000 | CHIP_REV_1_1;
668
+ break;
669
+ case 0x10:
670
+ system_rev = 0x51000 | CHIP_REV_2_0;
671
+ break;
672
+ default:
673
+ system_rev = 0x51000 | CHIP_REV_1_0;
674
+ }
675
+}
676
+
677
+static inline void set_board_rev(int rev)
678
+{
679
+ system_rev |= (rev & 0xF) << 8;
680
+}
681
+
682
+inline int is_soc_rev(int rev)
683
+{
684
+ return (system_rev & 0xFF) - rev;
685
+}
686
+
687
+int dram_init(void)
688
+{
689
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
690
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
691
+ return 0;
692
+}
693
+
694
+static void setup_uart(void)
695
+{
696
+ unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
697
+ PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
698
+ mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
699
+ mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
700
+ mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
701
+ mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
702
+ mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
703
+ mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
704
+ mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
705
+ mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
706
+}
707
+
708
+void setup_nfc(void)
709
+{
710
+ /* Enable NFC IOMUX */
711
+ mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
712
+ mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
713
+ mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
714
+ mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
715
+ mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
716
+ mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
717
+ mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
718
+ mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
719
+}
720
+
721
+static void setup_expio(void)
722
+{
723
+ u32 reg;
724
+ /* CS5 setup */
725
+ mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
726
+ writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1);
727
+ writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2);
728
+ /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
729
+ writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1);
730
+ /* APR = 0 */
731
+ writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2);
732
+ /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
733
+ * WCSA=0, WCSN=0
734
+ */
735
+ writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1);
736
+ if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) &&
737
+ (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) {
738
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
739
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
740
+ reg = (reg & (~0x70000)) | 0x30000;
741
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
742
+ /* make sure divider effective */
743
+ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
744
+ ;
745
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
746
+ }
747
+ mx51_io_base_addr = CS5_BASE_ADDR;
748
+ } else {
749
+ /* CS1 */
750
+ writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1);
751
+ writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2);
752
+ /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
753
+ writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1);
754
+ /* APR=0 */
755
+ writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2);
756
+ /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
757
+ * WEN=0, WCSA=0, WCSN=0
758
+ */
759
+ writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1);
760
+ mx51_io_base_addr = CS1_BASE_ADDR;
761
+ }
762
+
763
+ /* Reset interrupt status reg */
764
+ writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
765
+ writew(0x00, mx51_io_base_addr + PBC_INT_REST);
766
+ writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
767
+
768
+ /* Reset the XUART and Ethernet controllers */
769
+ reg = readw(mx51_io_base_addr + PBC_SW_RESET);
770
+ reg |= 0x9;
771
+ writew(reg, mx51_io_base_addr + PBC_SW_RESET);
772
+ reg &= ~0x9;
773
+ writew(reg, mx51_io_base_addr + PBC_SW_RESET);
774
+}
775
+
776
+int board_init(void)
777
+{
778
+ int pad;
779
+ setup_soc_rev();
780
+
781
+ gd->bd->bi_arch_number = MACH_TYPE_MX51_3DS; /* board id for linux */
782
+ /* address of boot parameters */
783
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
784
+
785
+ setup_uart();
786
+ setup_nfc();
787
+ setup_expio();
788
+ return 0;
789
+}
790
+
791
+#ifdef BOARD_LATE_INIT
792
+int board_late_init(void)
793
+{
794
+ return 0;
795
+}
796
+#endif
797
+
798
+int checkboard(void)
799
+{
800
+ printf("Board: MX51 3STACK [");
801
+ switch (__REG(SRC_BASE_ADDR + 0x8)) {
802
+ case 0x0001:
803
+ printf("POR");
804
+ break;
805
+ case 0x0009:
806
+ printf("RST");
807
+ break;
808
+ case 0x0010:
809
+ case 0x0011:
810
+ printf("WDOG");
811
+ break;
812
+ default:
813
+ printf("unknown");
814
+ }
815
+ printf("]\n");
816
+ return 0;
817
+}
818
+
819
+#ifdef CONFIG_NET_MULTI
820
+int board_eth_init(bd_t *bis)
821
+{
822
+ int rc = -ENODEV;
823
+#if defined(CONFIG_DRIVER_SMC911X)
824
+ rc = smc911x_initialize(bis);
825
+#endif
826
+ return rc;
827
+}
828
+#endif
829
diff --git a/board/freescale/mx51_3stack/u-boot.lds b/board/freescale/mx51_3stack/u-boot.lds
830
new file mode 100644
831
index 0000000..1cf3c3d
832
--- /dev/null
833
+++ b/board/freescale/mx51_3stack/u-boot.lds
834
@@ -0,0 +1,72 @@
835
+/*
836
+ * January 2004 - Changed to support H4 device
837
+ * Copyright (c) 2004 Texas Instruments
838
+ *
839
+ * (C) Copyright 2002
840
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
841
+ *
842
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
843
+ *
844
+ * See file CREDITS for list of people who contributed to this
845
+ * project.
846
+ *
847
+ * This program is free software; you can redistribute it and/or
848
+ * modify it under the terms of the GNU General Public License as
849
+ * published by the Free Software Foundation; either version 2 of
850
+ * the License, or (at your option) any later version.
851
+ *
852
+ * This program is distributed in the hope that it will be useful,
853
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
854
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
855
+ * GNU General Public License for more details.
856
+ *
857
+ * You should have received a copy of the GNU General Public License
858
+ * along with this program; if not, write to the Free Software
859
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
860
+ * MA 02111-1307 USA
861
+ */
862
+
863
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
864
+OUTPUT_ARCH(arm)
865
+ENTRY(_start)
866
+SECTIONS
867
+{
868
+ . = 0x00000000;
869
+
870
+ . = ALIGN(4);
871
+ .text :
872
+ {
873
+ /* WARNING - the following is hand-optimized to fit within */
874
+ /* the sector layout of our flash chips! XXX FIXME XXX */
875
+ board/freescale/mx51_3stack/flash_header.o (.text.flasheader)
876
+ cpu/arm_cortexa8/start.o
877
+ board/freescale/mx51_3stack/libmx51_3stack.a (.text)
878
+ lib_arm/libarm.a (.text)
879
+ net/libnet.a (.text)
880
+ drivers/mtd/libmtd.a (.text)
881
+
882
+ . = DEFINED(env_offset) ? env_offset : .;
883
+ common/env_embedded.o(.text)
884
+
885
+ *(.text)
886
+ }
887
+
888
+ . = ALIGN(4);
889
+ .rodata : { *(.rodata) }
890
+
891
+ . = ALIGN(4);
892
+ .data : { *(.data) }
893
+
894
+ . = ALIGN(4);
895
+ .got : { *(.got) }
896
+
897
+ . = .;
898
+ __u_boot_cmd_start = .;
899
+ .u_boot_cmd : { *(.u_boot_cmd) }
900
+ __u_boot_cmd_end = .;
901
+
902
+ . = ALIGN(4);
903
+ __bss_start = .;
904
+ .bss : { *(.bss) }
905
+ _end = .;
906
+}
907
diff --git a/cpu/arm_cortexa8/config.mk b/cpu/arm_cortexa8/config.mk
908
index b021762..5a1384c 100644
909
--- a/cpu/arm_cortexa8/config.mk
910
+++ b/cpu/arm_cortexa8/config.mk
911
@@ -30,7 +30,11 @@ PLATFORM_CPPFLAGS += -march=armv5
912
# Supply options according to compiler version
913
#
914
# =========================================================================
915
+ifdef CONFIG_SYS_APCS_GNU
916
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
917
+else
918
PLATFORM_CPPFLAGS +=$(call cc-option)
919
+endif
920
PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
921
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
922
- $(call cc-option,-malignment-traps,))
923
\ No newline at end of file
924
+ $(call cc-option,-malignment-traps,))
925
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
926
index ebc5ea2..f1ea13c 100644
927
--- a/cpu/arm_cortexa8/cpu.c
928
+++ b/cpu/arm_cortexa8/cpu.c
929
@@ -33,7 +33,10 @@
930
931
#include <common.h>
932
#include <command.h>
933
+
934
+#ifndef CONFIG_MXC
935
#include <asm/arch/sys_proto.h>
936
+#endif
937
938
#ifdef CONFIG_USE_IRQ
939
DECLARE_GLOBAL_DATA_PTR;
940
@@ -170,6 +173,7 @@ void dcache_disable (void)
941
write_p15_c1 (reg & ~C1_DC);
942
}
943
944
+#ifndef CONFIG_L2_OFF
945
void l2cache_enable()
946
{
947
unsigned long i;
948
@@ -228,6 +232,7 @@ void l2cache_disable()
949
__asm__ __volatile__("mov r12, %0":"=r"(j));
950
}
951
}
952
+#endif
953
954
int icache_status(void)
955
{
956
diff --git a/cpu/arm_cortexa8/mx51/Makefile b/cpu/arm_cortexa8/mx51/Makefile
957
new file mode 100644
958
index 0000000..6f10e3e
959
--- /dev/null
960
+++ b/cpu/arm_cortexa8/mx51/Makefile
961
@@ -0,0 +1,48 @@
962
+#
963
+# (C) Copyright 2000-2006
964
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
965
+#
966
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
967
+#
968
+# See file CREDITS for list of people who contributed to this
969
+# project.
970
+#
971
+# This program is free software; you can redistribute it and/or
972
+# modify it under the terms of the GNU General Public License as
973
+# published by the Free Software Foundation; either version 2 of
974
+# the License, or (at your option) any later version.
975
+#
976
+# This program is distributed in the hope that it will be useful,
977
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
978
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
979
+# GNU General Public License for more details.
980
+#
981
+# You should have received a copy of the GNU General Public License
982
+# along with this program; if not, write to the Free Software
983
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
984
+# MA 02111-1307 USA
985
+#
986
+
987
+include $(TOPDIR)/config.mk
988
+
989
+LIB = $(obj)lib$(SOC).a
990
+
991
+COBJS = interrupts.o serial.o generic.o iomux.o
992
+SOBJS = mxc_nand_load.o
993
+
994
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
995
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
996
+
997
+all: $(obj).depend $(LIB)
998
+
999
+$(LIB): $(OBJS)
1000
+ $(AR) $(ARFLAGS) $@ $(OBJS)
1001
+
1002
+#########################################################################
1003
+
1004
+# defines $(obj).depend target
1005
+include $(SRCTREE)/rules.mk
1006
+
1007
+sinclude $(obj).depend
1008
+
1009
+#########################################################################
1010
diff --git a/cpu/arm_cortexa8/mx51/crm_regs.h b/cpu/arm_cortexa8/mx51/crm_regs.h
1011
new file mode 100644
1012
index 0000000..8a2b2dc
1013
--- /dev/null
1014
+++ b/cpu/arm_cortexa8/mx51/crm_regs.h
1015
@@ -0,0 +1,669 @@
1016
+/*
1017
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
1018
+ */
1019
+
1020
+/*
1021
+ * The code contained herein is licensed under the GNU General Public
1022
+ * License. You may obtain a copy of the GNU General Public License
1023
+ * Version 2 or later at the following locations:
1024
+ *
1025
+ * http://www.opensource.org/licenses/gpl-license.html
1026
+ * http://www.gnu.org/copyleft/gpl.html
1027
+ */
1028
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
1029
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
1030
+
1031
+#define MXC_CCM_BASE CCM_BASE_ADDR
1032
+#define MXC_DPLL1_BASE PLL1_BASE_ADDR
1033
+#define MXC_DPLL2_BASE PLL2_BASE_ADDR
1034
+#define MXC_DPLL3_BASE PLL3_BASE_ADDR
1035
+
1036
+/* PLL Register Offsets */
1037
+#define MXC_PLL_DP_CTL 0x00
1038
+#define MXC_PLL_DP_CONFIG 0x04
1039
+#define MXC_PLL_DP_OP 0x08
1040
+#define MXC_PLL_DP_MFD 0x0C
1041
+#define MXC_PLL_DP_MFN 0x10
1042
+#define MXC_PLL_DP_MFNMINUS 0x14
1043
+#define MXC_PLL_DP_MFNPLUS 0x18
1044
+#define MXC_PLL_DP_HFS_OP 0x1C
1045
+#define MXC_PLL_DP_HFS_MFD 0x20
1046
+#define MXC_PLL_DP_HFS_MFN 0x24
1047
+#define MXC_PLL_DP_MFN_TOGC 0x28
1048
+#define MXC_PLL_DP_DESTAT 0x2c
1049
+
1050
+/* PLL Register Bit definitions */
1051
+#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
1052
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
1053
+#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
1054
+#define MXC_PLL_DP_CTL_ADE 0x800
1055
+#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
1056
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
1057
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
1058
+#define MXC_PLL_DP_CTL_HFSM 0x80
1059
+#define MXC_PLL_DP_CTL_PRE 0x40
1060
+#define MXC_PLL_DP_CTL_UPEN 0x20
1061
+#define MXC_PLL_DP_CTL_RST 0x10
1062
+#define MXC_PLL_DP_CTL_RCP 0x8
1063
+#define MXC_PLL_DP_CTL_PLM 0x4
1064
+#define MXC_PLL_DP_CTL_BRM0 0x2
1065
+#define MXC_PLL_DP_CTL_LRF 0x1
1066
+
1067
+#define MXC_PLL_DP_CONFIG_BIST 0x8
1068
+#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
1069
+#define MXC_PLL_DP_CONFIG_AREN 0x2
1070
+#define MXC_PLL_DP_CONFIG_LDREQ 0x1
1071
+
1072
+#define MXC_PLL_DP_OP_MFI_OFFSET 4
1073
+#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
1074
+#define MXC_PLL_DP_OP_PDF_OFFSET 0
1075
+#define MXC_PLL_DP_OP_PDF_MASK 0xF
1076
+
1077
+#define MXC_PLL_DP_MFD_OFFSET 0
1078
+#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
1079
+
1080
+#define MXC_PLL_DP_MFN_OFFSET 0x0
1081
+#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
1082
+
1083
+#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
1084
+#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
1085
+#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
1086
+#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
1087
+
1088
+#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
1089
+#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
1090
+
1091
+/* Register addresses of CCM*/
1092
+#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
1093
+#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
1094
+#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
1095
+#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
1096
+#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
1097
+#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
1098
+#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
1099
+#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
1100
+#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
1101
+#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
1102
+#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
1103
+#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
1104
+#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
1105
+#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
1106
+#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
1107
+#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
1108
+#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
1109
+#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
1110
+#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
1111
+#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
1112
+#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
1113
+#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
1114
+#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
1115
+#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
1116
+#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
1117
+#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
1118
+#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
1119
+#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
1120
+#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
1121
+#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
1122
+#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
1123
+#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
1124
+#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
1125
+#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x84)
1126
+
1127
+/* Define the bits in register CCR */
1128
+#define MXC_CCM_CCR_COSC_EN (1 << 12)
1129
+#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
1130
+#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
1131
+#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
1132
+#define MXC_CCM_CCR_FPM_EN (1 << 8)
1133
+#define MXC_CCM_CCR_OSCNT_OFFSET (0)
1134
+#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
1135
+
1136
+/* Define the bits in register CCDR */
1137
+#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
1138
+#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
1139
+#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
1140
+
1141
+/* Define the bits in register CSR */
1142
+#define MXC_CCM_CSR_COSR_READY (1 << 5)
1143
+#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
1144
+#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
1145
+#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
1146
+#define MXC_CCM_CSR_FPM_READY (1 << 1)
1147
+#define MXC_CCM_CSR_REF_EN_B (1 << 0)
1148
+
1149
+/* Define the bits in register CCSR */
1150
+#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
1151
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
1152
+#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
1153
+#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
1154
+#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
1155
+#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
1156
+#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
1157
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
1158
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
1159
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
1160
+
1161
+/* Define the bits in register CACRR */
1162
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
1163
+#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
1164
+
1165
+/* Define the bits in register CBCDR */
1166
+#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
1167
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
1168
+#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
1169
+#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
1170
+#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
1171
+#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
1172
+#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
1173
+#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
1174
+#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
1175
+#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
1176
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
1177
+#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
1178
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
1179
+#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
1180
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
1181
+#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
1182
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
1183
+#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
1184
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
1185
+#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
1186
+
1187
+/* Define the bits in register CBCMR */
1188
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
1189
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
1190
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
1191
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
1192
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
1193
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
1194
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
1195
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
1196
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
1197
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
1198
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
1199
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
1200
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
1201
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
1202
+
1203
+/* Define the bits in register CSCMR1 */
1204
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
1205
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
1206
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
1207
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
1208
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
1209
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
1210
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
1211
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
1212
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
1213
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
1214
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
1215
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
1216
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
1217
+#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
1218
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
1219
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
1220
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
1221
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
1222
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
1223
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
1224
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
1225
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
1226
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
1227
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
1228
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
1229
+#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
1230
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
1231
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
1232
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
1233
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
1234
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
1235
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
1236
+
1237
+/* Define the bits in register CSCMR2 */
1238
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET (26)
1239
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK (0x7 << 26)
1240
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
1241
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
1242
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
1243
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
1244
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
1245
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
1246
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
1247
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
1248
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
1249
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
1250
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
1251
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
1252
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
1253
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
1254
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
1255
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
1256
+#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
1257
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
1258
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
1259
+#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
1260
+#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
1261
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
1262
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
1263
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
1264
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
1265
+
1266
+/* Define the bits in register CSCDR1 */
1267
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
1268
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
1269
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
1270
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
1271
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
1272
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
1273
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
1274
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
1275
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
1276
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
1277
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
1278
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
1279
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
1280
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
1281
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
1282
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
1283
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
1284
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
1285
+
1286
+/* Define the bits in register CS1CDR and CS2CDR */
1287
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
1288
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
1289
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
1290
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
1291
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
1292
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
1293
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
1294
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
1295
+
1296
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
1297
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
1298
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
1299
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
1300
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
1301
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
1302
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
1303
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
1304
+
1305
+/* Define the bits in register CDCDR */
1306
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
1307
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
1308
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
1309
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
1310
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
1311
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
1312
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
1313
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
1314
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
1315
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
1316
+#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
1317
+#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
1318
+#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
1319
+#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
1320
+#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
1321
+#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
1322
+
1323
+/* Define the bits in register CHSCCDR */
1324
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
1325
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
1326
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
1327
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
1328
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
1329
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
1330
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
1331
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
1332
+
1333
+/* Define the bits in register CSCDR2 */
1334
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
1335
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
1336
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
1337
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
1338
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
1339
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
1340
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
1341
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
1342
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
1343
+#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
1344
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
1345
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
1346
+
1347
+/* Define the bits in register CSCDR3 */
1348
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
1349
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
1350
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
1351
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
1352
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
1353
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
1354
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
1355
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
1356
+
1357
+/* Define the bits in register CSCDR4 */
1358
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
1359
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
1360
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
1361
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
1362
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
1363
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
1364
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
1365
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
1366
+
1367
+/* Define the bits in register CDHIPR */
1368
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
1369
+#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
1370
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
1371
+#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
1372
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
1373
+#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
1374
+#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
1375
+#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
1376
+
1377
+/* Define the bits in register CDCR */
1378
+#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
1379
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
1380
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
1381
+
1382
+/* Define the bits in register CLPCR */
1383
+#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
1384
+#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
1385
+#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
1386
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
1387
+#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
1388
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
1389
+#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
1390
+#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
1391
+#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
1392
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
1393
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
1394
+#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
1395
+#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
1396
+#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
1397
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
1398
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
1399
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
1400
+#define MXC_CCM_CLPCR_LPM_OFFSET (0)
1401
+#define MXC_CCM_CLPCR_LPM_MASK (0x3)
1402
+
1403
+/* Define the bits in register CISR */
1404
+#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
1405
+#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
1406
+#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
1407
+#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
1408
+#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
1409
+#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
1410
+#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
1411
+#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
1412
+#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
1413
+#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
1414
+#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
1415
+#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
1416
+#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
1417
+#define MXC_CCM_CISR_LRF_PLL1 (0x1)
1418
+
1419
+/* Define the bits in register CIMR */
1420
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
1421
+#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
1422
+#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
1423
+#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
1424
+#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
1425
+#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
1426
+#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
1427
+#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
1428
+#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
1429
+#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
1430
+#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
1431
+#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
1432
+#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
1433
+
1434
+/* Define the bits in register CCOSR */
1435
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
1436
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
1437
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
1438
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
1439
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
1440
+#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
1441
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
1442
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
1443
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
1444
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
1445
+
1446
+/* Define the bits in registers CGPR */
1447
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
1448
+#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
1449
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
1450
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
1451
+
1452
+/* Define the bits in registers CCGRx */
1453
+#define MXC_CCM_CCGR_CG_MASK 0x3
1454
+
1455
+#define MXC_CCM_CCGR0_CG15_OFFSET 30
1456
+#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
1457
+#define MXC_CCM_CCGR0_CG14_OFFSET 28
1458
+#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
1459
+#define MXC_CCM_CCGR0_CG13_OFFSET 26
1460
+#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
1461
+#define MXC_CCM_CCGR0_CG12_OFFSET 24
1462
+#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
1463
+#define MXC_CCM_CCGR0_CG11_OFFSET 22
1464
+#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
1465
+#define MXC_CCM_CCGR0_CG10_OFFSET 20
1466
+#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
1467
+#define MXC_CCM_CCGR0_CG9_OFFSET 18
1468
+#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
1469
+#define MXC_CCM_CCGR0_CG8_OFFSET 16
1470
+#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
1471
+#define MXC_CCM_CCGR0_CG7_OFFSET 14
1472
+#define MXC_CCM_CCGR0_CG6_OFFSET 12
1473
+#define MXC_CCM_CCGR0_CG5_OFFSET 10
1474
+#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
1475
+#define MXC_CCM_CCGR0_CG4_OFFSET 8
1476
+#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
1477
+#define MXC_CCM_CCGR0_CG3_OFFSET 6
1478
+#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
1479
+#define MXC_CCM_CCGR0_CG2_OFFSET 4
1480
+#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
1481
+#define MXC_CCM_CCGR0_CG1_OFFSET 2
1482
+#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
1483
+#define MXC_CCM_CCGR0_CG0_OFFSET 0
1484
+#define MXC_CCM_CCGR0_CG0_MASK 0x3
1485
+
1486
+#define MXC_CCM_CCGR1_CG15_OFFSET 30
1487
+#define MXC_CCM_CCGR1_CG14_OFFSET 28
1488
+#define MXC_CCM_CCGR1_CG13_OFFSET 26
1489
+#define MXC_CCM_CCGR1_CG12_OFFSET 24
1490
+#define MXC_CCM_CCGR1_CG11_OFFSET 22
1491
+#define MXC_CCM_CCGR1_CG10_OFFSET 20
1492
+#define MXC_CCM_CCGR1_CG9_OFFSET 18
1493
+#define MXC_CCM_CCGR1_CG8_OFFSET 16
1494
+#define MXC_CCM_CCGR1_CG7_OFFSET 14
1495
+#define MXC_CCM_CCGR1_CG6_OFFSET 12
1496
+#define MXC_CCM_CCGR1_CG5_OFFSET 10
1497
+#define MXC_CCM_CCGR1_CG4_OFFSET 8
1498
+#define MXC_CCM_CCGR1_CG3_OFFSET 6
1499
+#define MXC_CCM_CCGR1_CG2_OFFSET 4
1500
+#define MXC_CCM_CCGR1_CG1_OFFSET 2
1501
+#define MXC_CCM_CCGR1_CG0_OFFSET 0
1502
+
1503
+#define MXC_CCM_CCGR2_CG15_OFFSET 30
1504
+#define MXC_CCM_CCGR2_CG14_OFFSET 28
1505
+#define MXC_CCM_CCGR2_CG13_OFFSET 26
1506
+#define MXC_CCM_CCGR2_CG12_OFFSET 24
1507
+#define MXC_CCM_CCGR2_CG11_OFFSET 22
1508
+#define MXC_CCM_CCGR2_CG10_OFFSET 20
1509
+#define MXC_CCM_CCGR2_CG9_OFFSET 18
1510
+#define MXC_CCM_CCGR2_CG8_OFFSET 16
1511
+#define MXC_CCM_CCGR2_CG7_OFFSET 14
1512
+#define MXC_CCM_CCGR2_CG6_OFFSET 12
1513
+#define MXC_CCM_CCGR2_CG5_OFFSET 10
1514
+#define MXC_CCM_CCGR2_CG4_OFFSET 8
1515
+#define MXC_CCM_CCGR2_CG3_OFFSET 6
1516
+#define MXC_CCM_CCGR2_CG2_OFFSET 4
1517
+#define MXC_CCM_CCGR2_CG1_OFFSET 2
1518
+#define MXC_CCM_CCGR2_CG0_OFFSET 0
1519
+
1520
+#define MXC_CCM_CCGR3_CG15_OFFSET 30
1521
+#define MXC_CCM_CCGR3_CG14_OFFSET 28
1522
+#define MXC_CCM_CCGR3_CG13_OFFSET 26
1523
+#define MXC_CCM_CCGR3_CG12_OFFSET 24
1524
+#define MXC_CCM_CCGR3_CG11_OFFSET 22
1525
+#define MXC_CCM_CCGR3_CG10_OFFSET 20
1526
+#define MXC_CCM_CCGR3_CG9_OFFSET 18
1527
+#define MXC_CCM_CCGR3_CG8_OFFSET 16
1528
+#define MXC_CCM_CCGR3_CG7_OFFSET 14
1529
+#define MXC_CCM_CCGR3_CG6_OFFSET 12
1530
+#define MXC_CCM_CCGR3_CG5_OFFSET 10
1531
+#define MXC_CCM_CCGR3_CG4_OFFSET 8
1532
+#define MXC_CCM_CCGR3_CG3_OFFSET 6
1533
+#define MXC_CCM_CCGR3_CG2_OFFSET 4
1534
+#define MXC_CCM_CCGR3_CG1_OFFSET 2
1535
+#define MXC_CCM_CCGR3_CG0_OFFSET 0
1536
+
1537
+#define MXC_CCM_CCGR4_CG15_OFFSET 30
1538
+#define MXC_CCM_CCGR4_CG14_OFFSET 28
1539
+#define MXC_CCM_CCGR4_CG13_OFFSET 26
1540
+#define MXC_CCM_CCGR4_CG12_OFFSET 24
1541
+#define MXC_CCM_CCGR4_CG11_OFFSET 22
1542
+#define MXC_CCM_CCGR4_CG10_OFFSET 20
1543
+#define MXC_CCM_CCGR4_CG9_OFFSET 18
1544
+#define MXC_CCM_CCGR4_CG8_OFFSET 16
1545
+#define MXC_CCM_CCGR4_CG7_OFFSET 14
1546
+#define MXC_CCM_CCGR4_CG6_OFFSET 12
1547
+#define MXC_CCM_CCGR4_CG5_OFFSET 10
1548
+#define MXC_CCM_CCGR4_CG4_OFFSET 8
1549
+#define MXC_CCM_CCGR4_CG3_OFFSET 6
1550
+#define MXC_CCM_CCGR4_CG2_OFFSET 4
1551
+#define MXC_CCM_CCGR4_CG1_OFFSET 2
1552
+#define MXC_CCM_CCGR4_CG0_OFFSET 0
1553
+
1554
+#define MXC_CCM_CCGR5_CG15_OFFSET 30
1555
+#define MXC_CCM_CCGR5_CG14_OFFSET 28
1556
+#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
1557
+#define MXC_CCM_CCGR5_CG13_OFFSET 26
1558
+#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
1559
+#define MXC_CCM_CCGR5_CG12_OFFSET 24
1560
+#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
1561
+#define MXC_CCM_CCGR5_CG11_OFFSET 22
1562
+#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
1563
+#define MXC_CCM_CCGR5_CG10_OFFSET 20
1564
+#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
1565
+#define MXC_CCM_CCGR5_CG9_OFFSET 18
1566
+#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
1567
+#define MXC_CCM_CCGR5_CG8_OFFSET 16
1568
+#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
1569
+#define MXC_CCM_CCGR5_CG7_OFFSET 14
1570
+#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
1571
+#define MXC_CCM_CCGR5_CG6_OFFSET 12
1572
+#define MXC_CCM_CCGR5_CG5_OFFSET 10
1573
+#define MXC_CCM_CCGR5_CG4_OFFSET 8
1574
+#define MXC_CCM_CCGR5_CG3_OFFSET 6
1575
+#define MXC_CCM_CCGR5_CG2_OFFSET 4
1576
+#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
1577
+#define MXC_CCM_CCGR5_CG1_OFFSET 2
1578
+#define MXC_CCM_CCGR5_CG0_OFFSET 0
1579
+
1580
+#define MXC_CCM_CCGR6_CG4_OFFSET 8
1581
+#define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8)
1582
+#define MXC_CCM_CCGR6_CG3_OFFSET 6
1583
+#define MXC_CCM_CCGR6_CG2_OFFSET 4
1584
+#define MXC_CCM_CCGR6_CG1_OFFSET 2
1585
+#define MXC_CCM_CCGR6_CG0_OFFSET 0
1586
+
1587
+#define MXC_CORTEXA8_BASE ARM_BASE_ADDR
1588
+#define MXC_GPC_BASE GPC_BASE_ADDR
1589
+#define MXC_DPTC_LP_BASE (GPC_BASE_ADDR + 0x80)
1590
+#define MXC_DPTC_GP_BASE (GPC_BASE_ADDR + 0x100)
1591
+#define MXC_DVFS_CORE_BASE (GPC_BASE_ADDR + 0x180)
1592
+#define MXC_DPTC_PER_BASE (GPC_BASE_ADDR + 0x1C0)
1593
+#define MXC_PGC_IPU_BASE (GPC_BASE_ADDR + 0x220)
1594
+#define MXC_PGC_VPU_BASE (GPC_BASE_ADDR + 0x240)
1595
+#define MXC_PGC_GPU_BASE (GPC_BASE_ADDR + 0x260)
1596
+#define MXC_SRPG_NEON_BASE (GPC_BASE_ADDR + 0x280)
1597
+#define MXC_SRPG_ARM_BASE (GPC_BASE_ADDR + 0x2A0)
1598
+#define MXC_SRPG_EMPGC0_BASE (GPC_BASE_ADDR + 0x2C0)
1599
+#define MXC_SRPG_EMPGC1_BASE (GPC_BASE_ADDR + 0x2D0)
1600
+#define MXC_SRPG_MEGAMIX_BASE (GPC_BASE_ADDR + 0x2E0)
1601
+#define MXC_SRPG_EMI_BASE (GPC_BASE_ADDR + 0x300)
1602
+
1603
+/* CORTEXA8 platform */
1604
+#define MXC_CORTEXA8_PLAT_PVID (MXC_CORTEXA8_BASE + 0x0)
1605
+#define MXC_CORTEXA8_PLAT_GPC (MXC_CORTEXA8_BASE + 0x4)
1606
+#define MXC_CORTEXA8_PLAT_PIC (MXC_CORTEXA8_BASE + 0x8)
1607
+#define MXC_CORTEXA8_PLAT_LPC (MXC_CORTEXA8_BASE + 0xC)
1608
+#define MXC_CORTEXA8_PLAT_NEON_LPC (MXC_CORTEXA8_BASE + 0x10)
1609
+#define MXC_CORTEXA8_PLAT_ICGC (MXC_CORTEXA8_BASE + 0x14)
1610
+#define MXC_CORTEXA8_PLAT_AMC (MXC_CORTEXA8_BASE + 0x18)
1611
+#define MXC_CORTEXA8_PLAT_NMC (MXC_CORTEXA8_BASE + 0x20)
1612
+#define MXC_CORTEXA8_PLAT_NMS (MXC_CORTEXA8_BASE + 0x24)
1613
+
1614
+/* DVFS CORE */
1615
+#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
1616
+#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
1617
+#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
1618
+#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
1619
+#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
1620
+#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
1621
+#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
1622
+#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
1623
+#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
1624
+#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
1625
+#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
1626
+#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
1627
+#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
1628
+#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
1629
+#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
1630
+#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
1631
+#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
1632
+
1633
+/* GPC */
1634
+#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
1635
+#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
1636
+#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
1637
+#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
1638
+#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
1639
+#define MXC_GPC_PGR_ARMPG_OFFSET 8
1640
+#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
1641
+
1642
+/* PGC */
1643
+#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
1644
+#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
1645
+#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
1646
+#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
1647
+#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
1648
+#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
1649
+
1650
+#define MXC_PGCR_PCR 1
1651
+#define MXC_SRPGCR_PCR 1
1652
+#define MXC_EMPGCR_PCR 1
1653
+#define MXC_PGSR_PSR 1
1654
+
1655
+
1656
+#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
1657
+#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
1658
+
1659
+/* SRPG */
1660
+#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
1661
+#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
1662
+#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
1663
+
1664
+#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
1665
+#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
1666
+#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
1667
+
1668
+#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
1669
+#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
1670
+#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
1671
+
1672
+#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
1673
+#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
1674
+#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
1675
+
1676
+#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
1677
+#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
1678
+#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
1679
+
1680
+#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
1681
+#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
1682
+#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
1683
+
1684
+#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
1685
diff --git a/cpu/arm_cortexa8/mx51/generic.c b/cpu/arm_cortexa8/mx51/generic.c
1686
new file mode 100644
1687
index 0000000..8982a80
1688
--- /dev/null
1689
+++ b/cpu/arm_cortexa8/mx51/generic.c
1690
@@ -0,0 +1,182 @@
1691
+/*
1692
+ * (C) Copyright 2007
1693
+ * Sascha Hauer, Pengutronix
1694
+ *
1695
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
1696
+ *
1697
+ * See file CREDITS for list of people who contributed to this
1698
+ * project.
1699
+ *
1700
+ * This program is free software; you can redistribute it and/or
1701
+ * modify it under the terms of the GNU General Public License as
1702
+ * published by the Free Software Foundation; either version 2 of
1703
+ * the License, or (at your option) any later version.
1704
+ *
1705
+ * This program is distributed in the hope that it will be useful,
1706
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1707
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1708
+ * GNU General Public License for more details.
1709
+ *
1710
+ * You should have received a copy of the GNU General Public License
1711
+ * along with this program; if not, write to the Free Software
1712
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1713
+ * MA 02111-1307 USA
1714
+ */
1715
+
1716
+#include <common.h>
1717
+#include <asm/arch/mx51.h>
1718
+#include "crm_regs.h"
1719
+
1720
+enum pll_clocks {
1721
+PLL1_CLK = MXC_DPLL1_BASE,
1722
+PLL2_CLK = MXC_DPLL2_BASE,
1723
+PLL3_CLK = MXC_DPLL3_BASE,
1724
+};
1725
+
1726
+enum pll_sw_clocks {
1727
+PLL1_SW_CLK,
1728
+PLL2_SW_CLK,
1729
+PLL3_SW_CLK,
1730
+};
1731
+
1732
+static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
1733
+{
1734
+ u32 mfi, mfn, mfd, pd;
1735
+
1736
+ mfn = __REG(pll + MXC_PLL_DP_MFN);
1737
+ mfd = __REG(pll + MXC_PLL_DP_MFD) + 1;
1738
+ mfi = __REG(pll + MXC_PLL_DP_OP);
1739
+ pd = (mfi & 0xF) + 1;
1740
+ mfi = (mfi >> 4) & 0xF;
1741
+ mfi = (mfi >= 5) ? mfi : 5;
1742
+ return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
1743
+}
1744
+
1745
+static u32 __get_mcu_main_clk(void)
1746
+{
1747
+ u32 reg, freq;
1748
+ reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
1749
+ MXC_CCM_CACRR_ARM_PODF_OFFSET;
1750
+ freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
1751
+ return freq / (reg + 1);
1752
+}
1753
+
1754
+static u32 __get_periph_clk(void)
1755
+{
1756
+ u32 reg;
1757
+ reg = __REG(MXC_CCM_CBCDR);
1758
+ if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
1759
+ reg = __REG(MXC_CCM_CBCMR);
1760
+ switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
1761
+ MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
1762
+ case 0:
1763
+ return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
1764
+ case 1:
1765
+ return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
1766
+ default:
1767
+ return 0;
1768
+ }
1769
+ }
1770
+ return __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
1771
+}
1772
+
1773
+static u32 __get_ipg_clk(void)
1774
+{
1775
+ u32 ahb_podf, ipg_podf;
1776
+
1777
+ ahb_podf = __REG(MXC_CCM_CBCDR);
1778
+ ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1779
+ MXC_CCM_CBCDR_IPG_PODF_OFFSET;
1780
+ ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
1781
+ MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1782
+ return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
1783
+}
1784
+
1785
+static u32 __get_ipg_per_clk(void)
1786
+{
1787
+ u32 pred1, pred2, podf;
1788
+ if (__REG(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
1789
+ return __get_ipg_clk();
1790
+ /* Fixme: not handle what about lpm*/
1791
+ podf = __REG(MXC_CCM_CBCDR);
1792
+ pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
1793
+ MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
1794
+ pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
1795
+ MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
1796
+ podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
1797
+ MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
1798
+
1799
+ return __get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
1800
+}
1801
+
1802
+static u32 __get_uart_clk(void)
1803
+{
1804
+ unsigned int freq, reg, pred, podf;
1805
+ reg = __REG(MXC_CCM_CSCMR1);
1806
+ switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
1807
+ MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
1808
+ case 0x0:
1809
+ freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
1810
+ break;
1811
+ case 0x1:
1812
+ freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
1813
+ break;
1814
+ case 0x2:
1815
+ freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
1816
+ break;
1817
+ default:
1818
+ return 66500000;
1819
+ }
1820
+
1821
+ reg = __REG(MXC_CCM_CSCDR1);
1822
+
1823
+ pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
1824
+ MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
1825
+
1826
+ podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
1827
+ MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
1828
+ freq /= (pred + 1) * (podf + 1);
1829
+ return freq;
1830
+}
1831
+
1832
+unsigned int mxc_get_clock(enum mxc_clock clk)
1833
+{
1834
+ switch (clk) {
1835
+ case MXC_ARM_CLK:
1836
+ return __get_mcu_main_clk();
1837
+ case MXC_AHB_CLK:
1838
+ break;
1839
+ case MXC_IPG_CLK:
1840
+ return __get_ipg_clk();
1841
+ case MXC_IPG_PERCLK:
1842
+ return __get_ipg_per_clk();
1843
+ case MXC_UART_CLK:
1844
+ return __get_uart_clk();
1845
+ }
1846
+ return -1;
1847
+}
1848
+
1849
+void mxc_dump_clocks(void)
1850
+{
1851
+ u32 freq;
1852
+ freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
1853
+ printf("mx51 pll1: %dMHz\n", freq / 1000000);
1854
+ freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
1855
+ printf("mx51 pll2: %dMHz\n", freq / 1000000);
1856
+ freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
1857
+ printf("mx51 pll3: %dMHz\n", freq / 1000000);
1858
+ printf("ipg clock : %dHz\n", __get_ipg_clk());
1859
+ printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
1860
+}
1861
+
1862
+#if defined(CONFIG_DISPLAY_CPUINFO)
1863
+int print_cpuinfo(void)
1864
+{
1865
+ printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n",
1866
+ (get_board_rev() & 0xFF) >> 4,
1867
+ (get_board_rev() & 0xF),
1868
+ __get_mcu_main_clk() / 1000000);
1869
+ mxc_dump_clocks();
1870
+ return 0;
1871
+}
1872
+#endif
1873
diff --git a/cpu/arm_cortexa8/mx51/interrupts.c b/cpu/arm_cortexa8/mx51/interrupts.c
1874
new file mode 100644
1875
index 0000000..1277d4e
1876
--- /dev/null
1877
+++ b/cpu/arm_cortexa8/mx51/interrupts.c
1878
@@ -0,0 +1,113 @@
1879
+/*
1880
+ * (C) Copyright 2007
1881
+ * Sascha Hauer, Pengutronix
1882
+ *
1883
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
1884
+ *
1885
+ * See file CREDITS for list of people who contributed to this
1886
+ * project.
1887
+ *
1888
+ * This program is free software; you can redistribute it and/or
1889
+ * modify it under the terms of the GNU General Public License as
1890
+ * published by the Free Software Foundation; either version 2 of
1891
+ * the License, or (at your option) any later version.
1892
+ *
1893
+ * This program is distributed in the hope that it will be useful,
1894
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1895
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1896
+ * GNU General Public License for more details.
1897
+ *
1898
+ * You should have received a copy of the GNU General Public License
1899
+ * along with this program; if not, write to the Free Software
1900
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1901
+ * MA 02111-1307 USA
1902
+ */
1903
+
1904
+#include <common.h>
1905
+#include <asm/arch/mx51.h>
1906
+
1907
+/* General purpose timers registers */
1908
+#define GPTCR __REG(GPT1_BASE_ADDR) /* Control register */
1909
+#define GPTPR __REG(GPT1_BASE_ADDR + 0x4) /* Prescaler register */
1910
+#define GPTSR __REG(GPT1_BASE_ADDR + 0x8) /* Status register */
1911
+#define GPTCNT __REG(GPT1_BASE_ADDR + 0x24) /* Counter register */
1912
+
1913
+/* General purpose timers bitfields */
1914
+#define GPTCR_SWR (1<<15) /* Software reset */
1915
+#define GPTCR_FRR (1<<9) /* Freerun / restart */
1916
+#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
1917
+#define GPTCR_TEN (1) /* Timer enable */
1918
+
1919
+/* nothing really to do with interrupts, just starts up a counter. */
1920
+int interrupt_init(void)
1921
+{
1922
+ int i;
1923
+ /* setup GP Timer 1 */
1924
+ GPTCR = GPTCR_SWR;
1925
+ for (i = 0; i < 100; i++)
1926
+ GPTCR = 0; /* We have no udelay by now */
1927
+ GPTPR = 0; /* 32Khz */
1928
+ /* Freerun Mode, PERCLK1 input */
1929
+ GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
1930
+ return 0;
1931
+}
1932
+
1933
+void reset_timer(void)
1934
+{
1935
+ reset_timer_masked();
1936
+}
1937
+
1938
+void reset_timer_masked(void)
1939
+{
1940
+ GPTCR = 0;
1941
+ /* Freerun Mode, PERCLK1 input */
1942
+ GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN;
1943
+}
1944
+
1945
+ulong get_timer_masked(void)
1946
+{
1947
+ ulong val = GPTCNT;
1948
+ return val;
1949
+}
1950
+
1951
+ulong get_timer(ulong base)
1952
+{
1953
+ return get_timer_masked() - base;
1954
+}
1955
+
1956
+void set_timer(ulong t)
1957
+{
1958
+}
1959
+
1960
+/* delay x useconds AND perserve advance timstamp value */
1961
+void udelay(unsigned long usec)
1962
+{
1963
+ ulong tmo, tmp;
1964
+
1965
+ /* if "big" number, spread normalization to seconds */
1966
+ if (usec >= 1000) {
1967
+ /* start to normalize for usec to ticks per sec */
1968
+ tmo = usec / 1000;
1969
+ /* find number of "ticks" to wait to achieve target */
1970
+ tmo *= CONFIG_SYS_HZ;
1971
+ tmo /= 1000; /* finish normalize. */
1972
+ } else {/* else small number, don't kill it prior to HZ multiply */
1973
+ tmo = usec * CONFIG_SYS_HZ;
1974
+ tmo /= (1000 * 1000);
1975
+ }
1976
+
1977
+ tmp = get_timer(0); /* get current timestamp */
1978
+ /* if setting this forward will roll time stamp */
1979
+ if ((tmo + tmp + 1) < tmp)
1980
+ /* reset "advancing" timestamp to 0, set lastinc value */
1981
+ reset_timer_masked();
1982
+ else /* else, set advancing stamp wake up time */
1983
+ tmo += tmp;
1984
+ while (get_timer_masked() < tmo) /* loop till event */
1985
+ /*NOP*/;
1986
+}
1987
+
1988
+void reset_cpu(ulong addr)
1989
+{
1990
+ __REG16(WDOG1_BASE_ADDR) = 4;
1991
+}
1992
diff --git a/cpu/arm_cortexa8/mx51/iomux.c b/cpu/arm_cortexa8/mx51/iomux.c
1993
new file mode 100644
1994
index 0000000..2947085
1995
--- /dev/null
1996
+++ b/cpu/arm_cortexa8/mx51/iomux.c
1997
@@ -0,0 +1,199 @@
1998
+/*
1999
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
2000
+ */
2001
+
2002
+/*
2003
+ * The code contained herein is licensed under the GNU General Public
2004
+ * License. You may obtain a copy of the GNU General Public License
2005
+ * Version 2 or later at the following locations:
2006
+ *
2007
+ * http://www.opensource.org/licenses/gpl-license.html
2008
+ * http://www.gnu.org/copyleft/gpl.html
2009
+ */
2010
+
2011
+/*!
2012
+ * @defgroup GPIO_MX51 Board GPIO and Muxing Setup
2013
+ * @ingroup MSL_MX51
2014
+ */
2015
+/*!
2016
+ * @file mach-mx51/iomux.c
2017
+ *
2018
+ * @brief I/O Muxing control functions
2019
+ *
2020
+ * @ingroup GPIO_MX51
2021
+ */
2022
+#include <common.h>
2023
+#include <asm/io.h>
2024
+#include <asm/arch/mx51.h>
2025
+#include <asm/arch/mx51_pins.h>
2026
+#include <asm/arch/iomux.h>
2027
+
2028
+/*!
2029
+ * IOMUX register (base) addresses
2030
+ */
2031
+enum iomux_reg_addr {
2032
+ IOMUXGPR0 = IOMUXC_BASE_ADDR,
2033
+ IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
2034
+ IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
2035
+ IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
2036
+ IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
2037
+ IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
2038
+};
2039
+
2040
+#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
2041
+
2042
+static inline u32 _get_mux_reg(iomux_pin_name_t pin)
2043
+{
2044
+ u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
2045
+
2046
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
2047
+ if ((pin == MX51_PIN_NANDF_RB5) ||
2048
+ (pin == MX51_PIN_NANDF_RB6) ||
2049
+ (pin == MX51_PIN_NANDF_RB7))
2050
+ ; /* Do nothing */
2051
+ else if (mux_reg >= 0x2FC)
2052
+ mux_reg += 8;
2053
+ else if (mux_reg >= 0x130)
2054
+ mux_reg += 0xC;
2055
+ }
2056
+ mux_reg += IOMUXSW_MUX_CTL;
2057
+ return mux_reg;
2058
+}
2059
+
2060
+static inline u32 _get_pad_reg(iomux_pin_name_t pin)
2061
+{
2062
+ u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
2063
+
2064
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
2065
+ if ((pin == MX51_PIN_NANDF_RB5) ||
2066
+ (pin == MX51_PIN_NANDF_RB6) ||
2067
+ (pin == MX51_PIN_NANDF_RB7))
2068
+ ; /* Do nothing */
2069
+ else if (pad_reg == 0x4D0 - PAD_I_START)
2070
+ pad_reg += 0x4C;
2071
+ else if (pad_reg == 0x860 - PAD_I_START)
2072
+ pad_reg += 0x9C;
2073
+ else if (pad_reg >= 0x804 - PAD_I_START)
2074
+ pad_reg += 0xB0;
2075
+ else if (pad_reg >= 0x7FC - PAD_I_START)
2076
+ pad_reg += 0xB4;
2077
+ else if (pad_reg >= 0x4E4 - PAD_I_START)
2078
+ pad_reg += 0xCC;
2079
+ else
2080
+ pad_reg += 8;
2081
+ }
2082
+ pad_reg += IOMUXSW_PAD_CTL;
2083
+ return pad_reg;
2084
+}
2085
+
2086
+static inline u32 _get_mux_end()
2087
+{
2088
+ if (is_soc_rev(CHIP_REV_2_0) < 0)
2089
+ return IOMUXC_BASE_ADDR + (0x3F8 - 4);
2090
+ else
2091
+ return IOMUXC_BASE_ADDR + (0x3F0 - 4);
2092
+}
2093
+
2094
+/*!
2095
+ * This function is used to configure a pin through the IOMUX module.
2096
+ * FIXED ME: for backward compatible. Will be static function!
2097
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
2098
+ * @param cfg an output function as defined in \b #iomux_pin_cfg_t
2099
+ *
2100
+ * @return 0 if successful; Non-zero otherwise
2101
+ */
2102
+static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
2103
+{
2104
+ u32 mux_reg = _get_mux_reg(pin);
2105
+
2106
+ if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
2107
+ return -1;
2108
+ if (cfg == IOMUX_CONFIG_GPIO)
2109
+ writel(PIN_TO_ALT_GPIO(pin), mux_reg);
2110
+ else
2111
+ writel(cfg, mux_reg);
2112
+
2113
+ return 0;
2114
+}
2115
+
2116
+/*!
2117
+ * Request ownership for an IO pin. This function has to be the first one
2118
+ * being called before that pin is used. The caller has to check the
2119
+ * return value to make sure it returns 0.
2120
+ *
2121
+ * @param pin a name defined by \b iomux_pin_name_t
2122
+ * @param cfg an input function as defined in \b #iomux_pin_cfg_t
2123
+ *
2124
+ * @return 0 if successful; Non-zero otherwise
2125
+ */
2126
+int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
2127
+{
2128
+ int ret = iomux_config_mux(pin, cfg);
2129
+ return ret;
2130
+}
2131
+
2132
+/*!
2133
+ * Release ownership for an IO pin
2134
+ *
2135
+ * @param pin a name defined by \b iomux_pin_name_t
2136
+ * @param cfg an input function as defined in \b #iomux_pin_cfg_t
2137
+ */
2138
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
2139
+{
2140
+}
2141
+
2142
+/*!
2143
+ * This function configures the pad value for a IOMUX pin.
2144
+ *
2145
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
2146
+ * @param config the ORed value of elements defined in \b #iomux_pad_config_t
2147
+ */
2148
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
2149
+{
2150
+ u32 pad_reg = _get_pad_reg(pin);
2151
+ writel(config, pad_reg);
2152
+}
2153
+
2154
+unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
2155
+{
2156
+ u32 pad_reg = _get_pad_reg(pin);
2157
+ return readl(pad_reg);
2158
+}
2159
+/*!
2160
+ * This function configures input path.
2161
+ *
2162
+ * @param input index of input select register as defined in \b
2163
+ * #iomux_input_select_t
2164
+ * @param config the binary value of elements defined in \b
2165
+ * #iomux_input_config_t
2166
+ */
2167
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
2168
+{
2169
+ u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
2170
+
2171
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
2172
+ if (input == MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT)
2173
+ input -= 4;
2174
+ else if (input ==
2175
+ MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT)
2176
+ input -= 3;
2177
+ else if (input >= MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT)
2178
+ input -= 2;
2179
+ else if (input >=
2180
+ MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT)
2181
+ input -= 5;
2182
+ else if (input >=
2183
+ MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT)
2184
+ input -= 3;
2185
+ else if (input >= MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT)
2186
+ input -= 2;
2187
+ else if (input >= MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT)
2188
+ input -= 1;
2189
+
2190
+ reg += INPUT_CTL_START_TO1;
2191
+ } else {
2192
+ reg += INPUT_CTL_START;
2193
+ }
2194
+
2195
+ writel(config, reg);
2196
+}
2197
diff --git a/cpu/arm_cortexa8/mx51/mxc_nand_load.S b/cpu/arm_cortexa8/mx51/mxc_nand_load.S
2198
new file mode 100644
2199
index 0000000..ca1f07b
2200
--- /dev/null
2201
+++ b/cpu/arm_cortexa8/mx51/mxc_nand_load.S
2202
@@ -0,0 +1,167 @@
2203
+/*
2204
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
2205
+ *
2206
+ * See file CREDITS for list of people who contributed to this
2207
+ * project.
2208
+ *
2209
+ * This program is free software; you can redistribute it and/or
2210
+ * modify it under the terms of the GNU General Public License as
2211
+ * published by the Free Software Foundation; either version 2 of
2212
+ * the License, or (at your option) any later version.
2213
+ *
2214
+ * This program is distributed in the hope that it will be useful,
2215
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2216
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2217
+ * GNU General Public License for more details.
2218
+ *
2219
+ * You should have received a copy of the GNU General Public License
2220
+ * along with this program; if not, write to the Free Software
2221
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2222
+ * MA 02111-1307 USA
2223
+ */
2224
+
2225
+#include <config.h>
2226
+#include <asm/arch/mx51.h>
2227
+.macro do_wait_op_done
2228
+1: ldr r7, [r3, #0x2C]
2229
+ ands r7, r7, #0x80000000
2230
+ beq 1b
2231
+ mov r7, #0x0
2232
+ str r7, [r3, #0x2C]
2233
+.endm // do_wait_op_done
2234
+
2235
+.section ".text.load", "x"
2236
+.globl mxc_nand_load
2237
+/*
2238
+ * R0: NFC BUF base address
2239
+ * R1: NFC BUF data end address
2240
+ * R2: RAM destination offset address
2241
+ * R3: NFC IP control register base
2242
+ * R4: NAND block address
2243
+ * R5: RAM destination end address
2244
+ * R6: NFC DATA register base
2245
+ * R7 - r14: 8 working buffer registers
2246
+ */
2247
+mxc_nand_load:
2248
+ ldr r0, =NFC_BASE_ADDR_AXI
2249
+ add r1, r0, #NFC_BUF_SIZE
2250
+
2251
+ /* For non-nand-boot, directly quit */
2252
+ cmp pc, r0
2253
+ movlo pc, lr
2254
+ cmp pc, r1
2255
+ movhi pc, lr
2256
+
2257
+ mov r4, #NFC_BUF_SIZE
2258
+ /* Get NAND page size */
2259
+ ldr r3, =NFC_BASE_ADDR
2260
+ ldr r2, [r3, #0x24]
2261
+ and r2, r2, #0x3
2262
+ cmp r2, #1
2263
+ moveq r2, #0x800
2264
+ movlt r2, #0x200
2265
+ adrls r5, NFC_PAGE_MODE
2266
+ strls r2, [r5]
2267
+ /* Get actually pre-loading size*/
2268
+ subls r1, r1, #0x800
2269
+ subls r4, r4, #0x800
2270
+
2271
+ /* r1 ~ r3, r12, lr(r14) must not change in relocated operation */
2272
+ ldr r2, U_BOOT_NAND_START
2273
+1: ldmia r0!, {r5-r11, r13}
2274
+ stmia r2!, {r5-r11, r13}
2275
+ cmp r0, r1
2276
+ blo 1b
2277
+
2278
+ ldr r0, CONST_0X0FFF
2279
+ ldr r5, U_BOOT_NAND_START
2280
+ and lr, lr, r0
2281
+ add lr, lr, r5
2282
+ and r12, r12, r0
2283
+ add r12, r12, r5
2284
+ add r5, r5, #0x8
2285
+ and r0, pc, r0
2286
+ add pc, r5, r0
2287
+ nop
2288
+ nop
2289
+ nop
2290
+ nop
2291
+ nop
2292
+ adr r0, SAVE_REGS /* Save r12 & R14(lr) */
2293
+ str r12, [r0]
2294
+ str lr, [r0, #4]
2295
+Copy_Main:
2296
+ ldr r0, =NFC_BASE_ADDR_AXI
2297
+
2298
+ add r6, r0, #0x1E00
2299
+ ldr r5, =_end /* Try get right image size */
2300
+ add r5, r2, #0x00040000 /* Fixme to get actual image size */
2301
+
2302
+ mov r7, #0xFF000000
2303
+ add r7, r7, #0x00FF0000
2304
+ str r7, [r3, #0x4]
2305
+ str r7, [r3, #0x8]
2306
+ str r7, [r3, #0xC]
2307
+ str r7, [r3, #0x10]
2308
+ str r7, [r3, #0x14]
2309
+ str r7, [r3, #0x18]
2310
+ str r7, [r3, #0x1C]
2311
+ str r7, [r3, #0x20]
2312
+ mov r8, #0x7
2313
+ mov r7, #0x84
2314
+1: add r9, r7, r8, lsr #3
2315
+ str r9, [r3, #0x0]
2316
+ subs r8, r8, #0x01
2317
+ bne 1b
2318
+
2319
+ mov r7, #0
2320
+ str r7, [r3, #0x2C]
2321
+
2322
+ ldr r7, NFC_PAGE_MODE
2323
+Read_Page:
2324
+ /* start_nfc_addr_ops1(pg_no, pg_off) */
2325
+ cmp r7, #0x800
2326
+ movgt r7, r4, lsr #12 /* Get the page number for 4K page */
2327
+ moveq r7, r4, lsr #11 /* Get the page number for 2K page */
2328
+ mov r7, r7, lsl #16
2329
+ str r7, [r6, #0x04] /* Set the address */
2330
+
2331
+ /* writel((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG)*/
2332
+ mov r7, #0x3000
2333
+ str r7, [r6,#0x0]
2334
+
2335
+ /* writel(0x00000000, NAND_CONFIGURATION1_REG) */
2336
+ mov r7, #0x0
2337
+ str r7, [r6, #0x34]
2338
+
2339
+ /* start auto-read
2340
+ * writel(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
2341
+ */
2342
+ mov r7, #0x80
2343
+ str r7, [r6, #0x40]
2344
+
2345
+ do_wait_op_done
2346
+
2347
+Copy_Good_Blk:
2348
+1: ldmia r0!, {r7-r14}
2349
+ stmia r2!, {r7-r14}
2350
+ cmp r0, r1
2351
+ blo 1b
2352
+ cmp r2, r5
2353
+ bge Copy_Main_done
2354
+ ldr r7, NFC_PAGE_MODE
2355
+ add r4, r4, r7
2356
+ ldr r0, =NFC_BASE_ADDR_AXI
2357
+ b Read_Page
2358
+
2359
+Copy_Main_done:
2360
+ adr r0, SAVE_REGS
2361
+ ldr r12, [r0]
2362
+ ldr lr, [r0, #4]
2363
+ mov pc, lr
2364
+
2365
+U_BOOT_NAND_START: .word TEXT_BASE
2366
+CONST_0X0FFF: .word 0x0FFF
2367
+NFC_PAGE_MODE: .word 0x1000
2368
+SAVE_REGS: .word 0x0
2369
+ .word 0x0
2370
diff --git a/cpu/arm_cortexa8/mx51/serial.c b/cpu/arm_cortexa8/mx51/serial.c
2371
new file mode 100644
2372
index 0000000..7fe74e5
2373
--- /dev/null
2374
+++ b/cpu/arm_cortexa8/mx51/serial.c
2375
@@ -0,0 +1,226 @@
2376
+/*
2377
+ * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
2378
+ *
2379
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
2380
+ *
2381
+ * This program is free software; you can redistribute it and/or modify
2382
+ * it under the terms of the GNU General Public License as published by
2383
+ * the Free Software Foundation; either version 2 of the License, or
2384
+ * (at your option) any later version.
2385
+ *
2386
+ * This program is distributed in the hope that it will be useful,
2387
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2388
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2389
+ * GNU General Public License for more details.
2390
+ *
2391
+ * You should have received a copy of the GNU General Public License
2392
+ * along with this program; if not, write to the Free Software
2393
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2394
+ *
2395
+ */
2396
+
2397
+#include <common.h>
2398
+
2399
+#if defined CONFIG_MX51_UART
2400
+
2401
+#include <asm/arch/mx51.h>
2402
+
2403
+#ifdef CONFIG_MX51_UART1
2404
+#define UART_PHYS UART1_BASE_ADDR
2405
+#elif defined(CONFIG_MX51_UART2)
2406
+#define UART_PHYS UART2_BASE_ADDR
2407
+#elif defined(CONFIG_MX51_UART3)
2408
+#define UART_PHYS UART3_BASE_ADDR
2409
+#else
2410
+#error "define CFG_MX51_UARTx to use the mx51 UART driver"
2411
+#endif
2412
+
2413
+/* Register definitions */
2414
+#define URXD 0x0 /* Receiver Register */
2415
+#define UTXD 0x40 /* Transmitter Register */
2416
+#define UCR1 0x80 /* Control Register 1 */
2417
+#define UCR2 0x84 /* Control Register 2 */
2418
+#define UCR3 0x88 /* Control Register 3 */
2419
+#define UCR4 0x8c /* Control Register 4 */
2420
+#define UFCR 0x90 /* FIFO Control Register */
2421
+#define USR1 0x94 /* Status Register 1 */
2422
+#define USR2 0x98 /* Status Register 2 */
2423
+#define UESC 0x9c /* Escape Character Register */
2424
+#define UTIM 0xa0 /* Escape Timer Register */
2425
+#define UBIR 0xa4 /* BRM Incremental Register */
2426
+#define UBMR 0xa8 /* BRM Modulator Register */
2427
+#define UBRC 0xac /* Baud Rate Count Register */
2428
+#define UTS 0xb4 /* UART Test Register (mx31) */
2429
+
2430
+/* UART Control Register Bit Fields.*/
2431
+#define URXD_CHARRDY (1<<15)
2432
+#define URXD_ERR (1<<14)
2433
+#define URXD_OVRRUN (1<<13)
2434
+#define URXD_FRMERR (1<<12)
2435
+#define URXD_BRK (1<<11)
2436
+#define URXD_PRERR (1<<10)
2437
+#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
2438
+#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
2439
+#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
2440
+#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
2441
+#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
2442
+#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
2443
+#define UCR1_IREN (1<<7) /* Infrared interface enable */
2444
+#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
2445
+#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
2446
+#define UCR1_SNDBRK (1<<4) /* Send break */
2447
+#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
2448
+#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
2449
+#define UCR1_DOZE (1<<1) /* Doze */
2450
+#define UCR1_UARTEN (1<<0) /* UART enabled */
2451
+#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
2452
+#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
2453
+#define UCR2_CTSC (1<<13) /* CTS pin control */
2454
+#define UCR2_CTS (1<<12) /* Clear to send */
2455
+#define UCR2_ESCEN (1<<11) /* Escape enable */
2456
+#define UCR2_PREN (1<<8) /* Parity enable */
2457
+#define UCR2_PROE (1<<7) /* Parity odd/even */
2458
+#define UCR2_STPB (1<<6) /* Stop */
2459
+#define UCR2_WS (1<<5) /* Word size */
2460
+#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
2461
+#define UCR2_TXEN (1<<2) /* Transmitter enabled */
2462
+#define UCR2_RXEN (1<<1) /* Receiver enabled */
2463
+#define UCR2_SRST (1<<0) /* SW reset */
2464
+#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
2465
+#define UCR3_PARERREN (1<<12) /* Parity enable */
2466
+#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
2467
+#define UCR3_DSR (1<<10) /* Data set ready */
2468
+#define UCR3_DCD (1<<9) /* Data carrier detect */
2469
+#define UCR3_RI (1<<8) /* Ring indicator */
2470
+#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
2471
+#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
2472
+#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
2473
+#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
2474
+#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
2475
+#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
2476
+#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
2477
+#define UCR3_BPEN (1<<0) /* Preset registers enable */
2478
+#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
2479
+#define UCR4_INVR (1<<9) /* Inverted infrared reception */
2480
+#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
2481
+#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
2482
+#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
2483
+#define UCR4_IRSC (1<<5) /* IR special case */
2484
+#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
2485
+#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
2486
+#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
2487
+#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
2488
+#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
2489
+#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
2490
+#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
2491
+#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
2492
+#define USR1_RTSS (1<<14) /* RTS pin status */
2493
+#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */
2494
+#define USR1_RTSD (1<<12) /* RTS delta */
2495
+#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
2496
+#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
2497
+#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
2498
+#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
2499
+#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
2500
+#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
2501
+#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
2502
+#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
2503
+#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
2504
+#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
2505
+#define USR2_IDLE (1<<12) /* Idle condition */
2506
+#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
2507
+#define USR2_WAKE (1<<7) /* Wake */
2508
+#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
2509
+#define USR2_TXDC (1<<3) /* Transmitter complete */
2510
+#define USR2_BRCD (1<<2) /* Break condition */
2511
+#define USR2_ORE (1<<1) /* Overrun error */
2512
+#define USR2_RDR (1<<0) /* Recv data ready */
2513
+#define UTS_FRCPERR (1<<13) /* Force parity error */
2514
+#define UTS_LOOP (1<<12) /* Loop tx and rx */
2515
+#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
2516
+#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
2517
+#define UTS_TXFULL (1<<4) /* TxFIFO full */
2518
+#define UTS_RXFULL (1<<3) /* RxFIFO full */
2519
+#define UTS_SOFTRST (1<<0) /* Software reset */
2520
+
2521
+DECLARE_GLOBAL_DATA_PTR;
2522
+
2523
+void serial_setbrg(void)
2524
+{
2525
+ u32 clk = mxc_get_clock(MXC_UART_CLK);
2526
+
2527
+ if (!gd->baudrate)
2528
+ gd->baudrate = CONFIG_BAUDRATE;
2529
+ __REG(UART_PHYS + UFCR) = 0x4 << 7; /* divide input clock by 2 */
2530
+ __REG(UART_PHYS + UBIR) = 0xf;
2531
+ __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
2532
+}
2533
+
2534
+int serial_getc(void)
2535
+{
2536
+ while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
2537
+ ;
2538
+ return __REG(UART_PHYS + URXD);
2539
+}
2540
+
2541
+void serial_putc(const char c)
2542
+{
2543
+ __REG(UART_PHYS + UTXD) = c;
2544
+
2545
+ /* wait for transmitter to be ready */
2546
+ while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
2547
+ ;
2548
+
2549
+ /* If \n, also do \r */
2550
+ if (c == '\n')
2551
+ serial_putc('\r');
2552
+}
2553
+
2554
+/*
2555
+ * Test whether a character is in the RX buffer
2556
+ */
2557
+int serial_tstc(void)
2558
+{
2559
+ /* If receive fifo is empty, return false */
2560
+ if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
2561
+ return 0;
2562
+ return 1;
2563
+}
2564
+
2565
+void serial_puts(const char *s)
2566
+{
2567
+ while (*s)
2568
+ serial_putc(*s++);
2569
+}
2570
+
2571
+/*
2572
+ * Initialise the serial port with the given baudrate. The settings
2573
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
2574
+ *
2575
+ */
2576
+int serial_init(void)
2577
+{
2578
+ __REG(UART_PHYS + UCR1) = 0x0;
2579
+ __REG(UART_PHYS + UCR2) = 0x0;
2580
+
2581
+ while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST))
2582
+ ;
2583
+
2584
+ __REG(UART_PHYS + UCR3) = 0x0704;
2585
+ __REG(UART_PHYS + UCR4) = 0x8000;
2586
+ __REG(UART_PHYS + UESC) = 0x002b;
2587
+ __REG(UART_PHYS + UTIM) = 0x0;
2588
+
2589
+ __REG(UART_PHYS + UTS) = 0x0;
2590
+
2591
+ serial_setbrg();
2592
+
2593
+ __REG(UART_PHYS + UCR2) =
2594
+ UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
2595
+
2596
+ __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
2597
+
2598
+ return 0;
2599
+}
2600
+
2601
+#endif /* CONFIG_MX51_UART */
2602
diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S
2603
index 07acdbd..4a6e0ea 100644
2604
--- a/cpu/arm_cortexa8/start.S
2605
+++ b/cpu/arm_cortexa8/start.S
2606
@@ -9,6 +9,7 @@
2607
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
2608
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
2609
* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
2610
+ * Copyright (c) 2009 Freescale Semiconductor, Inc.
2611
*
2612
* See file CREDITS for list of people who contributed to this
2613
* project.
2614
@@ -501,7 +502,7 @@ finished_inval:
2615
2616
ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
2617
2618
-
2619
+#ifdef PRM_RSTCTRL
2620
.align 5
2621
.global reset_cpu
2622
reset_cpu:
2623
@@ -514,3 +515,4 @@ _loop_forever:
2624
b _loop_forever
2625
rstctl:
2626
.word PRM_RSTCTRL
2627
+#endif
2628
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
2629
index 2260d31..eaf61f3 100644
2630
--- a/drivers/mtd/nand/Makefile
2631
+++ b/drivers/mtd/nand/Makefile
2632
@@ -40,6 +40,7 @@ COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
2633
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
2634
COBJS-$(CONFIG_MX31_NAND) += mx31_nand.o
2635
COBJS-$(CONFIG_MX35) += mxc_nand.o
2636
+COBJS-$(CONFIG_MX51) += mxc_nand.o
2637
endif
2638
2639
COBJS := $(COBJS-y)
2640
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
2641
index 790f35f..20682bb 100644
2642
--- a/drivers/net/smc911x.c
2643
+++ b/drivers/net/smc911x.c
2644
@@ -29,6 +29,15 @@
2645
#include <net.h>
2646
#include <miiphy.h>
2647
2648
+#ifndef CONFIG_DRIVER_SMC911X_BASE
2649
+#ifdef CONFIG_DRIVER_SMC911X_BASE_VARIABLE
2650
+extern u32 CONFIG_DRIVER_SMC911X_BASE_VARIABLE;
2651
+#define CONFIG_DRIVER_SMC911X_BASE CONFIG_DRIVER_SMC911X_BASE_VARIABLE
2652
+#else
2653
+#error "Please define base constant or variable!"
2654
+#endif
2655
+#endif
2656
+
2657
#if defined (CONFIG_DRIVER_SMC911X_32_BIT)
2658
static inline u32 reg_read(u32 addr)
2659
{
2660
diff --git a/include/asm-arm/arch-mx51/iomux.h b/include/asm-arm/arch-mx51/iomux.h
2661
new file mode 100644
2662
index 0000000..fa02984
2663
--- /dev/null
2664
+++ b/include/asm-arm/arch-mx51/iomux.h
2665
@@ -0,0 +1,240 @@
2666
+/*
2667
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
2668
+ */
2669
+
2670
+/*
2671
+ * The code contained herein is licensed under the GNU General Public
2672
+ * License. You may obtain a copy of the GNU General Public License
2673
+ * Version 2 or later at the following locations:
2674
+ *
2675
+ * http://www.opensource.org/licenses/gpl-license.html
2676
+ * http://www.gnu.org/copyleft/gpl.html
2677
+ */
2678
+#ifndef __MACH_MX51_IOMUX_H__
2679
+#define __MACH_MX51_IOMUX_H__
2680
+
2681
+#include <common.h>
2682
+#include <asm/io.h>
2683
+#include <asm/arch/mx51.h>
2684
+#include <asm/arch/mx51_pins.h>
2685
+
2686
+/*!
2687
+ * @file iomux.h
2688
+ *
2689
+ * @brief I/O Muxing control definitions and functions
2690
+ *
2691
+ * @ingroup GPIO_MX51
2692
+ */
2693
+
2694
+typedef unsigned int iomux_pin_name_t;
2695
+
2696
+/*!
2697
+ * various IOMUX output functions
2698
+ */
2699
+typedef enum iomux_config {
2700
+ IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
2701
+ IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
2702
+ IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
2703
+ IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
2704
+ IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
2705
+ IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
2706
+ IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
2707
+ IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
2708
+ IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
2709
+ IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
2710
+} iomux_pin_cfg_t;
2711
+
2712
+/*!
2713
+ * various IOMUX pad functions
2714
+ */
2715
+typedef enum iomux_pad_config {
2716
+ PAD_CTL_SRE_SLOW = 0x0 << 0,
2717
+ PAD_CTL_SRE_FAST = 0x1 << 0,
2718
+ PAD_CTL_DRV_LOW = 0x0 << 1,
2719
+ PAD_CTL_DRV_MEDIUM = 0x1 << 1,
2720
+ PAD_CTL_DRV_HIGH = 0x2 << 1,
2721
+ PAD_CTL_DRV_MAX = 0x3 << 1,
2722
+ PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
2723
+ PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
2724
+ PAD_CTL_100K_PD = 0x0 << 4,
2725
+ PAD_CTL_47K_PU = 0x1 << 4,
2726
+ PAD_CTL_100K_PU = 0x2 << 4,
2727
+ PAD_CTL_22K_PU = 0x3 << 4,
2728
+ PAD_CTL_PUE_KEEPER = 0x0 << 6,
2729
+ PAD_CTL_PUE_PULL = 0x1 << 6,
2730
+ PAD_CTL_PKE_NONE = 0x0 << 7,
2731
+ PAD_CTL_PKE_ENABLE = 0x1 << 7,
2732
+ PAD_CTL_HYS_NONE = 0x0 << 8,
2733
+ PAD_CTL_HYS_ENABLE = 0x1 << 8,
2734
+ PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
2735
+ PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
2736
+ PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
2737
+ PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
2738
+} iomux_pad_config_t;
2739
+
2740
+/*!
2741
+ * various IOMUX input select register index
2742
+ */
2743
+typedef enum iomux_input_select {
2744
+ MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
2745
+ MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
2746
+ MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
2747
+ MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
2748
+ MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
2749
+ MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
2750
+ MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
2751
+ MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
2752
+ MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
2753
+ MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
2754
+ MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
2755
+ MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
2756
+ MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
2757
+ MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
2758
+ MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
2759
+ MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
2760
+ MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
2761
+ /* TO2 */
2762
+ MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
2763
+ MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
2764
+ MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
2765
+ MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
2766
+ MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
2767
+ MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
2768
+ MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
2769
+ MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
2770
+ MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
2771
+ MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
2772
+ /* TO2 */
2773
+ MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
2774
+ MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
2775
+ MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
2776
+ MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
2777
+ MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
2778
+ MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
2779
+ MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
2780
+ MUX_IN_FEC_FEC_COL_SELECT_INPUT,
2781
+ MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
2782
+ MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
2783
+ MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
2784
+ MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
2785
+ MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
2786
+ MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
2787
+ MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
2788
+ MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
2789
+ MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
2790
+ MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
2791
+ MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
2792
+ MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
2793
+ MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
2794
+ MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
2795
+ MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
2796
+ MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
2797
+ MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
2798
+ MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
2799
+ /* TO2 */
2800
+ MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
2801
+ MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
2802
+ MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
2803
+ /* TO2 */
2804
+ MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
2805
+ /* TO2 */
2806
+ MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
2807
+ MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
2808
+ MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
2809
+ MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
2810
+ MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
2811
+ MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
2812
+
2813
+ MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
2814
+
2815
+ MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
2816
+
2817
+ MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
2818
+ MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
2819
+ MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
2820
+ MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
2821
+ MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
2822
+ MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
2823
+ MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
2824
+ MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
2825
+ MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
2826
+ MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
2827
+ MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
2828
+ MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
2829
+ MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
2830
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
2831
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
2832
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
2833
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
2834
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
2835
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
2836
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
2837
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
2838
+ MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
2839
+ MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
2840
+ MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
2841
+ MUX_INPUT_NUM_MUX,
2842
+} iomux_input_select_t;
2843
+
2844
+/*!
2845
+ * various IOMUX input functions
2846
+ */
2847
+typedef enum iomux_input_config {
2848
+ INPUT_CTL_PATH0 = 0x0,
2849
+ INPUT_CTL_PATH1,
2850
+ INPUT_CTL_PATH2,
2851
+ INPUT_CTL_PATH3,
2852
+ INPUT_CTL_PATH4,
2853
+ INPUT_CTL_PATH5,
2854
+ INPUT_CTL_PATH6,
2855
+ INPUT_CTL_PATH7,
2856
+} iomux_input_config_t;
2857
+
2858
+/*!
2859
+ * Request ownership for an IO pin. This function has to be the first one
2860
+ * being called before that pin is used. The caller has to check the
2861
+ * return value to make sure it returns 0.
2862
+ *
2863
+ * @param pin a name defined by \b iomux_pin_name_t
2864
+ * @param config config as defined in \b #iomux_pin_ocfg_t
2865
+ *
2866
+ * @return 0 if successful; Non-zero otherwise
2867
+ */
2868
+int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
2869
+
2870
+/*!
2871
+ * Release ownership for an IO pin
2872
+ *
2873
+ * @param pin a name defined by \b iomux_pin_name_t
2874
+ * @param config config as defined in \b #iomux_pin_ocfg_t
2875
+ */
2876
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
2877
+
2878
+/*!
2879
+ * This function configures the pad value for a IOMUX pin.
2880
+ *
2881
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
2882
+ * @param config the ORed value of elements defined in
2883
+ * \b #iomux_pad_config_t
2884
+ */
2885
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
2886
+
2887
+/*!
2888
+ * This function gets the current pad value for a IOMUX pin.
2889
+ *
2890
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
2891
+ * @return current pad value
2892
+ */
2893
+unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
2894
+
2895
+/*!
2896
+ * This function configures input path.
2897
+ *
2898
+ * @param input index of input select register as defined in
2899
+ * \b #iomux_input_select_t
2900
+ * @param config the binary value of elements defined in
2901
+ * \b #iomux_input_config_t
2902
+ */
2903
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
2904
+
2905
+#endif /* __MACH_MX51_IOMUX_H__ */
2906
diff --git a/include/asm-arm/arch-mx51/mx51.h b/include/asm-arm/arch-mx51/mx51.h
2907
new file mode 100644
2908
index 0000000..d9d8ef7
2909
--- /dev/null
2910
+++ b/include/asm-arm/arch-mx51/mx51.h
2911
@@ -0,0 +1,423 @@
2912
+/*
2913
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
2914
+ */
2915
+
2916
+/*
2917
+ * The code contained herein is licensed under the GNU General Public
2918
+ * License. You may obtain a copy of the GNU General Public License
2919
+ * Version 2 or later at the following locations:
2920
+ *
2921
+ * http://www.opensource.org/licenses/gpl-license.html
2922
+ * http://www.gnu.org/copyleft/gpl.html
2923
+ */
2924
+
2925
+#ifndef __ASM_ARCH_MXC_MX51_H__
2926
+#define __ASM_ARCH_MXC_MX51_H__
2927
+
2928
+#define __REG(x) (*((volatile u32 *)(x)))
2929
+#define __REG16(x) (*((volatile u16 *)(x)))
2930
+#define __REG8(x) (*((volatile u8 *)(x)))
2931
+/*
2932
+ * IRAM
2933
+ */
2934
+#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
2935
+/*
2936
+ * Graphics Memory of GPU
2937
+ */
2938
+#define GPU_BASE_ADDR 0x20000000
2939
+#define GPU_CTRL_BASE_ADDR 0x30000000
2940
+#define IPU_CTRL_BASE_ADDR 0x40000000
2941
+/*
2942
+ * Debug
2943
+ */
2944
+#define DEBUG_BASE_ADDR 0x60000000
2945
+#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
2946
+#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
2947
+#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
2948
+#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
2949
+#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
2950
+#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
2951
+#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
2952
+#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
2953
+
2954
+/*
2955
+ * SPBA global module enabled #0
2956
+ */
2957
+#define SPBA0_BASE_ADDR 0x70000000
2958
+
2959
+#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
2960
+#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
2961
+#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
2962
+#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
2963
+#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
2964
+#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
2965
+#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
2966
+#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
2967
+#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
2968
+#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
2969
+#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
2970
+#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
2971
+
2972
+/*
2973
+ * AIPS 1
2974
+ */
2975
+#define AIPS1_BASE_ADDR 0x73F00000
2976
+
2977
+#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
2978
+#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
2979
+#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
2980
+#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
2981
+#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
2982
+#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
2983
+#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
2984
+#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
2985
+#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
2986
+#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
2987
+#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
2988
+#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
2989
+#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
2990
+#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
2991
+#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
2992
+#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
2993
+#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
2994
+#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
2995
+#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
2996
+#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
2997
+
2998
+/*
2999
+ * AIPS 2
3000
+ */
3001
+#define AIPS2_BASE_ADDR 0x83F00000
3002
+
3003
+#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
3004
+#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
3005
+#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
3006
+#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
3007
+#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
3008
+#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
3009
+#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
3010
+#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
3011
+#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
3012
+#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
3013
+#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
3014
+#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
3015
+#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
3016
+#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
3017
+#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
3018
+#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
3019
+#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
3020
+#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
3021
+#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
3022
+#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
3023
+#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
3024
+#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
3025
+#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
3026
+#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
3027
+#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
3028
+#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
3029
+#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
3030
+#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
3031
+#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
3032
+#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
3033
+#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
3034
+#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
3035
+
3036
+#define TZIC_BASE_ADDR 0x8FFFC000
3037
+
3038
+/*
3039
+ * Memory regions and CS
3040
+ */
3041
+#define CSD0_BASE_ADDR 0x90000000
3042
+#define CSD1_BASE_ADDR 0xA0000000
3043
+#define CS0_BASE_ADDR 0xB0000000
3044
+#define CS1_BASE_ADDR 0xB8000000
3045
+#define CS2_BASE_ADDR 0xC0000000
3046
+#define CS3_BASE_ADDR 0xC8000000
3047
+#define CS4_BASE_ADDR 0xCC000000
3048
+#define CS5_BASE_ADDR 0xCE000000
3049
+
3050
+/*
3051
+ * NFC
3052
+ */
3053
+#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
3054
+
3055
+/*!
3056
+ * defines for SPBA modules
3057
+ */
3058
+#define SPBA_SDHC1 0x04
3059
+#define SPBA_SDHC2 0x08
3060
+#define SPBA_UART3 0x0C
3061
+#define SPBA_CSPI1 0x10
3062
+#define SPBA_SSI2 0x14
3063
+#define SPBA_SDHC3 0x20
3064
+#define SPBA_SDHC4 0x24
3065
+#define SPBA_SPDIF 0x28
3066
+#define SPBA_ATA 0x30
3067
+#define SPBA_SLIM 0x34
3068
+#define SPBA_HSI2C 0x38
3069
+#define SPBA_CTRL 0x3C
3070
+
3071
+/*
3072
+ * Interrupt numbers
3073
+ */
3074
+#define MXC_INT_BASE 0
3075
+#define MXC_INT_RESV0 0
3076
+#define MXC_INT_MMC_SDHC1 1
3077
+#define MXC_INT_MMC_SDHC2 2
3078
+#define MXC_INT_MMC_SDHC3 3
3079
+#define MXC_INT_MMC_SDHC4 4
3080
+#define MXC_INT_RESV5 5
3081
+#define MXC_INT_SDMA 6
3082
+#define MXC_INT_IOMUX 7
3083
+#define MXC_INT_NFC 8
3084
+#define MXC_INT_VPU 9
3085
+#define MXC_INT_IPU_ERR 10
3086
+#define MXC_INT_IPU_SYN 11
3087
+#define MXC_INT_GPU 12
3088
+#define MXC_INT_RESV13 13
3089
+#define MXC_INT_USB_H1 14
3090
+#define MXC_INT_EMI 15
3091
+#define MXC_INT_USB_H2 16
3092
+#define MXC_INT_USB_H3 17
3093
+#define MXC_INT_USB_OTG 18
3094
+#define MXC_INT_SAHARA_H0 19
3095
+#define MXC_INT_SAHARA_H1 20
3096
+#define MXC_INT_SCC_SMN 21
3097
+#define MXC_INT_SCC_STZ 22
3098
+#define MXC_INT_SCC_SCM 23
3099
+#define MXC_INT_SRTC_NTZ 24
3100
+#define MXC_INT_SRTC_TZ 25
3101
+#define MXC_INT_RTIC 26
3102
+#define MXC_INT_CSU 27
3103
+#define MXC_INT_SLIM_B 28
3104
+#define MXC_INT_SSI1 29
3105
+#define MXC_INT_SSI2 30
3106
+#define MXC_INT_UART1 31
3107
+#define MXC_INT_UART2 32
3108
+#define MXC_INT_UART3 33
3109
+#define MXC_INT_RESV34 34
3110
+#define MXC_INT_RESV35 35
3111
+#define MXC_INT_CSPI1 36
3112
+#define MXC_INT_CSPI2 37
3113
+#define MXC_INT_CSPI 38
3114
+#define MXC_INT_GPT 39
3115
+#define MXC_INT_EPIT1 40
3116
+#define MXC_INT_EPIT2 41
3117
+#define MXC_INT_GPIO1_INT7 42
3118
+#define MXC_INT_GPIO1_INT6 43
3119
+#define MXC_INT_GPIO1_INT5 44
3120
+#define MXC_INT_GPIO1_INT4 45
3121
+#define MXC_INT_GPIO1_INT3 46
3122
+#define MXC_INT_GPIO1_INT2 47
3123
+#define MXC_INT_GPIO1_INT1 48
3124
+#define MXC_INT_GPIO1_INT0 49
3125
+#define MXC_INT_GPIO1_LOW 50
3126
+#define MXC_INT_GPIO1_HIGH 51
3127
+#define MXC_INT_GPIO2_LOW 52
3128
+#define MXC_INT_GPIO2_HIGH 53
3129
+#define MXC_INT_GPIO3_LOW 54
3130
+#define MXC_INT_GPIO3_HIGH 55
3131
+#define MXC_INT_GPIO4_LOW 56
3132
+#define MXC_INT_GPIO4_HIGH 57
3133
+#define MXC_INT_WDOG1 58
3134
+#define MXC_INT_WDOG2 59
3135
+#define MXC_INT_KPP 60
3136
+#define MXC_INT_PWM1 61
3137
+#define MXC_INT_I2C1 62
3138
+#define MXC_INT_I2C2 63
3139
+#define MXC_INT_HS_I2C 64
3140
+#define MXC_INT_RESV65 65
3141
+#define MXC_INT_RESV66 66
3142
+#define MXC_INT_SIM_IPB 67
3143
+#define MXC_INT_SIM_DAT 68
3144
+#define MXC_INT_IIM 69
3145
+#define MXC_INT_ATA 70
3146
+#define MXC_INT_CCM1 71
3147
+#define MXC_INT_CCM2 72
3148
+#define MXC_INT_GPC1 73
3149
+#define MXC_INT_GPC2 74
3150
+#define MXC_INT_SRC 75
3151
+#define MXC_INT_NM 76
3152
+#define MXC_INT_PMU 77
3153
+#define MXC_INT_CTI_IRQ 78
3154
+#define MXC_INT_CTI1_TG0 79
3155
+#define MXC_INT_CTI1_TG1 80
3156
+#define MXC_INT_MCG_ERR 81
3157
+#define MXC_INT_MCG_TMR 82
3158
+#define MXC_INT_MCG_FUNC 83
3159
+#define MXC_INT_RESV84 84
3160
+#define MXC_INT_RESV85 85
3161
+#define MXC_INT_RESV86 86
3162
+#define MXC_INT_FEC 87
3163
+#define MXC_INT_OWIRE 88
3164
+#define MXC_INT_CTI1_TG2 89
3165
+#define MXC_INT_SJC 90
3166
+#define MXC_INT_SPDIF 91
3167
+#define MXC_INT_TVE 92
3168
+#define MXC_INT_FIRI 93
3169
+#define MXC_INT_PWM2 94
3170
+#define MXC_INT_SLIM_EXP 95
3171
+#define MXC_INT_SSI3 96
3172
+#define MXC_INT_RESV97 97
3173
+#define MXC_INT_CTI1_TG3 98
3174
+#define MXC_INT_SMC_RX 99
3175
+#define MXC_INT_VPU_IDLE 100
3176
+#define MXC_INT_RESV101 101
3177
+#define MXC_INT_GPU_IDLE 102
3178
+
3179
+#define MXC_MAX_INT_LINES 128
3180
+
3181
+#define MXC_GPIO_INT_BASE (MXC_MAX_INT_LINES)
3182
+
3183
+/*!
3184
+ * Number of GPIO port as defined in the IC Spec
3185
+ */
3186
+#define GPIO_PORT_NUM 4
3187
+/*!
3188
+ * Number of GPIO pins per port
3189
+ */
3190
+#define GPIO_NUM_PIN 32
3191
+
3192
+#define MXC_GPIO_SPLIT_IRQ_2
3193
+
3194
+#define IIM_SREV 0x24
3195
+#define ROM_SI_REV 0x48
3196
+
3197
+#define NFC_BUF_SIZE 0x1000
3198
+
3199
+/* WEIM registers */
3200
+#define CSGCR1 0x00
3201
+#define CSGCR2 0x04
3202
+#define CSRCR1 0x08
3203
+#define CSRCR2 0x0C
3204
+#define CSWCR1 0x10
3205
+
3206
+/* M4IF */
3207
+#define M4IF_FBPM0 0x40
3208
+#define M4IF_FIDBP 0x48
3209
+
3210
+/* ESDCTL */
3211
+#define ESDCTL_ESDCTL0 0x00
3212
+#define ESDCTL_ESDCFG0 0x04
3213
+#define ESDCTL_ESDCTL1 0x08
3214
+#define ESDCTL_ESDCFG1 0x0C
3215
+#define ESDCTL_ESDMISC 0x10
3216
+#define ESDCTL_ESDSCR 0x14
3217
+#define ESDCTL_ESDCDLY1 0x20
3218
+#define ESDCTL_ESDCDLY2 0x24
3219
+#define ESDCTL_ESDCDLY3 0x28
3220
+#define ESDCTL_ESDCDLY4 0x2C
3221
+#define ESDCTL_ESDCDLY5 0x30
3222
+#define ESDCTL_ESDCDLYGD 0x34
3223
+
3224
+/* CCM */
3225
+#define CLKCTL_CCR 0x00
3226
+#define CLKCTL_CCDR 0x04
3227
+#define CLKCTL_CSR 0x08
3228
+#define CLKCTL_CCSR 0x0C
3229
+#define CLKCTL_CACRR 0x10
3230
+#define CLKCTL_CBCDR 0x14
3231
+#define CLKCTL_CBCMR 0x18
3232
+#define CLKCTL_CSCMR1 0x1C
3233
+#define CLKCTL_CSCMR2 0x20
3234
+#define CLKCTL_CSCDR1 0x24
3235
+#define CLKCTL_CS1CDR 0x28
3236
+#define CLKCTL_CS2CDR 0x2C
3237
+#define CLKCTL_CDCDR 0x30
3238
+#define CLKCTL_CHSCCDR 0x34
3239
+#define CLKCTL_CSCDR2 0x38
3240
+#define CLKCTL_CSCDR3 0x3C
3241
+#define CLKCTL_CSCDR4 0x40
3242
+#define CLKCTL_CWDR 0x44
3243
+#define CLKCTL_CDHIPR 0x48
3244
+#define CLKCTL_CDCR 0x4C
3245
+#define CLKCTL_CTOR 0x50
3246
+#define CLKCTL_CLPCR 0x54
3247
+#define CLKCTL_CISR 0x58
3248
+#define CLKCTL_CIMR 0x5C
3249
+#define CLKCTL_CCOSR 0x60
3250
+#define CLKCTL_CGPR 0x64
3251
+#define CLKCTL_CCGR0 0x68
3252
+#define CLKCTL_CCGR1 0x6C
3253
+#define CLKCTL_CCGR2 0x70
3254
+#define CLKCTL_CCGR3 0x74
3255
+#define CLKCTL_CCGR4 0x78
3256
+#define CLKCTL_CCGR5 0x7C
3257
+#define CLKCTL_CMEOR 0x84
3258
+
3259
+/* DPLL */
3260
+#define PLL_DP_CTL 0x00
3261
+#define PLL_DP_CONFIG 0x04
3262
+#define PLL_DP_OP 0x08
3263
+#define PLL_DP_MFD 0x0C
3264
+#define PLL_DP_MFN 0x10
3265
+#define PLL_DP_MFNMINUS 0x14
3266
+#define PLL_DP_MFNPLUS 0x18
3267
+#define PLL_DP_HFS_OP 0x1C
3268
+#define PLL_DP_HFS_MFD 0x20
3269
+#define PLL_DP_HFS_MFN 0x24
3270
+#define PLL_DP_TOGC 0x28
3271
+#define PLL_DP_DESTAT 0x2C
3272
+
3273
+/* Assuming 24MHz input clock with doubler ON */
3274
+/* MFI PDF */
3275
+#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
3276
+#define DP_MFD_850 (48 - 1)
3277
+#define DP_MFN_850 41
3278
+
3279
+#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
3280
+#define DP_MFD_800 (3 - 1)
3281
+#define DP_MFN_800 1
3282
+
3283
+#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
3284
+#define DP_MFD_700 (24 - 1)
3285
+#define DP_MFN_700 7
3286
+
3287
+#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
3288
+#define DP_MFD_665 (96 - 1)
3289
+#define DP_MFN_665 89
3290
+
3291
+#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
3292
+#define DP_MFD_532 (24 - 1)
3293
+#define DP_MFN_532 13
3294
+
3295
+#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
3296
+#define DP_MFD_400 (3 - 1)
3297
+#define DP_MFN_400 1
3298
+
3299
+#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
3300
+#define DP_MFD_216 (4 - 1)
3301
+#define DP_MFN_216 3
3302
+
3303
+#define CHIP_REV_1_0 0x10
3304
+#define CHIP_REV_1_1 0x11
3305
+#define CHIP_REV_2_0 0x20
3306
+
3307
+#define BOARD_REV_1_0 0x0
3308
+#define BOARD_REV_2_0 0x1
3309
+
3310
+#ifndef __ASSEMBLER__
3311
+
3312
+enum mxc_clock {
3313
+MXC_ARM_CLK = 0,
3314
+MXC_AHB_CLK,
3315
+MXC_IPG_CLK,
3316
+MXC_IPG_PERCLK,
3317
+MXC_UART_CLK,
3318
+};
3319
+
3320
+/*!
3321
+ * NFMS bit in RCSR register for pagesize of nandflash
3322
+ */
3323
+#define NFMS (*((volatile u32 *)(CCM_BASE_ADDR+0x18)))
3324
+#define NFMS_BIT 8
3325
+#define NFMS_NF_DWIDTH 14
3326
+#define NFMS_NF_PG_SZ 8
3327
+
3328
+extern unsigned int mxc_get_clock(enum mxc_clock clk);
3329
+extern unsigned int get_board_rev(void);
3330
+extern int is_soc_rev(int rev);
3331
+
3332
+#endif /* __ASSEMBLER__*/
3333
+
3334
+#endif /* __ASM_ARCH_MXC_MX51_H__ */
3335
diff --git a/include/asm-arm/arch-mx51/mx51_pins.h b/include/asm-arm/arch-mx51/mx51_pins.h
3336
new file mode 100644
3337
index 0000000..63fdd8c
3338
--- /dev/null
3339
+++ b/include/asm-arm/arch-mx51/mx51_pins.h
3340
@@ -0,0 +1,370 @@
3341
+/*
3342
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3343
+ */
3344
+
3345
+/*
3346
+ * The code contained herein is licensed under the GNU General Public
3347
+ * License. You may obtain a copy of the GNU General Public License
3348
+ * Version 2 or later at the following locations:
3349
+ *
3350
+ * http://www.opensource.org/licenses/gpl-license.html
3351
+ * http://www.gnu.org/copyleft/gpl.html
3352
+ */
3353
+#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
3354
+#define __ASM_ARCH_MXC_MX51_PINS_H__
3355
+
3356
+/*!
3357
+ * @file arch-mxc/mx51_pins.h
3358
+ *
3359
+ * @brief MX51 I/O Pin List
3360
+ *
3361
+ * @ingroup GPIO_MX51
3362
+ */
3363
+
3364
+#ifndef __ASSEMBLY__
3365
+
3366
+/*!
3367
+ * @name IOMUX/PAD Bit field definitions
3368
+ */
3369
+
3370
+/*! @{ */
3371
+
3372
+/*!
3373
+ * In order to identify pins more effectively, each mux-controlled pin's
3374
+ * enumerated value is constructed in the following way:
3375
+ *
3376
+ * -------------------------------------------------------------------
3377
+ * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
3378
+ * -------------------------------------------------------------------
3379
+ * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
3380
+ * -------------------------------------------------------------------
3381
+ *
3382
+ * Bit 0 to 9 contains MUX_I used to identify the register
3383
+ * offset (0-based. base is IOMUX_module_base) defined in the Section
3384
+ * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
3385
+ * similar field definitions are used for the pad control register.
3386
+ * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
3387
+ * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
3388
+ * It means the mux control register is at register offset 0x28. The pad control
3389
+ * register offset is: 0x250 and also occupy the least significant bits
3390
+ * within the register.
3391
+ */
3392
+
3393
+/*!
3394
+ * Starting bit position within each entry of \b iomux_pins to represent the
3395
+ * MUX control register offset
3396
+ */
3397
+#define MUX_I 0
3398
+/*!
3399
+ * Starting bit position within each entry of \b iomux_pins to represent the
3400
+ * PAD control register offset
3401
+ */
3402
+#define PAD_I 10
3403
+/*!
3404
+ * Starting bit position within each entry of \b iomux_pins to represent which
3405
+ * mux mode is for GPIO (0-based)
3406
+ */
3407
+#define GPIO_I 21
3408
+
3409
+#define MUX_IO_P 29
3410
+#define MUX_IO_I 24
3411
+#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
3412
+ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
3413
+ ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
3414
+#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
3415
+#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
3416
+#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
3417
+
3418
+#define NON_GPIO_PORT 0x7
3419
+#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
3420
+#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
3421
+#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
3422
+
3423
+#define NON_MUX_I PIN_TO_MUX_MASK
3424
+#define MUX_I_START 0x001C
3425
+#define PAD_I_START 0x3F0
3426
+#define INPUT_CTL_START 0x8C4
3427
+#define INPUT_CTL_START_TO1 0x928
3428
+#define MUX_I_END (PAD_I_START - 4)
3429
+
3430
+#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
3431
+ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
3432
+ ((mi) << MUX_I) | \
3433
+ ((pi - PAD_I_START) << PAD_I) | \
3434
+ ((ga) << GPIO_I))
3435
+
3436
+#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
3437
+ _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
3438
+
3439
+#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
3440
+ _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
3441
+
3442
+#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
3443
+#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
3444
+#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
3445
+#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
3446
+
3447
+/*! @} End IOMUX/PAD Bit field definitions */
3448
+
3449
+/*!
3450
+ * This enumeration is constructed based on the Section
3451
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
3452
+ * value is constructed based on the rules described above.
3453
+ */
3454
+enum iomux_pins {
3455
+ MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
3456
+ MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
3457
+ MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
3458
+ MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
3459
+ MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
3460
+ MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
3461
+ MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
3462
+ MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
3463
+ MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
3464
+ MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
3465
+ MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
3466
+ MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
3467
+ MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
3468
+ MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
3469
+ MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
3470
+ MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
3471
+ MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
3472
+ MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
3473
+ MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
3474
+ MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
3475
+ MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
3476
+ MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
3477
+ MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
3478
+ MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
3479
+ MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
3480
+ MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
3481
+ MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
3482
+ MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
3483
+ MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
3484
+ MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
3485
+ MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
3486
+ MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
3487
+ MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
3488
+ MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
3489
+ MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
3490
+ MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
3491
+ MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
3492
+ MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
3493
+ MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
3494
+ MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
3495
+ MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
3496
+ MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
3497
+ MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
3498
+ MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
3499
+ MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
3500
+ MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
3501
+ MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
3502
+ MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
3503
+ MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
3504
+ MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
3505
+ MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
3506
+ MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
3507
+ MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
3508
+ MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
3509
+ MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
3510
+ MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
3511
+ MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
3512
+ MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
3513
+ MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
3514
+ MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
3515
+ MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
3516
+ MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
3517
+ MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
3518
+ MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
3519
+ MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
3520
+ MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
3521
+ MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
3522
+ MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
3523
+ MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
3524
+ MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
3525
+ MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
3526
+ MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
3527
+ MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
3528
+ MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
3529
+ MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
3530
+ MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
3531
+ MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
3532
+ MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
3533
+ MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
3534
+ MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
3535
+ MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
3536
+ MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
3537
+ MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
3538
+ MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
3539
+ MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
3540
+ MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
3541
+ MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
3542
+ MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
3543
+ MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
3544
+ MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
3545
+ MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
3546
+ MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
3547
+ MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
3548
+ MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
3549
+ MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
3550
+ MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
3551
+ MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
3552
+ MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
3553
+ MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
3554
+ MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
3555
+ MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
3556
+ MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
3557
+ MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
3558
+ MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
3559
+ MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
3560
+ MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
3561
+ MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
3562
+ MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
3563
+ MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
3564
+ MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
3565
+ MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
3566
+ MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
3567
+ MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
3568
+ MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
3569
+ MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
3570
+ MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
3571
+ MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
3572
+ MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
3573
+ MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
3574
+ MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
3575
+ MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
3576
+ MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
3577
+ MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
3578
+ MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
3579
+ MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
3580
+ MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
3581
+ MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
3582
+ MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
3583
+ MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
3584
+ MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
3585
+ MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
3586
+ MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
3587
+ MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
3588
+ MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
3589
+ MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
3590
+ MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
3591
+ MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
3592
+ MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
3593
+ MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
3594
+ MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
3595
+ MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
3596
+ MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
3597
+ MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
3598
+ MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
3599
+ MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
3600
+ MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
3601
+ MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
3602
+ MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
3603
+ MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
3604
+ MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
3605
+ MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
3606
+ MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
3607
+ MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
3608
+ MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
3609
+ MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
3610
+ MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
3611
+ MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
3612
+ MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
3613
+ MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
3614
+ MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
3615
+ MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
3616
+ MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
3617
+ MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
3618
+ MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
3619
+ MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
3620
+ MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
3621
+ MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
3622
+ MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
3623
+ MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
3624
+ MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
3625
+ MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
3626
+ MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
3627
+ MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
3628
+ MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
3629
+ MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
3630
+ MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
3631
+ MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
3632
+ MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
3633
+ MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
3634
+ MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
3635
+ MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
3636
+ MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
3637
+ MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
3638
+ MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
3639
+ MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
3640
+ MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
3641
+ MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
3642
+ MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
3643
+ MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
3644
+ MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
3645
+ MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
3646
+ MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
3647
+ MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
3648
+ MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
3649
+ MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
3650
+ MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
3651
+ MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
3652
+ MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
3653
+ MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
3654
+ MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
3655
+ MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
3656
+ MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
3657
+ MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
3658
+ MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
3659
+ MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
3660
+ MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
3661
+ MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
3662
+ MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
3663
+ MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
3664
+ MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
3665
+ MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
3666
+ MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
3667
+ MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
3668
+ MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
3669
+ MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
3670
+ MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
3671
+ MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
3672
+ MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
3673
+ MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
3674
+ MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
3675
+ MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
3676
+ MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
3677
+ MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
3678
+ MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
3679
+ MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
3680
+ MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
3681
+ MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
3682
+ MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
3683
+ MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
3684
+ MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
3685
+ MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
3686
+ MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
3687
+ MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
3688
+ MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
3689
+ MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
3690
+ MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
3691
+ MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
3692
+ MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
3693
+ MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
3694
+ MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
3695
+ MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
3696
+ MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
3697
+ MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
3698
+ MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
3699
+ MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
3700
+ MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
3701
+ MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
3702
+ MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
3703
+ MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
3704
+ MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
3705
+ MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
3706
+ MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
3707
+};
3708
+
3709
+#endif /* __ASSEMBLY__ */
3710
+#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */
3711
diff --git a/include/asm-arm/arch-mx51/mxc_nand.h b/include/asm-arm/arch-mx51/mxc_nand.h
3712
new file mode 100644
3713
index 0000000..aad93d1
3714
--- /dev/null
3715
+++ b/include/asm-arm/arch-mx51/mxc_nand.h
3716
@@ -0,0 +1,198 @@
3717
+/*
3718
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3719
+ */
3720
+
3721
+/*
3722
+ * The code contained herein is licensed under the GNU General Public
3723
+ * License. You may obtain a copy of the GNU General Public License
3724
+ * Version 2 or later at the following locations:
3725
+ *
3726
+ * http://www.opensource.org/licenses/gpl-license.html
3727
+ * http://www.gnu.org/copyleft/gpl.html
3728
+ */
3729
+
3730
+/*!
3731
+ * @file mxc_nd2.h
3732
+ *
3733
+ * @brief This file contains the NAND Flash Controller register information.
3734
+ *
3735
+ *
3736
+ * @ingroup NAND_MTD
3737
+ */
3738
+
3739
+#ifndef __MXC_NAND_H__
3740
+#define __MXC_NAND_H__
3741
+
3742
+#include <asm/arch/mx51.h>
3743
+
3744
+#define IS_2K_PAGE_NAND ((mtd->oobblock / info->num_of_intlv) \
3745
+ == NAND_PAGESIZE_2KB)
3746
+#define IS_4K_PAGE_NAND ((mtd->oobblock / info->num_of_intlv) \
3747
+ == NAND_PAGESIZE_4KB)
3748
+#define IS_LARGE_PAGE_NAND ((mtd->oobblock / info->num_of_intlv) > 512)
3749
+
3750
+#define NAND_PAGESIZE_2KB 2048
3751
+#define NAND_PAGESIZE_4KB 4096
3752
+#define NAND_MAX_PAGESIZE 4096
3753
+
3754
+/*
3755
+ * Addresses for NFC registers
3756
+ */
3757
+#define NFC_REG_BASE (NFC_BASE_ADDR + 0x1000)
3758
+#define NFC_BUF_ADDR (NFC_REG_BASE + 0xE04)
3759
+#define NFC_FLASH_ADDR (NFC_REG_BASE + 0xE06)
3760
+#define NFC_FLASH_CMD (NFC_REG_BASE + 0xE08)
3761
+#define NFC_CONFIG (NFC_REG_BASE + 0xE0A)
3762
+#define NFC_ECC_STATUS_RESULT (NFC_REG_BASE + 0xE0C)
3763
+#define NFC_SPAS (NFC_REG_BASE + 0xE10)
3764
+#define NFC_WRPROT (NFC_REG_BASE + 0xE12)
3765
+#define NFC_UNLOCKSTART_BLKADDR (NFC_REG_BASE + 0xE20)
3766
+#define NFC_UNLOCKEND_BLKADDR (NFC_REG_BASE + 0xE22)
3767
+#define NFC_CONFIG1 (NFC_REG_BASE + 0xE1A)
3768
+#define NFC_CONFIG2 (NFC_REG_BASE + 0xE1C)
3769
+
3770
+/*!
3771
+ * Addresses for NFC RAM BUFFER Main area 0
3772
+ */
3773
+#define MAIN_AREA0 (u16 *)(NFC_BASE_ADDR + 0x000)
3774
+#define MAIN_AREA1 (u16 *)(NFC_BASE_ADDR + 0x200)
3775
+
3776
+/*!
3777
+ * Addresses for NFC SPARE BUFFER Spare area 0
3778
+ */
3779
+#define SPARE_AREA0 (u16 *)(NFC_BASE_ADDR + 0x1000)
3780
+#define SPARE_LEN 64
3781
+#define SPARE_COUNT 8
3782
+#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT)
3783
+
3784
+
3785
+#define SPAS_SHIFT (0)
3786
+#define SPAS_MASK (0xFF00)
3787
+#define IS_4BIT_ECC \
3788
+ ((raw_read(REG_NFC_ECC_MODE) & NFC_ECC_MODE_4) >> 0)
3789
+
3790
+#define NFC_SET_SPAS(v) \
3791
+ raw_write(((raw_read(REG_NFC_SPAS) & SPAS_MASK) | \
3792
+ ((v<<SPAS_SHIFT))), \
3793
+ REG_NFC_SPAS)
3794
+
3795
+#define NFC_SET_ECC_MODE(v) \
3796
+do { \
3797
+ if ((v) == NFC_SPAS_218) { \
3798
+ raw_write((raw_read(REG_NFC_ECC_MODE) & \
3799
+ NFC_ECC_MODE_8), \
3800
+ REG_NFC_ECC_MODE); \
3801
+ } else { \
3802
+ raw_write((raw_read(REG_NFC_ECC_MODE) | \
3803
+ NFC_ECC_MODE_4), \
3804
+ REG_NFC_ECC_MODE); \
3805
+ } \
3806
+} while (0)
3807
+
3808
+#define GET_ECC_STATUS() \
3809
+ __raw_readl(REG_NFC_ECC_STATUS_RESULT);
3810
+
3811
+#define NFC_SET_NFMS(v) \
3812
+do { \
3813
+ (NFMS |= (v)); \
3814
+ if (((v) & (1 << NFMS_NF_PG_SZ))) { \
3815
+ if (IS_2K_PAGE_NAND) { \
3816
+ NFC_SET_SPAS(NFC_SPAS_64); \
3817
+ } else if (IS_4K_PAGE_NAND) { \
3818
+ NFC_SET_SPAS(NFC_SPAS_128); \
3819
+ } else { \
3820
+ NFC_SET_SPAS(NFC_SPAS_16); \
3821
+ } \
3822
+ NFC_SET_ECC_MODE(NFC_SPAS_128); \
3823
+ } \
3824
+} while (0)
3825
+
3826
+
3827
+#define WRITE_NFC_IP_REG(val, reg) \
3828
+ raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \
3829
+ REG_NFC_OPS_STAT)
3830
+
3831
+#define GET_NFC_ECC_STATUS() \
3832
+ raw_read(REG_NFC_ECC_STATUS_RESULT);
3833
+
3834
+/*!
3835
+ * Set INT to 0, Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC
3836
+ * Register for Specific operation
3837
+ */
3838
+#define NFC_CMD 0x1
3839
+#define NFC_ADDR 0x2
3840
+#define NFC_INPUT 0x4
3841
+#define NFC_OUTPUT 0x8
3842
+#define NFC_ID 0x10
3843
+#define NFC_STATUS 0x20
3844
+
3845
+/* Bit Definitions */
3846
+#define NFC_OPS_STAT (1 << 15)
3847
+#define NFC_SP_EN (1 << 2)
3848
+#define NFC_ECC_EN (1 << 3)
3849
+#define NFC_INT_MSK (1 << 4)
3850
+#define NFC_BIG (1 << 5)
3851
+#define NFC_RST (1 << 6)
3852
+#define NFC_CE (1 << 7)
3853
+#define NFC_ONE_CYCLE (1 << 8)
3854
+#define NFC_BLS_LOCKED 0
3855
+#define NFC_BLS_LOCKED_DEFAULT 1
3856
+#define NFC_BLS_UNLCOKED 2
3857
+#define NFC_WPC_LOCK_TIGHT 1
3858
+#define NFC_WPC_LOCK (1 << 1)
3859
+#define NFC_WPC_UNLOCK (1 << 2)
3860
+#define NFC_FLASH_ADDR_SHIFT 0
3861
+#define NFC_UNLOCK_END_ADDR_SHIFT 0
3862
+
3863
+#define NFC_ECC_MODE_4 (1<<0)
3864
+#define NFC_ECC_MODE_8 (~(1<<0))
3865
+#define NFC_SPAS_16 8
3866
+#define NFC_SPAS_64 32
3867
+#define NFC_SPAS_128 64
3868
+#define NFC_SPAS_218 109
3869
+
3870
+/* NFC Register Mapping */
3871
+#define REG_NFC_OPS_STAT NFC_CONFIG2
3872
+#define REG_NFC_INTRRUPT NFC_CONFIG1
3873
+#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR
3874
+#define REG_NFC_FLASH_CMD NFC_FLASH_CMD
3875
+#define REG_NFC_OPS NFC_CONFIG2
3876
+#define REG_NFC_SET_RBA NFC_BUF_ADDR
3877
+#define REG_NFC_ECC_EN NFC_CONFIG1
3878
+#define REG_NFC_ECC_STATUS_RESULT NFC_ECC_STATUS_RESULT
3879
+#define REG_NFC_CE NFC_CONFIG1
3880
+#define REG_NFC_SP_EN NFC_CONFIG1
3881
+#define REG_NFC_BLS NFC_CONFIG
3882
+#define REG_NFC_WPC NFC_WRPROT
3883
+#define REG_START_BLKADDR NFC_UNLOCKSTART_BLKADDR
3884
+#define REG_END_BLKADDR NFC_UNLOCKEND_BLKADDR
3885
+#define REG_NFC_RST NFC_CONFIG1
3886
+#define REG_NFC_ECC_MODE NFC_CONFIG1
3887
+#define REG_NFC_SPAS NFC_SPAS
3888
+
3889
+
3890
+/* NFC V1/V2 Specific MACRO functions definitions */
3891
+
3892
+#define raw_write(v, a) __raw_writew(v, a)
3893
+#define raw_read(a) __raw_readw(a)
3894
+
3895
+#define NFC_SET_BLS(val) val
3896
+
3897
+#define UNLOCK_ADDR(start_addr, end_addr) \
3898
+{ \
3899
+ raw_write(start_addr, REG_START_BLKADDR); \
3900
+ raw_write(end_addr, REG_END_BLKADDR); \
3901
+}
3902
+
3903
+#define NFC_SET_NFC_ACTIVE_CS(val)
3904
+#define NFC_SET_WPC(val) val
3905
+
3906
+/* NULL Definitions */
3907
+#define ACK_OPS
3908
+#define NFC_SET_RBA(val) raw_write(val, REG_NFC_SET_RBA);
3909
+
3910
+#define READ_PAGE() send_read_page(0)
3911
+#define PROG_PAGE() send_prog_page(0)
3912
+#define CHECK_NFC_RB 1
3913
+
3914
+#endif /* __MXC_NAND_H__ */
3915
diff --git a/include/configs/mx51_3stack.h b/include/configs/mx51_3stack.h
3916
new file mode 100644
3917
index 0000000..ae91982
3918
--- /dev/null
3919
+++ b/include/configs/mx51_3stack.h
3920
@@ -0,0 +1,191 @@
3921
+/*
3922
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3923
+ *
3924
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
3925
+ *
3926
+ * Configuration settings for the MX31ADS Freescale board.
3927
+ *
3928
+ * This program is free software; you can redistribute it and/or
3929
+ * modify it under the terms of the GNU General Public License as
3930
+ * published by the Free Software Foundation; either version 2 of
3931
+ * the License, or (at your option) any later version.
3932
+ *
3933
+ * This program is distributed in the hope that it will be useful,
3934
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3935
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3936
+ * GNU General Public License for more details.
3937
+ *
3938
+ * You should have received a copy of the GNU General Public License
3939
+ * along with this program; if not, write to the Free Software
3940
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3941
+ * MA 02111-1307 USA
3942
+ */
3943
+
3944
+#ifndef __CONFIG_H
3945
+#define __CONFIG_H
3946
+
3947
+#include <asm/arch/mx51.h>
3948
+
3949
+ /* High Level Configuration Options */
3950
+#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
3951
+#define CONFIG_SYS_APCS_GNU
3952
+#define CONFIG_L2_OFF
3953
+
3954
+#define CONFIG_MXC 1
3955
+#define CONFIG_MX51 1 /* in a mx51 */
3956
+#define CONFIG_FLASH_HEADER 1
3957
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
3958
+#define CONFIG_FLASH_HEADER_BARKER 0xB1
3959
+
3960
+#define CONFIG_SKIP_RELOCATE_UBOOT
3961
+
3962
+#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
3963
+#define CONFIG_MX51_CLK32 32768
3964
+#define CONFIG_DISPLAY_CPUINFO
3965
+#define CONFIG_DISPLAY_BOARDINFO
3966
+
3967
+#define BOARD_LATE_INIT
3968
+/*
3969
+ * Disabled for now due to build problems under Debian and a significant
3970
+ * increase in the final file size: 144260 vs. 109536 Bytes.
3971
+ */
3972
+
3973
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
3974
+#define CONFIG_REVISION_TAG 1
3975
+#define CONFIG_SETUP_MEMORY_TAGS 1
3976
+#define CONFIG_INITRD_TAG 1
3977
+
3978
+/*
3979
+ * Size of malloc() pool
3980
+ */
3981
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
3982
+/* size in bytes reserved for initial data */
3983
+#define CONFIG_SYS_GBL_DATA_SIZE 128
3984
+
3985
+/*
3986
+ * Hardware drivers
3987
+ */
3988
+#define CONFIG_MX51_UART 1
3989
+#define CONFIG_MX51_UART1 1
3990
+
3991
+/* allow to overwrite serial and ethaddr */
3992
+#define CONFIG_ENV_OVERWRITE
3993
+#define CONFIG_CONS_INDEX 1
3994
+#define CONFIG_BAUDRATE 115200
3995
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
3996
+
3997
+/***********************************************************
3998
+ * Command definition
3999
+ ***********************************************************/
4000
+
4001
+#include <config_cmd_default.h>
4002
+
4003
+#define CONFIG_CMD_PING
4004
+#define CONFIG_CMD_DHCP
4005
+/* Enable below configure when supporting nand */
4006
+/* #define CONFIG_CMD_NAND */
4007
+#undef CONFIG_CMD_IMLS
4008
+
4009
+#define CONFIG_BOOTDELAY 3
4010
+
4011
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
4012
+
4013
+#define CONFIG_EXTRA_ENV_SETTINGS \
4014
+ "netdev=eth0\0" \
4015
+ "ethprime=smc911x\0" \
4016
+ "uboot_addr=0xa0000000\0" \
4017
+ "uboot=u-boot.bin\0" \
4018
+ "kernel=uImage\0" \
4019
+ "nfsroot=/opt/eldk/arm\0" \
4020
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
4021
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
4022
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
4023
+ "bootcmd=run bootcmd_net\0" \
4024
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
4025
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
4026
+ "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
4027
+ "protect off ${uboot_addr} 0xa003ffff; " \
4028
+ "erase ${uboot_addr} 0xa003ffff; " \
4029
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
4030
+ "setenv filesize; saveenv\0"
4031
+
4032
+/*Support LAN9217*/
4033
+#define CONFIG_DRIVER_SMC911X 1
4034
+#define CONFIG_DRIVER_SMC911X_16_BIT 1
4035
+#define CONFIG_DRIVER_SMC911X_BASE_VARIABLE mx51_io_base_addr
4036
+
4037
+/*
4038
+ * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
4039
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
4040
+ * controller inverted. The controller is capable of detecting and correcting
4041
+ * this, but it needs 4 network packets for that. Which means, at startup, you
4042
+ * will not receive answers to the first 4 packest, unless there have been some
4043
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
4044
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
4045
+ * transfer, should the user wish one, significantly.
4046
+ */
4047
+#define CONFIG_ARP_TIMEOUT 200UL
4048
+
4049
+/*
4050
+ * Miscellaneous configurable options
4051
+ */
4052
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
4053
+#define CONFIG_SYS_PROMPT "=> "
4054
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
4055
+/* Print Buffer Size */
4056
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
4057
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
4058
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
4059
+
4060
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
4061
+#define CONFIG_SYS_MEMTEST_END 0x10000
4062
+
4063
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
4064
+
4065
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
4066
+
4067
+#define CONFIG_SYS_HZ CONFIG_MX51_CLK32/* use 32kHz clock as source */
4068
+
4069
+#define CONFIG_CMDLINE_EDITING 1
4070
+
4071
+/*-----------------------------------------------------------------------
4072
+ * Stack sizes
4073
+ *
4074
+ * The stack sizes are set up in start.S using the settings below
4075
+ */
4076
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
4077
+
4078
+/*-----------------------------------------------------------------------
4079
+ * Physical Memory Map
4080
+ */
4081
+#define CONFIG_NR_DRAM_BANKS 1
4082
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
4083
+/* TO1 boards */
4084
+/* #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) */
4085
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
4086
+
4087
+/*-----------------------------------------------------------------------
4088
+ * FLASH and environment organization
4089
+ */
4090
+#define CONFIG_SYS_NO_FLASH
4091
+
4092
+/*-----------------------------------------------------------------------
4093
+ * NAND FLASH driver setup
4094
+ */
4095
+#define NAND_MAX_CHIPS 1
4096
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
4097
+#define CONFIG_SYS_NAND_BASE 0x40000000
4098
+
4099
+/* Monitor at beginning of flash */
4100
+#define CONFIG_ENV_IS_NOWHERE 1
4101
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
4102
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
4103
+/* #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE) */
4104
+#define CONFIG_ENV_OFFSET 0x40000
4105
+/*
4106
+ * JFFS2 partitions
4107
+ */
4108
+#undef CONFIG_JFFS2_CMDLINE
4109
+#define CONFIG_JFFS2_DEV "nand0"
4110
+
4111
+#endif /* __CONFIG_H */
4112
--
4113
1.5.4.4
4114
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