1
//===- TableGen'erated file -------------------------------------*- C++ -*-===//
3
// Assembly Writer Source Fragment
5
// Automatically generated file, do not edit!
7
//===----------------------------------------------------------------------===//
9
/// printInstruction - This method is automatically generated by tablegen
10
/// from the instruction set description.
11
void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
12
static const unsigned OpInfo[] = {
23
0U, // COPY_TO_REGCLASS
42
541065286U, // ADJCALLSTACKDOWN
43
545259590U, // ADJCALLSTACKUP
49
268447826U, // ANDISo8
52
549453894U, // ATOMIC_CMP_SWAP_I16
53
553648198U, // ATOMIC_CMP_SWAP_I32
54
557842502U, // ATOMIC_CMP_SWAP_I64
55
562036806U, // ATOMIC_CMP_SWAP_I8
56
566231110U, // ATOMIC_LOAD_ADD_I16
57
570425414U, // ATOMIC_LOAD_ADD_I32
58
574619718U, // ATOMIC_LOAD_ADD_I64
59
578814022U, // ATOMIC_LOAD_ADD_I8
60
583008326U, // ATOMIC_LOAD_AND_I16
61
587202630U, // ATOMIC_LOAD_AND_I32
62
591396934U, // ATOMIC_LOAD_AND_I64
63
595591238U, // ATOMIC_LOAD_AND_I8
64
599785542U, // ATOMIC_LOAD_NAND_I16
65
603979846U, // ATOMIC_LOAD_NAND_I32
66
608174150U, // ATOMIC_LOAD_NAND_I64
67
612368454U, // ATOMIC_LOAD_NAND_I8
68
616562758U, // ATOMIC_LOAD_OR_I16
69
620757062U, // ATOMIC_LOAD_OR_I32
70
624951366U, // ATOMIC_LOAD_OR_I64
71
629145670U, // ATOMIC_LOAD_OR_I8
72
633339974U, // ATOMIC_LOAD_SUB_I16
73
637534278U, // ATOMIC_LOAD_SUB_I32
74
641728582U, // ATOMIC_LOAD_SUB_I64
75
645922886U, // ATOMIC_LOAD_SUB_I8
76
650117190U, // ATOMIC_LOAD_XOR_I16
77
654311494U, // ATOMIC_LOAD_XOR_I32
78
658505798U, // ATOMIC_LOAD_XOR_I64
79
662700102U, // ATOMIC_LOAD_XOR_I8
80
666894406U, // ATOMIC_SWAP_I16
81
671088710U, // ATOMIC_SWAP_I32
82
675283014U, // ATOMIC_SWAP_I64
83
679477318U, // ATOMIC_SWAP_I8
87
107U, // BCTRL8_Darwin
91
1493172337U, // BL8_Darwin
92
1493172337U, // BL8_ELF
93
1761607797U, // BLA8_Darwin
94
1761607797U, // BLA8_ELF
95
1761607797U, // BLA_Darwin
96
1761607797U, // BLA_SVR4
98
1493172337U, // BL_Darwin
99
1493172337U, // BL_SVR4
103
268447886U, // CMPLDI
105
268447901U, // CMPLWI
108
268468402U, // CNTLZD
109
268468410U, // CNTLZW
116
1879048417U, // DCBST
118
1879048430U, // DCBTST
120
1879048444U, // DCBZL
128
2415919401U, // DST64
129
2415919406U, // DSTST
130
2415919406U, // DSTST64
131
2415919413U, // DSTSTT
132
2415919413U, // DSTSTT64
134
2415919421U, // DSTT64
135
696254534U, // DYNALLOC
136
700448838U, // DYNALLOC8
140
268468552U, // EXTSB8
142
268468559U, // EXTSH8
144
268468566U, // EXTSW_32
145
268468566U, // EXTSW_32_64
150
268435811U, // FADDrtz
152
268435831U, // FCMPUD
153
268435831U, // FCMPUS
154
268468606U, // FCTIDZ
155
268468614U, // FCTIWZ
159
268435874U, // FMADDS
163
268435894U, // FMSUBS
166
268468683U, // FNABSD
167
268468683U, // FNABSS
170
268435928U, // FNMADD
171
268435936U, // FNMADDS
172
268435945U, // FNMSUB
173
268435953U, // FNMSUBS
178
268468749U, // FSQRTS
192
436208204U, // LDinto_toc
194
597U, // LDtoc_restore
238
419431179U, // MFCTR8
242
271581957U, // MFOCRF
243
440402718U, // MFVRSAVE
244
419431205U, // MFVSCR
245
2684355373U, // MTCRF
247
419431220U, // MTCTR8
248
2952790843U, // MTFSB0
249
2952790851U, // MTFSB1
250
3397387083U, // MTFSF
253
419431256U, // MTVRSAVE
254
419431268U, // MTVSCR
256
268436339U, // MULHDU
258
268436354U, // MULHWU
262
3489661041U, // MovePCtoLR
263
3489661041U, // MovePCtoLR8
272
268436403U, // OR4To8
274
268436403U, // OR8To4
282
268452814U, // RLDICL
283
268452822U, // RLDICR
284
271975390U, // RLDIMI
285
272008166U, // RLWIMI
286
268456942U, // RLWINM
287
268456950U, // RLWINMo
289
717226054U, // SELECT_CC_F4
290
717226054U, // SELECT_CC_F8
291
717226054U, // SELECT_CC_I4
292
717226054U, // SELECT_CC_I8
293
717226054U, // SELECT_CC_VRRC
296
721420358U, // SPILL_CR
306
3409970233U, // STBU8
314
270009439U, // STDX_32
315
270271557U, // STD_32
317
3409970283U, // STFDU
319
270009465U, // STFIWX
321
3409970311U, // STFSU
325
270009498U, // STHBRX
327
3409970338U, // STHU8
330
270009518U, // STVEBX
331
270009526U, // STVEHX
332
270009534U, // STVEWX
337
270009560U, // STWBRX
346
268436737U, // SUBFC8
348
268436744U, // SUBFE8
349
268440847U, // SUBFIC
350
268440847U, // SUBFIC8
351
268469527U, // SUBFME
352
268469527U, // SUBFME8
353
268469535U, // SUBFZE
354
268469535U, // SUBFZE8
356
1493172321U, // TAILB
357
1493172321U, // TAILB8
358
1761609004U, // TAILBA
359
1761609004U, // TAILBA8
362
1757447472U, // TCRETURNai
363
1757447485U, // TCRETURNai8
364
1489012043U, // TCRETURNdi
365
1489012056U, // TCRETURNdi8
366
415270246U, // TCRETURNri
367
415270259U, // TCRETURNri8
369
268469638U, // UPDATE_VRSAVE
370
268436885U, // VADDCUW
371
268436894U, // VADDFP
372
268436902U, // VADDSBS
373
268436911U, // VADDSHS
374
268436920U, // VADDSWS
375
268436929U, // VADDUBM
376
268436938U, // VADDUBS
377
268436947U, // VADDUHM
378
268436956U, // VADDUHS
379
268436965U, // VADDUWM
380
268436974U, // VADDUWS
383
268436996U, // VAVGSB
384
268437004U, // VAVGSH
385
268437012U, // VAVGSW
386
268437020U, // VAVGUB
387
268437028U, // VAVGUH
388
268437036U, // VAVGUW
391
268437058U, // VCMPBFP
392
268437067U, // VCMPBFPo
393
268437077U, // VCMPEQFP
394
268437087U, // VCMPEQFPo
395
268437098U, // VCMPEQUB
396
268437108U, // VCMPEQUBo
397
268437119U, // VCMPEQUH
398
268437129U, // VCMPEQUHo
399
268437140U, // VCMPEQUW
400
268437150U, // VCMPEQUWo
401
268437161U, // VCMPGEFP
402
268437171U, // VCMPGEFPo
403
268437182U, // VCMPGTFP
404
268437192U, // VCMPGTFPo
405
268437203U, // VCMPGTSB
406
268437213U, // VCMPGTSBo
407
268437224U, // VCMPGTSH
408
268437234U, // VCMPGTSHo
409
268437245U, // VCMPGTSW
410
268437255U, // VCMPGTSWo
411
268437266U, // VCMPGTUB
412
268437276U, // VCMPGTUBo
413
268437287U, // VCMPGTUH
414
268437297U, // VCMPGTUHo
415
268437308U, // VCMPGTUW
416
268437318U, // VCMPGTUWo
417
272041809U, // VCTSXS
418
272041817U, // VCTUXS
419
268470113U, // VEXPTEFP
420
268470123U, // VLOGEFP
421
268437364U, // VMADDFP
422
268437373U, // VMAXFP
423
268437381U, // VMAXSB
424
268437389U, // VMAXSH
425
268437397U, // VMAXSW
426
268437405U, // VMAXUB
427
268437413U, // VMAXUH
428
268437421U, // VMAXUW
429
268437429U, // VMHADDSHS
430
268437440U, // VMHRADDSHS
431
268437452U, // VMINFP
432
268437460U, // VMINSB
433
268437468U, // VMINSH
434
268437476U, // VMINSW
435
268437484U, // VMINUB
436
268437492U, // VMINUH
437
268437500U, // VMINUW
438
268437508U, // VMLADDUHM
439
268437519U, // VMRGHB
440
268437527U, // VMRGHH
441
268437535U, // VMRGHW
442
268437543U, // VMRGLB
443
268437551U, // VMRGLH
444
268437559U, // VMRGLW
445
268437567U, // VMSUMMBM
446
268437577U, // VMSUMSHM
447
268437587U, // VMSUMSHS
448
268437597U, // VMSUMUBM
449
268437607U, // VMSUMUHM
450
268437617U, // VMSUMUHS
451
268437627U, // VMULESB
452
268437636U, // VMULESH
453
268437645U, // VMULEUB
454
268437654U, // VMULEUH
455
268437663U, // VMULOSB
456
268437672U, // VMULOSH
457
268437681U, // VMULOUB
458
268437690U, // VMULOUH
459
268437699U, // VNMSUBFP
464
268437734U, // VPKSHSS
465
268437743U, // VPKSHUS
466
268437752U, // VPKSWSS
467
268437761U, // VPKSWUS
468
268437770U, // VPKUHUM
469
268437779U, // VPKUHUS
470
268437788U, // VPKUWUM
471
268437797U, // VPKUWUS
480
268470627U, // VRSQRTEFP
484
268437887U, // VSLDOI
488
272042393U, // VSPLTB
489
272042401U, // VSPLTH
490
272107945U, // VSPLTISB
491
272107955U, // VSPLTISH
492
272107965U, // VSPLTISW
493
272042439U, // VSPLTW
502
268438017U, // VSUBCUW
503
268438026U, // VSUBFP
504
268438034U, // VSUBSBS
505
268438043U, // VSUBSHS
506
268438052U, // VSUBSWS
507
268438061U, // VSUBUBM
508
268438070U, // VSUBUBS
509
268438079U, // VSUBUHM
510
268438088U, // VSUBUHS
511
268438097U, // VSUBUWM
512
268438106U, // VSUBUWS
513
268438115U, // VSUM2SWS
514
268438125U, // VSUM4SBS
515
268438135U, // VSUM4SHS
516
268438145U, // VSUM4UBS
517
268438155U, // VSUMSWS
518
268470932U, // VUPKHPX
519
268470941U, // VUPKHSB
520
268470950U, // VUPKHSH
521
268470959U, // VUPKLPX
522
268470968U, // VUPKLSB
523
268470977U, // VUPKLSH
525
268962506U, // V_SET0
531
268450523U, // XORIS8
535
const char *AsmStrs =
536
"DBG_VALUE\000add \000addc \000adde \000addi \000addic \000addic. \000ad"
537
"dis \000addme \000addze \000\000and \000andc \000andis. \000andi. \000b"
538
" \000b\000bctr\000bctrl\000bl \000bla \000cmpd \000cmpdi \000cmpld \000"
539
"cmpldi \000cmplw \000cmplwi \000cmpw \000cmpwi \000cntlzd \000cntlzw \000"
540
"creqv \000cror \000dcba \000dcbf \000dcbi \000dcbst \000dcbt \000dcbtst"
541
" \000dcbz \000dcbzl \000divd \000divdu \000divw \000divwu \000dss \000d"
542
"ssall\000dst \000dstst \000dststt \000dstt \000eqv \000extsb \000extsh "
543
"\000extsw \000fabs \000fadd \000fadds \000fcfid \000fcmpu \000fctidz \000"
544
"fctiwz \000fdiv \000fdivs \000fmadd \000fmadds \000fmr \000fmsub \000fm"
545
"subs \000fmul \000fmuls \000fnabs \000fneg \000fnmadd \000fnmadds \000f"
546
"nmsub \000fnmsubs \000frsp \000fsel \000fsqrt \000fsqrts \000fsub \000f"
547
"subs \000la \000lbz \000lbzu \000lbzx \000ld \000ldarx \000ldu \000ldx "
548
"\000ld 2, 8(\000ld 2, 40(1)\000lfd \000lfdx \000lfs \000lfsx \000lha \000"
549
"lhau \000lhax \000lhbrx \000lhz \000lhzu \000lhzx \000li \000lis \000lv"
550
"ebx \000lvehx \000lvewx \000lvsl \000lvsr \000lvx \000lvxl \000lwa \000"
551
"lwarx \000lwax \000lwbrx \000lwz \000lwzu \000lwzx \000mcrf \000mfcr \000"
552
"mfctr \000mffs \000mflr \000mfspr \000mfvscr \000mtcrf \000mtctr \000mt"
553
"fsb0 \000mtfsb1 \000mtfsf \000mtlr \000mtspr 256, \000mtvscr \000mulhd "
554
"\000mulhdu \000mulhw \000mulhwu \000mulld \000mulli \000mullw \000nand "
555
"\000neg \000nop\000nor \000or \000orc \000ori \000oris \000rldcl \000rl"
556
"dicl \000rldicr \000rldimi \000rlwimi \000rlwinm \000rlwinm. \000rlwnm "
557
"\000sld \000slw \000srad \000sradi \000sraw \000srawi \000srd \000srw \000"
558
"stb \000stbu \000stbx \000std \000stdcx. \000stdu \000stdux \000stdx \000"
559
"stfd \000stfdu \000stfdx \000stfiwx \000stfs \000stfsu \000stfsx \000st"
560
"h \000sthbrx \000sthu \000sthx \000stvebx \000stvehx \000stvewx \000stv"
561
"x \000stvxl \000stw \000stwbrx \000stwcx. \000stwu \000stwux \000stwx \000"
562
"subf \000subfc \000subfe \000subfic \000subfme \000subfze \000sync\000b"
563
"a \000#TC_RETURNa \000#TC_RETURNa8 \000#TC_RETURNd \000#TC_RETURNd8 \000"
564
"#TC_RETURNr \000#TC_RETURNr8 \000trap\000UPDATE_VRSAVE \000vaddcuw \000"
565
"vaddfp \000vaddsbs \000vaddshs \000vaddsws \000vaddubm \000vaddubs \000"
566
"vadduhm \000vadduhs \000vadduwm \000vadduws \000vand \000vandc \000vavg"
567
"sb \000vavgsh \000vavgsw \000vavgub \000vavguh \000vavguw \000vcfsx \000"
568
"vcfux \000vcmpbfp \000vcmpbfp. \000vcmpeqfp \000vcmpeqfp. \000vcmpequb "
569
"\000vcmpequb. \000vcmpequh \000vcmpequh. \000vcmpequw \000vcmpequw. \000"
570
"vcmpgefp \000vcmpgefp. \000vcmpgtfp \000vcmpgtfp. \000vcmpgtsb \000vcmp"
571
"gtsb. \000vcmpgtsh \000vcmpgtsh. \000vcmpgtsw \000vcmpgtsw. \000vcmpgtu"
572
"b \000vcmpgtub. \000vcmpgtuh \000vcmpgtuh. \000vcmpgtuw \000vcmpgtuw. \000"
573
"vctsxs \000vctuxs \000vexptefp \000vlogefp \000vmaddfp \000vmaxfp \000v"
574
"maxsb \000vmaxsh \000vmaxsw \000vmaxub \000vmaxuh \000vmaxuw \000vmhadd"
575
"shs \000vmhraddshs \000vminfp \000vminsb \000vminsh \000vminsw \000vmin"
576
"ub \000vminuh \000vminuw \000vmladduhm \000vmrghb \000vmrghh \000vmrghw"
577
" \000vmrglb \000vmrglh \000vmrglw \000vmsummbm \000vmsumshm \000vmsumsh"
578
"s \000vmsumubm \000vmsumuhm \000vmsumuhs \000vmulesb \000vmulesh \000vm"
579
"uleub \000vmuleuh \000vmulosb \000vmulosh \000vmuloub \000vmulouh \000v"
580
"nmsubfp \000vnor \000vor \000vperm \000vpkpx \000vpkshss \000vpkshus \000"
581
"vpkswss \000vpkswus \000vpkuhum \000vpkuhus \000vpkuwum \000vpkuwus \000"
582
"vrefp \000vrfim \000vrfin \000vrfip \000vrfiz \000vrlb \000vrlh \000vrl"
583
"w \000vrsqrtefp \000vsel \000vsl \000vslb \000vsldoi \000vslh \000vslo "
584
"\000vslw \000vspltb \000vsplth \000vspltisb \000vspltish \000vspltisw \000"
585
"vspltw \000vsr \000vsrab \000vsrah \000vsraw \000vsrb \000vsrh \000vsro"
586
" \000vsrw \000vsubcuw \000vsubfp \000vsubsbs \000vsubshs \000vsubsws \000"
587
"vsububm \000vsububs \000vsubuhm \000vsubuhs \000vsubuwm \000vsubuws \000"
588
"vsum2sws \000vsum4sbs \000vsum4shs \000vsum4ubs \000vsumsws \000vupkhpx"
589
" \000vupkhsb \000vupkhsh \000vupklpx \000vupklsb \000vupklsh \000vxor \000"
590
"xor \000xori \000xoris \000";
594
// Emit the opcode for the instruction.
595
unsigned Bits = OpInfo[MI->getOpcode()];
596
assert(Bits != 0 && "Cannot print this instruction.");
597
O << AsmStrs+(Bits & 4095)-1;
600
// Fragment 0 encoded into 4 bits for 14 unique commands.
601
switch ((Bits >> 28) & 15) {
602
default: // unreachable.
604
// DBG_VALUE, BCTR, BCTRL8_Darwin, BCTRL8_ELF, BCTRL_Darwin, BCTRL_SVR4, ...
608
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
612
// ADJCALLSTACKDOWN, ADJCALLSTACKUP, ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP...
613
PrintSpecial(MI, "comment");
617
printBranchOperand(MI, 0);
622
printPredicateOperand(MI, 0, "cc");
625
// BL8_Darwin, BL8_ELF, BL_Darwin, BL_SVR4, TAILB, TAILB8, TCRETURNdi, TC...
626
printCallOperand(MI, 0);
629
// BLA8_Darwin, BLA8_ELF, BLA_Darwin, BLA_SVR4, TAILBA, TAILBA8, TCRETURN...
630
printAbsAddrOperand(MI, 0);
633
// DCBA, DCBF, DCBI, DCBST, DCBT, DCBTST, DCBZ, DCBZL
634
printMemRegReg(MI, 0);
639
printU5ImmOperand(MI, 1);
643
// DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64
648
printU5ImmOperand(MI, 1);
660
printU5ImmOperand(MI, 0);
664
// MTFSF, STBU, STBU8, STDU, STFDU, STFSU, STHU, STHU8, STWU
669
// MovePCtoLR, MovePCtoLR8
670
printPICLabel(MI, 0);
676
// Fragment 1 encoded into 6 bits for 47 unique commands.
677
switch ((Bits >> 22) & 63) {
678
default: // unreachable.
680
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
685
O << " ADJCALLSTACKDOWN";
690
O << " ADJCALLSTACKUP";
694
// ATOMIC_CMP_SWAP_I16
695
O << " ATOMIC_CMP_SWAP_I16 PSEUDO!";
699
// ATOMIC_CMP_SWAP_I32
700
O << " ATOMIC_CMP_SWAP_I32 PSEUDO!";
704
// ATOMIC_CMP_SWAP_I64
705
O << " ATOMIC_CMP_SWAP_I64 PSEUDO!";
709
// ATOMIC_CMP_SWAP_I8
710
O << " ATOMIC_CMP_SWAP_I8 PSEUDO!";
714
// ATOMIC_LOAD_ADD_I16
715
O << " ATOMIC_LOAD_ADD_I16 PSEUDO!";
719
// ATOMIC_LOAD_ADD_I32
720
O << " ATOMIC_LOAD_ADD_I32 PSEUDO!";
724
// ATOMIC_LOAD_ADD_I64
725
O << " ATOMIC_LOAD_ADD_I64 PSEUDO!";
729
// ATOMIC_LOAD_ADD_I8
730
O << " ATOMIC_LOAD_ADD_I8 PSEUDO!";
734
// ATOMIC_LOAD_AND_I16
735
O << " ATOMIC_LOAD_AND_I16 PSEUDO!";
739
// ATOMIC_LOAD_AND_I32
740
O << " ATOMIC_LOAD_AND_I32 PSEUDO!";
744
// ATOMIC_LOAD_AND_I64
745
O << " ATOMIC_LOAD_AND_I64 PSEUDO!";
749
// ATOMIC_LOAD_AND_I8
750
O << " ATOMIC_LOAD_AND_I8 PSEUDO!";
754
// ATOMIC_LOAD_NAND_I16
755
O << " ATOMIC_LOAD_NAND_I16 PSEUDO!";
759
// ATOMIC_LOAD_NAND_I32
760
O << " ATOMIC_LOAD_NAND_I32 PSEUDO!";
764
// ATOMIC_LOAD_NAND_I64
765
O << " ATOMIC_LOAD_NAND_I64 PSEUDO!";
769
// ATOMIC_LOAD_NAND_I8
770
O << " ATOMIC_LOAD_NAND_I8 PSEUDO!";
774
// ATOMIC_LOAD_OR_I16
775
O << " ATOMIC_LOAD_OR_I16 PSEUDO!";
779
// ATOMIC_LOAD_OR_I32
780
O << " ATOMIC_LOAD_OR_I32 PSEUDO!";
784
// ATOMIC_LOAD_OR_I64
785
O << " ATOMIC_LOAD_OR_I64 PSEUDO!";
790
O << " ATOMIC_LOAD_OR_I8 PSEUDO!";
794
// ATOMIC_LOAD_SUB_I16
795
O << " ATOMIC_LOAD_SUB_I16 PSEUDO!";
799
// ATOMIC_LOAD_SUB_I32
800
O << " ATOMIC_LOAD_SUB_I32 PSEUDO!";
804
// ATOMIC_LOAD_SUB_I64
805
O << " ATOMIC_LOAD_SUB_I64 PSEUDO!";
809
// ATOMIC_LOAD_SUB_I8
810
O << " ATOMIC_LOAD_SUB_I8 PSEUDO!";
814
// ATOMIC_LOAD_XOR_I16
815
O << " ATOMIC_LOAD_XOR_I16 PSEUDO!";
819
// ATOMIC_LOAD_XOR_I32
820
O << " ATOMIC_LOAD_XOR_I32 PSEUDO!";
824
// ATOMIC_LOAD_XOR_I64
825
O << " ATOMIC_LOAD_XOR_I64 PSEUDO!";
829
// ATOMIC_LOAD_XOR_I8
830
O << " ATOMIC_LOAD_XOR_I8 PSEUDO!";
835
O << " ATOMIC_SWAP_I16 PSEUDO!";
840
O << " ATOMIC_SWAP_I32 PSEUDO!";
845
O << " ATOMIC_SWAP_I64 PSEUDO!";
850
O << " ATOMIC_SWAP_I8 PSEUDO!";
854
// BCC, TCRETURNai, TCRETURNai8, TCRETURNdi, TCRETURNdi8, TCRETURNri, TCR...
858
// BL8_Darwin, BL8_ELF, BLA8_Darwin, BLA8_ELF, BLA_Darwin, BLA_SVR4, BL_D...
864
printPredicateOperand(MI, 0, "reg");
874
printMemRegImm(MI, 2);
884
printMemRegImm(MI, 2);
903
// SELECT_CC_F4, SELECT_CC_F8, SELECT_CC_I4, SELECT_CC_I8, SELECT_CC_VRRC
904
O << " SELECT_CC PSEUDO!";
912
printMemRegImm(MI, 1);
916
// STBU, STBU8, STFDU, STFSU, STHU, STHU8, STWU
917
printSymbolLo(MI, 2);
925
printS16X4ImmOperand(MI, 2);
934
// Fragment 2 encoded into 4 bits for 15 unique commands.
935
switch ((Bits >> 18) & 15) {
936
default: // unreachable.
938
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
943
printPredicateOperand(MI, 0, "reg");
945
printBranchOperand(MI, 2);
957
printSymbolLo(MI, 2);
961
// LBZ, LBZ8, LFD, LFS, LHA, LHA8, LHZ, LHZ8, LWZ, LWZ8, STB, STB8, STFD,...
962
printMemRegImm(MI, 1);
966
// LBZU, LBZU8, LFDU, LFSU, LHAU, LHZU, LHZU8, LWZU, LWZU8
967
printMemRegImm(MI, 2);
971
// LBZX, LBZX8, LDARX, LDX, LFDX, LFSX, LHAX, LHAX8, LHBRX, LHZX, LHZX8, ...
972
printMemRegReg(MI, 1);
976
// LD, LWA, STD, STD_32
977
printMemRegImmShifted(MI, 1);
982
printMemRegImmShifted(MI, 2);
987
printTOCEntryLabel(MI, 1);
995
printSymbolLo(MI, 1);
1000
printSymbolHi(MI, 1);
1009
// RLDIMI, RLWIMI, VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTH, VSPLTW
1010
printOperand(MI, 2);
1014
// VSPLTISB, VSPLTISH, VSPLTISW
1015
printS5ImmOperand(MI, 1);
1021
// Fragment 3 encoded into 3 bits for 7 unique commands.
1022
switch ((Bits >> 15) & 7) {
1023
default: // unreachable.
1025
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
1029
// ADDME, ADDME8, ADDZE, ADDZE8, CNTLZD, CNTLZW, EXTSB, EXTSB8, EXTSH, EX...
1034
printOperand(MI, 1);
1040
printOperand(MI, 3);
1046
printU6ImmOperand(MI, 3);
1048
printU6ImmOperand(MI, 4);
1053
printU5ImmOperand(MI, 3);
1055
printU5ImmOperand(MI, 4);
1057
printU5ImmOperand(MI, 5);
1061
// VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTH, VSPLTW
1062
printU5ImmOperand(MI, 1);
1068
// Fragment 4 encoded into 3 bits for 6 unique commands.
1069
switch ((Bits >> 12) & 7) {
1070
default: // unreachable.
1072
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, AND, AND8, ANDC, ANDC8, CMPD, CM...
1073
printOperand(MI, 2);
1076
// ADDI, ADDI8, ADDIC, ADDIC8, ADDICo, CMPDI, CMPWI, MULLI, SUBFIC, SUBFI...
1077
printS16ImmOperand(MI, 2);
1082
printSymbolHi(MI, 2);
1086
// ANDISo, ANDISo8, ANDIo, ANDIo8, CMPLDI, CMPLWI, ORI, ORI8, ORIS, ORIS8...
1087
printU16ImmOperand(MI, 2);
1091
// RLDICL, RLDICR, SRADI
1092
printU6ImmOperand(MI, 2);
1095
// RLWINM, RLWINMo, SRAWI
1096
printU5ImmOperand(MI, 2);
1100
switch (MI->getOpcode()) {
1187
case PPC::VCMPEQFPo:
1189
case PPC::VCMPEQUBo:
1191
case PPC::VCMPEQUHo:
1193
case PPC::VCMPEQUWo:
1195
case PPC::VCMPGEFPo:
1197
case PPC::VCMPGTFPo:
1199
case PPC::VCMPGTSBo:
1201
case PPC::VCMPGTSHo:
1203
case PPC::VCMPGTSWo:
1205
case PPC::VCMPGTUBo:
1207
case PPC::VCMPGTUHo:
1209
case PPC::VCMPGTUWo:
1300
case PPC::VMHADDSHS:
1301
case PPC::VMHRADDSHS:
1302
case PPC::VMLADDUHM:
1314
switch (MI->getOpcode()) {
1326
case PPC::VMHADDSHS:
1327
case PPC::VMHRADDSHS:
1328
case PPC::VMLADDUHM:
1337
case PPC::VSEL: printOperand(MI, 3); break;
1340
case PPC::RLDICR: printU6ImmOperand(MI, 3); break;
1341
case PPC::VSLDOI: printU5ImmOperand(MI, 3); break;
1349
printU5ImmOperand(MI, 3);
1351
printU5ImmOperand(MI, 4);
1359
/// getRegisterName - This method is automatically generated by tblgen
1360
/// from the register set description. This returns the assembler name
1361
/// for the specified register.
1362
const char *PPCAsmPrinter::getRegisterName(unsigned RegNo) {
1363
assert(RegNo && RegNo < 176 && "Invalid register number!");
1365
static const unsigned RegAsmOffset[] = {
1366
0, 3, 7, 9, 11, 13, 15, 19, 21, 23, 25, 27, 31, 34,
1367
36, 38, 41, 45, 48, 51, 54, 57, 61, 64, 67, 70, 73, 77,
1368
80, 83, 86, 89, 93, 96, 99, 102, 105, 109, 112, 115, 118, 121,
1369
121, 125, 128, 131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171,
1370
174, 178, 182, 186, 190, 194, 198, 202, 206, 210, 214, 217, 221, 225,
1371
228, 231, 234, 237, 240, 243, 243, 246, 249, 252, 256, 260, 264, 268,
1372
272, 276, 280, 284, 288, 292, 295, 299, 303, 307, 311, 315, 319, 323,
1373
327, 331, 335, 338, 342, 346, 349, 352, 355, 358, 361, 364, 382, 385,
1374
388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 431, 435, 439,
1375
443, 447, 451, 455, 459, 463, 467, 471, 474, 478, 482, 485, 488, 491,
1376
494, 497, 500, 246, 249, 252, 256, 260, 264, 268, 272, 276, 280, 284,
1377
288, 292, 295, 299, 303, 307, 311, 315, 319, 323, 327, 331, 335, 338,
1378
342, 346, 349, 352, 355, 358, 361, 0
1381
const char *AsmStrs =
1382
"ca\000cr0\0002\0001\0000\0003\000cr1\0006\0005\0004\0007\000cr2\00010\000"
1383
"9\0008\00011\000cr3\00014\00013\00012\00015\000cr4\00018\00017\00016\000"
1384
"19\000cr5\00022\00021\00020\00023\000cr6\00026\00025\00024\00027\000cr7"
1385
"\00030\00029\00028\00031\000ctr\000f0\000f1\000f10\000f11\000f12\000f13"
1386
"\000f14\000f15\000f16\000f17\000f18\000f19\000f2\000f20\000f21\000f22\000"
1387
"f23\000f24\000f25\000f26\000f27\000f28\000f29\000f3\000f30\000f31\000f4"
1388
"\000f5\000f6\000f7\000f8\000f9\000lr\000r0\000r1\000r10\000r11\000r12\000"
1389
"r13\000r14\000r15\000r16\000r17\000r18\000r19\000r2\000r20\000r21\000r2"
1390
"2\000r23\000r24\000r25\000r26\000r27\000r28\000r29\000r3\000r30\000r31\000"
1391
"r4\000r5\000r6\000r7\000r8\000r9\000**ROUNDING MODE**\000v0\000v1\000v1"
1392
"0\000v11\000v12\000v13\000v14\000v15\000v16\000v17\000v18\000v19\000v2\000"
1393
"v20\000v21\000v22\000v23\000v24\000v25\000v26\000v27\000v28\000v29\000v"
1394
"3\000v30\000v31\000v4\000v5\000v6\000v7\000v8\000v9\000VRsave\000";
1395
return AsmStrs+RegAsmOffset[RegNo-1];
1399
#ifdef GET_INSTRUCTION_NAME
1400
#undef GET_INSTRUCTION_NAME
1402
/// getInstructionName: This method is automatically generated by tblgen
1403
/// from the instruction set description. This returns the enum name of the
1404
/// specified instruction.
1405
const char *PPCAsmPrinter::getInstructionName(unsigned Opcode) {
1406
assert(Opcode < 519 && "Invalid instruction number!");
1408
static const unsigned InstAsmOffset[] = {
1409
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 135,
1410
140, 145, 151, 156, 162, 167, 173, 179, 186, 193, 199, 206, 212, 219,
1411
225, 232, 249, 264, 268, 273, 278, 284, 291, 299, 305, 312, 332, 352,
1412
372, 391, 411, 431, 451, 470, 490, 510, 530, 549, 570, 591, 612, 632,
1413
651, 670, 689, 707, 727, 747, 767, 786, 806, 826, 846, 865, 881, 897,
1414
913, 928, 930, 934, 939, 953, 964, 977, 988, 999, 1007, 1019, 1028, 1039,
1415
1048, 1052, 1062, 1070, 1075, 1081, 1087, 1094, 1100, 1107, 1112, 1118, 1125, 1132,
1416
1138, 1143, 1149, 1154, 1159, 1164, 1170, 1175, 1182, 1187, 1193, 1198, 1204, 1209,
1417
1215, 1219, 1226, 1230, 1236, 1242, 1250, 1257, 1266, 1271, 1278, 1287, 1297, 1301,
1418
1306, 1312, 1319, 1325, 1332, 1338, 1347, 1359, 1365, 1371, 1376, 1382, 1390, 1396,
1419
1403, 1410, 1417, 1424, 1429, 1435, 1441, 1448, 1452, 1458, 1464, 1471, 1476, 1482,
1420
1489, 1496, 1502, 1508, 1515, 1523, 1530, 1538, 1543, 1549, 1555, 1561, 1568, 1573,
1421
1579, 1582, 1586, 1591, 1596, 1602, 1607, 1613, 1616, 1622, 1626, 1630, 1641, 1647,
1422
1661, 1665, 1670, 1675, 1679, 1684, 1689, 1693, 1698, 1703, 1709, 1714, 1720, 1726,
1423
1730, 1735, 1740, 1746, 1751, 1757, 1760, 1764, 1768, 1773, 1779, 1785, 1791, 1796,
1424
1801, 1805, 1810, 1814, 1820, 1825, 1831, 1835, 1840, 1845, 1851, 1856, 1862, 1867,
1425
1872, 1878, 1885, 1890, 1895, 1901, 1908, 1917, 1924, 1930, 1936, 1943, 1950, 1957,
1426
1963, 1968, 1974, 1983, 1990, 1996, 2003, 2009, 2016, 2022, 2028, 2034, 2045, 2057,
1427
2062, 2068, 2072, 2077, 2081, 2085, 2090, 2093, 2100, 2104, 2111, 2115, 2120, 2124,
1428
2129, 2134, 2140, 2146, 2153, 2160, 2167, 2174, 2181, 2189, 2195, 2208, 2221, 2234,
1429
2247, 2262, 2266, 2270, 2279, 2284, 2290, 2295, 2301, 2305, 2309, 2313, 2318, 2323,
1430
2329, 2334, 2340, 2344, 2350, 2355, 2361, 2366, 2374, 2381, 2386, 2392, 2398, 2405,
1431
2410, 2416, 2422, 2426, 2431, 2438, 2443, 2449, 2454, 2460, 2467, 2474, 2481, 2486,
1432
2492, 2496, 2501, 2508, 2514, 2519, 2525, 2530, 2536, 2541, 2547, 2553, 2560, 2566,
1433
2573, 2580, 2588, 2595, 2603, 2610, 2618, 2623, 2629, 2636, 2643, 2651, 2660, 2670,
1434
2681, 2693, 2704, 2716, 2727, 2739, 2744, 2758, 2766, 2773, 2781, 2789, 2797, 2805,
1435
2813, 2821, 2829, 2837, 2845, 2850, 2856, 2863, 2870, 2877, 2884, 2891, 2898, 2904,
1436
2910, 2918, 2927, 2936, 2946, 2955, 2965, 2974, 2984, 2993, 3003, 3012, 3022, 3031,
1437
3041, 3050, 3060, 3069, 3079, 3088, 3098, 3107, 3117, 3126, 3136, 3145, 3155, 3162,
1438
3169, 3178, 3186, 3194, 3201, 3208, 3215, 3222, 3229, 3236, 3243, 3253, 3264, 3271,
1439
3278, 3285, 3292, 3299, 3306, 3313, 3323, 3330, 3337, 3344, 3351, 3358, 3365, 3374,
1440
3383, 3392, 3401, 3410, 3419, 3427, 3435, 3443, 3451, 3459, 3467, 3475, 3483, 3492,
1441
3497, 3501, 3507, 3513, 3521, 3529, 3537, 3545, 3553, 3561, 3569, 3577, 3583, 3589,
1442
3595, 3601, 3607, 3612, 3617, 3622, 3632, 3637, 3641, 3646, 3653, 3658, 3663, 3668,
1443
3675, 3682, 3691, 3700, 3709, 3716, 3720, 3726, 3732, 3738, 3743, 3748, 3753, 3758,
1444
3766, 3773, 3781, 3789, 3797, 3805, 3813, 3821, 3829, 3837, 3845, 3854, 3863, 3872,
1445
3881, 3889, 3897, 3905, 3913, 3921, 3929, 3937, 3942, 3949, 3953, 3958, 3963, 3969,
1450
"PHI\000INLINEASM\000DBG_LABEL\000EH_LABEL\000GC_LABEL\000KILL\000EXTRAC"
1451
"T_SUBREG\000INSERT_SUBREG\000IMPLICIT_DEF\000SUBREG_TO_REG\000COPY_TO_R"
1452
"EGCLASS\000DBG_VALUE\000ADD4\000ADD8\000ADDC\000ADDC8\000ADDE\000ADDE8\000"
1453
"ADDI\000ADDI8\000ADDIC\000ADDIC8\000ADDICo\000ADDIS\000ADDIS8\000ADDME\000"
1454
"ADDME8\000ADDZE\000ADDZE8\000ADJCALLSTACKDOWN\000ADJCALLSTACKUP\000AND\000"
1455
"AND8\000ANDC\000ANDC8\000ANDISo\000ANDISo8\000ANDIo\000ANDIo8\000ATOMIC"
1456
"_CMP_SWAP_I16\000ATOMIC_CMP_SWAP_I32\000ATOMIC_CMP_SWAP_I64\000ATOMIC_C"
1457
"MP_SWAP_I8\000ATOMIC_LOAD_ADD_I16\000ATOMIC_LOAD_ADD_I32\000ATOMIC_LOAD"
1458
"_ADD_I64\000ATOMIC_LOAD_ADD_I8\000ATOMIC_LOAD_AND_I16\000ATOMIC_LOAD_AN"
1459
"D_I32\000ATOMIC_LOAD_AND_I64\000ATOMIC_LOAD_AND_I8\000ATOMIC_LOAD_NAND_"
1460
"I16\000ATOMIC_LOAD_NAND_I32\000ATOMIC_LOAD_NAND_I64\000ATOMIC_LOAD_NAND"
1461
"_I8\000ATOMIC_LOAD_OR_I16\000ATOMIC_LOAD_OR_I32\000ATOMIC_LOAD_OR_I64\000"
1462
"ATOMIC_LOAD_OR_I8\000ATOMIC_LOAD_SUB_I16\000ATOMIC_LOAD_SUB_I32\000ATOM"
1463
"IC_LOAD_SUB_I64\000ATOMIC_LOAD_SUB_I8\000ATOMIC_LOAD_XOR_I16\000ATOMIC_"
1464
"LOAD_XOR_I32\000ATOMIC_LOAD_XOR_I64\000ATOMIC_LOAD_XOR_I8\000ATOMIC_SWA"
1465
"P_I16\000ATOMIC_SWAP_I32\000ATOMIC_SWAP_I64\000ATOMIC_SWAP_I8\000B\000B"
1466
"CC\000BCTR\000BCTRL8_Darwin\000BCTRL8_ELF\000BCTRL_Darwin\000BCTRL_SVR4"
1467
"\000BL8_Darwin\000BL8_ELF\000BLA8_Darwin\000BLA8_ELF\000BLA_Darwin\000B"
1468
"LA_SVR4\000BLR\000BL_Darwin\000BL_SVR4\000CMPD\000CMPDI\000CMPLD\000CMP"
1469
"LDI\000CMPLW\000CMPLWI\000CMPW\000CMPWI\000CNTLZD\000CNTLZW\000CREQV\000"
1470
"CROR\000CRSET\000DCBA\000DCBF\000DCBI\000DCBST\000DCBT\000DCBTST\000DCB"
1471
"Z\000DCBZL\000DIVD\000DIVDU\000DIVW\000DIVWU\000DSS\000DSSALL\000DST\000"
1472
"DST64\000DSTST\000DSTST64\000DSTSTT\000DSTSTT64\000DSTT\000DSTT64\000DY"
1473
"NALLOC\000DYNALLOC8\000EQV\000EQV8\000EXTSB\000EXTSB8\000EXTSH\000EXTSH"
1474
"8\000EXTSW\000EXTSW_32\000EXTSW_32_64\000FABSD\000FABSS\000FADD\000FADD"
1475
"S\000FADDrtz\000FCFID\000FCMPUD\000FCMPUS\000FCTIDZ\000FCTIWZ\000FDIV\000"
1476
"FDIVS\000FMADD\000FMADDS\000FMR\000FMRSD\000FMSUB\000FMSUBS\000FMUL\000"
1477
"FMULS\000FNABSD\000FNABSS\000FNEGD\000FNEGS\000FNMADD\000FNMADDS\000FNM"
1478
"SUB\000FNMSUBS\000FRSP\000FSELD\000FSELS\000FSQRT\000FSQRTS\000FSUB\000"
1479
"FSUBS\000LA\000LBZ\000LBZ8\000LBZU\000LBZU8\000LBZX\000LBZX8\000LD\000L"
1480
"DARX\000LDU\000LDX\000LDinto_toc\000LDtoc\000LDtoc_restore\000LFD\000LF"
1481
"DU\000LFDX\000LFS\000LFSU\000LFSX\000LHA\000LHA8\000LHAU\000LHAU8\000LH"
1482
"AX\000LHAX8\000LHBRX\000LHZ\000LHZ8\000LHZU\000LHZU8\000LHZX\000LHZX8\000"
1483
"LI\000LI8\000LIS\000LIS8\000LVEBX\000LVEHX\000LVEWX\000LVSL\000LVSR\000"
1484
"LVX\000LVXL\000LWA\000LWARX\000LWAX\000LWBRX\000LWZ\000LWZ8\000LWZU\000"
1485
"LWZU8\000LWZX\000LWZX8\000MCRF\000MFCR\000MFCTR\000MFCTR8\000MFFS\000MF"
1486
"LR\000MFLR8\000MFOCRF\000MFVRSAVE\000MFVSCR\000MTCRF\000MTCTR\000MTCTR8"
1487
"\000MTFSB0\000MTFSB1\000MTFSF\000MTLR\000MTLR8\000MTVRSAVE\000MTVSCR\000"
1488
"MULHD\000MULHDU\000MULHW\000MULHWU\000MULLD\000MULLI\000MULLW\000MovePC"
1489
"toLR\000MovePCtoLR8\000NAND\000NAND8\000NEG\000NEG8\000NOP\000NOR\000NO"
1490
"R8\000OR\000OR4To8\000OR8\000OR8To4\000ORC\000ORC8\000ORI\000ORI8\000OR"
1491
"IS\000ORIS8\000RLDCL\000RLDICL\000RLDICR\000RLDIMI\000RLWIMI\000RLWINM\000"
1492
"RLWINMo\000RLWNM\000SELECT_CC_F4\000SELECT_CC_F8\000SELECT_CC_I4\000SEL"
1493
"ECT_CC_I8\000SELECT_CC_VRRC\000SLD\000SLW\000SPILL_CR\000SRAD\000SRADI\000"
1494
"SRAW\000SRAWI\000SRD\000SRW\000STB\000STB8\000STBU\000STBU8\000STBX\000"
1495
"STBX8\000STD\000STDCX\000STDU\000STDUX\000STDX\000STDX_32\000STD_32\000"
1496
"STFD\000STFDU\000STFDX\000STFIWX\000STFS\000STFSU\000STFSX\000STH\000ST"
1497
"H8\000STHBRX\000STHU\000STHU8\000STHX\000STHX8\000STVEBX\000STVEHX\000S"
1498
"TVEWX\000STVX\000STVXL\000STW\000STW8\000STWBRX\000STWCX\000STWU\000STW"
1499
"UX\000STWX\000STWX8\000SUBF\000SUBF8\000SUBFC\000SUBFC8\000SUBFE\000SUB"
1500
"FE8\000SUBFIC\000SUBFIC8\000SUBFME\000SUBFME8\000SUBFZE\000SUBFZE8\000S"
1501
"YNC\000TAILB\000TAILB8\000TAILBA\000TAILBA8\000TAILBCTR\000TAILBCTR8\000"
1502
"TCRETURNai\000TCRETURNai8\000TCRETURNdi\000TCRETURNdi8\000TCRETURNri\000"
1503
"TCRETURNri8\000TRAP\000UPDATE_VRSAVE\000VADDCUW\000VADDFP\000VADDSBS\000"
1504
"VADDSHS\000VADDSWS\000VADDUBM\000VADDUBS\000VADDUHM\000VADDUHS\000VADDU"
1505
"WM\000VADDUWS\000VAND\000VANDC\000VAVGSB\000VAVGSH\000VAVGSW\000VAVGUB\000"
1506
"VAVGUH\000VAVGUW\000VCFSX\000VCFUX\000VCMPBFP\000VCMPBFPo\000VCMPEQFP\000"
1507
"VCMPEQFPo\000VCMPEQUB\000VCMPEQUBo\000VCMPEQUH\000VCMPEQUHo\000VCMPEQUW"
1508
"\000VCMPEQUWo\000VCMPGEFP\000VCMPGEFPo\000VCMPGTFP\000VCMPGTFPo\000VCMP"
1509
"GTSB\000VCMPGTSBo\000VCMPGTSH\000VCMPGTSHo\000VCMPGTSW\000VCMPGTSWo\000"
1510
"VCMPGTUB\000VCMPGTUBo\000VCMPGTUH\000VCMPGTUHo\000VCMPGTUW\000VCMPGTUWo"
1511
"\000VCTSXS\000VCTUXS\000VEXPTEFP\000VLOGEFP\000VMADDFP\000VMAXFP\000VMA"
1512
"XSB\000VMAXSH\000VMAXSW\000VMAXUB\000VMAXUH\000VMAXUW\000VMHADDSHS\000V"
1513
"MHRADDSHS\000VMINFP\000VMINSB\000VMINSH\000VMINSW\000VMINUB\000VMINUH\000"
1514
"VMINUW\000VMLADDUHM\000VMRGHB\000VMRGHH\000VMRGHW\000VMRGLB\000VMRGLH\000"
1515
"VMRGLW\000VMSUMMBM\000VMSUMSHM\000VMSUMSHS\000VMSUMUBM\000VMSUMUHM\000V"
1516
"MSUMUHS\000VMULESB\000VMULESH\000VMULEUB\000VMULEUH\000VMULOSB\000VMULO"
1517
"SH\000VMULOUB\000VMULOUH\000VNMSUBFP\000VNOR\000VOR\000VPERM\000VPKPX\000"
1518
"VPKSHSS\000VPKSHUS\000VPKSWSS\000VPKSWUS\000VPKUHUM\000VPKUHUS\000VPKUW"
1519
"UM\000VPKUWUS\000VREFP\000VRFIM\000VRFIN\000VRFIP\000VRFIZ\000VRLB\000V"
1520
"RLH\000VRLW\000VRSQRTEFP\000VSEL\000VSL\000VSLB\000VSLDOI\000VSLH\000VS"
1521
"LO\000VSLW\000VSPLTB\000VSPLTH\000VSPLTISB\000VSPLTISH\000VSPLTISW\000V"
1522
"SPLTW\000VSR\000VSRAB\000VSRAH\000VSRAW\000VSRB\000VSRH\000VSRO\000VSRW"
1523
"\000VSUBCUW\000VSUBFP\000VSUBSBS\000VSUBSHS\000VSUBSWS\000VSUBUBM\000VS"
1524
"UBUBS\000VSUBUHM\000VSUBUHS\000VSUBUWM\000VSUBUWS\000VSUM2SWS\000VSUM4S"
1525
"BS\000VSUM4SHS\000VSUM4UBS\000VSUMSWS\000VUPKHPX\000VUPKHSB\000VUPKHSH\000"
1526
"VUPKLPX\000VUPKLSB\000VUPKLSH\000VXOR\000V_SET0\000XOR\000XOR8\000XORI\000"
1527
"XORI8\000XORIS\000XORIS8\000";
1528
return Strs+InstAsmOffset[Opcode];
added
removed
libclamav/c++/PPCGenAsmWriter.inc
