1
package com.sun.electric.tool.simulation.test;
4
* Created by IntelliJ IDEA.
8
* To change this template use File | Settings | File Templates.
10
public class JtagSubchainTesterModel extends BypassJtagTester {
12
private final String phi2;
13
private final String phi1;
14
private final String write;
15
private final String read;
16
private final String sin;
17
private final String sout;
20
* Create a subchain tester based on the 8- or 9-wire jtag interface.
21
* jtag[8:0] = {scan_data_return, phi2_return, phi1_return, rd, wr, phi1, phi2, sin, mc*}
22
* Note that mc is not present on older designs, so they are jtag[8:1].
23
* If jtagOutBus is null or "", it assumes the chain has been capped off with
24
* an endcap, and scanout is actually jtagIn[8].
25
* @param vm the Verilog simulation model
26
* @param jtagInBus the name of the 9-bit wide input bus, i.e. "jtagIn" or "jtagIn[8:0]"
27
* @param jtagOutBus the name of the 9-bit wide output bus, i.e. "jtagOut" or "jtagOut[8:0]".
28
* This may be null if the chain ends in an endCap.
30
JtagSubchainTesterModel(SimulationModel vm, String jtagInBus, String jtagOutBus) {
32
int i = jtagInBus.indexOf('[');
33
if (i != -1) jtagInBus = jtagInBus.substring(0, i);
34
phi2 = jtagInBus + "[2]";
35
phi1 = jtagInBus + "[3]";
36
write = jtagInBus + "[4]";
37
read = jtagInBus + "[5]";
38
sin = jtagInBus + "[1]";
39
if (jtagOutBus != null && !jtagOutBus.equals("")) {
40
i = jtagOutBus.indexOf('[');
41
if (i != -1) jtagOutBus = jtagOutBus.substring(0, i);
42
sout = jtagOutBus + "[1]";
44
sout = jtagInBus + "[8]";
46
configure((float)vm.getVdd(), 100000); // 100MHz
50
* Create a subchain tester based on the 5-wire jtag interface.
51
* @param vm the Verilog simulation model
52
* @param phi2 name of the phi2 signal
53
* @param phi1 name of the phi1 signal
54
* @param write name of the write signal
55
* @param read name of the read signal
56
* @param sin name of the scan data in signal
57
* @param sout name of the scan data out signal
59
JtagSubchainTesterModel(SimulationModel vm, String phi2, String phi1, String write, String read, String sin, String sout) {
67
configure((float)vm.getVdd(), 100000); // 100MHz
72
model.setNodeState(phi2, 1);
73
model.setNodeState(phi1, 0);
74
model.setNodeState(write, 0);
75
model.setNodeState(read, 0);
76
model.setNodeState(sin, 0);
79
public void tms_reset() {
83
void shift(ChainNode chain, boolean readEnable, boolean writeEnable, int irBadSeverity) {
84
if (isBypassScanning()) {
85
doBypassScanning(chain, readEnable, writeEnable);
90
model.setNodeState(read, 1);
91
model.waitNS(delay*4); // assert read for 2 clock cycles
92
model.setNodeState(read, 0);
93
model.waitNS(delay*2); // deassert for 1 clock cycle
96
BitVector in = chain.getInBits();
97
BitVector out = new BitVector(in.getNumBits(), "scannedOut");
98
for (int i=in.getNumBits()-1; i>=0; i--) {
100
int state = model.getNodeState(sout);
101
if (state != 1 && state != 0) {
102
System.out.println("Invalid state "+state+" scanned out, setting it to zero");
105
out.set(i, (state==0 ? false : true));
106
// set input, scan it in
107
state = in.get(i) ? 1 : 0;
108
model.setNodeState(sin, state);
111
chain.getOutBits().put(0, out);
115
model.setNodeState(write, 1);
116
model.waitNS(delay*4); // assert write for 2 clock cycles
117
model.setNodeState(write, 0);
118
model.waitNS(delay*2); // deassert for 1 clock cycle
120
BitVector bitsToCheck = new BitVector(chain.getInBits().getNumBits(), "bitsToCheck");
121
bitsToCheck.set(0, chain.getInBits().getNumBits(), true);
122
checkDataNets(chain, 0, bitsToCheck);
123
checkDataNets(chain, 1, bitsToCheck);
127
// --------------------------------------------------------------------------
130
* Cycle phi2, phi1. Note this waits at the beginning of the method before
131
* setting phi2 low (phi2 is high normally) to allow any change on scan in data
133
* @param times the number of times to cycle phi2,phi1.
135
private void cycleClks(int times) {
136
for (int i=0; i<times; i++) {
137
model.waitNS(delay*0.45);
138
model.setNodeState(phi2, 0);
139
model.waitNS(delay*0.05); // non-overlaping by 5% of half-freq
140
model.setNodeState(phi1, 1);
141
model.waitNS(delay*0.95);
142
model.setNodeState(phi1, 0);
143
model.waitNS(delay*0.05); // non-overlaping by 5% of half-freq
144
model.setNodeState(phi2, 1);
145
model.waitNS(delay*0.50);