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//------------------------------------------------------------------------------
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// <copyright file="ar6k.c" company="Atheros">
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// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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//------------------------------------------------------------------------------
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//==============================================================================
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// AR6K device layer that handles register level I/O
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// Author(s): ="Atheros"
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//==============================================================================
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#include "AR6002/hw2.0/hw/mbox_host_reg.h"
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#include "../htc_debug.h"
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#include "htc_packet.h"
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#define MAILBOX_FOR_BLOCK_SIZE 1
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A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
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A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
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static void DevCleanupVirtualScatterSupport(AR6K_DEVICE *pDev);
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void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket)
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HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket);
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HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev)
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pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList);
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void DevCleanup(AR6K_DEVICE *pDev)
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DevCleanupGMbox(pDev);
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if (pDev->HifAttached) {
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HIFDetachHTC(pDev->HIFDevice);
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pDev->HifAttached = FALSE;
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DevCleanupVirtualScatterSupport(pDev);
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if (A_IS_MUTEX_VALID(&pDev->Lock)) {
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A_MUTEX_DELETE(&pDev->Lock);
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A_STATUS DevSetup(AR6K_DEVICE *pDev)
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A_UINT32 blocksizes[AR6K_MAILBOXES];
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A_STATUS status = A_OK;
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HTC_CALLBACKS htcCallbacks;
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DL_LIST_INIT(&pDev->ScatterReqHead);
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/* initialize our free list of IO packets */
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INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList);
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A_MUTEX_INIT(&pDev->Lock);
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A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS));
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/* the device layer handles these */
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htcCallbacks.rwCompletionHandler = DevRWCompletionHandler;
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htcCallbacks.dsrHandler = DevDsrHandler;
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htcCallbacks.context = pDev;
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status = HIFAttachHTC(pDev->HIFDevice, &htcCallbacks);
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if (A_FAILED(status)) {
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pDev->HifAttached = TRUE;
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/* get the addresses for all 4 mailboxes */
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status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
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&pDev->MailBoxInfo, sizeof(pDev->MailBoxInfo));
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if (status != A_OK) {
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/* carve up register I/O packets (these are for ASYNC register I/O ) */
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for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) {
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HTC_PACKET *pIOPacket;
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pIOPacket = &pDev->RegIOBuffers[i].HtcPacket;
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SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket,
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pDev->RegIOBuffers[i].Buffer,
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AR6K_REG_IO_BUFFER_SIZE,
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AR6KFreeIOPacket(pDev,pIOPacket);
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/* get the block sizes */
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status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
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blocksizes, sizeof(blocksizes));
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if (status != A_OK) {
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/* note: we actually get the block size of a mailbox other than 0, for SDIO the block
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* size on mailbox 0 is artificially set to 1. So we use the block size that is set
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* for the other 3 mailboxes */
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pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE];
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/* must be a power of 2 */
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A_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0);
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/* assemble mask, used for padding to a block */
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pDev->BlockMask = pDev->BlockSize - 1;
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AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n",
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pDev->BlockSize, pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX]));
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pDev->GetPendingEventsFunc = NULL;
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/* see if the HIF layer implements the get pending events function */
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HIFConfigureDevice(pDev->HIFDevice,
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HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
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&pDev->GetPendingEventsFunc,
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sizeof(pDev->GetPendingEventsFunc));
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/* assume we can process HIF interrupt events asynchronously */
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pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC;
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/* see if the HIF layer overrides this assumption */
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HIFConfigureDevice(pDev->HIFDevice,
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HIF_DEVICE_GET_IRQ_PROC_MODE,
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&pDev->HifIRQProcessingMode,
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sizeof(pDev->HifIRQProcessingMode));
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switch (pDev->HifIRQProcessingMode) {
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case HIF_DEVICE_IRQ_SYNC_ONLY:
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AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("HIF Interrupt processing is SYNC ONLY\n"));
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/* see if HIF layer wants HTC to yield */
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HIFConfigureDevice(pDev->HIFDevice,
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HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
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&pDev->HifIRQYieldParams,
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sizeof(pDev->HifIRQYieldParams));
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if (pDev->HifIRQYieldParams.RecvPacketYieldCount > 0) {
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AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
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("HIF requests that DSR yield per %d RECV packets \n",
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pDev->HifIRQYieldParams.RecvPacketYieldCount));
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pDev->DSRCanYield = TRUE;
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case HIF_DEVICE_IRQ_ASYNC_SYNC:
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AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n"));
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pDev->HifMaskUmaskRecvEvent = NULL;
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/* see if the HIF layer implements the mask/unmask recv events function */
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HIFConfigureDevice(pDev->HIFDevice,
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HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
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&pDev->HifMaskUmaskRecvEvent,
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sizeof(pDev->HifMaskUmaskRecvEvent));
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AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%lX , 0x%lX\n",
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(unsigned long)pDev->GetPendingEventsFunc, (unsigned long)pDev->HifMaskUmaskRecvEvent));
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status = DevDisableInterrupts(pDev);
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if (A_FAILED(status)) {
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status = DevSetupGMbox(pDev);
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if (A_FAILED(status)) {
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if (pDev->HifAttached) {
210
HIFDetachHTC(pDev->HIFDevice);
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pDev->HifAttached = FALSE;
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A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev)
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AR6K_IRQ_ENABLE_REGISTERS regs;
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/* Enable all the interrupts except for the internal AR6000 CPU interrupt */
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pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) |
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INT_STATUS_ENABLE_CPU_SET(0x01) |
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INT_STATUS_ENABLE_COUNTER_SET(0x01);
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if (NULL == pDev->GetPendingEventsFunc) {
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pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
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/* The HIF layer provided us with a pending events function which means that
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* the detection of pending mbox messages is handled in the HIF layer.
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* This is the case for the SPI2 interface.
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* In the normal case we enable MBOX interrupts, for the case
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* with HIFs that offer this mechanism, we keep these interrupts
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pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
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/* Set up the CPU Interrupt Status Register */
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pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00);
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/* Set up the Error Interrupt Status Register */
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pDev->IrqEnableRegisters.error_status_enable =
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ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) |
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ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01);
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/* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */
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pDev->IrqEnableRegisters.counter_int_status_enable =
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COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK);
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/* copy into our temp area */
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A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
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/* always synchronous */
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status = HIFReadWrite(pDev->HIFDevice,
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INT_STATUS_ENABLE_ADDRESS,
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®s.int_status_enable,
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AR6K_IRQ_ENABLE_REGS_SIZE,
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HIF_WR_SYNC_BYTE_INC,
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if (status != A_OK) {
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/* Can't write it for some reason */
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
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("Failed to update interrupt control registers err: %d\n", status));
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A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev)
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AR6K_IRQ_ENABLE_REGISTERS regs;
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/* Disable all interrupts */
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pDev->IrqEnableRegisters.int_status_enable = 0;
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pDev->IrqEnableRegisters.cpu_int_status_enable = 0;
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pDev->IrqEnableRegisters.error_status_enable = 0;
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pDev->IrqEnableRegisters.counter_int_status_enable = 0;
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/* copy into our temp area */
290
A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
294
/* always synchronous */
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return HIFReadWrite(pDev->HIFDevice,
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INT_STATUS_ENABLE_ADDRESS,
297
®s.int_status_enable,
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AR6K_IRQ_ENABLE_REGS_SIZE,
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HIF_WR_SYNC_BYTE_INC,
303
/* enable device interrupts */
304
A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev)
306
/* for good measure, make sure interrupt are disabled before unmasking at the HIF
308
* The rationale here is that between device insertion (where we clear the interrupts the first time)
309
* and when HTC is finally ready to handle interrupts, other software can perform target "soft" resets.
310
* The AR6K interrupt enables reset back to an "enabled" state when this happens.
312
A_STATUS IntStatus = A_OK;
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DevDisableInterrupts(pDev);
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IntStatus = DevEnableInterrupts(pDev);
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/* Unmask the host controller interrupts */
319
HIFUnMaskInterrupt(pDev->HIFDevice);
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/* Unmask the host controller interrupts */
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HIFUnMaskInterrupt(pDev->HIFDevice);
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IntStatus = DevEnableInterrupts(pDev);
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/* disable all device interrupts */
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A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev)
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/* mask the interrupt at the HIF layer, we don't want a stray interrupt taken while
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* we zero out our shadow registers in DevDisableInterrupts()*/
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HIFMaskInterrupt(pDev->HIFDevice);
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return DevDisableInterrupts(pDev);
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/* callback when our fetch to enable/disable completes */
340
static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket)
342
AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
346
if (A_FAILED(pPacket->Status)) {
347
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
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(" Failed to disable receiver, status:%d \n", pPacket->Status));
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/* free this IO packet */
351
AR6KFreeIOPacket(pDev,pPacket);
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AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n"));
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/* disable packet reception (used in case the host runs out of buffers)
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* this is the "override" method when the HIF reports another methods to
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* disable recv events */
358
static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
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A_STATUS status = A_OK;
361
HTC_PACKET *pIOPacket = NULL;
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AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n",
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EnableRecv,AsyncMode));
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pIOPacket = AR6KAllocIOPacket(pDev);
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if (NULL == pIOPacket) {
373
status = A_NO_MEMORY;
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/* stick in our completion routine when the I/O operation completes */
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pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
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pIOPacket->pContext = pDev;
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/* call the HIF layer override and do this asynchronously */
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status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
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EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
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/* if we get here we are doing it synchronously */
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status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
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EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
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if (A_FAILED(status) && (pIOPacket != NULL)) {
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AR6KFreeIOPacket(pDev,pIOPacket);
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/* disable packet reception (used in case the host runs out of buffers)
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* this is the "normal" method using the interrupt enable registers through
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static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
408
A_STATUS status = A_OK;
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HTC_PACKET *pIOPacket = NULL;
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AR6K_IRQ_ENABLE_REGISTERS regs;
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/* take the lock to protect interrupt enable shadows */
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pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
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pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
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/* copy into our temp area */
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A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
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pIOPacket = AR6KAllocIOPacket(pDev);
431
if (NULL == pIOPacket) {
432
status = A_NO_MEMORY;
437
/* copy values to write to our async I/O buffer */
438
A_MEMCPY(pIOPacket->pBuffer,®s,AR6K_IRQ_ENABLE_REGS_SIZE);
440
/* stick in our completion routine when the I/O operation completes */
441
pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
442
pIOPacket->pContext = pDev;
444
/* write it out asynchronously */
445
HIFReadWrite(pDev->HIFDevice,
446
INT_STATUS_ENABLE_ADDRESS,
448
AR6K_IRQ_ENABLE_REGS_SIZE,
449
HIF_WR_ASYNC_BYTE_INC,
454
/* if we get here we are doing it synchronously */
456
status = HIFReadWrite(pDev->HIFDevice,
457
INT_STATUS_ENABLE_ADDRESS,
458
®s.int_status_enable,
459
AR6K_IRQ_ENABLE_REGS_SIZE,
460
HIF_WR_SYNC_BYTE_INC,
465
if (A_FAILED(status) && (pIOPacket != NULL)) {
466
AR6KFreeIOPacket(pDev,pIOPacket);
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A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
475
if (NULL == pDev->HifMaskUmaskRecvEvent) {
476
return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode);
478
return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode);
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A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
484
if (NULL == pDev->HifMaskUmaskRecvEvent) {
485
return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode);
487
return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode);
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A_STATUS DevWaitForPendingRecv(AR6K_DEVICE *pDev,A_UINT32 TimeoutInMs,A_BOOL *pbIsRecvPending)
493
A_STATUS status = A_OK;
494
A_UCHAR host_int_status = 0x0;
495
A_UINT32 counter = 0x0;
497
if(TimeoutInMs < 100)
502
counter = TimeoutInMs / 100;
506
//Read the Host Interrupt Status Register
507
status = HIFReadWrite(pDev->HIFDevice,
508
HOST_INT_STATUS_ADDRESS,
511
HIF_RD_SYNC_BYTE_INC,
515
AR_DEBUG_PRINTF(ATH_LOG_ERR,("DevWaitForPendingRecv:Read HOST_INT_STATUS_ADDRESS Failed 0x%X\n",status));
519
host_int_status = A_SUCCESS(status) ? (host_int_status & (1 << 0)):0;
523
*pbIsRecvPending = FALSE;
528
*pbIsRecvPending = TRUE;
539
void DevDumpRegisters(AR6K_DEVICE *pDev,
540
AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs,
541
AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs)
544
AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("\n<------- Register Table -------->\n"));
546
if (pIrqProcRegs != NULL) {
547
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
548
("Host Int Status: 0x%x\n",pIrqProcRegs->host_int_status));
549
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
550
("CPU Int Status: 0x%x\n",pIrqProcRegs->cpu_int_status));
551
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
552
("Error Int Status: 0x%x\n",pIrqProcRegs->error_int_status));
553
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
554
("Counter Int Status: 0x%x\n",pIrqProcRegs->counter_int_status));
555
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
556
("Mbox Frame: 0x%x\n",pIrqProcRegs->mbox_frame));
557
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
558
("Rx Lookahead Valid: 0x%x\n",pIrqProcRegs->rx_lookahead_valid));
559
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
560
("Rx Lookahead 0: 0x%x\n",pIrqProcRegs->rx_lookahead[0]));
561
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
562
("Rx Lookahead 1: 0x%x\n",pIrqProcRegs->rx_lookahead[1]));
564
if (pDev->MailBoxInfo.GMboxAddress != 0) {
565
/* if the target supports GMBOX hardware, dump some additional state */
566
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
567
("GMBOX Host Int Status 2: 0x%x\n",pIrqProcRegs->host_int_status2));
568
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
569
("GMBOX RX Avail: 0x%x\n",pIrqProcRegs->gmbox_rx_avail));
570
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
571
("GMBOX lookahead alias 0: 0x%x\n",pIrqProcRegs->rx_gmbox_lookahead_alias[0]));
572
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
573
("GMBOX lookahead alias 1: 0x%x\n",pIrqProcRegs->rx_gmbox_lookahead_alias[1]));
578
if (pIrqEnableRegs != NULL) {
579
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
580
("Int Status Enable: 0x%x\n",pIrqEnableRegs->int_status_enable));
581
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
582
("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable));
584
AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------->\n"));
588
#define DEV_GET_VIRT_DMA_INFO(p) ((DEV_SCATTER_DMA_VIRTUAL_INFO *)((p)->HIFPrivate[0]))
590
static HIF_SCATTER_REQ *DevAllocScatterReq(HIF_DEVICE *Context)
593
AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
595
pItem = DL_ListRemoveItemFromHead(&pDev->ScatterReqHead);
598
return A_CONTAINING_STRUCT(pItem, HIF_SCATTER_REQ, ListLink);
603
static void DevFreeScatterReq(HIF_DEVICE *Context, HIF_SCATTER_REQ *pReq)
605
AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
607
DL_ListInsertTail(&pDev->ScatterReqHead, &pReq->ListLink);
611
A_STATUS DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, A_BOOL FromDMA)
613
A_UINT8 *pDMABuffer = NULL;
617
pDMABuffer = pReq->pScatterBounceBuffer;
619
if (pDMABuffer == NULL) {
624
remaining = (int)pReq->TotalLength;
626
for (i = 0; i < pReq->ValidScatterEntries; i++) {
628
length = min((int)pReq->ScatterList[i].Length, remaining);
630
if (length != (int)pReq->ScatterList[i].Length) {
632
/* there is a problem with the scatter list */
637
/* from DMA buffer */
638
A_MEMCPY(pReq->ScatterList[i].pBuffer, pDMABuffer , length);
641
A_MEMCPY(pDMABuffer, pReq->ScatterList[i].pBuffer, length);
644
pDMABuffer += length;
651
static void DevReadWriteScatterAsyncHandler(void *Context, HTC_PACKET *pPacket)
653
AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
654
HIF_SCATTER_REQ *pReq = (HIF_SCATTER_REQ *)pPacket->pPktContext;
656
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevReadWriteScatterAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
658
pReq->CompletionStatus = pPacket->Status;
660
AR6KFreeIOPacket(pDev,pPacket);
662
pReq->CompletionRoutine(pReq);
664
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevReadWriteScatterAsyncHandler \n"));
667
static A_STATUS DevReadWriteScatter(HIF_DEVICE *Context, HIF_SCATTER_REQ *pReq)
669
AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
670
A_STATUS status = A_OK;
671
HTC_PACKET *pIOPacket = NULL;
672
A_UINT32 request = pReq->Request;
676
if (pReq->TotalLength > AR6K_MAX_TRANSFER_SIZE_PER_SCATTER) {
677
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
678
("Invalid length: %d \n", pReq->TotalLength));
682
if (pReq->TotalLength == 0) {
687
if (request & HIF_ASYNCHRONOUS) {
688
/* use an I/O packet to carry this request */
689
pIOPacket = AR6KAllocIOPacket(pDev);
690
if (NULL == pIOPacket) {
691
status = A_NO_MEMORY;
695
/* save the request */
696
pIOPacket->pPktContext = pReq;
697
/* stick in our completion routine when the I/O operation completes */
698
pIOPacket->Completion = DevReadWriteScatterAsyncHandler;
699
pIOPacket->pContext = pDev;
702
if (request & HIF_WRITE) {
703
/* in virtual DMA, we are issuing the requests through the legacy HIFReadWrite API
704
* this API will adjust the address automatically for the last byte to fall on the mailbox
707
/* if the address is an extended address, we can adjust the address here since the extended
708
* address will bypass the normal checks in legacy HIF layers */
709
if (pReq->Address == pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedAddress) {
710
pReq->Address += pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedSize - pReq->TotalLength;
714
/* use legacy readwrite */
715
status = HIFReadWrite(pDev->HIFDevice,
717
DEV_GET_VIRT_DMA_INFO(pReq)->pVirtDmaBuffer,
720
(request & HIF_ASYNCHRONOUS) ? pIOPacket : NULL);
724
if ((status != A_PENDING) && A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) {
725
if (pIOPacket != NULL) {
726
AR6KFreeIOPacket(pDev,pIOPacket);
728
pReq->CompletionStatus = status;
729
pReq->CompletionRoutine(pReq);
737
static void DevCleanupVirtualScatterSupport(AR6K_DEVICE *pDev)
739
HIF_SCATTER_REQ *pReq;
742
pReq = DevAllocScatterReq((HIF_DEVICE *)pDev);
751
/* function to set up virtual scatter support if HIF layer has not implemented the interface */
752
static A_STATUS DevSetupVirtualScatterSupport(AR6K_DEVICE *pDev)
754
A_STATUS status = A_OK;
755
int bufferSize, sgreqSize;
757
DEV_SCATTER_DMA_VIRTUAL_INFO *pVirtualInfo;
758
HIF_SCATTER_REQ *pReq;
760
bufferSize = sizeof(DEV_SCATTER_DMA_VIRTUAL_INFO) +
761
2 * (A_GET_CACHE_LINE_BYTES()) + AR6K_MAX_TRANSFER_SIZE_PER_SCATTER;
763
sgreqSize = sizeof(HIF_SCATTER_REQ) +
764
(AR6K_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(HIF_SCATTER_ITEM));
766
for (i = 0; i < AR6K_SCATTER_REQS; i++) {
767
/* allocate the scatter request, buffer info and the actual virtual buffer itself */
768
pReq = (HIF_SCATTER_REQ *)A_MALLOC(sgreqSize + bufferSize);
771
status = A_NO_MEMORY;
775
A_MEMZERO(pReq, sgreqSize);
777
/* the virtual DMA starts after the scatter request struct */
778
pVirtualInfo = (DEV_SCATTER_DMA_VIRTUAL_INFO *)((A_UINT8 *)pReq + sgreqSize);
779
A_MEMZERO(pVirtualInfo, sizeof(DEV_SCATTER_DMA_VIRTUAL_INFO));
781
pVirtualInfo->pVirtDmaBuffer = &pVirtualInfo->DataArea[0];
782
/* align buffer to cache line in case host controller can actually DMA this */
783
pVirtualInfo->pVirtDmaBuffer = A_ALIGN_TO_CACHE_LINE(pVirtualInfo->pVirtDmaBuffer);
784
/* store the structure in the private area */
785
pReq->HIFPrivate[0] = pVirtualInfo;
786
/* we emulate a DMA bounce interface */
787
pReq->ScatterMethod = HIF_SCATTER_DMA_BOUNCE;
788
pReq->pScatterBounceBuffer = pVirtualInfo->pVirtDmaBuffer;
789
/* free request to the list */
790
DevFreeScatterReq((HIF_DEVICE *)pDev,pReq);
793
if (A_FAILED(status)) {
794
DevCleanupVirtualScatterSupport(pDev);
796
pDev->HifScatterInfo.pAllocateReqFunc = DevAllocScatterReq;
797
pDev->HifScatterInfo.pFreeReqFunc = DevFreeScatterReq;
798
pDev->HifScatterInfo.pReadWriteScatterFunc = DevReadWriteScatter;
799
if (pDev->MailBoxInfo.MboxBusIFType == MBOX_BUS_IF_SPI) {
800
AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("AR6K: SPI bus requires RX scatter limits\n"));
801
pDev->HifScatterInfo.MaxScatterEntries = AR6K_MIN_SCATTER_ENTRIES_PER_REQ;
802
pDev->HifScatterInfo.MaxTransferSizePerScatterReq = AR6K_MIN_TRANSFER_SIZE_PER_SCATTER;
804
pDev->HifScatterInfo.MaxScatterEntries = AR6K_SCATTER_ENTRIES_PER_REQ;
805
pDev->HifScatterInfo.MaxTransferSizePerScatterReq = AR6K_MAX_TRANSFER_SIZE_PER_SCATTER;
807
pDev->ScatterIsVirtual = TRUE;
814
A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer)
818
if (pDev->MailBoxInfo.Flags & HIF_MBOX_FLAG_NO_BUNDLING) {
819
AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HIF requires bundling disabled\n"));
823
status = HIFConfigureDevice(pDev->HIFDevice,
824
HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
825
&pDev->HifScatterInfo,
826
sizeof(pDev->HifScatterInfo));
828
if (A_FAILED(status)) {
829
AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
830
("AR6K: ** HIF layer does not support scatter requests (%d) \n",status));
832
/* we can try to use a virtual DMA scatter mechanism using legacy HIFReadWrite() */
833
status = DevSetupVirtualScatterSupport(pDev);
835
if (A_SUCCESS(status)) {
836
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
837
("AR6K: virtual scatter transfers enabled (max scatter items:%d: maxlen:%d) \n",
838
DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev)));
842
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
843
("AR6K: HIF layer supports scatter requests (max scatter items:%d: maxlen:%d) \n",
844
DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev)));
847
if (A_SUCCESS(status)) {
848
/* for the recv path, the maximum number of bytes per recv bundle is just limited
849
* by the maximum transfer size at the HIF layer */
850
pDev->MaxRecvBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq;
852
if (pDev->MailBoxInfo.MboxBusIFType == MBOX_BUS_IF_SPI) {
853
AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("AR6K : SPI bus requires TX bundling disabled\n"));
854
pDev->MaxSendBundleSize = 0;
856
/* for the send path, the max transfer size is limited by the existence and size of
857
* the extended mailbox address range */
858
if (pDev->MailBoxInfo.MboxProp[0].ExtendedAddress != 0) {
859
pDev->MaxSendBundleSize = pDev->MailBoxInfo.MboxProp[0].ExtendedSize;
862
pDev->MaxSendBundleSize = AR6K_LEGACY_MAX_WRITE_LENGTH;
865
if (pDev->MaxSendBundleSize > pDev->HifScatterInfo.MaxTransferSizePerScatterReq) {
866
/* limit send bundle size to what the HIF can support for scatter requests */
867
pDev->MaxSendBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq;
871
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
872
("AR6K: max recv: %d max send: %d \n",
873
DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev), DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev)));
879
A_STATUS DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, A_BOOL Read, A_BOOL Async)
885
pScatterReq->Request = (Async) ? HIF_RD_ASYNC_BLOCK_FIX : HIF_RD_SYNC_BLOCK_FIX;
886
pScatterReq->Address = pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX];
887
A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev));
889
A_UINT32 mailboxWidth;
891
/* write operation */
892
pScatterReq->Request = (Async) ? HIF_WR_ASYNC_BLOCK_INC : HIF_WR_SYNC_BLOCK_INC;
893
A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev));
894
if (pScatterReq->TotalLength > AR6K_LEGACY_MAX_WRITE_LENGTH) {
895
/* for large writes use the extended address */
896
pScatterReq->Address = pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedAddress;
897
mailboxWidth = pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedSize;
899
pScatterReq->Address = pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX];
900
mailboxWidth = AR6K_LEGACY_MAX_WRITE_LENGTH;
903
if (!pDev->ScatterIsVirtual) {
904
/* we are passing this scatter list down to the HIF layer' scatter request handler, fixup the address
905
* so that the last byte falls on the EOM, we do this for those HIFs that support the
907
pScatterReq->Address += (mailboxWidth - pScatterReq->TotalLength);
912
AR_DEBUG_PRINTF(ATH_DEBUG_RECV | ATH_DEBUG_SEND,
913
("DevSubmitScatterRequest, Entries: %d, Total Length: %d Mbox:0x%X (mode: %s : %s)\n",
914
pScatterReq->ValidScatterEntries,
915
pScatterReq->TotalLength,
916
pScatterReq->Address,
917
Async ? "ASYNC" : "SYNC",
918
(Read) ? "RD" : "WR"));
920
status = DEV_PREPARE_SCATTER_OPERATION(pScatterReq);
922
if (A_FAILED(status)) {
924
pScatterReq->CompletionStatus = status;
925
pScatterReq->CompletionRoutine(pScatterReq);
931
status = pDev->HifScatterInfo.pReadWriteScatterFunc(pDev->ScatterIsVirtual ? pDev : pDev->HIFDevice,
934
/* in sync mode, we can touch the scatter request */
935
pScatterReq->CompletionStatus = status;
936
DEV_FINISH_SCATTER_OPERATION(pScatterReq);
938
if (status == A_PENDING) {
947
#ifdef MBOXHW_UNIT_TEST
950
/* This is a mailbox hardware unit test that must be called in a schedulable context
951
* This test is very simple, it will send a list of buffers with a counting pattern
952
* and the target will invert the data and send the message back
954
* the unit test has the following constraints:
956
* The target has at least 8 buffers of 256 bytes each. The host will send
957
* the following pattern of buffers in rapid succession :
959
* 1 buffer - 128 bytes
960
* 1 buffer - 256 bytes
961
* 1 buffer - 512 bytes
962
* 1 buffer - 1024 bytes
964
* The host will send the buffers to one mailbox and wait for buffers to be reflected
965
* back from the same mailbox. The target sends the buffers FIFO order.
966
* Once the final buffer has been received for a mailbox, the next mailbox is tested.
969
* Note: To simplifythe test , we assume that the chosen buffer sizes
970
* will fall on a nice block pad
972
* It is expected that higher-order tests will be written to stress the mailboxes using
973
* a message-based protocol (with some performance timming) that can create more
974
* randomness in the packets sent over mailboxes.
978
#define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1))
980
#define BUFFER_BLOCK_PAD 128
996
#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \
997
A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \
998
A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \
999
A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) )
1001
#define TEST_BYTES (BUFFER1 + BUFFER2 + BUFFER3 + BUFFER4)
1003
#define TEST_CREDITS_RECV_TIMEOUT 100
1005
static A_UINT8 g_Buffer[TOTAL_BYTES];
1006
static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES];
1007
static A_UINT32 g_BlockSizes[AR6K_MAILBOXES];
1009
#define BUFFER_PROC_LIST_DEPTH 4
1011
typedef struct _BUFFER_PROC_LIST{
1017
#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \
1019
(pList)->pBuffer = (pCurrpos); \
1020
(pList)->length = (len); \
1021
(pCurrpos) += (len); \
1025
/* a simple and crude way to send different "message" sizes */
1026
static void AssembleBufferList(BUFFER_PROC_LIST *pList)
1028
A_UINT8 *pBuffer = g_Buffer;
1030
#if BUFFER_PROC_LIST_DEPTH < 4
1031
#error "Buffer processing list depth is not deep enough!!"
1034
PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer);
1035
PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer);
1036
PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer);
1037
PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer);
1041
#define FILL_ZERO TRUE
1042
#define FILL_COUNTING FALSE
1043
static void InitBuffers(A_BOOL Zero)
1045
A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer;
1048
/* fill buffer with 16 bit counting pattern or zeros */
1049
for (i = 0; i < (TOTAL_BYTES / 2) ; i++) {
1051
pBuffer16[i] = (A_UINT16)i;
1059
static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length)
1062
A_UINT16 startCount;
1063
A_BOOL success = TRUE;
1065
/* get the starting count */
1066
startCount = pBuffer16[0];
1067
/* invert it, this is the expected value */
1068
startCount = ~startCount;
1069
/* scan the buffer and verify */
1070
for (i = 0; i < (Length / 2) ; i++,startCount++) {
1071
/* target will invert all the data */
1072
if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) {
1074
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n",
1075
pBuffer16[i], ((A_UINT16)~startCount), i, Length));
1076
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n",
1077
pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3]));
1085
static A_BOOL CheckBuffers(void)
1088
A_BOOL success = TRUE;
1089
BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
1091
/* assemble the list */
1092
AssembleBufferList(checkList);
1094
/* scan the buffers and verify */
1095
for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) {
1096
success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length);
1098
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n",
1099
(A_UINT32)checkList[i].pBuffer, checkList[i].length));
1107
/* find the end marker for the last buffer we will be sending */
1108
static A_UINT16 GetEndMarker(void)
1111
BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
1113
/* fill up buffers with the normal counting pattern */
1114
InitBuffers(FILL_COUNTING);
1116
/* assemble the list we will be sending down */
1117
AssembleBufferList(checkList);
1118
/* point to the last 2 bytes of the last buffer */
1119
pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]);
1121
/* the last count in the last buffer is the marker */
1122
return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8);
1125
#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR
1127
/* send the ordered buffers to the target */
1128
static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox)
1130
A_STATUS status = A_OK;
1131
A_UINT32 request = HIF_WR_SYNC_BLOCK_INC;
1132
BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH];
1136
int totalwPadding = 0;
1138
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox));
1140
/* fill buffer with counting pattern */
1141
InitBuffers(FILL_COUNTING);
1143
/* assemble the order in which we send */
1144
AssembleBufferList(sendList);
1146
for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) {
1148
/* we are doing block transfers, so we need to pad everything to a block size */
1149
paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) &
1150
(~(g_BlockSizes[mbox] - 1));
1152
/* send each buffer synchronously */
1153
status = HIFReadWrite(pDev->HIFDevice,
1154
g_MailboxAddrs[mbox],
1155
sendList[i].pBuffer,
1159
if (status != A_OK) {
1162
totalBytes += sendList[i].length;
1163
totalwPadding += paddedLength;
1166
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox));
1171
/* poll the mailbox credit counter until we get a credit or timeout */
1172
static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits)
1174
A_STATUS status = A_OK;
1175
int timeout = TEST_CREDITS_RECV_TIMEOUT;
1176
A_UINT8 credits = 0;
1181
/* Read the counter register to get credits, this auto-decrements */
1182
address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4;
1183
status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits),
1184
HIF_RD_SYNC_BYTE_FIX, NULL);
1185
if (status != A_OK) {
1186
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
1187
("Unable to decrement the command credit count register (mbox=%d)\n",mbox));
1199
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
1200
(" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address));
1205
/* delay a little, target may not be ready */
1210
if (status == A_OK) {
1211
*pCredits = credits;
1218
/* wait for the buffers to come back */
1219
static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox)
1221
A_STATUS status = A_OK;
1222
A_UINT32 request = HIF_RD_SYNC_BLOCK_INC;
1223
BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH];
1229
int totalwPadding = 0;
1231
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox));
1233
/* zero the buffers */
1234
InitBuffers(FILL_ZERO);
1236
/* assemble the order in which we should receive */
1237
AssembleBufferList(recvList);
1241
while (curBuffer < BUFFER_PROC_LIST_DEPTH) {
1243
/* get number of buffers that have been completed, this blocks
1244
* until we get at least 1 credit or it times out */
1245
status = GetCredits(pDev, mbox, &credits);
1247
if (status != A_OK) {
1251
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox));
1253
/* get all the buffers that are sitting on the queue */
1254
for (i = 0; i < credits; i++) {
1255
A_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH);
1256
/* recv the current buffer synchronously, the buffers should come back in
1257
* order... with padding applied by the target */
1258
paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) &
1259
(~(g_BlockSizes[mbox] - 1));
1261
status = HIFReadWrite(pDev->HIFDevice,
1262
g_MailboxAddrs[mbox],
1263
recvList[curBuffer].pBuffer,
1267
if (status != A_OK) {
1268
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n",
1269
recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox]));
1273
totalwPadding += paddedLength;
1274
totalBytes += recvList[curBuffer].length;
1278
if (status != A_OK) {
1281
/* go back and get some more */
1285
if (totalBytes != TEST_BYTES) {
1288
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n",
1289
mbox, totalBytes, totalwPadding));
1297
static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox)
1302
/* send out buffers */
1303
status = SendBuffers(pDev,mbox);
1305
if (status != A_OK) {
1306
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox));
1310
/* go get them, this will block */
1311
status = RecvBuffers(pDev, mbox);
1313
if (status != A_OK) {
1314
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox));
1318
/* check the returned data patterns */
1319
if (!CheckBuffers()) {
1320
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox));
1325
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox));
1332
/* here is where the test starts */
1333
A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev)
1344
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START - \n"));
1347
/* get the addresses for all 4 mailboxes */
1348
status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
1349
g_MailboxAddrs, sizeof(g_MailboxAddrs));
1351
if (status != A_OK) {
1356
/* get the block sizes */
1357
status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
1358
g_BlockSizes, sizeof(g_BlockSizes));
1360
if (status != A_OK) {
1365
/* note, the HIF layer usually reports mbox 0 to have a block size of
1366
* 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes
1368
g_BlockSizes[0] = g_BlockSizes[1];
1369
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0]));
1371
if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) {
1372
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n",
1373
g_BlockSizes[1], BUFFER_BLOCK_PAD));
1377
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n"));
1379
/* the target lets us know it is ready by giving us 1 credit on
1381
status = GetCredits(pDev, 0, &credits);
1383
if (status != A_OK) {
1384
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n"));
1388
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n"));
1390
/* read the first 4 scratch registers */
1391
status = HIFReadWrite(pDev->HIFDevice,
1395
HIF_RD_SYNC_BYTE_INC,
1398
if (status != A_OK) {
1399
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n"));
1403
numBufs = params[0];
1404
bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]);
1406
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE,
1407
("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n",
1408
numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES));
1410
if ((numBufs * bufferSize) < TOTAL_BYTES) {
1411
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n",
1412
TOTAL_BYTES, (numBufs*bufferSize)));
1417
temp = GetEndMarker();
1419
status = HIFReadWrite(pDev->HIFDevice,
1420
SCRATCH_ADDRESS + 4,
1423
HIF_WR_SYNC_BYTE_INC,
1426
if (status != A_OK) {
1427
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n"));
1431
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp));
1433
temp = (A_UINT16)g_BlockSizes[1];
1434
/* convert to a mask */
1436
status = HIFReadWrite(pDev->HIFDevice,
1437
SCRATCH_ADDRESS + 6,
1440
HIF_WR_SYNC_BYTE_INC,
1443
if (status != A_OK) {
1444
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n"));
1448
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp));
1450
/* execute the test on each mailbox */
1451
for (i = 0; i < AR6K_MAILBOXES; i++) {
1452
status = DoOneMboxHWTest(pDev, i);
1453
if (status != A_OK) {
1460
if (status == A_OK) {
1461
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! - \n"));
1463
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! - \n"));
1465
/* don't let HTC_Start continue, the target is actually not running any HTC code */
added
removed
updates/compat-wireless-2.6.37/drivers/staging/ath6kl/htc2/AR6000/ar6k.c
