4
* Copyright (c) 2004,2005 by Sun Microsystems, Inc.
6
* Created on Apr 20, 2005
9
/* Verilog for cell testCell{sch} from Library jtag */
10
/* Created on Tue April 26, 2005 11:27:36 */
11
/* Last revised on Tue April 26, 2005 11:29:37 */
12
/* Written on Tue April 26, 2005 11:30:54 by Electric VLSI Design System, version 8.02l */
14
module redFour__NMOSwk_X_1_Delay_100(g, d, s);
20
rtranif1 #(100) NMOSfwk_0 (d, s, g);
21
endmodule /* redFour__NMOSwk_X_1_Delay_100 */
23
module redFour__PMOSwk_X_0_833_Delay_100(g, d, s);
29
rtranif0 #(100) PMOSfwk_0 (d, s, g);
30
endmodule /* redFour__PMOSwk_X_0_833_Delay_100 */
32
module scanChainFive__scanL(in, out);
40
redFour__NMOSwk_X_1_Delay_100 NMOSwk_0(.g(out), .d(in), .s(net_7));
41
redFour__NMOSwk_X_1_Delay_100 NMOSwk_1(.g(out), .d(net_7), .s(gnd));
42
redFour__PMOSwk_X_0_833_Delay_100 PMOSwk_0(.g(out), .d(net_4), .s(vdd));
43
redFour__PMOSwk_X_0_833_Delay_100 PMOSwk_1(.g(out), .d(in), .s(net_4));
44
not (strong0, strong1) #(100) invV_0 (out, in);
45
endmodule /* scanChainFive__scanL */
47
module redFour__NMOS_X_6_667_Delay_100(g, d, s);
53
tranif1 #(100) NMOSf_0 (d, s, g);
54
endmodule /* redFour__NMOS_X_6_667_Delay_100 */
56
module redFour__PMOS_X_3_333_Delay_100(g, d, s);
62
tranif0 #(100) PMOSf_0 (d, s, g);
63
endmodule /* redFour__PMOS_X_3_333_Delay_100 */
65
module scanChainFive__scanP(in, src, drn);
74
redFour__NMOS_X_6_667_Delay_100 NMOS_0(.g(in), .d(drn), .s(src));
75
redFour__PMOS_X_3_333_Delay_100 PMOS_0(.g(net_1), .d(drn), .s(src));
76
not (strong0, strong1) #(0) inv_0 (net_1, in);
77
endmodule /* scanChainFive__scanP */
79
module scanChainFive__scanRL(phi1, phi2, rd, sin, sout);
88
wire net_0, net_2, net_3;
90
scanChainFive__scanL foo1(.in(net_2), .out(net_3));
91
scanChainFive__scanL foo2(.in(net_0), .out(sout));
92
scanChainFive__scanP scanP_0(.in(rd), .src(vdd), .drn(net_0));
93
scanChainFive__scanP scanP_1(.in(phi1), .src(net_3), .drn(net_0));
94
scanChainFive__scanP scanP_2(.in(phi2), .src(sin), .drn(net_2));
95
endmodule /* scanChainFive__scanRL */
97
module jtag__BR(SDI, phi1, phi2, read, SDO);
106
scanChainFive__scanRL scanRL_0(.phi1(phi1), .phi2(phi2), .rd(read),
107
.sin(SDI), .sout(SDO));
108
endmodule /* jtag__BR */
110
module scanChainFive__scanIRH(mclr, phi1, phi2, rd, sin, wr, dout, doutb,
124
wire net_2, net_4, net_6, net_7;
126
scanChainFive__scanL foo1(.in(net_6), .out(net_7));
127
scanChainFive__scanL foo2(.in(net_2), .out(sout));
128
scanChainFive__scanL foo3(.in(net_4), .out(doutb));
129
not (strong0, strong1) #(100) invLT_0 (dout, doutb);
130
scanChainFive__scanP scanP_0(.in(wr), .src(sout), .drn(net_4));
131
scanChainFive__scanP scanP_1(.in(rd), .src(gnd), .drn(net_2));
132
scanChainFive__scanP scanP_2(.in(mclr), .src(vdd), .drn(net_4));
133
scanChainFive__scanP scanP_3(.in(phi1), .src(net_7), .drn(net_2));
134
scanChainFive__scanP scanP_4(.in(phi2), .src(sin), .drn(net_6));
135
endmodule /* scanChainFive__scanIRH */
137
module scanChainFive__scanIRL(mclr, phi1, phi2, rd, sin, wr, dout, doutb,
151
wire net_2, net_3, net_4, net_6;
153
scanChainFive__scanL foo1(.in(net_2), .out(net_3));
154
scanChainFive__scanL foo2(.in(net_4), .out(sout));
155
scanChainFive__scanL foo3(.in(net_6), .out(doutb));
156
not (strong0, strong1) #(100) invLT_0 (dout, doutb);
157
scanChainFive__scanP scanP_0(.in(rd), .src(vdd), .drn(net_4));
158
scanChainFive__scanP scanP_1(.in(mclr), .src(vdd), .drn(net_6));
159
scanChainFive__scanP scanP_2(.in(wr), .src(sout), .drn(net_6));
160
scanChainFive__scanP scanP_3(.in(phi1), .src(net_3), .drn(net_4));
161
scanChainFive__scanP scanP_4(.in(phi2), .src(sin), .drn(net_2));
162
endmodule /* scanChainFive__scanIRL */
164
module jtag__IR(SDI, phi1, phi2, read, reset, write, IR, IRb, SDO);
177
wire net_1, net_2, net_3, net_4, net_5, net_6, net_7;
179
scanChainFive__scanIRH scanIRH_0(.mclr(reset), .phi1(phi1), .phi2(phi2),
180
.rd(read), .sin(net_1), .wr(write), .dout(IR[1]), .doutb(IRb[1]),
182
scanChainFive__scanIRL scanIRL_0(.mclr(reset), .phi1(phi1), .phi2(phi2),
183
.rd(read), .sin(net_3), .wr(write), .dout(IR[7]), .doutb(IRb[7]),
185
scanChainFive__scanIRL scanIRL_1(.mclr(reset), .phi1(phi1), .phi2(phi2),
186
.rd(read), .sin(net_5), .wr(write), .dout(IR[5]), .doutb(IRb[5]),
188
scanChainFive__scanIRL scanIRL_2(.mclr(reset), .phi1(phi1), .phi2(phi2),
189
.rd(read), .sin(net_2), .wr(write), .dout(IR[6]), .doutb(IRb[6]),
191
scanChainFive__scanIRL scanIRL_3(.mclr(reset), .phi1(phi1), .phi2(phi2),
192
.rd(read), .sin(net_7), .wr(write), .dout(IR[3]), .doutb(IRb[3]),
194
scanChainFive__scanIRL scanIRL_4(.mclr(reset), .phi1(phi1), .phi2(phi2),
195
.rd(read), .sin(net_6), .wr(write), .dout(IR[2]), .doutb(IRb[2]),
197
scanChainFive__scanIRL scanIRL_5(.mclr(reset), .phi1(phi1), .phi2(phi2),
198
.rd(read), .sin(net_4), .wr(write), .dout(IR[4]), .doutb(IRb[4]),
200
scanChainFive__scanIRL scanIRL_6(.mclr(reset), .phi1(phi1), .phi2(phi2),
201
.rd(read), .sin(SDI), .wr(write), .dout(IR[8]), .doutb(IRb[8]),
203
endmodule /* jtag__IR */
205
module redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
213
nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
214
endmodule /* redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 */
216
module jtag__IRdecode(IR, IRb, Bypass, ExTest, SamplePreload, ScanPath);
221
output SamplePreload;
222
output [12:0] ScanPath;
226
wire H00, H01, H10, H11, L00, L01, L10, L11, net_19, net_21, net_23, net_25;
227
wire net_26, net_27, net_28, net_29, net_30, net_31, net_32, net_33, net_34;
228
wire net_35, net_36, net_37;
230
not (strong0, strong1) #(100) inv_0 (Bypass, net_19);
231
not (strong0, strong1) #(100) inv_1 (SamplePreload, net_21);
232
not (strong0, strong1) #(100) inv_2 (ExTest, net_23);
233
not (strong0, strong1) #(100) inv_3 (ScanPath[12], net_25);
234
not (strong0, strong1) #(100) inv_4 (ScanPath[11], net_26);
235
not (strong0, strong1) #(100) inv_5 (ScanPath[10], net_27);
236
not (strong0, strong1) #(100) inv_6 (ScanPath[9], net_28);
237
not (strong0, strong1) #(100) inv_7 (ScanPath[8], net_29);
238
not (strong0, strong1) #(100) inv_8 (ScanPath[7], net_30);
239
not (strong0, strong1) #(100) inv_9 (ScanPath[6], net_31);
240
not (strong0, strong1) #(100) inv_10 (ScanPath[5], net_32);
241
not (strong0, strong1) #(100) inv_11 (ScanPath[4], net_33);
242
not (strong0, strong1) #(100) inv_12 (ScanPath[3], net_34);
243
not (strong0, strong1) #(100) inv_13 (ScanPath[2], net_35);
244
not (strong0, strong1) #(100) inv_14 (ScanPath[1], net_36);
245
not (strong0, strong1) #(100) inv_15 (ScanPath[0], net_37);
246
nand (strong0, strong1) #(100) nand2_0 (net_19, L11, H11);
247
nand (strong0, strong1) #(100) nand2_1 (net_21, L10, H11);
248
nand (strong0, strong1) #(100) nand2_2 (net_23, L01, H11);
249
nand (strong0, strong1) #(100) nand2_3 (net_25, L00, H11);
250
nand (strong0, strong1) #(100) nand2_4 (net_26, L11, H10);
251
nand (strong0, strong1) #(100) nand2_5 (net_27, L10, H10);
252
nand (strong0, strong1) #(100) nand2_6 (net_28, L01, H10);
253
nand (strong0, strong1) #(100) nand2_7 (net_29, L00, H10);
254
nand (strong0, strong1) #(100) nand2_8 (net_30, L11, H01);
255
nand (strong0, strong1) #(100) nand2_9 (net_31, L10, H01);
256
nand (strong0, strong1) #(100) nand2_10 (net_32, L01, H01);
257
nand (strong0, strong1) #(100) nand2_11 (net_33, L00, H01);
258
nand (strong0, strong1) #(100) nand2_12 (net_34, L11, H00);
259
nand (strong0, strong1) #(100) nand2_13 (net_35, L10, H00);
260
nand (strong0, strong1) #(100) nand2_14 (net_36, L01, H00);
261
nand (strong0, strong1) #(100) nand2_15 (net_37, L00, H00);
262
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
263
nor2n_0(.ina(IR[1]), .inb(IR[2]), .out(L00));
264
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
265
nor2n_1(.ina(IRb[1]), .inb(IR[2]), .out(L01));
266
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
267
nor2n_2(.ina(IR[1]), .inb(IRb[2]), .out(L10));
268
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
269
nor2n_3(.ina(IRb[1]), .inb(IRb[2]), .out(L11));
270
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
271
nor2n_4(.ina(IR[3]), .inb(IR[4]), .out(H00));
272
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
273
nor2n_5(.ina(IRb[3]), .inb(IR[4]), .out(H01));
274
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
275
nor2n_6(.ina(IR[3]), .inb(IRb[4]), .out(H10));
276
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
277
nor2n_7(.ina(IRb[3]), .inb(IRb[4]), .out(H11));
278
endmodule /* jtag__IRdecode */
280
module redFour__PMOSwk_X_0_222_Delay_100(g, d, s);
286
rtranif0 #(100) PMOSfwk_0 (d, s, g);
287
endmodule /* redFour__PMOSwk_X_0_222_Delay_100 */
289
module jtag__clockGen(clk, phi1_fb, phi2_fb, phi1_out, phi2_out);
298
wire net_0, net_1, net_3, net_4, net_6;
300
not (strong0, strong1) #(100) inv_0 (phi2_out, net_3);
301
not (strong0, strong1) #(100) inv_1 (phi1_out, net_6);
302
not (strong0, strong1) #(100) inv_2 (net_4, clk);
303
not (strong0, strong1) #(100) invLT_0 (net_0, phi1_fb);
304
not (strong0, strong1) #(100) invLT_1 (net_1, phi2_fb);
305
nand (strong0, strong1) #(100) nand2_0 (net_3, net_0, net_4);
306
nand (strong0, strong1) #(100) nand2_1 (net_6, net_1, clk);
307
endmodule /* jtag__clockGen */
309
module jtag__capture_ctl(capture, phi2, sel, out, phi1);
318
wire net_1, net_2, net_3, net_4;
320
scanChainFive__scanL foo(.in(net_2), .out(net_3));
321
not (strong0, strong1) #(100) inv_0 (net_1, capture);
322
not (strong0, strong1) #(100) inv_1 (out, net_4);
323
nand (strong0, strong1) #(100) nand3_0 (net_4, sel, net_3, phi1);
324
scanChainFive__scanP scanP_0(.in(phi2), .src(net_1), .drn(net_2));
325
endmodule /* jtag__capture_ctl */
327
module jtag__shift_ctl(phi1_fb, phi2_fb, sel, shift, phi1_out, phi2_out,
340
wire net_1, net_2, net_3, net_4, net_7;
342
jtag__clockGen clockGen_0(.clk(net_7), .phi1_fb(phi1_fb), .phi2_fb(phi2_fb),
343
.phi1_out(phi1_out), .phi2_out(phi2_out));
344
scanChainFive__scanL foo(.in(net_2), .out(net_3));
345
not (strong0, strong1) #(100) inv_0 (net_7, net_4);
346
not (strong0, strong1) #(100) inv_1 (net_1, shift);
347
nand (strong0, strong1) #(100) nand3_0 (net_4, sel, net_3, phi1_in);
348
scanChainFive__scanP scanP_0(.in(phi2_in), .src(net_1), .drn(net_2));
349
endmodule /* jtag__shift_ctl */
351
module jtag__update_ctl(sel, update, out, phi2);
361
not (strong0, strong1) #(100) inv_0 (out, net_1);
362
nand (strong0, strong1) #(100) nand3_0 (net_1, sel, update, phi2);
363
endmodule /* jtag__update_ctl */
365
module jtag__jtagIRControl(capture, phi1_fb, phi1_in, phi2_fb, phi2_in, shift,
366
update, phi1_out, phi2_out, read, write);
381
jtag__capture_ctl capture__0(.capture(capture), .phi2(phi2_in), .sel(vdd),
382
.out(read), .phi1(phi1_in));
383
jtag__shift_ctl shift_ct_0(.phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .sel(vdd),
384
.shift(shift), .phi1_out(phi1_out), .phi2_out(phi2_out),
385
.phi1_in(phi1_in), .phi2_in(phi2_in));
386
jtag__update_ctl update_c_0(.sel(vdd), .update(update), .out(write),
388
endmodule /* jtag__jtagIRControl */
390
module redFour__NMOS_X_8_Delay_100(g, d, s);
396
tranif1 #(100) NMOSf_0 (d, s, g);
397
endmodule /* redFour__NMOS_X_8_Delay_100 */
399
module redFour__PMOS_X_4_Delay_100(g, d, s);
405
tranif0 #(100) PMOSf_0 (d, s, g);
406
endmodule /* redFour__PMOS_X_4_Delay_100 */
408
module jtag__tsinvBig(Din, en, enb, Dout);
416
wire net_13, net_14, net_22, net_23;
418
redFour__NMOS_X_8_Delay_100 NMOS_0(.g(Din), .d(net_13), .s(gnd));
419
redFour__NMOS_X_8_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_13));
420
redFour__NMOS_X_8_Delay_100 NMOS_2(.g(en), .d(Dout), .s(net_23));
421
redFour__NMOS_X_8_Delay_100 NMOS_3(.g(Din), .d(net_23), .s(gnd));
422
redFour__PMOS_X_4_Delay_100 PMOS_0(.g(enb), .d(Dout), .s(net_14));
423
redFour__PMOS_X_4_Delay_100 PMOS_1(.g(Din), .d(net_14), .s(vdd));
424
redFour__PMOS_X_4_Delay_100 PMOS_2(.g(enb), .d(Dout), .s(net_22));
425
redFour__PMOS_X_4_Delay_100 PMOS_3(.g(Din), .d(net_22), .s(vdd));
426
endmodule /* jtag__tsinvBig */
428
module jtag__jtagScanControl(TDI, capture, phi1_fb, phi1_in, phi2_fb, phi2_in,
429
sel, shift, update, TDO, phi1_out, phi2_out, read, write);
449
jtag__capture_ctl capture__0(.capture(capture), .phi2(phi2_in), .sel(sel),
450
.out(read), .phi1(phi1_in));
451
not (strong0, strong1) #(100) inv_0 (net_2, sel);
452
not (strong0, strong1) #(100) inv_1 (net_0, TDI);
453
jtag__shift_ctl shift_ct_0(.phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .sel(sel),
454
.shift(shift), .phi1_out(phi1_out), .phi2_out(phi2_out),
455
.phi1_in(phi1_in), .phi2_in(phi2_in));
456
jtag__tsinvBig tsinvBig_0(.Din(net_0), .en(sel), .enb(net_2), .Dout(TDO));
457
jtag__update_ctl update_c_0(.sel(sel), .update(update), .out(write),
459
endmodule /* jtag__jtagScanControl */
461
module redFour__NMOS_X_5_667_Delay_100(g, d, s);
467
tranif1 #(100) NMOSf_0 (d, s, g);
468
endmodule /* redFour__NMOS_X_5_667_Delay_100 */
470
module redFour__PMOS_X_2_833_Delay_100(g, d, s);
476
tranif0 #(100) PMOSf_0 (d, s, g);
477
endmodule /* redFour__PMOS_X_2_833_Delay_100 */
479
module jtag__tsinv(Din, Dout, en, enb);
489
redFour__NMOS_X_5_667_Delay_100 NMOS_0(.g(Din), .d(net_1), .s(gnd));
490
redFour__NMOS_X_5_667_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_1));
491
redFour__PMOS_X_2_833_Delay_100 PMOS_0(.g(Din), .d(net_2), .s(vdd));
492
redFour__PMOS_X_2_833_Delay_100 PMOS_1(.g(enb), .d(Dout), .s(net_2));
493
endmodule /* jtag__tsinv */
495
module jtag__mux2_phi2(Din0, Din1, phi2, sel, Dout);
504
wire net_1, net_2, net_3, net_5, net_6;
506
not (strong0, strong1) #(100) inv_0 (net_5, sel);
507
not (strong0, strong1) #(100) inv_1 (net_1, net_6);
508
not (strong0, strong1) #(100) inv_2 (Dout, net_3);
509
scanChainFive__scanL scanL_0(.in(net_2), .out(net_3));
510
scanChainFive__scanP scanP_0(.in(phi2), .src(net_1), .drn(net_2));
511
jtag__tsinv tsinv_0(.Din(Din0), .Dout(net_6), .en(net_5), .enb(sel));
512
jtag__tsinv tsinv_1(.Din(Din1), .Dout(net_6), .en(sel), .enb(net_5));
513
endmodule /* jtag__mux2_phi2 */
515
module jtag__scanAmp1w1648(in, out);
523
tranif1 nmos_0(gnd, net_0, in);
524
tranif1 nmos_1(gnd, out, net_0);
525
tranif0 pmos_0(net_0, vdd, in);
526
tranif0 pmos_1(out, vdd, net_0);
527
endmodule /* jtag__scanAmp1w1648 */
529
module redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
537
nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
538
endmodule /* redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1 */
540
module redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
548
nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
549
endmodule /* redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 */
551
module redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
559
nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
560
endmodule /* redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 */
562
module orangeTSMC180nm__wire_R_26m_100_C_0_025f(a);
566
endmodule /* orangeTSMC180nm__wire_R_26m_100_C_0_025f */
568
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100(a);
572
orangeTSMC180nm__wire_R_26m_100_C_0_025f wire_0(.a(a));
573
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 */
575
module jtag__o2a(inAa, inAb, inOb, out);
585
nor (strong0, strong1) #(100) nor2_0 (net_0, inAa, inAb);
586
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
587
nor2n_0(.ina(inOb), .inb(net_0), .out(out));
588
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_0(.a(net_0));
589
endmodule /* jtag__o2a */
591
module orangeTSMC180nm__wire_R_26m_500_C_0_025f(a);
595
endmodule /* orangeTSMC180nm__wire_R_26m_500_C_0_025f */
597
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500(a);
601
orangeTSMC180nm__wire_R_26m_500_C_0_025f wire_0(.a(a));
602
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500 */
604
module jtag__slaveBit(din, phi2, slave);
613
not (strong0, strong1) #(100) inv_0 (slave, net_7);
614
scanChainFive__scanL scanL_0(.in(net_6), .out(net_7));
615
scanChainFive__scanP scanP_0(.in(phi2), .src(din), .drn(net_6));
616
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500 wire180_0(.a(slave));
617
endmodule /* jtag__slaveBit */
619
module redFour__NMOS_X_1_667_Delay_100(g, d, s);
625
tranif1 #(100) NMOSf_0 (d, s, g);
626
endmodule /* redFour__NMOS_X_1_667_Delay_100 */
628
module orangeTSMC180nm__wire_R_26m_750_C_0_025f(a);
632
endmodule /* orangeTSMC180nm__wire_R_26m_750_C_0_025f */
634
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750(a);
638
orangeTSMC180nm__wire_R_26m_750_C_0_025f wire_0(.a(a));
639
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 */
641
module orangeTSMC180nm__wire_R_26m_1000_C_0_025f(a);
645
endmodule /* orangeTSMC180nm__wire_R_26m_1000_C_0_025f */
647
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000(a);
651
orangeTSMC180nm__wire_R_26m_1000_C_0_025f wire_0(.a(a));
652
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 */
654
module jtag__stateBit(next, phi1, phi2, rst, master, slave, slaveBar);
665
wire net_12, net_13, net_14, net_17;
667
redFour__NMOS_X_1_667_Delay_100 NMOS_0(.g(rst), .d(net_12), .s(gnd));
668
not (strong0, strong1) #(100) inv_0 (slave, slaveBar);
669
not (strong0, strong1) #(100) inv_1 (slaveBar, net_17);
670
not (strong0, strong1) #(100) inv_2 (master, net_13);
671
scanChainFive__scanL scanL_0(.in(net_12), .out(net_13));
672
scanChainFive__scanL scanL_1(.in(net_14), .out(net_17));
673
scanChainFive__scanP scanP_0(.in(phi1), .src(next), .drn(net_12));
674
scanChainFive__scanP scanP_1(.in(phi2), .src(net_13), .drn(net_14));
675
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 wire180_0(.a(master));
676
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 wire180_1(.a(slave));
677
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500
678
wire180_2(.a(slaveBar));
679
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_3(.a(next));
680
endmodule /* jtag__stateBit */
682
module redFour__PMOS_X_1_5_Delay_100(g, d, s);
688
tranif0 #(100) PMOSf_0 (d, s, g);
689
endmodule /* redFour__PMOS_X_1_5_Delay_100 */
691
module jtag__stateBitHI(next, phi1, phi2, rstb, master, slave, slaveBar);
702
wire net_10, net_11, net_12, net_15;
704
redFour__PMOS_X_1_5_Delay_100 PMOS_0(.g(rstb), .d(net_12), .s(vdd));
705
not (strong0, strong1) #(100) inv_0 (slave, slaveBar);
706
not (strong0, strong1) #(100) inv_1 (slaveBar, net_15);
707
not (strong0, strong1) #(100) inv_2 (master, net_10);
708
scanChainFive__scanL scanL_0(.in(net_12), .out(net_10));
709
scanChainFive__scanL scanL_1(.in(net_11), .out(net_15));
710
scanChainFive__scanP scanP_0(.in(phi1), .src(next), .drn(net_12));
711
scanChainFive__scanP scanP_1(.in(phi2), .src(net_10), .drn(net_11));
712
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 wire180_0(.a(slave));
713
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500
714
wire180_1(.a(slaveBar));
715
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_2(.a(next));
716
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 wire180_3(.a(master));
717
endmodule /* jtag__stateBitHI */
719
module orangeTSMC180nm__wire_R_26m_675_C_0_025f(a);
723
endmodule /* orangeTSMC180nm__wire_R_26m_675_C_0_025f */
725
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675(a);
729
orangeTSMC180nm__wire_R_26m_675_C_0_025f wire_0(.a(a));
730
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675 */
732
module orangeTSMC180nm__wire_R_26m_1500_C_0_025f(a);
736
endmodule /* orangeTSMC180nm__wire_R_26m_1500_C_0_025f */
738
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500(a);
742
orangeTSMC180nm__wire_R_26m_1500_C_0_025f wire_0(.a(a));
743
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500 */
745
module jtag__tapCtlJKL(TMS, TRSTb, phi1, phi2, CapDR, CapIR, Idle, PauseDR,
746
PauseIR, Reset, Reset_s, SelDR, SelIR, ShftDR, ShftIR, UpdDR, UpdIR,
747
X1DR, X1IR, X2DR, X2IR);
772
wire net_0, net_2, net_4, net_6, net_12, net_13, net_14, net_15, net_16;
773
wire net_17, net_18, net_19, net_20, net_22, net_23, net_24, net_25, net_26;
774
wire net_28, net_29, net_31, net_32, net_34, net_40, net_43, net_44, net_48;
775
wire net_50, net_52, net_54, net_55, net_56, net_58, net_59, net_60, net_64;
776
wire net_67, net_68, net_70, net_71, net_72, net_74, net_75, net_76, net_79;
777
wire net_80, rst, stateBit_1_slave, stateBit_5_slaveBar, stateBit_6_slaveBar;
778
wire stateBit_9_slaveBar, stateBit_10_slaveBar, stateBit_11_slave;
779
wire stateBit_12_slave;
781
not (strong0, strong1) #(100) inv_0 (rst, TRSTb);
782
not (strong0, strong1) #(100) inv_1 (net_24, net_12);
783
redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1
784
nand2n_0(.ina(net_13), .inb(net_14), .out(net_0));
785
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
786
nand2n_1(.ina(net_15), .inb(net_16), .out(net_4));
787
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
788
nand2n_2(.ina(net_17), .inb(net_18), .out(net_2));
789
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
790
nand2n_3(.ina(net_19), .inb(net_20), .out(net_6));
791
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
792
nor2n_0(.ina(net_12), .inb(net_23), .out(net_22));
793
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
794
nor2n_1(.ina(net_24), .inb(net_26), .out(net_25));
795
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
796
nor2n_2(.ina(net_24), .inb(net_29), .out(net_28));
797
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
798
nor2n_3(.ina(net_24), .inb(net_32), .out(net_31));
799
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
800
nor2n_4(.ina(net_12), .inb(net_26), .out(net_34));
801
jtag__o2a o2a_0(.inAa(net_2), .inAb(net_43), .inOb(net_12), .out(net_40));
802
jtag__o2a o2a_1(.inAa(net_6), .inAb(net_0), .inOb(net_12), .out(net_44));
803
jtag__o2a o2a_2(.inAa(net_50), .inAb(net_0), .inOb(net_24), .out(net_48));
804
jtag__o2a o2a_3(.inAa(net_54), .inAb(net_55), .inOb(net_12), .out(net_52));
805
jtag__o2a o2a_4(.inAa(net_58), .inAb(net_59), .inOb(net_12), .out(net_56));
806
jtag__o2a o2a_5(.inAa(net_58), .inAb(net_43), .inOb(net_24), .out(net_60));
807
jtag__o2a o2a_6(.inAa(net_54), .inAb(net_67), .inOb(net_24), .out(net_64));
808
jtag__o2a o2a_7(.inAa(net_70), .inAb(net_71), .inOb(net_24), .out(net_68));
809
jtag__o2a o2a_8(.inAa(net_74), .inAb(net_75), .inOb(net_24), .out(net_72));
810
jtag__o2a o2a_9(.inAa(Reset_s), .inAb(net_79), .inOb(net_24), .out(net_76));
811
jtag__o2a o2a_10(.inAa(net_4), .inAb(net_67), .inOb(net_12), .out(net_80));
812
jtag__slaveBit slaveBit_0(.din(TMS), .phi2(phi2), .slave(net_12));
813
jtag__stateBit stateBit_0(.next(net_25), .phi1(phi1), .phi2(phi2), .rst(rst),
814
.master(SelIR), .slave(net_79), .slaveBar(net_23));
815
jtag__stateBit stateBit_1(.next(net_48), .phi1(phi1), .phi2(phi2), .rst(rst),
816
.master(SelDR), .slave(stateBit_1_slave), .slaveBar(net_26));
817
jtag__stateBit stateBit_2(.next(net_34), .phi1(phi1), .phi2(phi2), .rst(rst),
818
.master(CapDR), .slave(net_75), .slaveBar(net_16));
819
jtag__stateBit stateBit_3(.next(net_22), .phi1(phi1), .phi2(phi2), .rst(rst),
820
.master(CapIR), .slave(net_71), .slaveBar(net_18));
821
jtag__stateBit stateBit_4(.next(net_44), .phi1(phi1), .phi2(phi2), .rst(rst),
822
.master(Idle), .slave(net_50), .slaveBar(net_20));
823
jtag__stateBit stateBit_5(.next(net_68), .phi1(phi1), .phi2(phi2), .rst(rst),
824
.master(X1IR), .slave(net_58), .slaveBar(stateBit_5_slaveBar));
825
jtag__stateBit stateBit_6(.next(net_72), .phi1(phi1), .phi2(phi2), .rst(rst),
826
.master(X1DR), .slave(net_54), .slaveBar(stateBit_6_slaveBar));
827
jtag__stateBit stateBit_7(.next(net_80), .phi1(phi1), .phi2(phi2), .rst(rst),
828
.master(ShftDR), .slave(net_74), .slaveBar(net_15));
829
jtag__stateBit stateBit_8(.next(net_40), .phi1(phi1), .phi2(phi2), .rst(rst),
830
.master(ShftIR), .slave(net_70), .slaveBar(net_17));
831
jtag__stateBit stateBit_9(.next(net_28), .phi1(phi1), .phi2(phi2), .rst(rst),
832
.master(X2IR), .slave(net_43), .slaveBar(stateBit_9_slaveBar));
833
jtag__stateBit stateBit_10(.next(net_31), .phi1(phi1), .phi2(phi2),
834
.rst(rst), .master(X2DR), .slave(net_67),
835
.slaveBar(stateBit_10_slaveBar));
836
jtag__stateBit stateBit_11(.next(net_64), .phi1(phi1), .phi2(phi2),
837
.rst(rst), .master(UpdDR), .slave(stateBit_11_slave),
839
jtag__stateBit stateBit_12(.next(net_60), .phi1(phi1), .phi2(phi2),
840
.rst(rst), .master(UpdIR), .slave(stateBit_12_slave),
842
jtag__stateBit stateBit_13(.next(net_56), .phi1(phi1), .phi2(phi2),
843
.rst(rst), .master(PauseIR), .slave(net_59), .slaveBar(net_29));
844
jtag__stateBit stateBit_14(.next(net_52), .phi1(phi1), .phi2(phi2),
845
.rst(rst), .master(PauseDR), .slave(net_55), .slaveBar(net_32));
846
jtag__stateBitHI stateBit_15(.next(net_76), .phi1(phi1), .phi2(phi2),
847
.rstb(TRSTb), .master(Reset), .slave(Reset_s), .slaveBar(net_19));
848
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_0(.a(net_4));
849
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_1(.a(net_2));
850
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_2(.a(net_6));
851
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675 wire180_3(.a(net_0));
852
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500 wire180_4(.a(rst));
853
endmodule /* jtag__tapCtlJKL */
855
module jtag__jtagControl(TCK, TDI, TDIx, TMS, TRSTb, phi1_fb, phi2_fb, Cap,
856
ExTest, SelBS, SelDR, Shft, TDOb, Upd, phi1, phi2);
876
wire jtagScan_0_write, net_0, net_1, net_2, net_3, net_6, net_8, net_10;
877
wire net_33, net_35, net_37, net_38, net_41, net_47, net_48, net_50, net_51;
878
wire net_52, net_55, net_56, net_62, net_64, net_68, net_73, net_75, net_79;
879
wire net_97, net_99, net_103, net_128, tapCtlJK_0_Idle, tapCtlJK_0_PauseDR;
880
wire tapCtlJK_0_PauseIR, tapCtlJK_0_Reset, tapCtlJK_0_SelDR, tapCtlJK_0_SelIR;
881
wire tapCtlJK_0_X1DR, tapCtlJK_0_X2DR, tapCtlJK_0_X2IR;
885
jtag__BR BR_0(.SDI(TDI), .phi1(net_68), .phi2(net_73), .read(net_99),
887
jtag__IR IR_0(.SDI(TDI), .phi1(net_79), .phi2(net_75), .read(net_55),
888
.reset(net_56), .write(net_103), .IR(IR[8:1]), .IRb(IRb[8:1]),
890
jtag__IRdecode IRdecode_0(.IR(IR[4:1]), .IRb(IRb[4:1]), .Bypass(net_41),
891
.ExTest(ExTest), .SamplePreload(net_47), .ScanPath(SelDR[12:0]));
892
redFour__PMOSwk_X_0_222_Delay_100 PMOSwk_0(.g(gnd), .d(TDIx), .s(vdd));
893
jtag__clockGen clockGen_0(.clk(TCK), .phi1_fb(phi1_fb), .phi2_fb(phi2_fb),
894
.phi1_out(net_10), .phi2_out(net_8));
895
not (strong0, strong1) #(100) inv_0 (net_0, net_3);
896
not (strong0, strong1) #(100) inv_1 (SelBS, net_48);
897
not (strong0, strong1) #(100) inv_2 (net_6, net_50);
898
not (strong0, strong1) #(100) inv_3 (Cap, net_37);
899
not (strong0, strong1) #(100) inv_4 (Shft, net_51);
900
not (strong0, strong1) #(100) inv_5 (net_51, net_52);
901
not (strong0, strong1) #(100) inv_6 (Upd, net_38);
902
jtag__jtagIRControl jtagIRCo_0(.capture(net_62), .phi1_fb(net_79),
903
.phi1_in(phi1), .phi2_fb(net_75), .phi2_in(phi2), .shift(net_2),
904
.update(net_64), .phi1_out(net_79), .phi2_out(net_75), .read(net_55),
906
jtag__jtagScanControl jtagScan_0(.TDI(net_97), .capture(Cap),
907
.phi1_fb(net_68), .phi1_in(phi1), .phi2_fb(net_73), .phi2_in(phi2),
908
.sel(net_41), .shift(Shft), .update(gnd), .TDO(TDIx), .phi1_out(net_68),
909
.phi2_out(net_73), .read(net_99), .write(jtagScan_0_write));
910
jtag__mux2_phi2 mux2_phi_0(.Din0(TDIx), .Din1(net_128), .phi2(phi2),
911
.sel(net_0), .Dout(net_50));
912
nand (strong0, strong1) #(100) nand2_0 (net_37, IR[8], net_35);
913
nand (strong0, strong1) #(100) nand2_1 (net_38, IR[7], net_33);
914
nor (strong0, strong1) #(100) nor2_0 (net_3, net_1, net_2);
915
nor (strong0, strong1) #(100) nor2_1 (net_48, net_47, ExTest);
916
jtag__scanAmp1w1648 scanAmp1_0(.in(net_6), .out(TDOb));
917
jtag__scanAmp1w1648 scanAmp1_1(.in(net_8), .out(phi2));
918
jtag__scanAmp1w1648 scanAmp1_2(.in(net_10), .out(phi1));
919
jtag__tapCtlJKL tapCtlJK_0(.TMS(TMS), .TRSTb(TRSTb), .phi1(phi1),
920
.phi2(phi2), .CapDR(net_35), .CapIR(net_62), .Idle(tapCtlJK_0_Idle),
921
.PauseDR(tapCtlJK_0_PauseDR), .PauseIR(tapCtlJK_0_PauseIR),
922
.Reset(tapCtlJK_0_Reset), .Reset_s(net_56), .SelDR(tapCtlJK_0_SelDR),
923
.SelIR(tapCtlJK_0_SelIR), .ShftDR(net_52), .ShftIR(net_2),
924
.UpdDR(net_33), .UpdIR(net_64), .X1DR(tapCtlJK_0_X1DR), .X1IR(net_1),
925
.X2DR(tapCtlJK_0_X2DR), .X2IR(tapCtlJK_0_X2IR));
926
endmodule /* jtag__jtagControl */
928
module jtag__JTAGamp(leaf, root);
934
jtag__scanAmp1w1648 toLeaf_5_(.in(root[5]), .out(leaf[5]));
935
jtag__scanAmp1w1648 toLeaf_4_(.in(root[4]), .out(leaf[4]));
936
jtag__scanAmp1w1648 toLeaf_3_(.in(root[3]), .out(leaf[3]));
937
jtag__scanAmp1w1648 toLeaf_2_(.in(root[2]), .out(leaf[2]));
938
jtag__scanAmp1w1648 toLeaf_1_(.in(root[1]), .out(leaf[1]));
939
endmodule /* jtag__JTAGamp */
941
module jtag__jtagScanCtlWBuf(TDI, cap, phi1, phi2, sel, shift, upd, TDO,
957
jtag__JTAGamp JTAGamp_0(.leaf(leaf[8:1]), .root({a[5], a[4], a[3], a[2],
959
jtag__jtagScanControl jtagScan_0(.TDI(leaf[8]), .capture(cap),
960
.phi1_fb(leaf[6]), .phi1_in(phi1), .phi2_fb(leaf[7]), .phi2_in(phi2),
961
.sel(sel), .shift(shift), .update(upd), .TDO(TDO), .phi1_out(a[3]),
962
.phi2_out(a[2]), .read(a[5]), .write(a[4]));
963
endmodule /* jtag__jtagScanCtlWBuf */
965
module jtag__jtagScanCtlGroup(TDI, capture, phi1_in, phi2_in, selBS, sel,
966
shift, update, TDO, BS, leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6,
967
leaf7, leaf8, leaf9, leaf10, leaf11, leaf12);
994
jtag__jtagScanCtlWBuf jtagScan_1(.TDI(TDI), .cap(capture), .phi1(phi1_in),
995
.phi2(phi2_in), .sel(sel[0]), .shift(shift), .upd(update), .TDO(TDO),
997
jtag__jtagScanCtlWBuf jtagScan_2(.TDI(TDI), .cap(capture), .phi1(phi1_in),
998
.phi2(phi2_in), .sel(sel[10]), .shift(shift), .upd(update), .TDO(TDO),
1000
jtag__jtagScanCtlWBuf jtagScan_3(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1001
.phi2(phi2_in), .sel(sel[12]), .shift(shift), .upd(update), .TDO(TDO),
1002
.leaf(leaf12[8:1]));
1003
jtag__jtagScanCtlWBuf jtagScan_4(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1004
.phi2(phi2_in), .sel(sel[11]), .shift(shift), .upd(update), .TDO(TDO),
1005
.leaf(leaf11[8:1]));
1006
jtag__jtagScanCtlWBuf jtagScan_5(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1007
.phi2(phi2_in), .sel(sel[9]), .shift(shift), .upd(update), .TDO(TDO),
1009
jtag__jtagScanCtlWBuf jtagScan_6(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1010
.phi2(phi2_in), .sel(sel[8]), .shift(shift), .upd(update), .TDO(TDO),
1012
jtag__jtagScanCtlWBuf jtagScan_7(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1013
.phi2(phi2_in), .sel(sel[6]), .shift(shift), .upd(update), .TDO(TDO),
1015
jtag__jtagScanCtlWBuf jtagScan_8(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1016
.phi2(phi2_in), .sel(sel[5]), .shift(shift), .upd(update), .TDO(TDO),
1018
jtag__jtagScanCtlWBuf jtagScan_9(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1019
.phi2(phi2_in), .sel(sel[4]), .shift(shift), .upd(update), .TDO(TDO),
1021
jtag__jtagScanCtlWBuf jtagScan_10(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1022
.phi2(phi2_in), .sel(sel[3]), .shift(shift), .upd(update), .TDO(TDO),
1024
jtag__jtagScanCtlWBuf jtagScan_11(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1025
.phi2(phi2_in), .sel(sel[2]), .shift(shift), .upd(update), .TDO(TDO),
1027
jtag__jtagScanCtlWBuf jtagScan_12(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1028
.phi2(phi2_in), .sel(sel[1]), .shift(shift), .upd(update), .TDO(TDO),
1030
jtag__jtagScanCtlWBuf jtagScan_13(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1031
.phi2(phi2_in), .sel(sel[7]), .shift(shift), .upd(update), .TDO(TDO),
1033
jtag__jtagScanCtlWBuf jtagScan_16(.TDI(TDI), .cap(capture), .phi1(phi1_in),
1034
.phi2(phi2_in), .sel(selBS), .shift(shift), .upd(update), .TDO(TDO),
1036
endmodule /* jtag__jtagScanCtlGroup */
1038
module jtag__jtagCentral_LEIGNORE_1(TCK, TDI, TMS, TRSTb, ExTest, TDOb, BS,
1039
leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6, leaf7, leaf8, leaf9,
1040
leaf10, leaf11, leaf12);
1064
wire net_10, net_14, net_15, net_17, net_24, net_25, net_50;
1067
jtag__jtagControl jtagCont_0(.TCK(TCK), .TDI(TDI), .TDIx(net_15), .TMS(TMS),
1068
.TRSTb(TRSTb), .phi1_fb(net_24), .phi2_fb(net_10), .Cap(net_25),
1069
.ExTest(ExTest), .SelBS(net_50), .SelDR({net_6[0], net_6[1], net_6[2],
1070
net_6[3], net_6[4], net_6[5], net_6[6], net_6[7], net_6[8], net_6[9],
1071
net_6[10], net_6[11], net_6[12]}), .Shft(net_17), .TDOb(TDOb),
1072
.Upd(net_14), .phi1(net_24), .phi2(net_10));
1073
jtag__jtagScanCtlGroup jtagScan_0(.TDI(TDI), .capture(net_25),
1074
.phi1_in(net_24), .phi2_in(net_10), .selBS(net_50), .sel({net_6[0],
1075
net_6[1], net_6[2], net_6[3], net_6[4], net_6[5], net_6[6], net_6[7],
1076
net_6[8], net_6[9], net_6[10], net_6[11], net_6[12]}), .shift(net_17),
1077
.update(net_14), .TDO(net_15), .BS(BS[8:1]), .leaf0(leaf0[8:1]),
1078
.leaf1(leaf1[8:1]), .leaf2(leaf2[8:1]), .leaf3(leaf3[8:1]),
1079
.leaf4(leaf4[8:1]), .leaf5(leaf5[8:1]), .leaf6(leaf6[8:1]),
1080
.leaf7(leaf7[8:1]), .leaf8(leaf8[8:1]), .leaf9(leaf9[8:1]),
1081
.leaf10(leaf10[8:1]), .leaf11(leaf11[8:1]), .leaf12(leaf12[8:1]));
1082
endmodule /* jtag__jtagCentral_LEIGNORE_1 */
1084
module scanFansFour__jtag_endcap(jtag);
1087
endmodule /* scanFansFour__jtag_endcap */
1089
module testCell(TCK, TDI, TMS, TRSTb, TDOb);
1098
wire jtagCent_0_ExTest;
1114
jtag__jtagCentral_LEIGNORE_1 jtagCent_0(.TCK(TCK), .TDI(TDI), .TMS(TMS),
1115
.TRSTb(TRSTb), .ExTest(jtagCent_0_ExTest), .TDOb(TDOb), .BS({net_6[0],
1116
net_6[1], net_6[2], net_6[3], net_6[4], net_6[2], net_6[1], net_6[0]}),
1117
.leaf0({net_7[0], net_7[1], net_7[2], net_7[3], net_7[4], net_7[2],
1118
net_7[1], net_7[0]}), .leaf1({net_18[0], net_18[1], net_18[2], net_18[3],
1119
net_18[4], net_18[2], net_18[1], net_18[0]}), .leaf2({net_17[0],
1120
net_17[1], net_17[2], net_17[3], net_17[4], net_17[2], net_17[1],
1121
net_17[0]}), .leaf3({net_16[0], net_16[1], net_16[2], net_16[3],
1122
net_16[4], net_16[2], net_16[1], net_16[0]}), .leaf4({net_15[0],
1123
net_15[1], net_15[2], net_15[3], net_15[4], net_15[2], net_15[1],
1124
net_15[0]}), .leaf5({net_14[0], net_14[1], net_14[2], net_14[3],
1125
net_14[4], net_14[2], net_14[1], net_14[0]}), .leaf6({net_13[0],
1126
net_13[1], net_13[2], net_13[3], net_13[4], net_13[2], net_13[1],
1127
net_13[0]}), .leaf7({net_12[0], net_12[1], net_12[2], net_12[3],
1128
net_12[4], net_12[2], net_12[1], net_12[0]}), .leaf8({net_11[0],
1129
net_11[1], net_11[2], net_11[3], net_11[4], net_11[2], net_11[1],
1130
net_11[0]}), .leaf9({net_10[0], net_10[1], net_10[2], net_10[3],
1131
net_10[4], net_10[2], net_10[1], net_10[0]}), .leaf10({net_9[0],
1132
net_9[1], net_9[2], net_9[3], net_9[4], net_9[2], net_9[1], net_9[0]}),
1133
.leaf11({net_8[0], net_8[1], net_8[2], net_8[3], net_8[4], net_8[2],
1134
net_8[1], net_8[0]}), .leaf12({net_5[0], net_5[1], net_5[2], net_5[3],
1135
net_5[4], net_5[2], net_5[1], net_5[0]}));
1136
scanFansFour__jtag_endcap jtag_end_0(.jtag({net_5[0], net_5[1], net_5[2],
1137
net_5[4], net_5[3]}));
1138
scanFansFour__jtag_endcap jtag_end_1(.jtag({net_8[0], net_8[1], net_8[2],
1139
net_8[4], net_8[3]}));
1140
scanFansFour__jtag_endcap jtag_end_2(.jtag({net_9[0], net_9[1], net_9[2],
1141
net_9[4], net_9[3]}));
1142
scanFansFour__jtag_endcap jtag_end_3(.jtag({net_10[0], net_10[1], net_10[2],
1143
net_10[4], net_10[3]}));
1144
scanFansFour__jtag_endcap jtag_end_4(.jtag({net_11[0], net_11[1], net_11[2],
1145
net_11[4], net_11[3]}));
1146
scanFansFour__jtag_endcap jtag_end_5(.jtag({net_12[0], net_12[1], net_12[2],
1147
net_12[4], net_12[3]}));
1148
scanFansFour__jtag_endcap jtag_end_6(.jtag({net_13[0], net_13[1], net_13[2],
1149
net_13[4], net_13[3]}));
1150
scanFansFour__jtag_endcap jtag_end_7(.jtag({net_14[0], net_14[1], net_14[2],
1151
net_14[4], net_14[3]}));
1152
scanFansFour__jtag_endcap jtag_end_8(.jtag({net_15[0], net_15[1], net_15[2],
1153
net_15[4], net_15[3]}));
1154
scanFansFour__jtag_endcap jtag_end_9(.jtag({net_16[0], net_16[1], net_16[2],
1155
net_16[4], net_16[3]}));
1156
scanFansFour__jtag_endcap jtag_end_10(.jtag({net_17[0], net_17[1], net_17[2],
1157
net_17[4], net_17[3]}));
1158
scanFansFour__jtag_endcap jtag_end_11(.jtag({net_18[0], net_18[1], net_18[2],
1159
net_18[4], net_18[3]}));
1160
scanFansFour__jtag_endcap jtag_end_12(.jtag({net_7[0], net_7[1], net_7[2],
1161
net_7[4], net_7[3]}));
1162
scanFansFour__jtag_endcap jtag_end_13(.jtag({net_6[0], net_6[1], net_6[2],
1163
net_6[4], net_6[3]}));
1164
endmodule /* testCell */