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intel/intel_chipset.h

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#define PCI_CHIP_IVYBRIDGE_M_GT1        0x0156 /* mobile */

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#define PCI_CHIP_IVYBRIDGE_M_GT2        0x0166

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#define PCI_CHIP_IVYBRIDGE_S            0x015a /* server */

 

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#define PCI_CHIP_IVYBRIDGE_S_GT2        0x016a /* server */

 

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#define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */

 

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#define PCI_CHIP_HASWELL_GT2            0x0412

 

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#define PCI_CHIP_HASWELL_GT2_PLUS       0x0422

 

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#define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */

 

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#define PCI_CHIP_HASWELL_M_GT2          0x0416

 

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#define PCI_CHIP_HASWELL_M_GT2_PLUS     0x0426

 

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#define PCI_CHIP_HASWELL_S_GT1          0x040A /* Server */

 

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#define PCI_CHIP_HASWELL_S_GT2          0x041A

 

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#define PCI_CHIP_HASWELL_S_GT2_PLUS     0x042A

 

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#define PCI_CHIP_HASWELL_SDV_GT1        0x0C02 /* Desktop */

 

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#define PCI_CHIP_HASWELL_SDV_GT2        0x0C12

 

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#define PCI_CHIP_HASWELL_SDV_GT2_PLUS   0x0C22

 

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#define PCI_CHIP_HASWELL_SDV_M_GT1      0x0C06 /* Mobile */

 

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#define PCI_CHIP_HASWELL_SDV_M_GT2      0x0C16

 

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#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26

 

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#define PCI_CHIP_HASWELL_SDV_S_GT1      0x0C0A /* Server */

 

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#define PCI_CHIP_HASWELL_SDV_S_GT2      0x0C1A

 

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#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A

 

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#define PCI_CHIP_HASWELL_ULT_GT1        0x0A02 /* Desktop */

 

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#define PCI_CHIP_HASWELL_ULT_GT2        0x0A12

 

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#define PCI_CHIP_HASWELL_ULT_GT2_PLUS   0x0A22

 

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#define PCI_CHIP_HASWELL_ULT_M_GT1      0x0A06 /* Mobile */

 

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#define PCI_CHIP_HASWELL_ULT_M_GT2      0x0A16

 

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#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26

 

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#define PCI_CHIP_HASWELL_ULT_S_GT1      0x0A0A /* Server */

 

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#define PCI_CHIP_HASWELL_ULT_S_GT2      0x0A1A

 

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#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A

 

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#define PCI_CHIP_HASWELL_CRW_GT1        0x0D12 /* Desktop */

 

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#define PCI_CHIP_HASWELL_CRW_GT2        0x0D22

 

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#define PCI_CHIP_HASWELL_CRW_GT2_PLUS   0x0D32

 

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#define PCI_CHIP_HASWELL_CRW_M_GT1      0x0D16 /* Mobile */

 

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#define PCI_CHIP_HASWELL_CRW_M_GT2      0x0D26

 

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#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36

 

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#define PCI_CHIP_HASWELL_CRW_S_GT1      0x0D1A /* Server */

 

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#define PCI_CHIP_HASWELL_CRW_S_GT2      0x0D2A

 

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#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A

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#define IS_830(dev) (dev == 0x3577)

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#define IS_845(dev) (dev == 0x2562)

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                         dev == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \

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                         dev == PCI_CHIP_SANDYBRIDGE_S)

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#define IS_GEN7(dev)    (dev == PCI_CHIP_IVYBRIDGE_GT1 || \

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                         dev == PCI_CHIP_IVYBRIDGE_GT2 || \

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                         dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \

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                         dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \

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                         dev == PCI_CHIP_IVYBRIDGE_S)

 

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#define IS_GEN7(devid)          (IS_IVYBRIDGE(devid) || \

 

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                                 IS_HASWELL(devid))

 

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#define IS_IVYBRIDGE(dev)       (dev == PCI_CHIP_IVYBRIDGE_GT1 || \

 

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                                 dev == PCI_CHIP_IVYBRIDGE_GT2 || \

 

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                                 dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \

 

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                                 dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \

 

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                                 dev == PCI_CHIP_IVYBRIDGE_S || \

 

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                                 dev == PCI_CHIP_IVYBRIDGE_S_GT2)

 

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#define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1 || \

 

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                                 devid == PCI_CHIP_HASWELL_M_GT1 || \

 

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                                 devid == PCI_CHIP_HASWELL_S_GT1 || \

 

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                                 devid == PCI_CHIP_HASWELL_SDV_GT1 || \

 

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                                 devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \

 

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                                 devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \

 

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                                 devid == PCI_CHIP_HASWELL_ULT_GT1 || \

 

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                                 devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \

 

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                                 devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \

 

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                                 devid == PCI_CHIP_HASWELL_CRW_GT1 || \

 

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                                 devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \

 

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                                 devid == PCI_CHIP_HASWELL_CRW_S_GT1)

 

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#define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_M_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_S_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_SDV_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_ULT_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_CRW_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \

 

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                                 devid == PCI_CHIP_HASWELL_GT2_PLUS || \

 

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                                 devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \

 

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                                 devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \

 

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                                 devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \

 

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                                 devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \

 

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                                 devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \

 

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                                 devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \

 

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                                 devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \

 

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                                 devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \

 

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                                 devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \

 

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                                 devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \

 

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                                 devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)

 

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#define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \

 

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                                 IS_HSW_GT2(devid))

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#define IS_G4X(dev) (dev == 0x2E02 || \

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                     dev == 0x2E12 || \

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