76
Intersil/Zilker Labs DC-DC controllers require a minimum interval between I2C
77
bus accesses. According to Intersil, the minimum interval is 2 ms, though 1 ms
78
appears to be sufficient and has not caused any problems in testing. The problem
79
is known to affect all currently supported chips. For manual override, the
80
driver provides a writeable module parameter, 'delay', which can be used to set
81
the interval to a value between 0 and 65,535 microseconds.
76
Some Intersil/Zilker Labs DC-DC controllers require a minimum interval between
77
I2C bus accesses. According to Intersil, the minimum interval is 2 ms, though
78
1 ms appears to be sufficient and has not caused any problems in testing.
79
The problem is known to affect ZL6100, ZL2105, and ZL2008. It is known not to
80
affect ZL2004 and ZL6105. The driver automatically sets the interval to 1 ms
81
except for ZL2004 and ZL6105. To enable manual override, the driver provides a
82
writeable module parameter, 'delay', which can be used to set the interval to
83
a value between 0 and 65,535 microseconds.