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// Code for handling OHCI USB controllers.
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// Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#include "util.h" // dprintf
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#include "pci.h" // pci_bdf_to_bus
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#include "config.h" // CONFIG_*
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#include "usb-ohci.h" // struct ohci_hcca
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#include "pci_regs.h" // PCI_BASE_ADDRESS_0
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#include "usb.h" // struct usb_s
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#include "farptr.h" // GET_FLATPTR
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struct ohci_regs *regs;
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/****************************************************************
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****************************************************************/
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// Check if device attached to port
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ohci_hub_detect(struct usbhub_s *hub, u32 port)
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struct usb_ohci_s *cntl = container_of(hub->cntl, struct usb_ohci_s, usb);
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u32 sts = readl(&cntl->regs->roothub_portstatus[port]);
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if (!(sts & RH_PS_CCS))
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// XXX - need to wait for USB_TIME_ATTDB if just powered up?
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ohci_hub_disconnect(struct usbhub_s *hub, u32 port)
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struct usb_ohci_s *cntl = container_of(hub->cntl, struct usb_ohci_s, usb);
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writel(&cntl->regs->roothub_portstatus[port], RH_PS_CCS|RH_PS_LSDA);
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// Reset device on port
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ohci_hub_reset(struct usbhub_s *hub, u32 port)
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struct usb_ohci_s *cntl = container_of(hub->cntl, struct usb_ohci_s, usb);
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writel(&cntl->regs->roothub_portstatus[port], RH_PS_PRS);
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u64 end = calc_future_tsc(USB_TIME_DRSTR * 2);
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sts = readl(&cntl->regs->roothub_portstatus[port]);
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if (!(sts & RH_PS_PRS))
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// XXX - need to ensure USB_TIME_DRSTR time in reset?
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ohci_hub_disconnect(hub, port);
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if ((sts & (RH_PS_CCS|RH_PS_PES)) != (RH_PS_CCS|RH_PS_PES))
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// Device no longer present
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return !!(sts & RH_PS_LSDA);
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static struct usbhub_op_s ohci_HubOp = {
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.detect = ohci_hub_detect,
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.reset = ohci_hub_reset,
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.disconnect = ohci_hub_disconnect,
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// Find any devices connected to the root hub.
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check_ohci_ports(struct usb_ohci_s *cntl)
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// Turn on power for all devices on roothub.
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u32 rha = readl(&cntl->regs->roothub_a);
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rha &= ~(RH_A_PSM | RH_A_OCPM);
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writel(&cntl->regs->roothub_status, RH_HS_LPSC);
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writel(&cntl->regs->roothub_b, RH_B_PPCM);
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msleep((rha >> 24) * 2);
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// XXX - need to sleep for USB_TIME_SIGATT if just powered up?
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memset(&hub, 0, sizeof(hub));
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hub.cntl = &cntl->usb;
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hub.portcount = rha & RH_A_NDP;
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hub.op = &ohci_HubOp;
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/****************************************************************
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****************************************************************/
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start_ohci(struct usb_ohci_s *cntl, struct ohci_hcca *hcca)
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u32 oldfminterval = readl(&cntl->regs->fminterval);
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u32 oldrwc = readl(&cntl->regs->control) & OHCI_CTRL_RWC;
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// XXX - check if already running?
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writel(&cntl->regs->control, OHCI_USB_RESET | oldrwc);
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readl(&cntl->regs->control); // flush writes
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msleep(USB_TIME_DRSTR);
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// Do software init (min 10us, max 2ms)
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u64 end = calc_future_tsc_usec(10);
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writel(&cntl->regs->cmdstatus, OHCI_HCR);
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u32 status = readl(&cntl->regs->cmdstatus);
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if (! status & OHCI_HCR)
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if (check_tsc(end)) {
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writel(&cntl->regs->ed_controlhead, 0);
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writel(&cntl->regs->ed_bulkhead, 0);
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writel(&cntl->regs->hcca, (u32)hcca);
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u32 fi = oldfminterval & 0x3fff;
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writel(&cntl->regs->fminterval
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, (((oldfminterval & FIT) ^ FIT)
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| fi | (((6 * (fi - 210)) / 7) << 16)));
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writel(&cntl->regs->periodicstart, ((9 * fi) / 10) & 0x3fff);
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readl(&cntl->regs->control); // flush writes
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// XXX - verify that fminterval was setup correctly.
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// Go into operational state
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writel(&cntl->regs->control
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, (OHCI_CTRL_CBSR | OHCI_CTRL_CLE | OHCI_CTRL_PLE
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| OHCI_USB_OPER | oldrwc));
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readl(&cntl->regs->control); // flush writes
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stop_ohci(struct usb_ohci_s *cntl)
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u32 oldrwc = readl(&cntl->regs->control) & OHCI_CTRL_RWC;
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writel(&cntl->regs->control, oldrwc);
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readl(&cntl->regs->control); // flush writes
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configure_ohci(void *data)
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struct usb_ohci_s *cntl = data;
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struct ohci_hcca *hcca = memalign_high(256, sizeof(*hcca));
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struct ohci_ed *intr_ed = malloc_high(sizeof(*intr_ed));
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if (!hcca || !intr_ed) {
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memset(hcca, 0, sizeof(*hcca));
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memset(intr_ed, 0, sizeof(*intr_ed));
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intr_ed->hwINFO = ED_SKIP;
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for (i=0; i<ARRAY_SIZE(hcca->int_table); i++)
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hcca->int_table[i] = (u32)intr_ed;
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int ret = start_ohci(cntl, hcca);
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int count = check_ohci_ports(cntl);
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free_pipe(cntl->usb.defaultpipe);
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ohci_init(u16 bdf, int busid)
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if (! CONFIG_USB_OHCI)
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struct usb_ohci_s *cntl = malloc_tmphigh(sizeof(*cntl));
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memset(cntl, 0, sizeof(*cntl));
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cntl->usb.busid = busid;
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cntl->usb.type = USB_TYPE_OHCI;
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u32 baseaddr = pci_config_readl(bdf, PCI_BASE_ADDRESS_0);
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cntl->regs = (void*)(baseaddr & PCI_BASE_ADDRESS_MEM_MASK);
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dprintf(1, "OHCI init on dev %02x:%02x.%x (regs=%p)\n"
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, pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf)
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, pci_bdf_to_fn(bdf), cntl->regs);
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// Enable bus mastering and memory access.
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pci_config_maskw(bdf, PCI_COMMAND
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, 0, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY);
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// XXX - check for and disable SMM control?
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// Disable interrupts
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writel(&cntl->regs->intrdisable, ~0);
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writel(&cntl->regs->intrstatus, ~0);
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run_thread(configure_ohci, cntl);
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/****************************************************************
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* End point communication
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****************************************************************/
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wait_ed(struct ohci_ed *ed)
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// XXX - 500ms just a guess
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u64 end = calc_future_tsc(500);
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if (ed->hwHeadP == ed->hwTailP)
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if (check_tsc(end)) {
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// Wait for next USB frame to start - for ensuring safe memory release.
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ohci_waittick(struct usb_ohci_s *cntl)
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struct ohci_hcca *hcca = (void*)cntl->regs->hcca;
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u32 startframe = hcca->frame_no;
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u64 end = calc_future_tsc(1000 * 5);
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if (hcca->frame_no != startframe)
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if (check_tsc(end)) {
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signal_freelist(struct usb_ohci_s *cntl)
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u32 v = readl(&cntl->regs->control);
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if (v & OHCI_CTRL_CLE) {
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writel(&cntl->regs->control, v & ~(OHCI_CTRL_CLE|OHCI_CTRL_BLE));
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writel(&cntl->regs->ed_controlcurrent, 0);
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writel(&cntl->regs->ed_bulkcurrent, 0);
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writel(&cntl->regs->control, v);
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struct usb_pipe pipe;
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ohci_free_pipe(struct usb_pipe *p)
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if (! CONFIG_USB_OHCI)
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dprintf(7, "ohci_free_pipe %p\n", p);
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struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
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struct usb_ohci_s *cntl = container_of(
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pipe->pipe.cntl, struct usb_ohci_s, usb);
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u32 *pos = &cntl->regs->ed_controlhead;
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struct ohci_ed *next = (void*)*pos;
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// Not found?! Exit without freeing.
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warn_internalerror();
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if (next == &pipe->ed) {
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*pos = next->hwNextED;
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signal_freelist(cntl);
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pos = &next->hwNextED;
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ohci_alloc_control_pipe(struct usb_pipe *dummy)
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if (! CONFIG_USB_OHCI)
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struct usb_ohci_s *cntl = container_of(
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dummy->cntl, struct usb_ohci_s, usb);
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dprintf(7, "ohci_alloc_control_pipe %p\n", &cntl->usb);
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// Allocate a queue head.
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struct ohci_pipe *pipe = malloc_tmphigh(sizeof(*pipe));
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memset(pipe, 0, sizeof(*pipe));
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memcpy(&pipe->pipe, dummy, sizeof(pipe->pipe));
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pipe->ed.hwINFO = ED_SKIP;
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// Add queue head to controller list.
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pipe->ed.hwNextED = cntl->regs->ed_controlhead;
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cntl->regs->ed_controlhead = (u32)&pipe->ed;
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ohci_control(struct usb_pipe *p, int dir, const void *cmd, int cmdsize
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, void *data, int datasize)
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if (! CONFIG_USB_OHCI)
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dprintf(5, "ohci_control %p\n", p);
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if (datasize > 4096) {
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// XXX - should support larger sizes.
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struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
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struct usb_ohci_s *cntl = container_of(
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pipe->pipe.cntl, struct usb_ohci_s, usb);
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int maxpacket = pipe->pipe.maxpacket;
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int lowspeed = pipe->pipe.speed;
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int devaddr = pipe->pipe.devaddr | (pipe->pipe.ep << 7);
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// Setup transfer descriptors
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struct ohci_td *tds = malloc_tmphigh(sizeof(*tds) * 3);
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struct ohci_td *td = tds;
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td->hwINFO = TD_DP_SETUP | TD_T_DATA0 | TD_CC;
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td->hwCBP = (u32)cmd;
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td->hwNextTD = (u32)&td[1];
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td->hwBE = (u32)cmd + cmdsize - 1;
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td->hwINFO = (dir ? TD_DP_IN : TD_DP_OUT) | TD_T_DATA1 | TD_CC;
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td->hwCBP = (u32)data;
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td->hwNextTD = (u32)&td[1];
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td->hwBE = (u32)data + datasize - 1;
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td->hwINFO = (dir ? TD_DP_OUT : TD_DP_IN) | TD_T_DATA1 | TD_CC;
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td->hwNextTD = (u32)&td[1];
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pipe->ed.hwINFO = ED_SKIP;
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pipe->ed.hwHeadP = (u32)tds;
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pipe->ed.hwTailP = (u32)td;
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pipe->ed.hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
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writel(&cntl->regs->cmdstatus, OHCI_CLF);
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int ret = wait_ed(&pipe->ed);
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pipe->ed.hwINFO = ED_SKIP;
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ohci_alloc_bulk_pipe(struct usb_pipe *dummy)
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if (! CONFIG_USB_OHCI)
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dprintf(1, "OHCI Bulk transfers not supported.\n");
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ohci_send_bulk(struct usb_pipe *p, int dir, void *data, int datasize)
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ohci_alloc_intr_pipe(struct usb_pipe *dummy, int frameexp)
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if (! CONFIG_USB_OHCI)
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struct usb_ohci_s *cntl = container_of(
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dummy->cntl, struct usb_ohci_s, usb);
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dprintf(7, "ohci_alloc_intr_pipe %p %d\n", &cntl->usb, frameexp);
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int maxpacket = dummy->maxpacket;
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int lowspeed = dummy->speed;
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int devaddr = dummy->devaddr | (dummy->ep << 7);
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// Determine number of entries needed for 2 timer ticks.
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int ms = 1<<frameexp;
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int count = DIV_ROUND_UP(PIT_TICK_INTERVAL * 1000 * 2, PIT_TICK_RATE * ms)+1;
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struct ohci_pipe *pipe = malloc_low(sizeof(*pipe));
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struct ohci_td *tds = malloc_low(sizeof(*tds) * count);
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void *data = malloc_low(maxpacket * count);
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if (!pipe || !tds || !data)
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memset(pipe, 0, sizeof(*pipe));
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memcpy(&pipe->pipe, dummy, sizeof(pipe->pipe));
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struct ohci_ed *ed = &pipe->ed;
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ed->hwHeadP = (u32)&tds[0];
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ed->hwTailP = (u32)&tds[count-1];
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ed->hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
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for (i=0; i<count-1; i++) {
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tds[i].hwINFO = TD_DP_IN | TD_T_TOGGLE | TD_CC;
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tds[i].hwCBP = (u32)data + maxpacket * i;
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tds[i].hwNextTD = (u32)&tds[i+1];
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tds[i].hwBE = tds[i].hwCBP + maxpacket - 1;
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// Add to interrupt schedule.
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struct ohci_hcca *hcca = (void*)cntl->regs->hcca;
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// Add to existing interrupt entry.
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struct ohci_ed *intr_ed = (void*)hcca->int_table[0];
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ed->hwNextED = intr_ed->hwNextED;
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intr_ed->hwNextED = (u32)ed;
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int startpos = 1<<(frameexp-1);
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ed->hwNextED = hcca->int_table[startpos];
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for (i=startpos; i<ARRAY_SIZE(hcca->int_table); i+=ms)
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hcca->int_table[i] = (u32)ed;
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ohci_poll_intr(struct usb_pipe *p, void *data)
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if (! CONFIG_USB_OHCI)
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struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
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struct ohci_td *tds = GET_FLATPTR(pipe->tds);
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struct ohci_td *head = (void*)(GET_FLATPTR(pipe->ed.hwHeadP) & ~(ED_C|ED_H));
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struct ohci_td *tail = (void*)GET_FLATPTR(pipe->ed.hwTailP);
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int count = GET_FLATPTR(pipe->count);
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int pos = (tail - tds + 1) % count;
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struct ohci_td *next = &tds[pos];
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// XXX - check for errors.
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int maxpacket = GET_FLATPTR(pipe->pipe.maxpacket);
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void *pipedata = GET_FLATPTR(pipe->data);
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void *intrdata = pipedata + maxpacket * pos;
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memcpy_far(GET_SEG(SS), data
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, FLATPTR_TO_SEG(intrdata), (void*)FLATPTR_TO_OFFSET(intrdata)
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SET_FLATPTR(tail->hwINFO, TD_DP_IN | TD_T_TOGGLE | TD_CC);
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intrdata = pipedata + maxpacket * (tail-tds);
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SET_FLATPTR(tail->hwCBP, (u32)intrdata);
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SET_FLATPTR(tail->hwNextTD, (u32)next);
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SET_FLATPTR(tail->hwBE, (u32)intrdata + maxpacket - 1);
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SET_FLATPTR(pipe->ed.hwTailP, (u32)next);