~ubuntu-branches/ubuntu/precise/xen/precise-security
» Revision
33
: .pc/xen-backport-per-device-vector-map.patch/xen/arch/x86/io_apic.c
« back to all changes in this revision
Viewing changes to .pc/xen-backport-per-device-vector-map.patch/xen/arch/x86/io_apic.c
- browse files at revision 33
- compare with another revision
- download diff
- download tarball
- view history from revision 33
- Committer: Package Import Robot
- Author(s): Stefan Bader
- Date: 2013-01-30 12:36:41 UTC
- Revision ID: package-import@ubuntu.com-20130130123641-fuyocy2uh9vkhzef
Tags: 4.1.2-2ubuntu2.6
* Applying Xen Security Advisories:
- ACPI: acpi_table_parse() should return handler's error code
CVE-2013-0153 / XSA-36
- oxenstored incorrect handling of certain Xenbus ring states
CVE-2013-0215 / XSA-38
* xen-introduce-xzalloc.patch
Cherry-picked from upstream xen stable-4.1 as prerequisite for XSA-36
* xen-backport-per-device-vector-map.patch
Cherry-picked from upstream xen stable-4.1 as prerequisite for XSA-36
Also fixes issues on AMD systems which could cause Dom0 to loose disks
under heavy I/O (because PCI-E devices could use the same IOAPIC vector
as the SMBus).
- ACPI: acpi_table_parse() should return handler's error code
CVE-2013-0153 / XSA-36
- oxenstored incorrect handling of certain Xenbus ring states
CVE-2013-0215 / XSA-38
* xen-introduce-xzalloc.patch
Cherry-picked from upstream xen stable-4.1 as prerequisite for XSA-36
* xen-backport-per-device-vector-map.patch
Cherry-picked from upstream xen stable-4.1 as prerequisite for XSA-36
Also fixes issues on AMD systems which could cause Dom0 to loose disks
under heavy I/O (because PCI-E devices could use the same IOAPIC vector
as the SMBus).
- files added:
- .pc/xen-backport-per-device-vector-map.patch
- .pc/xen-backport-per-device-vector-map.patch/docs
- .pc/xen-backport-per-device-vector-map.patch/docs/src
- .pc/xen-backport-per-device-vector-map.patch/xen
- .pc/xen-backport-per-device-vector-map.patch/xen/arch
- .pc/xen-backport-per-device-vector-map.patch/xen/arch/x86
- .pc/xen-backport-per-device-vector-map.patch/xen/drivers
- .pc/xen-backport-per-device-vector-map.patch/xen/drivers/passthrough
- .pc/xen-backport-per-device-vector-map.patch/xen/drivers/passthrough/amd
- .pc/xen-backport-per-device-vector-map.patch/xen/include
- .pc/xen-backport-per-device-vector-map.patch/xen/include/asm-x86
- .pc/xen-backport-per-device-vector-map.patch/xen/include/xen
- .pc/xen-introduce-xzalloc.patch
- .pc/xen-introduce-xzalloc.patch/xen
- .pc/xen-introduce-xzalloc.patch/xen/common
- .pc/xen-introduce-xzalloc.patch/xen/include
- .pc/xen-introduce-xzalloc.patch/xen/include/acpi
- .pc/xen-introduce-xzalloc.patch/xen/include/acpi/platform
- .pc/xen-introduce-xzalloc.patch/xen/include/xen
- .pc/xsa36-4.1.patch
- .pc/xsa36-4.1.patch/xen
- .pc/xsa36-4.1.patch/xen/arch
- .pc/xsa36-4.1.patch/xen/arch/x86
- .pc/xsa36-4.1.patch/xen/drivers
- .pc/xsa36-4.1.patch/xen/drivers/acpi
- .pc/xsa36-4.1.patch/xen/drivers/passthrough
- .pc/xsa36-4.1.patch/xen/drivers/passthrough/amd
- .pc/xsa36-4.1.patch/xen/include
- .pc/xsa36-4.1.patch/xen/include/asm-x86
- .pc/xsa36-4.1.patch/xen/include/asm-x86/hvm
- .pc/xsa36-4.1.patch/xen/include/asm-x86/hvm/svm
- .pc/xsa38.patch
- .pc/xsa38.patch/tools
- .pc/xsa38.patch/tools/ocaml
- .pc/xsa38.patch/tools/ocaml/libs
- .pc/xsa38.patch/tools/ocaml/libs/xb
- files modified:
- .pc/applied-patches
added
removed
.pc/xen-backport-per-device-vector-map.patch/xen/arch/x86/io_apic.c
1
/*
2
* Intel IO-APIC support for multi-Pentium hosts.
3
*
4
* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5
*
6
* Many thanks to Stig Venaas for trying out countless experimental
7
* patches and reporting/debugging problems patiently!
8
*
9
* (c) 1999, Multiple IO-APIC support, developed by
10
* Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11
* Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12
* further tested and cleaned up by Zach Brown <zab@redhat.com>
13
* and Ingo Molnar <mingo@redhat.com>
14
*
15
* Fixes
16
* Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17
* thanks to Eric Gilmore
18
* and Rolf G. Tews
19
* for testing these extensively
20
* Paul Diefenbaugh : Added full ACPI support
21
*/
22
23
#include <xen/config.h>
24
#include <xen/lib.h>
25
#include <xen/init.h>
26
#include <xen/irq.h>
27
#include <xen/delay.h>
28
#include <xen/sched.h>
29
#include <xen/acpi.h>
30
#include <xen/pci.h>
31
#include <xen/pci_regs.h>
32
#include <xen/keyhandler.h>
33
#include <asm/mc146818rtc.h>
34
#include <asm/smp.h>
35
#include <asm/desc.h>
36
#include <asm/msi.h>
37
#include <mach_apic.h>
38
#include <io_ports.h>
39
#include <public/physdev.h>
40
41
/* Where if anywhere is the i8259 connect in external int mode */
42
static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
43
44
static DEFINE_SPINLOCK(ioapic_lock);
45
46
bool_t __read_mostly skip_ioapic_setup;
47
48
#ifndef sis_apic_bug
49
/*
50
* Is the SiS APIC rmw bug present?
51
* -1 = don't know, 0 = no, 1 = yes
52
*/
53
int sis_apic_bug = -1;
54
#endif
55
56
/*
57
* # of IRQ routing registers
58
*/
59
int __read_mostly nr_ioapic_registers[MAX_IO_APICS];
60
int __read_mostly nr_ioapics;
61
62
/*
63
* Rough estimation of how many shared IRQs there are, can
64
* be changed anytime.
65
*/
66
#define MAX_PLUS_SHARED_IRQS nr_irqs_gsi
67
#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + nr_irqs_gsi)
68
69
70
#define ioapic_has_eoi_reg(apic) (mp_ioapics[(apic)].mpc_apicver >= 0x20)
71
72
#define io_apic_eoi_vector(apic, vector) io_apic_eoi((apic), (vector), -1)
73
#define io_apic_eoi_pin(apic, pin) io_apic_eoi((apic), -1, (pin))
74
75
76
/*
77
* This is performance-critical, we want to do it O(1)
78
*
79
* the indexing order of this array favors 1:1 mappings
80
* between pins and IRQs.
81
*/
82
83
static struct irq_pin_list {
84
int apic, pin;
85
unsigned int next;
86
} *irq_2_pin;
87
88
static unsigned int irq_2_pin_free_entry;
89
90
/*
91
* The common case is 1:1 IRQ<->pin mappings. Sometimes there are
92
* shared ISA-space IRQs, so we have to support them. We are super
93
* fast in the common case, and fast for shared ISA-space IRQs.
94
*/
95
static void add_pin_to_irq(unsigned int irq, int apic, int pin)
96
{
97
struct irq_pin_list *entry = irq_2_pin + irq;
98
99
while (entry->next) {
100
BUG_ON((entry->apic == apic) && (entry->pin == pin));
101
entry = irq_2_pin + entry->next;
102
}
103
104
BUG_ON((entry->apic == apic) && (entry->pin == pin));
105
106
if (entry->pin != -1) {
107
if (irq_2_pin_free_entry >= PIN_MAP_SIZE)
108
panic("io_apic.c: whoops");
109
entry->next = irq_2_pin_free_entry;
110
entry = irq_2_pin + entry->next;
111
irq_2_pin_free_entry = entry->next;
112
entry->next = 0;
113
}
114
entry->apic = apic;
115
entry->pin = pin;
116
}
117
118
/*
119
* Reroute an IRQ to a different pin.
120
*/
121
static void __init replace_pin_at_irq(unsigned int irq,
122
int oldapic, int oldpin,
123
int newapic, int newpin)
124
{
125
struct irq_pin_list *entry = irq_2_pin + irq;
126
127
while (1) {
128
if (entry->apic == oldapic && entry->pin == oldpin) {
129
entry->apic = newapic;
130
entry->pin = newpin;
131
}
132
if (!entry->next)
133
break;
134
entry = irq_2_pin + entry->next;
135
}
136
}
137
138
struct IO_APIC_route_entry **alloc_ioapic_entries(void)
139
{
140
int apic;
141
struct IO_APIC_route_entry **ioapic_entries;
142
143
ioapic_entries = xmalloc_array(struct IO_APIC_route_entry *, nr_ioapics);
144
if (!ioapic_entries)
145
return 0;
146
147
for (apic = 0; apic < nr_ioapics; apic++) {
148
ioapic_entries[apic] =
149
xmalloc_array(struct IO_APIC_route_entry,
150
nr_ioapic_registers[apic]);
151
if (!ioapic_entries[apic])
152
goto nomem;
153
}
154
155
return ioapic_entries;
156
157
nomem:
158
while (--apic >= 0)
159
xfree(ioapic_entries[apic]);
160
xfree(ioapic_entries);
161
162
return 0;
163
}
164
165
union entry_union {
166
struct { u32 w1, w2; };
167
struct IO_APIC_route_entry entry;
168
};
169
170
static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin, int raw)
171
{
172
unsigned int (*read)(unsigned int, unsigned int)
173
= raw ? __io_apic_read : io_apic_read;
174
union entry_union eu;
175
eu.w1 = (*read)(apic, 0x10 + 2 * pin);
176
eu.w2 = (*read)(apic, 0x11 + 2 * pin);
177
return eu.entry;
178
}
179
180
static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin, int raw)
181
{
182
struct IO_APIC_route_entry entry;
183
unsigned long flags;
184
185
spin_lock_irqsave(&ioapic_lock, flags);
186
entry = __ioapic_read_entry(apic, pin, raw);
187
spin_unlock_irqrestore(&ioapic_lock, flags);
188
return entry;
189
}
190
191
static void
192
__ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e)
193
{
194
void (*write)(unsigned int, unsigned int, unsigned int)
195
= raw ? __io_apic_write : io_apic_write;
196
union entry_union eu = {{0, 0}};
197
198
eu.entry = e;
199
(*write)(apic, 0x11 + 2*pin, eu.w2);
200
(*write)(apic, 0x10 + 2*pin, eu.w1);
201
}
202
203
static void ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e)
204
{
205
unsigned long flags;
206
spin_lock_irqsave(&ioapic_lock, flags);
207
__ioapic_write_entry(apic, pin, raw, e);
208
spin_unlock_irqrestore(&ioapic_lock, flags);
209
}
210
211
/* EOI an IO-APIC entry. One of vector or pin may be -1, indicating that
212
* it should be worked out using the other. This function expect that the
213
* ioapic_lock is taken, and interrupts are disabled (or there is a good reason
214
* not to), and that if both pin and vector are passed, that they refer to the
215
* same redirection entry in the IO-APIC. */
216
static void __io_apic_eoi(unsigned int apic, unsigned int vector, unsigned int pin)
217
{
218
/* Ensure some useful information is passed in */
219
BUG_ON( (vector == -1 && pin == -1) );
220
221
/* Prefer the use of the EOI register if available */
222
if ( ioapic_has_eoi_reg(apic) )
223
{
224
/* If vector is unknown, read it from the IO-APIC */
225
if ( vector == -1 )
226
vector = __ioapic_read_entry(apic, pin, TRUE).vector;
227
228
*(IO_APIC_BASE(apic)+16) = vector;
229
}
230
else
231
{
232
/* Else fake an EOI by switching to edge triggered mode
233
* and back */
234
struct IO_APIC_route_entry entry;
235
bool_t need_to_unmask = 0;
236
237
/* If pin is unknown, search for it */
238
if ( pin == -1 )
239
{
240
unsigned int p;
241
for ( p = 0; p < nr_ioapic_registers[apic]; ++p )
242
{
243
entry = __ioapic_read_entry(apic, p, TRUE);
244
if ( entry.vector == vector )
245
{
246
pin = p;
247
/* break; */
248
249
/* Here should be a break out of the loop, but at the
250
* Xen code doesn't actually prevent multiple IO-APIC
251
* entries being assigned the same vector, so EOI all
252
* pins which have the correct vector.
253
*
254
* Remove the following code when the above assertion
255
* is fulfilled. */
256
__io_apic_eoi(apic, vector, p);
257
}
258
}
259
260
/* If search fails, nothing to do */
261
262
/* if ( pin == -1 ) */
263
264
/* Because the loop wasn't broken out of (see comment above),
265
* all relevant pins have been EOI, so we can always return.
266
*
267
* Re-instate the if statement above when the Xen logic has been
268
* fixed.*/
269
270
return;
271
}
272
273
entry = __ioapic_read_entry(apic, pin, TRUE);
274
275
if ( ! entry.mask )
276
{
277
/* If entry is not currently masked, mask it and make
278
* a note to unmask it later */
279
entry.mask = 1;
280
__ioapic_write_entry(apic, pin, TRUE, entry);
281
need_to_unmask = 1;
282
}
283
284
/* Flip the trigger mode to edge and back */
285
entry.trigger = 0;
286
__ioapic_write_entry(apic, pin, TRUE, entry);
287
entry.trigger = 1;
288
__ioapic_write_entry(apic, pin, TRUE, entry);
289
290
if ( need_to_unmask )
291
{
292
/* Unmask if neccesary */
293
entry.mask = 0;
294
__ioapic_write_entry(apic, pin, TRUE, entry);
295
}
296
}
297
}
298
299
/* EOI an IO-APIC entry. One of vector or pin may be -1, indicating that
300
* it should be worked out using the other. This function disables interrupts
301
* and takes the ioapic_lock */
302
static void io_apic_eoi(unsigned int apic, unsigned int vector, unsigned int pin)
303
{
304
unsigned int flags;
305
spin_lock_irqsave(&ioapic_lock, flags);
306
__io_apic_eoi(apic, vector, pin);
307
spin_unlock_irqrestore(&ioapic_lock, flags);
308
}
309
310
/*
311
* Saves all the IO-APIC RTE's
312
*/
313
int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
314
{
315
int apic, pin;
316
317
if (!ioapic_entries)
318
return -ENOMEM;
319
320
for (apic = 0; apic < nr_ioapics; apic++) {
321
if (!ioapic_entries[apic])
322
return -ENOMEM;
323
324
for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
325
ioapic_entries[apic][pin] = __ioapic_read_entry(apic, pin, 1);
326
}
327
328
return 0;
329
}
330
331
/*
332
* Mask all IO APIC entries.
333
*/
334
void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
335
{
336
int apic, pin;
337
338
if (!ioapic_entries)
339
return;
340
341
for (apic = 0; apic < nr_ioapics; apic++) {
342
if (!ioapic_entries[apic])
343
break;
344
345
for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
346
struct IO_APIC_route_entry entry;
347
348
entry = ioapic_entries[apic][pin];
349
if (!entry.mask) {
350
entry.mask = 1;
351
352
ioapic_write_entry(apic, pin, 1, entry);
353
}
354
}
355
}
356
}
357
358
/*
359
* Restore IO APIC entries which was saved in ioapic_entries.
360
*/
361
int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
362
{
363
int apic, pin;
364
365
if (!ioapic_entries)
366
return -ENOMEM;
367
368
for (apic = 0; apic < nr_ioapics; apic++) {
369
if (!ioapic_entries[apic])
370
return -ENOMEM;
371
372
for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
373
ioapic_write_entry(apic, pin, 1, ioapic_entries[apic][pin]);
374
}
375
376
return 0;
377
}
378
379
void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
380
{
381
int apic;
382
383
for (apic = 0; apic < nr_ioapics; apic++)
384
xfree(ioapic_entries[apic]);
385
386
xfree(ioapic_entries);
387
}
388
389
static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
390
{
391
struct irq_pin_list *entry = irq_2_pin + irq;
392
unsigned int pin, reg;
393
394
for (;;) {
395
pin = entry->pin;
396
if (pin == -1)
397
break;
398
reg = io_apic_read(entry->apic, 0x10 + pin*2);
399
reg &= ~disable;
400
reg |= enable;
401
io_apic_modify(entry->apic, 0x10 + pin*2, reg);
402
if (!entry->next)
403
break;
404
entry = irq_2_pin + entry->next;
405
}
406
}
407
408
/* mask = 1 */
409
static void __mask_IO_APIC_irq (unsigned int irq)
410
{
411
__modify_IO_APIC_irq(irq, 0x00010000, 0);
412
}
413
414
/* mask = 0 */
415
static void __unmask_IO_APIC_irq (unsigned int irq)
416
{
417
__modify_IO_APIC_irq(irq, 0, 0x00010000);
418
}
419
420
/* trigger = 0 */
421
static void __edge_IO_APIC_irq (unsigned int irq)
422
{
423
__modify_IO_APIC_irq(irq, 0, 0x00008000);
424
}
425
426
/* trigger = 1 */
427
static void __level_IO_APIC_irq (unsigned int irq)
428
{
429
__modify_IO_APIC_irq(irq, 0x00008000, 0);
430
}
431
432
static void mask_IO_APIC_irq (unsigned int irq)
433
{
434
unsigned long flags;
435
436
spin_lock_irqsave(&ioapic_lock, flags);
437
__mask_IO_APIC_irq(irq);
438
spin_unlock_irqrestore(&ioapic_lock, flags);
439
}
440
441
static void unmask_IO_APIC_irq (unsigned int irq)
442
{
443
unsigned long flags;
444
445
spin_lock_irqsave(&ioapic_lock, flags);
446
__unmask_IO_APIC_irq(irq);
447
spin_unlock_irqrestore(&ioapic_lock, flags);
448
}
449
450
static void __eoi_IO_APIC_irq(unsigned int irq)
451
{
452
struct irq_pin_list *entry = irq_2_pin + irq;
453
unsigned int pin, vector = IO_APIC_VECTOR(irq);
454
455
for (;;) {
456
pin = entry->pin;
457
if (pin == -1)
458
break;
459
__io_apic_eoi(entry->apic, vector, pin);
460
if (!entry->next)
461
break;
462
entry = irq_2_pin + entry->next;
463
}
464
}
465
466
static void eoi_IO_APIC_irq(unsigned int irq)
467
{
468
unsigned long flags;
469
spin_lock_irqsave(&ioapic_lock, flags);
470
__eoi_IO_APIC_irq(irq);
471
spin_unlock_irqrestore(&ioapic_lock, flags);
472
}
473
474
#define clear_IO_APIC_pin(a,p) __clear_IO_APIC_pin(a,p,0)
475
#define clear_IO_APIC_pin_raw(a,p) __clear_IO_APIC_pin(a,p,1)
476
static void __clear_IO_APIC_pin(unsigned int apic, unsigned int pin, int raw)
477
{
478
struct IO_APIC_route_entry entry;
479
480
/* Check delivery_mode to be sure we're not clearing an SMI pin */
481
entry = ioapic_read_entry(apic, pin, raw);
482
if (entry.delivery_mode == dest_SMI)
483
return;
484
485
/*
486
* Disable it in the IO-APIC irq-routing table:
487
*/
488
memset(&entry, 0, sizeof(entry));
489
entry.mask = 1;
490
ioapic_write_entry(apic, pin, raw, entry);
491
}
492
493
static void clear_IO_APIC (void)
494
{
495
int apic, pin;
496
497
for (apic = 0; apic < nr_ioapics; apic++) {
498
for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
499
clear_IO_APIC_pin(apic, pin);
500
clear_IO_APIC_pin_raw(apic, pin);
501
}
502
}
503
}
504
505
#ifdef CONFIG_SMP
506
fastcall void smp_irq_move_cleanup_interrupt(struct cpu_user_regs *regs)
507
{
508
unsigned vector, me;
509
struct cpu_user_regs *old_regs = set_irq_regs(regs);
510
511
ack_APIC_irq();
512
irq_enter();
513
514
me = smp_processor_id();
515
for (vector = FIRST_DYNAMIC_VECTOR; vector < NR_VECTORS; vector++) {
516
unsigned int irq;
517
unsigned int irr;
518
struct irq_desc *desc;
519
struct irq_cfg *cfg;
520
irq = __get_cpu_var(vector_irq)[vector];
521
522
if (irq == -1)
523
continue;
524
525
desc = irq_to_desc(irq);
526
if (!desc)
527
continue;
528
529
cfg = desc->chip_data;
530
spin_lock(&desc->lock);
531
if (!cfg->move_cleanup_count)
532
goto unlock;
533
534
if (vector == cfg->vector && cpu_isset(me, cfg->cpu_mask))
535
goto unlock;
536
537
irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
538
/*
539
* Check if the vector that needs to be cleanedup is
540
* registered at the cpu's IRR. If so, then this is not
541
* the best time to clean it up. Lets clean it up in the
542
* next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
543
* to myself.
544
*/
545
if (irr & (1 << (vector % 32))) {
546
genapic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
547
goto unlock;
548
}
549
__get_cpu_var(vector_irq)[vector] = -1;
550
cfg->move_cleanup_count--;
551
unlock:
552
spin_unlock(&desc->lock);
553
}
554
555
irq_exit();
556
set_irq_regs(old_regs);
557
}
558
559
static void send_cleanup_vector(struct irq_cfg *cfg)
560
{
561
cpumask_t cleanup_mask;
562
563
cpus_and(cleanup_mask, cfg->old_cpu_mask, cpu_online_map);
564
cfg->move_cleanup_count = cpus_weight(cleanup_mask);
565
genapic->send_IPI_mask(&cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
566
567
cfg->move_in_progress = 0;
568
}
569
570
void irq_complete_move(struct irq_desc **descp)
571
{
572
struct irq_desc *desc = *descp;
573
struct irq_cfg *cfg = desc->chip_data;
574
unsigned vector, me;
575
576
if (likely(!cfg->move_in_progress))
577
return;
578
579
vector = get_irq_regs()->entry_vector;
580
me = smp_processor_id();
581
582
if (vector == cfg->vector && cpu_isset(me, cfg->cpu_mask))
583
send_cleanup_vector(cfg);
584
}
585
586
unsigned int set_desc_affinity(struct irq_desc *desc, const cpumask_t *mask)
587
{
588
struct irq_cfg *cfg;
589
unsigned int irq;
590
int ret;
591
unsigned long flags;
592
cpumask_t dest_mask;
593
594
if (!cpus_intersects(*mask, cpu_online_map))
595
return BAD_APICID;
596
597
irq = desc->irq;
598
cfg = desc->chip_data;
599
600
local_irq_save(flags);
601
lock_vector_lock();
602
ret = __assign_irq_vector(irq, cfg, mask);
603
unlock_vector_lock();
604
local_irq_restore(flags);
605
606
if (ret < 0)
607
return BAD_APICID;
608
609
cpus_copy(desc->affinity, *mask);
610
cpus_and(dest_mask, *mask, cfg->cpu_mask);
611
612
return cpu_mask_to_apicid(&dest_mask);
613
}
614
615
static void
616
set_ioapic_affinity_irq_desc(struct irq_desc *desc, const cpumask_t *mask)
617
{
618
unsigned long flags;
619
unsigned int dest;
620
int pin, irq;
621
struct irq_cfg *cfg;
622
struct irq_pin_list *entry;
623
624
irq = desc->irq;
625
cfg = desc->chip_data;
626
627
spin_lock_irqsave(&ioapic_lock, flags);
628
dest = set_desc_affinity(desc, mask);
629
if (dest != BAD_APICID) {
630
if ( !x2apic_enabled )
631
dest = SET_APIC_LOGICAL_ID(dest);
632
entry = irq_2_pin + irq;
633
for (;;) {
634
unsigned int data;
635
pin = entry->pin;
636
if (pin == -1)
637
break;
638
639
io_apic_write(entry->apic, 0x10 + 1 + pin*2, dest);
640
data = io_apic_read(entry->apic, 0x10 + pin*2);
641
data &= ~IO_APIC_REDIR_VECTOR_MASK;
642
data |= cfg->vector & 0xFF;
643
io_apic_modify(entry->apic, 0x10 + pin*2, data);
644
645
if (!entry->next)
646
break;
647
entry = irq_2_pin + entry->next;
648
}
649
}
650
spin_unlock_irqrestore(&ioapic_lock, flags);
651
652
}
653
654
static void
655
set_ioapic_affinity_irq(unsigned int irq, const struct cpumask mask)
656
{
657
struct irq_desc *desc;
658
659
desc = irq_to_desc(irq);
660
661
set_ioapic_affinity_irq_desc(desc, &mask);
662
}
663
#endif /* CONFIG_SMP */
664
665
/*
666
* Find the IRQ entry number of a certain pin.
667
*/
668
static int find_irq_entry(int apic, int pin, int type)
669
{
670
int i;
671
672
for (i = 0; i < mp_irq_entries; i++)
673
if (mp_irqs[i].mpc_irqtype == type &&
674
(mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
675
mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
676
mp_irqs[i].mpc_dstirq == pin)
677
return i;
678
679
return -1;
680
}
681
682
/*
683
* Find the pin to which IRQ[irq] (ISA) is connected
684
*/
685
static int __init find_isa_irq_pin(int irq, int type)
686
{
687
int i;
688
689
for (i = 0; i < mp_irq_entries; i++) {
690
int lbus = mp_irqs[i].mpc_srcbus;
691
692
if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
693
mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
694
mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
695
mp_bus_id_to_type[lbus] == MP_BUS_NEC98
696
) &&
697
(mp_irqs[i].mpc_irqtype == type) &&
698
(mp_irqs[i].mpc_srcbusirq == irq))
699
700
return mp_irqs[i].mpc_dstirq;
701
}
702
return -1;
703
}
704
705
static int __init find_isa_irq_apic(int irq, int type)
706
{
707
int i;
708
709
for (i = 0; i < mp_irq_entries; i++) {
710
int lbus = mp_irqs[i].mpc_srcbus;
711
712
if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
713
mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
714
mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
715
mp_bus_id_to_type[lbus] == MP_BUS_NEC98
716
) &&
717
(mp_irqs[i].mpc_irqtype == type) &&
718
(mp_irqs[i].mpc_srcbusirq == irq))
719
break;
720
}
721
if (i < mp_irq_entries) {
722
int apic;
723
for(apic = 0; apic < nr_ioapics; apic++) {
724
if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
725
return apic;
726
}
727
}
728
729
return -1;
730
}
731
732
/*
733
* Find a specific PCI IRQ entry.
734
* Not an __init, possibly needed by modules
735
*/
736
static int pin_2_irq(int idx, int apic, int pin);
737
738
/*
739
* This function currently is only a helper for the i386 smp boot process where
740
* we need to reprogram the ioredtbls to cater for the cpus which have come online
741
* so mask in all cases should simply be TARGET_CPUS
742
*/
743
#ifdef CONFIG_SMP
744
void /*__init*/ setup_ioapic_dest(void)
745
{
746
int pin, ioapic, irq, irq_entry;
747
struct irq_cfg *cfg;
748
749
if (skip_ioapic_setup)
750
return;
751
752
for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
753
for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
754
irq_entry = find_irq_entry(ioapic, pin, mp_INT);
755
if (irq_entry == -1)
756
continue;
757
irq = pin_2_irq(irq_entry, ioapic, pin);
758
cfg = irq_cfg(irq);
759
BUG_ON(cpus_empty(cfg->cpu_mask));
760
set_ioapic_affinity_irq(irq, cfg->cpu_mask);
761
}
762
763
}
764
}
765
#endif
766
767
/*
768
* EISA Edge/Level control register, ELCR
769
*/
770
static int EISA_ELCR(unsigned int irq)
771
{
772
if (platform_legacy_irq(irq)) {
773
unsigned int port = 0x4d0 + (irq >> 3);
774
return (inb(port) >> (irq & 7)) & 1;
775
}
776
apic_printk(APIC_VERBOSE, KERN_INFO
777
"Broken MPtable reports ISA irq %d\n", irq);
778
return 0;
779
}
780
781
/* EISA interrupts are always polarity zero and can be edge or level
782
* trigger depending on the ELCR value. If an interrupt is listed as
783
* EISA conforming in the MP table, that means its trigger type must
784
* be read in from the ELCR */
785
786
#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
787
#define default_EISA_polarity(idx) (0)
788
789
/* ISA interrupts are always polarity zero edge triggered,
790
* when listed as conforming in the MP table. */
791
792
#define default_ISA_trigger(idx) (0)
793
#define default_ISA_polarity(idx) (0)
794
795
/* PCI interrupts are always polarity one level triggered,
796
* when listed as conforming in the MP table. */
797
798
#define default_PCI_trigger(idx) (1)
799
#define default_PCI_polarity(idx) (1)
800
801
/* MCA interrupts are always polarity zero level triggered,
802
* when listed as conforming in the MP table. */
803
804
#define default_MCA_trigger(idx) (1)
805
#define default_MCA_polarity(idx) (0)
806
807
/* NEC98 interrupts are always polarity zero edge triggered,
808
* when listed as conforming in the MP table. */
809
810
#define default_NEC98_trigger(idx) (0)
811
#define default_NEC98_polarity(idx) (0)
812
813
static int __init MPBIOS_polarity(int idx)
814
{
815
int bus = mp_irqs[idx].mpc_srcbus;
816
int polarity;
817
818
/*
819
* Determine IRQ line polarity (high active or low active):
820
*/
821
switch (mp_irqs[idx].mpc_irqflag & 3)
822
{
823
case 0: /* conforms, ie. bus-type dependent polarity */
824
{
825
switch (mp_bus_id_to_type[bus])
826
{
827
case MP_BUS_ISA: /* ISA pin */
828
{
829
polarity = default_ISA_polarity(idx);
830
break;
831
}
832
case MP_BUS_EISA: /* EISA pin */
833
{
834
polarity = default_EISA_polarity(idx);
835
break;
836
}
837
case MP_BUS_PCI: /* PCI pin */
838
{
839
polarity = default_PCI_polarity(idx);
840
break;
841
}
842
case MP_BUS_MCA: /* MCA pin */
843
{
844
polarity = default_MCA_polarity(idx);
845
break;
846
}
847
case MP_BUS_NEC98: /* NEC 98 pin */
848
{
849
polarity = default_NEC98_polarity(idx);
850
break;
851
}
852
default:
853
{
854
printk(KERN_WARNING "broken BIOS!!\n");
855
polarity = 1;
856
break;
857
}
858
}
859
break;
860
}
861
case 1: /* high active */
862
{
863
polarity = 0;
864
break;
865
}
866
case 2: /* reserved */
867
{
868
printk(KERN_WARNING "broken BIOS!!\n");
869
polarity = 1;
870
break;
871
}
872
case 3: /* low active */
873
{
874
polarity = 1;
875
break;
876
}
877
default: /* invalid */
878
{
879
printk(KERN_WARNING "broken BIOS!!\n");
880
polarity = 1;
881
break;
882
}
883
}
884
return polarity;
885
}
886
887
static int MPBIOS_trigger(int idx)
888
{
889
int bus = mp_irqs[idx].mpc_srcbus;
890
int trigger;
891
892
/*
893
* Determine IRQ trigger mode (edge or level sensitive):
894
*/
895
switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
896
{
897
case 0: /* conforms, ie. bus-type dependent */
898
{
899
switch (mp_bus_id_to_type[bus])
900
{
901
case MP_BUS_ISA: /* ISA pin */
902
{
903
trigger = default_ISA_trigger(idx);
904
break;
905
}
906
case MP_BUS_EISA: /* EISA pin */
907
{
908
trigger = default_EISA_trigger(idx);
909
break;
910
}
911
case MP_BUS_PCI: /* PCI pin */
912
{
913
trigger = default_PCI_trigger(idx);
914
break;
915
}
916
case MP_BUS_MCA: /* MCA pin */
917
{
918
trigger = default_MCA_trigger(idx);
919
break;
920
}
921
case MP_BUS_NEC98: /* NEC 98 pin */
922
{
923
trigger = default_NEC98_trigger(idx);
924
break;
925
}
926
default:
927
{
928
printk(KERN_WARNING "broken BIOS!!\n");
929
trigger = 1;
930
break;
931
}
932
}
933
break;
934
}
935
case 1: /* edge */
936
{
937
trigger = 0;
938
break;
939
}
940
case 2: /* reserved */
941
{
942
printk(KERN_WARNING "broken BIOS!!\n");
943
trigger = 1;
944
break;
945
}
946
case 3: /* level */
947
{
948
trigger = 1;
949
break;
950
}
951
default: /* invalid */
952
{
953
printk(KERN_WARNING "broken BIOS!!\n");
954
trigger = 0;
955
break;
956
}
957
}
958
return trigger;
959
}
960
961
static inline int irq_polarity(int idx)
962
{
963
return MPBIOS_polarity(idx);
964
}
965
966
static inline int irq_trigger(int idx)
967
{
968
return MPBIOS_trigger(idx);
969
}
970
971
static int pin_2_irq(int idx, int apic, int pin)
972
{
973
int irq, i;
974
int bus = mp_irqs[idx].mpc_srcbus;
975
976
/*
977
* Debugging check, we are in big trouble if this message pops up!
978
*/
979
if (mp_irqs[idx].mpc_dstirq != pin)
980
printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
981
982
switch (mp_bus_id_to_type[bus])
983
{
984
case MP_BUS_ISA: /* ISA pin */
985
case MP_BUS_EISA:
986
case MP_BUS_MCA:
987
case MP_BUS_NEC98:
988
{
989
irq = mp_irqs[idx].mpc_srcbusirq;
990
break;
991
}
992
case MP_BUS_PCI: /* PCI pin */
993
{
994
/*
995
* PCI IRQs are mapped in order
996
*/
997
i = irq = 0;
998
while (i < apic)
999
irq += nr_ioapic_registers[i++];
1000
irq += pin;
1001
break;
1002
}
1003
default:
1004
{
1005
printk(KERN_ERR "unknown bus type %d.\n",bus);
1006
irq = 0;
1007
break;
1008
}
1009
}
1010
1011
return irq;
1012
}
1013
1014
static inline int IO_APIC_irq_trigger(int irq)
1015
{
1016
int apic, idx, pin;
1017
1018
for (apic = 0; apic < nr_ioapics; apic++) {
1019
for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1020
idx = find_irq_entry(apic,pin,mp_INT);
1021
if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1022
return irq_trigger(idx);
1023
}
1024
}
1025
/*
1026
* nonexistent IRQs are edge default
1027
*/
1028
return 0;
1029
}
1030
1031
static hw_irq_controller ioapic_level_type;
1032
static hw_irq_controller ioapic_edge_type;
1033
1034
#define IOAPIC_AUTO -1
1035
#define IOAPIC_EDGE 0
1036
#define IOAPIC_LEVEL 1
1037
1038
#define SET_DEST(x, y, value) \
1039
do { if ( x2apic_enabled ) x = value; else y = value; } while(0)
1040
1041
static inline void ioapic_register_intr(int irq, unsigned long trigger)
1042
{
1043
if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1044
trigger == IOAPIC_LEVEL)
1045
irq_desc[irq].handler = &ioapic_level_type;
1046
else
1047
irq_desc[irq].handler = &ioapic_edge_type;
1048
}
1049
1050
static void __init setup_IO_APIC_irqs(void)
1051
{
1052
struct IO_APIC_route_entry entry;
1053
int apic, pin, idx, irq, first_notcon = 1, vector;
1054
unsigned long flags;
1055
struct irq_cfg *cfg;
1056
1057
apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1058
1059
for (apic = 0; apic < nr_ioapics; apic++) {
1060
for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1061
1062
/*
1063
* add it to the IO-APIC irq-routing table:
1064
*/
1065
memset(&entry,0,sizeof(entry));
1066
1067
entry.delivery_mode = INT_DELIVERY_MODE;
1068
entry.dest_mode = INT_DEST_MODE;
1069
entry.mask = 0; /* enable IRQ */
1070
1071
idx = find_irq_entry(apic,pin,mp_INT);
1072
if (idx == -1) {
1073
if (first_notcon) {
1074
apic_printk(APIC_VERBOSE, KERN_DEBUG
1075
" IO-APIC (apicid-pin) %d-%d",
1076
mp_ioapics[apic].mpc_apicid,
1077
pin);
1078
first_notcon = 0;
1079
} else
1080
apic_printk(APIC_VERBOSE, ", %d-%d",
1081
mp_ioapics[apic].mpc_apicid, pin);
1082
continue;
1083
}
1084
1085
entry.trigger = irq_trigger(idx);
1086
entry.polarity = irq_polarity(idx);
1087
1088
if (irq_trigger(idx)) {
1089
entry.trigger = 1;
1090
entry.mask = 1;
1091
}
1092
1093
irq = pin_2_irq(idx, apic, pin);
1094
/*
1095
* skip adding the timer int on secondary nodes, which causes
1096
* a small but painful rift in the time-space continuum
1097
*/
1098
if (multi_timer_check(apic, irq))
1099
continue;
1100
else
1101
add_pin_to_irq(irq, apic, pin);
1102
1103
if (!apic && !IO_APIC_IRQ(irq))
1104
continue;
1105
1106
if (IO_APIC_IRQ(irq)) {
1107
vector = assign_irq_vector(irq);
1108
BUG_ON(vector < 0);
1109
entry.vector = vector;
1110
ioapic_register_intr(irq, IOAPIC_AUTO);
1111
1112
if (!apic && platform_legacy_irq(irq))
1113
disable_8259A_irq(irq);
1114
}
1115
cfg = irq_cfg(irq);
1116
SET_DEST(entry.dest.dest32, entry.dest.logical.logical_dest,
1117
cpu_mask_to_apicid(&cfg->cpu_mask));
1118
spin_lock_irqsave(&ioapic_lock, flags);
1119
__ioapic_write_entry(apic, pin, 0, entry);
1120
set_native_irq_info(irq, TARGET_CPUS);
1121
spin_unlock_irqrestore(&ioapic_lock, flags);
1122
}
1123
}
1124
1125
if (!first_notcon)
1126
apic_printk(APIC_VERBOSE, " not connected.\n");
1127
}
1128
1129
/*
1130
* Set up the 8259A-master output pin:
1131
*/
1132
static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1133
{
1134
struct IO_APIC_route_entry entry;
1135
1136
memset(&entry,0,sizeof(entry));
1137
1138
disable_8259A_irq(0);
1139
1140
/* mask LVT0 */
1141
apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1142
1143
/*
1144
* We use logical delivery to get the timer IRQ
1145
* to the first CPU.
1146
*/
1147
entry.dest_mode = INT_DEST_MODE;
1148
entry.mask = 0; /* unmask IRQ now */
1149
SET_DEST(entry.dest.dest32, entry.dest.logical.logical_dest,
1150
cpu_mask_to_apicid(TARGET_CPUS));
1151
entry.delivery_mode = INT_DELIVERY_MODE;
1152
entry.polarity = 0;
1153
entry.trigger = 0;
1154
entry.vector = vector;
1155
1156
/*
1157
* The timer IRQ doesn't have to know that behind the
1158
* scene we have a 8259A-master in AEOI mode ...
1159
*/
1160
irq_desc[0].handler = &ioapic_edge_type;
1161
1162
/*
1163
* Add it to the IO-APIC irq-routing table:
1164
*/
1165
ioapic_write_entry(apic, pin, 0, entry);
1166
1167
enable_8259A_irq(0);
1168
}
1169
1170
static inline void UNEXPECTED_IO_APIC(void)
1171
{
1172
}
1173
1174
static void /*__init*/ __print_IO_APIC(void)
1175
{
1176
int apic, i;
1177
union IO_APIC_reg_00 reg_00;
1178
union IO_APIC_reg_01 reg_01;
1179
union IO_APIC_reg_02 reg_02;
1180
union IO_APIC_reg_03 reg_03;
1181
unsigned long flags;
1182
1183
printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1184
for (i = 0; i < nr_ioapics; i++)
1185
printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1186
mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1187
1188
/*
1189
* We are a bit conservative about what we expect. We have to
1190
* know about every hardware change ASAP.
1191
*/
1192
printk(KERN_INFO "testing the IO APIC.......................\n");
1193
1194
for (apic = 0; apic < nr_ioapics; apic++) {
1195
1196
spin_lock_irqsave(&ioapic_lock, flags);
1197
reg_00.raw = io_apic_read(apic, 0);
1198
reg_01.raw = io_apic_read(apic, 1);
1199
if (reg_01.bits.version >= 0x10)
1200
reg_02.raw = io_apic_read(apic, 2);
1201
if (reg_01.bits.version >= 0x20)
1202
reg_03.raw = io_apic_read(apic, 3);
1203
spin_unlock_irqrestore(&ioapic_lock, flags);
1204
1205
printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1206
printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1207
printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1208
printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1209
printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1210
if (reg_00.bits.ID >= get_physical_broadcast())
1211
UNEXPECTED_IO_APIC();
1212
if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1213
UNEXPECTED_IO_APIC();
1214
1215
printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1216
printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1217
if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1218
(reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1219
(reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1220
(reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1221
(reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1222
(reg_01.bits.entries != 0x2E) &&
1223
(reg_01.bits.entries != 0x3F)
1224
)
1225
UNEXPECTED_IO_APIC();
1226
1227
printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1228
printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1229
if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1230
(reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1231
(reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1232
(reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1233
(reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1234
)
1235
UNEXPECTED_IO_APIC();
1236
if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1237
UNEXPECTED_IO_APIC();
1238
1239
/*
1240
* Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1241
* but the value of reg_02 is read as the previous read register
1242
* value, so ignore it if reg_02 == reg_01.
1243
*/
1244
if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1245
printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1246
printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1247
if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1248
UNEXPECTED_IO_APIC();
1249
}
1250
1251
/*
1252
* Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1253
* or reg_03, but the value of reg_0[23] is read as the previous read
1254
* register value, so ignore it if reg_03 == reg_0[12].
1255
*/
1256
if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1257
reg_03.raw != reg_01.raw) {
1258
printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1259
printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1260
if (reg_03.bits.__reserved_1)
1261
UNEXPECTED_IO_APIC();
1262
}
1263
1264
printk(KERN_DEBUG ".... IRQ redirection table:\n");
1265
1266
printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1267
" Stat Dest Deli Vect: \n");
1268
1269
for (i = 0; i <= reg_01.bits.entries; i++) {
1270
struct IO_APIC_route_entry entry;
1271
1272
entry = ioapic_read_entry(apic, i, 0);
1273
1274
printk(KERN_DEBUG " %02x %03X %02X ",
1275
i,
1276
entry.dest.logical.logical_dest,
1277
entry.dest.physical.physical_dest
1278
);
1279
1280
printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1281
entry.mask,
1282
entry.trigger,
1283
entry.irr,
1284
entry.polarity,
1285
entry.delivery_status,
1286
entry.dest_mode,
1287
entry.delivery_mode,
1288
entry.vector
1289
);
1290
}
1291
}
1292
printk(KERN_INFO "Using vector-based indexing\n");
1293
printk(KERN_DEBUG "IRQ to pin mappings:\n");
1294
for (i = 0; i < nr_irqs_gsi; i++) {
1295
struct irq_pin_list *entry = irq_2_pin + i;
1296
if (entry->pin < 0)
1297
continue;
1298
printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1299
for (;;) {
1300
printk("-> %d:%d", entry->apic, entry->pin);
1301
if (!entry->next)
1302
break;
1303
entry = irq_2_pin + entry->next;
1304
}
1305
printk("\n");
1306
}
1307
1308
printk(KERN_INFO ".................................... done.\n");
1309
1310
return;
1311
}
1312
1313
void print_IO_APIC(void)
1314
{
1315
if (apic_verbosity != APIC_QUIET)
1316
__print_IO_APIC();
1317
}
1318
1319
static void _print_IO_APIC_keyhandler(unsigned char key)
1320
{
1321
__print_IO_APIC();
1322
}
1323
static struct keyhandler print_IO_APIC_keyhandler = {
1324
.diagnostic = 1,
1325
.u.fn = _print_IO_APIC_keyhandler,
1326
.desc = "print ioapic info"
1327
};
1328
1329
static void __init enable_IO_APIC(void)
1330
{
1331
int i8259_apic, i8259_pin;
1332
int i, apic;
1333
1334
/* Initialise dynamic irq_2_pin free list. */
1335
irq_2_pin = xmalloc_array(struct irq_pin_list, PIN_MAP_SIZE);
1336
memset(irq_2_pin, 0, PIN_MAP_SIZE * sizeof(*irq_2_pin));
1337
1338
for (i = 0; i < PIN_MAP_SIZE; i++)
1339
irq_2_pin[i].pin = -1;
1340
for (i = irq_2_pin_free_entry = nr_irqs_gsi; i < PIN_MAP_SIZE; i++)
1341
irq_2_pin[i].next = i + 1;
1342
1343
for(apic = 0; apic < nr_ioapics; apic++) {
1344
int pin;
1345
/* See if any of the pins is in ExtINT mode */
1346
for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1347
struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin, 0);
1348
1349
/* If the interrupt line is enabled and in ExtInt mode
1350
* I have found the pin where the i8259 is connected.
1351
*/
1352
if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1353
ioapic_i8259.apic = apic;
1354
ioapic_i8259.pin = pin;
1355
goto found_i8259;
1356
}
1357
}
1358
}
1359
found_i8259:
1360
/* Look to see what if the MP table has reported the ExtINT */
1361
/* If we could not find the appropriate pin by looking at the ioapic
1362
* the i8259 probably is not connected the ioapic but give the
1363
* mptable a chance anyway.
1364
*/
1365
i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1366
i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1367
/* Trust the MP table if nothing is setup in the hardware */
1368
if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1369
printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1370
ioapic_i8259.pin = i8259_pin;
1371
ioapic_i8259.apic = i8259_apic;
1372
}
1373
/* Complain if the MP table and the hardware disagree */
1374
if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1375
(i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1376
{
1377
printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1378
}
1379
1380
/*
1381
* Do not trust the IO-APIC being empty at bootup
1382
*/
1383
clear_IO_APIC();
1384
}
1385
1386
/*
1387
* Not an __init, needed by the reboot code
1388
*/
1389
void disable_IO_APIC(void)
1390
{
1391
/*
1392
* Clear the IO-APIC before rebooting:
1393
*/
1394
clear_IO_APIC();
1395
1396
/*
1397
* If the i8259 is routed through an IOAPIC
1398
* Put that IOAPIC in virtual wire mode
1399
* so legacy interrupts can be delivered.
1400
*/
1401
if (ioapic_i8259.pin != -1) {
1402
struct IO_APIC_route_entry entry;
1403
1404
memset(&entry, 0, sizeof(entry));
1405
entry.mask = 0; /* Enabled */
1406
entry.trigger = 0; /* Edge */
1407
entry.irr = 0;
1408
entry.polarity = 0; /* High */
1409
entry.delivery_status = 0;
1410
entry.dest_mode = 0; /* Physical */
1411
entry.delivery_mode = dest_ExtINT; /* ExtInt */
1412
entry.vector = 0;
1413
SET_DEST(entry.dest.dest32, entry.dest.physical.physical_dest,
1414
get_apic_id());
1415
1416
/*
1417
* Add it to the IO-APIC irq-routing table:
1418
*/
1419
ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, 0, entry);
1420
}
1421
disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1422
}
1423
1424
/*
1425
* function to set the IO-APIC physical IDs based on the
1426
* values stored in the MPC table.
1427
*
1428
* by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1429
*/
1430
1431
#ifndef CONFIG_X86_NUMAQ
1432
static void __init setup_ioapic_ids_from_mpc(void)
1433
{
1434
union IO_APIC_reg_00 reg_00;
1435
physid_mask_t phys_id_present_map;
1436
int apic;
1437
int i;
1438
unsigned char old_id;
1439
unsigned long flags;
1440
1441
/*
1442
* Don't check I/O APIC IDs for xAPIC systems. They have
1443
* no meaning without the serial APIC bus.
1444
*/
1445
if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1446
|| APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1447
return;
1448
1449
/*
1450
* This is broken; anything with a real cpu count has to
1451
* circumvent this idiocy regardless.
1452
*/
1453
phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1454
1455
/*
1456
* Set the IOAPIC ID to the value stored in the MPC table.
1457
*/
1458
for (apic = 0; apic < nr_ioapics; apic++) {
1459
1460
/* Read the register 0 value */
1461
spin_lock_irqsave(&ioapic_lock, flags);
1462
reg_00.raw = io_apic_read(apic, 0);
1463
spin_unlock_irqrestore(&ioapic_lock, flags);
1464
1465
old_id = mp_ioapics[apic].mpc_apicid;
1466
1467
if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1468
printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1469
apic, mp_ioapics[apic].mpc_apicid);
1470
printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1471
reg_00.bits.ID);
1472
mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1473
}
1474
1475
/*
1476
* Sanity check, is the ID really free? Every APIC in a
1477
* system must have a unique ID or we get lots of nice
1478
* 'stuck on smp_invalidate_needed IPI wait' messages.
1479
*/
1480
if (check_apicid_used(phys_id_present_map,
1481
mp_ioapics[apic].mpc_apicid)) {
1482
printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1483
apic, mp_ioapics[apic].mpc_apicid);
1484
for (i = 0; i < get_physical_broadcast(); i++)
1485
if (!physid_isset(i, phys_id_present_map))
1486
break;
1487
if (i >= get_physical_broadcast())
1488
panic("Max APIC ID exceeded!\n");
1489
printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1490
i);
1491
physid_set(i, phys_id_present_map);
1492
mp_ioapics[apic].mpc_apicid = i;
1493
} else {
1494
physid_mask_t tmp;
1495
tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1496
apic_printk(APIC_VERBOSE, "Setting %d in the "
1497
"phys_id_present_map\n",
1498
mp_ioapics[apic].mpc_apicid);
1499
physids_or(phys_id_present_map, phys_id_present_map, tmp);
1500
}
1501
1502
1503
/*
1504
* We need to adjust the IRQ routing table
1505
* if the ID changed.
1506
*/
1507
if (old_id != mp_ioapics[apic].mpc_apicid)
1508
for (i = 0; i < mp_irq_entries; i++)
1509
if (mp_irqs[i].mpc_dstapic == old_id)
1510
mp_irqs[i].mpc_dstapic
1511
= mp_ioapics[apic].mpc_apicid;
1512
1513
/*
1514
* Read the right value from the MPC table and
1515
* write it into the ID register.
1516
*/
1517
apic_printk(APIC_VERBOSE, KERN_INFO
1518
"...changing IO-APIC physical APIC ID to %d ...",
1519
mp_ioapics[apic].mpc_apicid);
1520
1521
reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1522
spin_lock_irqsave(&ioapic_lock, flags);
1523
io_apic_write(apic, 0, reg_00.raw);
1524
spin_unlock_irqrestore(&ioapic_lock, flags);
1525
1526
/*
1527
* Sanity check
1528
*/
1529
spin_lock_irqsave(&ioapic_lock, flags);
1530
reg_00.raw = io_apic_read(apic, 0);
1531
spin_unlock_irqrestore(&ioapic_lock, flags);
1532
if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1533
printk("could not set ID!\n");
1534
else
1535
apic_printk(APIC_VERBOSE, " ok.\n");
1536
}
1537
}
1538
#else
1539
static void __init setup_ioapic_ids_from_mpc(void) { }
1540
#endif
1541
1542
/*
1543
* There is a nasty bug in some older SMP boards, their mptable lies
1544
* about the timer IRQ. We do the following to work around the situation:
1545
*
1546
* - timer IRQ defaults to IO-APIC IRQ
1547
* - if this function detects that timer IRQs are defunct, then we fall
1548
* back to ISA timer IRQs
1549
*/
1550
static int __init timer_irq_works(void)
1551
{
1552
extern unsigned long pit0_ticks;
1553
unsigned long t1, flags;
1554
1555
t1 = pit0_ticks;
1556
mb();
1557
1558
local_save_flags(flags);
1559
local_irq_enable();
1560
/* Let ten ticks pass... */
1561
mdelay((10 * 1000) / HZ);
1562
local_irq_restore(flags);
1563
1564
/*
1565
* Expect a few ticks at least, to be sure some possible
1566
* glue logic does not lock up after one or two first
1567
* ticks in a non-ExtINT mode. Also the local APIC
1568
* might have cached one ExtINT interrupt. Finally, at
1569
* least one tick may be lost due to delays.
1570
*/
1571
mb();
1572
if (pit0_ticks - t1 > 4)
1573
return 1;
1574
1575
return 0;
1576
}
1577
1578
/*
1579
* In the SMP+IOAPIC case it might happen that there are an unspecified
1580
* number of pending IRQ events unhandled. These cases are very rare,
1581
* so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1582
* better to do it this way as thus we do not have to be aware of
1583
* 'pending' interrupts in the IRQ path, except at this point.
1584
*/
1585
/*
1586
* Edge triggered needs to resend any interrupt
1587
* that was delayed but this is now handled in the device
1588
* independent code.
1589
*/
1590
1591
/*
1592
* Starting up a edge-triggered IO-APIC interrupt is
1593
* nasty - we need to make sure that we get the edge.
1594
* If it is already asserted for some reason, we need
1595
* return 1 to indicate that is was pending.
1596
*
1597
* This is not complete - we should be able to fake
1598
* an edge even if it isn't on the 8259A...
1599
*/
1600
static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1601
{
1602
int was_pending = 0;
1603
unsigned long flags;
1604
1605
spin_lock_irqsave(&ioapic_lock, flags);
1606
if (platform_legacy_irq(irq)) {
1607
disable_8259A_irq(irq);
1608
if (i8259A_irq_pending(irq))
1609
was_pending = 1;
1610
}
1611
__unmask_IO_APIC_irq(irq);
1612
spin_unlock_irqrestore(&ioapic_lock, flags);
1613
1614
return was_pending;
1615
}
1616
1617
/*
1618
* Once we have recorded IRQ_PENDING already, we can mask the
1619
* interrupt for real. This prevents IRQ storms from unhandled
1620
* devices.
1621
*/
1622
static void ack_edge_ioapic_irq(unsigned int irq)
1623
{
1624
struct irq_desc *desc = irq_to_desc(irq);
1625
1626
irq_complete_move(&desc);
1627
move_native_irq(irq);
1628
1629
if ((desc->status & (IRQ_PENDING | IRQ_DISABLED))
1630
== (IRQ_PENDING | IRQ_DISABLED))
1631
mask_IO_APIC_irq(irq);
1632
ack_APIC_irq();
1633
}
1634
1635
/*
1636
* Level triggered interrupts can just be masked,
1637
* and shutting down and starting up the interrupt
1638
* is the same as enabling and disabling them -- except
1639
* with a startup need to return a "was pending" value.
1640
*
1641
* Level triggered interrupts are special because we
1642
* do not touch any IO-APIC register while handling
1643
* them. We ack the APIC in the end-IRQ handler, not
1644
* in the start-IRQ-handler. Protection against reentrance
1645
* from the same interrupt is still provided, both by the
1646
* generic IRQ layer and by the fact that an unacked local
1647
* APIC does not accept IRQs.
1648
*/
1649
static unsigned int startup_level_ioapic_irq (unsigned int irq)
1650
{
1651
unmask_IO_APIC_irq(irq);
1652
1653
return 0; /* don't check for pending */
1654
}
1655
1656
int __read_mostly ioapic_ack_new = 1;
1657
static void setup_ioapic_ack(char *s)
1658
{
1659
if ( !strcmp(s, "old") )
1660
ioapic_ack_new = 0;
1661
else if ( !strcmp(s, "new") )
1662
ioapic_ack_new = 1;
1663
else
1664
printk("Unknown ioapic_ack value specified: '%s'\n", s);
1665
}
1666
custom_param("ioapic_ack", setup_ioapic_ack);
1667
1668
static bool_t io_apic_level_ack_pending(unsigned int irq)
1669
{
1670
struct irq_pin_list *entry;
1671
unsigned long flags;
1672
1673
spin_lock_irqsave(&ioapic_lock, flags);
1674
entry = &irq_2_pin[irq];
1675
for (;;) {
1676
unsigned int reg;
1677
int pin;
1678
1679
if (!entry)
1680
break;
1681
1682
pin = entry->pin;
1683
if (pin == -1)
1684
continue;
1685
reg = io_apic_read(entry->apic, 0x10 + pin*2);
1686
/* Is the remote IRR bit set? */
1687
if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1688
spin_unlock_irqrestore(&ioapic_lock, flags);
1689
return 1;
1690
}
1691
if (!entry->next)
1692
break;
1693
entry = irq_2_pin + entry->next;
1694
}
1695
spin_unlock_irqrestore(&ioapic_lock, flags);
1696
1697
return 0;
1698
}
1699
1700
static void mask_and_ack_level_ioapic_irq (unsigned int irq)
1701
{
1702
unsigned long v;
1703
int i;
1704
struct irq_desc *desc = irq_to_desc(irq);
1705
1706
irq_complete_move(&desc);
1707
1708
if ( ioapic_ack_new )
1709
return;
1710
1711
if ( !directed_eoi_enabled )
1712
mask_IO_APIC_irq(irq);
1713
1714
/*
1715
* It appears there is an erratum which affects at least version 0x11
1716
* of I/O APIC (that's the 82093AA and cores integrated into various
1717
* chipsets). Under certain conditions a level-triggered interrupt is
1718
* erroneously delivered as edge-triggered one but the respective IRR
1719
* bit gets set nevertheless. As a result the I/O unit expects an EOI
1720
* message but it will never arrive and further interrupts are blocked
1721
* from the source. The exact reason is so far unknown, but the
1722
* phenomenon was observed when two consecutive interrupt requests
1723
* from a given source get delivered to the same CPU and the source is
1724
* temporarily disabled in between.
1725
*
1726
* A workaround is to simulate an EOI message manually. We achieve it
1727
* by setting the trigger mode to edge and then to level when the edge
1728
* trigger mode gets detected in the TMR of a local APIC for a
1729
* level-triggered interrupt. We mask the source for the time of the
1730
* operation to prevent an edge-triggered interrupt escaping meanwhile.
1731
* The idea is from Manfred Spraul. --macro
1732
*/
1733
i = IO_APIC_VECTOR(irq);
1734
1735
v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1736
1737
ack_APIC_irq();
1738
1739
if ( directed_eoi_enabled )
1740
return;
1741
1742
if ((irq_desc[irq].status & IRQ_MOVE_PENDING) &&
1743
!io_apic_level_ack_pending(irq))
1744
move_masked_irq(irq);
1745
1746
if ( !(v & (1 << (i & 0x1f))) ) {
1747
spin_lock(&ioapic_lock);
1748
__edge_IO_APIC_irq(irq);
1749
__level_IO_APIC_irq(irq);
1750
spin_unlock(&ioapic_lock);
1751
}
1752
}
1753
1754
static void end_level_ioapic_irq (unsigned int irq, u8 vector)
1755
{
1756
unsigned long v;
1757
int i;
1758
1759
if ( !ioapic_ack_new )
1760
{
1761
if ( directed_eoi_enabled )
1762
{
1763
if ( !(irq_desc[irq].status & (IRQ_DISABLED|IRQ_MOVE_PENDING)) )
1764
{
1765
eoi_IO_APIC_irq(irq);
1766
return;
1767
}
1768
1769
mask_IO_APIC_irq(irq);
1770
eoi_IO_APIC_irq(irq);
1771
if ( (irq_desc[irq].status & IRQ_MOVE_PENDING) &&
1772
!io_apic_level_ack_pending(irq) )
1773
move_masked_irq(irq);
1774
}
1775
1776
if ( !(irq_desc[irq].status & IRQ_DISABLED) )
1777
unmask_IO_APIC_irq(irq);
1778
1779
return;
1780
}
1781
1782
/*
1783
* It appears there is an erratum which affects at least version 0x11
1784
* of I/O APIC (that's the 82093AA and cores integrated into various
1785
* chipsets). Under certain conditions a level-triggered interrupt is
1786
* erroneously delivered as edge-triggered one but the respective IRR
1787
* bit gets set nevertheless. As a result the I/O unit expects an EOI
1788
* message but it will never arrive and further interrupts are blocked
1789
* from the source. The exact reason is so far unknown, but the
1790
* phenomenon was observed when two consecutive interrupt requests
1791
* from a given source get delivered to the same CPU and the source is
1792
* temporarily disabled in between.
1793
*
1794
* A workaround is to simulate an EOI message manually. We achieve it
1795
* by setting the trigger mode to edge and then to level when the edge
1796
* trigger mode gets detected in the TMR of a local APIC for a
1797
* level-triggered interrupt. We mask the source for the time of the
1798
* operation to prevent an edge-triggered interrupt escaping meanwhile.
1799
* The idea is from Manfred Spraul. --macro
1800
*/
1801
i = IO_APIC_VECTOR(irq);
1802
1803
/* Manually EOI the old vector if we are moving to the new */
1804
if ( vector && i != vector )
1805
{
1806
int ioapic;
1807
for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
1808
io_apic_eoi_vector(ioapic, i);
1809
}
1810
1811
v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1812
1813
ack_APIC_irq();
1814
1815
if ((irq_desc[irq].status & IRQ_MOVE_PENDING) &&
1816
!io_apic_level_ack_pending(irq))
1817
move_native_irq(irq);
1818
1819
if (!(v & (1 << (i & 0x1f)))) {
1820
spin_lock(&ioapic_lock);
1821
__mask_IO_APIC_irq(irq);
1822
__edge_IO_APIC_irq(irq);
1823
__level_IO_APIC_irq(irq);
1824
if ( !(irq_desc[irq].status & IRQ_DISABLED) )
1825
__unmask_IO_APIC_irq(irq);
1826
spin_unlock(&ioapic_lock);
1827
}
1828
}
1829
1830
static void disable_edge_ioapic_irq(unsigned int irq)
1831
{
1832
}
1833
1834
static void end_edge_ioapic_irq(unsigned int irq, u8 vector)
1835
{
1836
}
1837
1838
/*
1839
* Level and edge triggered IO-APIC interrupts need different handling,
1840
* so we use two separate IRQ descriptors. Edge triggered IRQs can be
1841
* handled with the level-triggered descriptor, but that one has slightly
1842
* more overhead. Level-triggered interrupts cannot be handled with the
1843
* edge-triggered handler, without risking IRQ storms and other ugly
1844
* races.
1845
*/
1846
static hw_irq_controller ioapic_edge_type = {
1847
.typename = "IO-APIC-edge",
1848
.startup = startup_edge_ioapic_irq,
1849
.shutdown = disable_edge_ioapic_irq,
1850
.enable = unmask_IO_APIC_irq,
1851
.disable = disable_edge_ioapic_irq,
1852
.ack = ack_edge_ioapic_irq,
1853
.end = end_edge_ioapic_irq,
1854
.set_affinity = set_ioapic_affinity_irq,
1855
};
1856
1857
static hw_irq_controller ioapic_level_type = {
1858
.typename = "IO-APIC-level",
1859
.startup = startup_level_ioapic_irq,
1860
.shutdown = mask_IO_APIC_irq,
1861
.enable = unmask_IO_APIC_irq,
1862
.disable = mask_IO_APIC_irq,
1863
.ack = mask_and_ack_level_ioapic_irq,
1864
.end = end_level_ioapic_irq,
1865
.set_affinity = set_ioapic_affinity_irq,
1866
};
1867
1868
static unsigned int startup_msi_irq(unsigned int irq)
1869
{
1870
unmask_msi_irq(irq);
1871
return 0;
1872
}
1873
1874
static void ack_msi_irq(unsigned int irq)
1875
{
1876
struct irq_desc *desc = irq_to_desc(irq);
1877
1878
irq_complete_move(&desc);
1879
move_native_irq(irq);
1880
1881
if ( msi_maskable_irq(desc->msi_desc) )
1882
ack_APIC_irq(); /* ACKTYPE_NONE */
1883
}
1884
1885
static void end_msi_irq(unsigned int irq, u8 vector)
1886
{
1887
if ( !msi_maskable_irq(irq_desc[irq].msi_desc) )
1888
ack_APIC_irq(); /* ACKTYPE_EOI */
1889
}
1890
1891
#define shutdown_msi_irq mask_msi_irq
1892
1893
/*
1894
* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1895
* which implement the MSI or MSI-X Capability Structure.
1896
*/
1897
hw_irq_controller pci_msi_type = {
1898
.typename = "PCI-MSI",
1899
.startup = startup_msi_irq,
1900
.shutdown = shutdown_msi_irq,
1901
.enable = unmask_msi_irq,
1902
.disable = mask_msi_irq,
1903
.ack = ack_msi_irq,
1904
.end = end_msi_irq,
1905
.set_affinity = set_msi_affinity,
1906
};
1907
1908
static inline void init_IO_APIC_traps(void)
1909
{
1910
int irq;
1911
/* Xen: This is way simpler than the Linux implementation. */
1912
for (irq = 0; platform_legacy_irq(irq); irq++)
1913
if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq))
1914
make_8259A_irq(irq);
1915
}
1916
1917
static void enable_lapic_irq(unsigned int irq)
1918
{
1919
unsigned long v;
1920
1921
v = apic_read(APIC_LVT0);
1922
apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1923
}
1924
1925
static void disable_lapic_irq(unsigned int irq)
1926
{
1927
unsigned long v;
1928
1929
v = apic_read(APIC_LVT0);
1930
apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1931
}
1932
1933
static void ack_lapic_irq(unsigned int irq)
1934
{
1935
ack_APIC_irq();
1936
}
1937
1938
#define end_lapic_irq end_edge_ioapic_irq
1939
1940
static hw_irq_controller lapic_irq_type = {
1941
.typename = "local-APIC-edge",
1942
.startup = NULL, /* startup_irq() not used for IRQ0 */
1943
.shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1944
.enable = enable_lapic_irq,
1945
.disable = disable_lapic_irq,
1946
.ack = ack_lapic_irq,
1947
.end = end_lapic_irq,
1948
};
1949
1950
/*
1951
* This looks a bit hackish but it's about the only one way of sending
1952
* a few INTA cycles to 8259As and any associated glue logic. ICR does
1953
* not support the ExtINT mode, unfortunately. We need to send these
1954
* cycles as some i82489DX-based boards have glue logic that keeps the
1955
* 8259A interrupt line asserted until INTA. --macro
1956
*/
1957
static void __init unlock_ExtINT_logic(void)
1958
{
1959
int apic, pin, i;
1960
struct IO_APIC_route_entry entry0, entry1;
1961
unsigned char save_control, save_freq_select;
1962
1963
pin = find_isa_irq_pin(8, mp_INT);
1964
apic = find_isa_irq_apic(8, mp_INT);
1965
if (pin == -1)
1966
return;
1967
1968
entry0 = ioapic_read_entry(apic, pin, 0);
1969
clear_IO_APIC_pin(apic, pin);
1970
1971
memset(&entry1, 0, sizeof(entry1));
1972
1973
entry1.dest_mode = 0; /* physical delivery */
1974
entry1.mask = 0; /* unmask IRQ now */
1975
SET_DEST(entry1.dest.dest32, entry1.dest.physical.physical_dest,
1976
hard_smp_processor_id());
1977
entry1.delivery_mode = dest_ExtINT;
1978
entry1.polarity = entry0.polarity;
1979
entry1.trigger = 0;
1980
entry1.vector = 0;
1981
1982
ioapic_write_entry(apic, pin, 0, entry1);
1983
1984
save_control = CMOS_READ(RTC_CONTROL);
1985
save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1986
CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1987
RTC_FREQ_SELECT);
1988
CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1989
1990
i = 100;
1991
while (i-- > 0) {
1992
mdelay(10);
1993
if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1994
i -= 10;
1995
}
1996
1997
CMOS_WRITE(save_control, RTC_CONTROL);
1998
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1999
clear_IO_APIC_pin(apic, pin);
2000
2001
ioapic_write_entry(apic, pin, 0, entry0);
2002
}
2003
2004
/*
2005
* This code may look a bit paranoid, but it's supposed to cooperate with
2006
* a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2007
* is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2008
* fanatically on his truly buggy board.
2009
*/
2010
static void __init check_timer(void)
2011
{
2012
int apic1, pin1, apic2, pin2;
2013
int vector, ret;
2014
unsigned long flags;
2015
2016
local_irq_save(flags);
2017
2018
/*
2019
* get/set the timer IRQ vector:
2020
*/
2021
disable_8259A_irq(0);
2022
vector = FIRST_HIPRIORITY_VECTOR;
2023
clear_irq_vector(0);
2024
2025
if ((ret = bind_irq_vector(0, vector, (cpumask_t)CPU_MASK_ALL)))
2026
printk(KERN_ERR"..IRQ0 is not set correctly with ioapic!!!, err:%d\n", ret);
2027
2028
irq_desc[0].depth = 0;
2029
irq_desc[0].status &= ~IRQ_DISABLED;
2030
2031
/*
2032
* Subtle, code in do_timer_interrupt() expects an AEOI
2033
* mode for the 8259A whenever interrupts are routed
2034
* through I/O APICs. Also IRQ0 has to be enabled in
2035
* the 8259A which implies the virtual wire has to be
2036
* disabled in the local APIC.
2037
*/
2038
apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2039
init_8259A(1);
2040
/* XEN: Ripped out the legacy missed-tick logic, so below is not needed. */
2041
/*timer_ack = 1;*/
2042
/*enable_8259A_irq(0);*/
2043
2044
pin1 = find_isa_irq_pin(0, mp_INT);
2045
apic1 = find_isa_irq_apic(0, mp_INT);
2046
pin2 = ioapic_i8259.pin;
2047
apic2 = ioapic_i8259.apic;
2048
2049
printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2050
vector, apic1, pin1, apic2, pin2);
2051
2052
if (pin1 != -1) {
2053
/*
2054
* Ok, does IRQ0 through the IOAPIC work?
2055
*/
2056
unmask_IO_APIC_irq(0);
2057
if (timer_irq_works()) {
2058
local_irq_restore(flags);
2059
return;
2060
}
2061
clear_IO_APIC_pin(apic1, pin1);
2062
printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2063
"IO-APIC\n");
2064
}
2065
2066
printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2067
if (pin2 != -1) {
2068
printk("\n..... (found pin %d) ...", pin2);
2069
/*
2070
* legacy devices should be connected to IO APIC #0
2071
*/
2072
setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2073
if (timer_irq_works()) {
2074
local_irq_restore(flags);
2075
printk("works.\n");
2076
if (pin1 != -1)
2077
replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2078
else
2079
add_pin_to_irq(0, apic2, pin2);
2080
return;
2081
}
2082
/*
2083
* Cleanup, just in case ...
2084
*/
2085
clear_IO_APIC_pin(apic2, pin2);
2086
}
2087
printk(" failed.\n");
2088
2089
if (nmi_watchdog == NMI_IO_APIC) {
2090
printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2091
nmi_watchdog = 0;
2092
}
2093
2094
printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2095
2096
disable_8259A_irq(0);
2097
irq_desc[0].handler = &lapic_irq_type;
2098
apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2099
enable_8259A_irq(0);
2100
2101
if (timer_irq_works()) {
2102
local_irq_restore(flags);
2103
printk(" works.\n");
2104
return;
2105
}
2106
apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2107
printk(" failed.\n");
2108
2109
printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2110
2111
/*timer_ack = 0;*/
2112
init_8259A(0);
2113
make_8259A_irq(0);
2114
apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2115
2116
unlock_ExtINT_logic();
2117
2118
local_irq_restore(flags);
2119
2120
if (timer_irq_works()) {
2121
printk(" works.\n");
2122
return;
2123
}
2124
printk(" failed :(.\n");
2125
panic("IO-APIC + timer doesn't work! Boot with apic_verbosity=debug "
2126
"and send a report. Then try booting with the 'noapic' option");
2127
}
2128
2129
/*
2130
*
2131
* IRQ's that are handled by the PIC in the MPS IOAPIC case.
2132
* - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2133
* Linux doesn't really care, as it's not actually used
2134
* for any interrupt handling anyway.
2135
*/
2136
#define PIC_IRQS (1 << PIC_CASCADE_IR)
2137
2138
static struct IO_APIC_route_entry *ioapic_pm_state;
2139
2140
static void __init ioapic_pm_state_alloc(void)
2141
{
2142
int i, nr_entry = 0;
2143
2144
for (i = 0; i < nr_ioapics; i++)
2145
nr_entry += nr_ioapic_registers[i];
2146
2147
ioapic_pm_state = _xmalloc(sizeof(struct IO_APIC_route_entry)*nr_entry,
2148
sizeof(struct IO_APIC_route_entry));
2149
BUG_ON(ioapic_pm_state == NULL);
2150
}
2151
2152
void __init setup_IO_APIC(void)
2153
{
2154
enable_IO_APIC();
2155
2156
if (acpi_ioapic)
2157
io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2158
else
2159
io_apic_irqs = ~PIC_IRQS;
2160
2161
printk("ENABLING IO-APIC IRQs\n");
2162
printk(" -> Using %s ACK method\n", ioapic_ack_new ? "new" : "old");
2163
2164
/*
2165
* Set up IO-APIC IRQ routing.
2166
*/
2167
if (!acpi_ioapic)
2168
setup_ioapic_ids_from_mpc();
2169
sync_Arb_IDs();
2170
setup_IO_APIC_irqs();
2171
init_IO_APIC_traps();
2172
check_timer();
2173
print_IO_APIC();
2174
ioapic_pm_state_alloc();
2175
2176
register_keyhandler('z', &print_IO_APIC_keyhandler);
2177
}
2178
2179
void ioapic_suspend(void)
2180
{
2181
struct IO_APIC_route_entry *entry = ioapic_pm_state;
2182
unsigned long flags;
2183
int apic, i;
2184
2185
spin_lock_irqsave(&ioapic_lock, flags);
2186
for (apic = 0; apic < nr_ioapics; apic++) {
2187
for (i = 0; i < nr_ioapic_registers[apic]; i ++, entry ++ ) {
2188
*(((int *)entry) + 1) = __io_apic_read(apic, 0x11 + 2 * i);
2189
*(((int *)entry) + 0) = __io_apic_read(apic, 0x10 + 2 * i);
2190
}
2191
}
2192
spin_unlock_irqrestore(&ioapic_lock, flags);
2193
}
2194
2195
void ioapic_resume(void)
2196
{
2197
struct IO_APIC_route_entry *entry = ioapic_pm_state;
2198
unsigned long flags;
2199
union IO_APIC_reg_00 reg_00;
2200
int i, apic;
2201
2202
spin_lock_irqsave(&ioapic_lock, flags);
2203
for (apic = 0; apic < nr_ioapics; apic++){
2204
reg_00.raw = __io_apic_read(apic, 0);
2205
if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) {
2206
reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
2207
__io_apic_write(apic, 0, reg_00.raw);
2208
}
2209
for (i = 0; i < nr_ioapic_registers[apic]; i++, entry++) {
2210
__io_apic_write(apic, 0x11+2*i, *(((int *)entry)+1));
2211
__io_apic_write(apic, 0x10+2*i, *(((int *)entry)+0));
2212
}
2213
}
2214
spin_unlock_irqrestore(&ioapic_lock, flags);
2215
}
2216
2217
/* --------------------------------------------------------------------------
2218
ACPI-based IOAPIC Configuration
2219
-------------------------------------------------------------------------- */
2220
2221
#ifdef CONFIG_ACPI_BOOT
2222
2223
int __init io_apic_get_unique_id (int ioapic, int apic_id)
2224
{
2225
union IO_APIC_reg_00 reg_00;
2226
static physid_mask_t __initdata apic_id_map = PHYSID_MASK_NONE;
2227
physid_mask_t tmp;
2228
unsigned long flags;
2229
int i = 0;
2230
2231
/*
2232
* The P4 platform supports up to 256 APIC IDs on two separate APIC
2233
* buses (one for LAPICs, one for IOAPICs), where predecessors only
2234
* supports up to 16 on one shared APIC bus.
2235
*
2236
* TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2237
* advantage of new APIC bus architecture.
2238
*/
2239
2240
if (physids_empty(apic_id_map))
2241
apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2242
2243
spin_lock_irqsave(&ioapic_lock, flags);
2244
reg_00.raw = io_apic_read(ioapic, 0);
2245
spin_unlock_irqrestore(&ioapic_lock, flags);
2246
2247
if (apic_id >= get_physical_broadcast()) {
2248
printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2249
"%d\n", ioapic, apic_id, reg_00.bits.ID);
2250
apic_id = reg_00.bits.ID;
2251
}
2252
2253
/*
2254
* Every APIC in a system must have a unique ID or we get lots of nice
2255
* 'stuck on smp_invalidate_needed IPI wait' messages.
2256
*/
2257
if (check_apicid_used(apic_id_map, apic_id)) {
2258
2259
for (i = 0; i < get_physical_broadcast(); i++) {
2260
if (!check_apicid_used(apic_id_map, i))
2261
break;
2262
}
2263
2264
if (i == get_physical_broadcast())
2265
panic("Max apic_id exceeded!\n");
2266
2267
printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2268
"trying %d\n", ioapic, apic_id, i);
2269
2270
apic_id = i;
2271
}
2272
2273
tmp = apicid_to_cpu_present(apic_id);
2274
physids_or(apic_id_map, apic_id_map, tmp);
2275
2276
if (reg_00.bits.ID != apic_id) {
2277
reg_00.bits.ID = apic_id;
2278
2279
spin_lock_irqsave(&ioapic_lock, flags);
2280
io_apic_write(ioapic, 0, reg_00.raw);
2281
reg_00.raw = io_apic_read(ioapic, 0);
2282
spin_unlock_irqrestore(&ioapic_lock, flags);
2283
2284
/* Sanity check */
2285
if (reg_00.bits.ID != apic_id) {
2286
printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2287
return -1;
2288
}
2289
}
2290
2291
apic_printk(APIC_VERBOSE, KERN_INFO
2292
"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2293
2294
return apic_id;
2295
}
2296
2297
2298
int __init io_apic_get_version (int ioapic)
2299
{
2300
union IO_APIC_reg_01 reg_01;
2301
unsigned long flags;
2302
2303
spin_lock_irqsave(&ioapic_lock, flags);
2304
reg_01.raw = io_apic_read(ioapic, 1);
2305
spin_unlock_irqrestore(&ioapic_lock, flags);
2306
2307
return reg_01.bits.version;
2308
}
2309
2310
2311
int __init io_apic_get_redir_entries (int ioapic)
2312
{
2313
union IO_APIC_reg_01 reg_01;
2314
unsigned long flags;
2315
2316
spin_lock_irqsave(&ioapic_lock, flags);
2317
reg_01.raw = io_apic_read(ioapic, 1);
2318
spin_unlock_irqrestore(&ioapic_lock, flags);
2319
2320
return reg_01.bits.entries;
2321
}
2322
2323
2324
int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2325
{
2326
struct irq_desc *desc = irq_to_desc(irq);
2327
struct IO_APIC_route_entry entry;
2328
unsigned long flags;
2329
int vector;
2330
2331
if (!IO_APIC_IRQ(irq)) {
2332
printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2333
ioapic);
2334
return -EINVAL;
2335
}
2336
2337
/*
2338
* Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2339
* Note that we mask (disable) IRQs now -- these get enabled when the
2340
* corresponding device driver registers for this IRQ.
2341
*/
2342
2343
memset(&entry,0,sizeof(entry));
2344
2345
entry.delivery_mode = INT_DELIVERY_MODE;
2346
entry.dest_mode = INT_DEST_MODE;
2347
SET_DEST(entry.dest.dest32, entry.dest.logical.logical_dest,
2348
cpu_mask_to_apicid(TARGET_CPUS));
2349
entry.trigger = edge_level;
2350
entry.polarity = active_high_low;
2351
entry.mask = 1;
2352
2353
/*
2354
* IRQs < 16 are already in the irq_2_pin[] map
2355
*/
2356
if (!platform_legacy_irq(irq))
2357
add_pin_to_irq(irq, ioapic, pin);
2358
2359
vector = assign_irq_vector(irq);
2360
if (vector < 0)
2361
return vector;
2362
entry.vector = vector;
2363
2364
apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2365
"(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2366
mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2367
edge_level, active_high_low);
2368
2369
ioapic_register_intr(irq, edge_level);
2370
2371
if (!ioapic && platform_legacy_irq(irq))
2372
disable_8259A_irq(irq);
2373
2374
spin_lock_irqsave(&ioapic_lock, flags);
2375
__ioapic_write_entry(ioapic, pin, 0, entry);
2376
set_native_irq_info(irq, TARGET_CPUS);
2377
spin_unlock(&ioapic_lock);
2378
2379
spin_lock(&desc->lock);
2380
if (!(desc->status & (IRQ_DISABLED | IRQ_GUEST)))
2381
desc->handler->startup(irq);
2382
spin_unlock_irqrestore(&desc->lock, flags);
2383
2384
return 0;
2385
}
2386
2387
#endif /*CONFIG_ACPI_BOOT*/
2388
2389
static int ioapic_physbase_to_id(unsigned long physbase)
2390
{
2391
int apic;
2392
for ( apic = 0; apic < nr_ioapics; apic++ )
2393
if ( mp_ioapics[apic].mpc_apicaddr == physbase )
2394
return apic;
2395
return -EINVAL;
2396
}
2397
2398
unsigned apic_gsi_base(int apic);
2399
2400
static int apic_pin_2_gsi_irq(int apic, int pin)
2401
{
2402
int idx, irq;
2403
2404
if (apic < 0)
2405
return -EINVAL;
2406
2407
irq = apic_gsi_base(apic) + pin;
2408
if (apic == 0) {
2409
idx = find_irq_entry(apic, pin, mp_INT);
2410
if (idx >= 0)
2411
irq = pin_2_irq(idx, apic, pin);
2412
}
2413
return irq;
2414
}
2415
2416
int ioapic_guest_read(unsigned long physbase, unsigned int reg, u32 *pval)
2417
{
2418
int apic;
2419
unsigned long flags;
2420
2421
if ( (apic = ioapic_physbase_to_id(physbase)) < 0 )
2422
return apic;
2423
2424
spin_lock_irqsave(&ioapic_lock, flags);
2425
*pval = io_apic_read(apic, reg);
2426
spin_unlock_irqrestore(&ioapic_lock, flags);
2427
2428
return 0;
2429
}
2430
2431
#define WARN_BOGUS_WRITE(f, a...) \
2432
dprintk(XENLOG_INFO, "\n%s: " \
2433
"apic=%d, pin=%d, irq=%d\n" \
2434
"%s: new_entry=%08x\n" \
2435
"%s: " f, __FUNCTION__, apic, pin, irq, \
2436
__FUNCTION__, *(u32 *)&rte, \
2437
__FUNCTION__ , ##a )
2438
2439
int ioapic_guest_write(unsigned long physbase, unsigned int reg, u32 val)
2440
{
2441
int apic, pin, irq, ret, vector, pirq;
2442
struct IO_APIC_route_entry rte = { 0 };
2443
unsigned long flags;
2444
struct irq_cfg *cfg;
2445
struct irq_desc *desc;
2446
2447
if ( (apic = ioapic_physbase_to_id(physbase)) < 0 )
2448
return apic;
2449
2450
/* Only write to the first half of a route entry. */
2451
if ( (reg < 0x10) || (reg & 1) )
2452
return 0;
2453
2454
pin = (reg - 0x10) >> 1;
2455
2456
/* Write first half from guest; second half is target info. */
2457
*(u32 *)&rte = val;
2458
2459
/*
2460
* What about weird destination types?
2461
* SMI: Ignore? Ought to be set up by the BIOS.
2462
* NMI: Ignore? Watchdog functionality is Xen's concern.
2463
* INIT: Definitely ignore: probably a guest OS bug.
2464
* ExtINT: Ignore? Linux only asserts this at start of day.
2465
* For now, print a message and return an error. We can fix up on demand.
2466
*/
2467
if ( rte.delivery_mode > dest_LowestPrio )
2468
{
2469
printk("ERROR: Attempt to write weird IOAPIC destination mode!\n");
2470
printk(" APIC=%d/%d, lo-reg=%x\n", apic, pin, val);
2471
return -EINVAL;
2472
}
2473
2474
/*
2475
* The guest does not know physical APIC arrangement (flat vs. cluster).
2476
* Apply genapic conventions for this platform.
2477
*/
2478
rte.delivery_mode = INT_DELIVERY_MODE;
2479
rte.dest_mode = INT_DEST_MODE;
2480
2481
irq = apic_pin_2_gsi_irq(apic, pin);
2482
if ( irq < 0 )
2483
return irq;
2484
2485
desc = irq_to_desc(irq);
2486
cfg = desc->chip_data;
2487
2488
/*
2489
* Since PHYSDEVOP_alloc_irq_vector is dummy, rte.vector is the pirq
2490
* which corresponds to this ioapic pin, retrieve it for building
2491
* pirq and irq mapping. Where the GSI is greater than 256, we assume
2492
* that dom0 pirq == irq.
2493
*/
2494
pirq = (irq >= 256) ? irq : rte.vector;
2495
if ( (pirq < 0) || (pirq >= dom0->nr_pirqs) )
2496
return -EINVAL;
2497
2498
if ( desc->action )
2499
{
2500
spin_lock_irqsave(&ioapic_lock, flags);
2501
ret = io_apic_read(apic, 0x10 + 2 * pin);
2502
spin_unlock_irqrestore(&ioapic_lock, flags);
2503
rte.vector = cfg->vector;
2504
if ( *(u32*)&rte != ret )
2505
WARN_BOGUS_WRITE("old_entry=%08x pirq=%d\n%s: "
2506
"Attempt to modify IO-APIC pin for in-use IRQ!\n",
2507
ret, pirq, __FUNCTION__);
2508
return 0;
2509
}
2510
2511
if ( cfg->vector <= 0 || cfg->vector > LAST_DYNAMIC_VECTOR ) {
2512
vector = assign_irq_vector(irq);
2513
if ( vector < 0 )
2514
return vector;
2515
2516
printk(XENLOG_INFO "allocated vector %02x for irq %d\n", vector, irq);
2517
2518
add_pin_to_irq(irq, apic, pin);
2519
}
2520
spin_lock(&pcidevs_lock);
2521
spin_lock(&dom0->event_lock);
2522
ret = map_domain_pirq(dom0, pirq, irq,
2523
MAP_PIRQ_TYPE_GSI, NULL);
2524
spin_unlock(&dom0->event_lock);
2525
spin_unlock(&pcidevs_lock);
2526
if ( ret < 0 )
2527
return ret;
2528
2529
spin_lock_irqsave(&ioapic_lock, flags);
2530
/* Set the correct irq-handling type. */
2531
desc->handler = rte.trigger ?
2532
&ioapic_level_type: &ioapic_edge_type;
2533
2534
/* Mask iff level triggered. */
2535
rte.mask = rte.trigger;
2536
/* Set the vector field to the real vector! */
2537
rte.vector = cfg->vector;
2538
2539
SET_DEST(rte.dest.dest32, rte.dest.logical.logical_dest,
2540
cpu_mask_to_apicid(&cfg->cpu_mask));
2541
2542
io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&rte) + 0));
2543
io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&rte) + 1));
2544
2545
spin_unlock_irqrestore(&ioapic_lock, flags);
2546
2547
return 0;
2548
}
2549
2550
void dump_ioapic_irq_info(void)
2551
{
2552
struct irq_pin_list *entry;
2553
struct IO_APIC_route_entry rte;
2554
unsigned int irq, pin, printed = 0;
2555
unsigned long flags;
2556
2557
if ( !irq_2_pin )
2558
return;
2559
2560
for ( irq = 0; irq < nr_irqs_gsi; irq++ )
2561
{
2562
entry = &irq_2_pin[irq];
2563
if ( entry->pin == -1 )
2564
continue;
2565
2566
if ( !printed++ )
2567
printk("IO-APIC interrupt information:\n");
2568
2569
printk(" IRQ%3d Vec%3d:\n", irq, irq_to_vector(irq));
2570
2571
for ( ; ; )
2572
{
2573
pin = entry->pin;
2574
2575
printk(" Apic 0x%02x, Pin %2d: ", entry->apic, pin);
2576
2577
spin_lock_irqsave(&ioapic_lock, flags);
2578
*(((int *)&rte) + 0) = io_apic_read(entry->apic, 0x10 + 2 * pin);
2579
*(((int *)&rte) + 1) = io_apic_read(entry->apic, 0x11 + 2 * pin);
2580
spin_unlock_irqrestore(&ioapic_lock, flags);
2581
2582
printk("vector=%u, delivery_mode=%u, dest_mode=%s, "
2583
"delivery_status=%d, polarity=%d, irr=%d, "
2584
"trigger=%s, mask=%d, dest_id:%d\n",
2585
rte.vector, rte.delivery_mode,
2586
rte.dest_mode ? "logical" : "physical",
2587
rte.delivery_status, rte.polarity, rte.irr,
2588
rte.trigger ? "level" : "edge", rte.mask,
2589
rte.dest.logical.logical_dest);
2590
2591
if ( entry->next == 0 )
2592
break;
2593
entry = &irq_2_pin[entry->next];
2594
}
2595
}
2596
}
2597
2598
unsigned highest_gsi(void);
2599
2600
static unsigned int __initdata max_gsi_irqs;
2601
integer_param("max_gsi_irqs", max_gsi_irqs);
2602
2603
void __init init_ioapic_mappings(void)
2604
{
2605
unsigned long ioapic_phys;
2606
unsigned int i, idx = FIX_IO_APIC_BASE_0;
2607
union IO_APIC_reg_01 reg_01;
2608
2609
if ( smp_found_config )
2610
nr_irqs_gsi = 0;
2611
for ( i = 0; i < nr_ioapics; i++ )
2612
{
2613
if ( smp_found_config )
2614
{
2615
ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2616
if ( !ioapic_phys )
2617
{
2618
printk(KERN_ERR "WARNING: bogus zero IO-APIC address "
2619
"found in MPTABLE, disabling IO/APIC support!\n");
2620
smp_found_config = 0;
2621
skip_ioapic_setup = 1;
2622
goto fake_ioapic_page;
2623
}
2624
}
2625
else
2626
{
2627
fake_ioapic_page:
2628
ioapic_phys = __pa(alloc_xenheap_page());
2629
clear_page(__va(ioapic_phys));
2630
}
2631
set_fixmap_nocache(idx, ioapic_phys);
2632
apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2633
__fix_to_virt(idx), ioapic_phys);
2634
idx++;
2635
2636
if ( smp_found_config )
2637
{
2638
/* The number of IO-APIC IRQ registers (== #pins): */
2639
reg_01.raw = io_apic_read(i, 1);
2640
nr_ioapic_registers[i] = reg_01.bits.entries + 1;
2641
nr_irqs_gsi += nr_ioapic_registers[i];
2642
}
2643
}
2644
2645
nr_irqs_gsi = max(nr_irqs_gsi, highest_gsi());
2646
2647
if ( max_gsi_irqs == 0 )
2648
max_gsi_irqs = nr_irqs ? nr_irqs / 8 : PAGE_SIZE;
2649
else if ( nr_irqs != 0 && max_gsi_irqs > nr_irqs )
2650
{
2651
printk(XENLOG_WARNING "\"max_gsi_irqs=\" cannot be specified larger"
2652
" than \"nr_irqs=\"\n");
2653
max_gsi_irqs = nr_irqs;
2654
}
2655
if ( max_gsi_irqs < 16 )
2656
max_gsi_irqs = 16;
2657
2658
/* for PHYSDEVOP_pirq_eoi_gmfn guest assumptions */
2659
if ( max_gsi_irqs > PAGE_SIZE * 8 )
2660
max_gsi_irqs = PAGE_SIZE * 8;
2661
2662
if ( !smp_found_config || skip_ioapic_setup || nr_irqs_gsi < 16 )
2663
nr_irqs_gsi = 16;
2664
else if ( nr_irqs_gsi > max_gsi_irqs )
2665
{
2666
printk(XENLOG_WARNING "Limiting to %u GSI IRQs (found %u)\n",
2667
max_gsi_irqs, nr_irqs_gsi);
2668
nr_irqs_gsi = max_gsi_irqs;
2669
}
2670
2671
if ( nr_irqs == 0 )
2672
nr_irqs = cpu_has_apic ?
2673
max(16U + num_present_cpus() * NR_DYNAMIC_VECTORS,
2674
8 * nr_irqs_gsi) :
2675
nr_irqs_gsi;
2676
else if ( nr_irqs < 16 )
2677
nr_irqs = 16;
2678
printk(XENLOG_INFO "IRQ limits: %u GSI, %u MSI/MSI-X\n",
2679
nr_irqs_gsi, nr_irqs - nr_irqs_gsi);
2680
}
2681
Loggerhead is a web-based interface for Breezy
Version: 2.0.1