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- Committer: Bazaar Package Importer
- Author(s): Christopher James Halse Rogers, Timo Aaltonen, Christopher James Halse Rogers
- Date: 2011-06-02 18:27:35 UTC
- mfrom: (1.5.20 sid)
- Revision ID: james.westby@ubuntu.com-20110602182735-ettcix23ikesyg79
Tags: 2:2.15.0-3ubuntu1
[ Timo Aaltonen ]
* Merge from Debian unstable, remaining changes:
- 101_copy-fb.patch
+ Plymouth integration patch
- 120_check_privates.patch
+ Check for null privates pointer on render_dest_picture.
- debian/xserver-xorg-video-intel.preinst.in:
- debian/xserver-xorg-video-intel.postinst.in:
+ Remove obsolete /etc/modprobe.d/i915-kms.conf file on upgrades.
KMS is the kernel default.
* Dropped patches:
102_gen6_invalidate_texture_cache.patch
107_solid_nullptr_check.patch
108_undo_dmg_trans_before_append.patch
109_dont_reconstruct_glyph_cache_on_rotate.patch
111_fix_clipped_window_plane_offset.patch
112_fix_error_in_4c4ad555.patch
113_remove_broken_max_base_addresses.patch
114_warnings_cleanup_part_2.patch
115_quell_vblank_counter_failed.patch
117_946gz_isreally_965g.patch
119_disable_relaxed_fencing.path
- all upstream.
[ Christopher James Halse Rogers ]
* debian/patches/101_copy-fb.patch
- Refresh for new upstream.
* Merge from Debian unstable, remaining changes:
- 101_copy-fb.patch
+ Plymouth integration patch
- 120_check_privates.patch
+ Check for null privates pointer on render_dest_picture.
- debian/xserver-xorg-video-intel.preinst.in:
- debian/xserver-xorg-video-intel.postinst.in:
+ Remove obsolete /etc/modprobe.d/i915-kms.conf file on upgrades.
KMS is the kernel default.
* Dropped patches:
102_gen6_invalidate_texture_cache.patch
107_solid_nullptr_check.patch
108_undo_dmg_trans_before_append.patch
109_dont_reconstruct_glyph_cache_on_rotate.patch
111_fix_clipped_window_plane_offset.patch
112_fix_error_in_4c4ad555.patch
113_remove_broken_max_base_addresses.patch
114_warnings_cleanup_part_2.patch
115_quell_vblank_counter_failed.patch
117_946gz_isreally_965g.patch
119_disable_relaxed_fencing.path
- all upstream.
[ Christopher James Halse Rogers ]
* debian/patches/101_copy-fb.patch
- Refresh for new upstream.
- files added:
- build-aux
- m4
- files removed:
- debian/apport-gpu-error-intel.py
- files modified:
- ChangeLog
added
removed
src/i965_render.c
43
43
#include "brw_defines.h"
44
44
#include "brw_structs.h"
45
45
46
struct blendinfo {
46
// refer vol2, 3d rasterization 3.8.1
47
48
/* defined in brw_defines.h */
49
static const struct blendinfo {
47
50
Bool dst_alpha;
48
51
Bool src_alpha;
49
52
uint32_t src_blend;
50
53
uint32_t dst_blend;
51
};
52
53
struct formatinfo {
54
int fmt;
55
uint32_t card_fmt;
56
};
57
58
// refer vol2, 3d rasterization 3.8.1
59
60
/* defined in brw_defines.h */
61
static struct blendinfo i965_blend_op[] = {
54
} i965_blend_op[] = {
62
55
/* Clear */
63
56
{0, 0, BRW_BLENDFACTOR_ZERO, BRW_BLENDFACTOR_ZERO},
64
57
/* Src */
99
92
/* FIXME: surface format defined in brw_defines.h, shared Sampling engine
100
93
* 1.7.2
101
94
*/
102
static struct formatinfo i965_tex_formats[] = {
95
static const struct formatinfo {
96
int fmt;
97
uint32_t card_fmt;
98
} i965_tex_formats[] = {
103
99
{PICT_a8, BRW_SURFACEFORMAT_A8_UNORM},
104
100
{PICT_a8r8g8b8, BRW_SURFACEFORMAT_B8G8R8A8_UNORM},
105
101
{PICT_x8r8g8b8, BRW_SURFACEFORMAT_B8G8R8X8_UNORM},
149
145
150
146
}
151
147
152
static Bool i965_get_dest_format(PicturePtr dest_picture, uint32_t * dst_format)
148
static uint32_t i965_get_dest_format(PicturePtr dest_picture)
153
149
{
154
ScrnInfoPtr scrn = xf86Screens[dest_picture->pDrawable->pScreen->myNum];
155
156
150
switch (dest_picture->format) {
157
151
case PICT_a8r8g8b8:
158
152
case PICT_x8r8g8b8:
159
*dst_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
160
break;
153
return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
161
154
case PICT_a8b8g8r8:
162
155
case PICT_x8b8g8r8:
163
*dst_format = BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
164
break;
156
return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
165
157
#if XORG_VERSION_CURRENT >= 10699900
166
158
case PICT_a2r10g10b10:
167
159
case PICT_x2r10g10b10:
168
*dst_format = BRW_SURFACEFORMAT_B10G10R10A2_UNORM;
169
break;
160
return BRW_SURFACEFORMAT_B10G10R10A2_UNORM;
170
161
#endif
171
162
case PICT_r5g6b5:
172
*dst_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
173
break;
163
return BRW_SURFACEFORMAT_B5G6R5_UNORM;
174
164
case PICT_x1r5g5b5:
175
165
case PICT_a1r5g5b5:
176
*dst_format = BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
177
break;
166
return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
178
167
case PICT_a8:
179
*dst_format = BRW_SURFACEFORMAT_A8_UNORM;
180
break;
168
return BRW_SURFACEFORMAT_A8_UNORM;
181
169
case PICT_a4r4g4b4:
182
170
case PICT_x4r4g4b4:
183
*dst_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
184
break;
171
return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
185
172
default:
186
intel_debug_fallback(scrn, "Unsupported dest format 0x%x\n",
187
(int)dest_picture->format);
188
return FALSE;
173
return -1;
189
174
}
190
191
return TRUE;
192
175
}
193
176
194
177
Bool
199
182
int width, int height)
200
183
{
201
184
ScrnInfoPtr scrn = xf86Screens[dest_picture->pDrawable->pScreen->myNum];
202
uint32_t tmp1;
203
185
204
186
/* Check for unsupported compositing operations. */
205
187
if (op >= sizeof(i965_blend_op) / sizeof(i965_blend_op[0])) {
224
206
}
225
207
}
226
208
227
if (!i965_get_dest_format(dest_picture, &tmp1)) {
228
intel_debug_fallback(scrn, "Get Color buffer format\n");
209
if (i965_get_dest_format(dest_picture) == -1) {
210
intel_debug_fallback(scrn, "Usupported Color buffer format 0x%x\n",
211
(int)dest_picture->format);
229
212
return FALSE;
230
213
}
231
214
401
384
#include "exa_wm_write.g4b"
402
385
};
403
386
404
/* new programs for IGDNG */
387
/* new programs for Ironlake */
405
388
static const uint32_t sf_kernel_static_gen5[][4] = {
406
389
#include "exa_sf.g4b.gen5"
407
390
};
551
534
#include "exa_wm_write.g6b"
552
535
};
553
536
554
#define WM_STATE_DECL(kernel) \
555
struct brw_wm_unit_state wm_state_ ## kernel[SAMPLER_STATE_FILTER_COUNT] \
556
[SAMPLER_STATE_EXTEND_COUNT] \
557
[SAMPLER_STATE_FILTER_COUNT] \
558
[SAMPLER_STATE_EXTEND_COUNT]
559
560
/* Many of the fields in the state structure must be aligned to a
561
* 64-byte boundary, (or a 32-byte boundary, but 64 is good enough for
562
* those too).
563
*/
564
#define PAD64_MULTI(previous, idx, factor) char previous ## _pad ## idx [(64 - (sizeof(struct previous) * (factor)) % 64) % 64]
565
#define PAD64(previous, idx) PAD64_MULTI(previous, idx, 1)
566
567
537
typedef enum {
568
538
SAMPLER_STATE_FILTER_NEAREST,
569
539
SAMPLER_STATE_FILTER_BILINEAR,
570
SAMPLER_STATE_FILTER_COUNT
540
FILTER_COUNT
571
541
} sampler_state_filter_t;
572
542
573
543
typedef enum {
575
545
SAMPLER_STATE_EXTEND_REPEAT,
576
546
SAMPLER_STATE_EXTEND_PAD,
577
547
SAMPLER_STATE_EXTEND_REFLECT,
578
SAMPLER_STATE_EXTEND_COUNT
548
EXTEND_COUNT
579
549
} sampler_state_extend_t;
580
550
581
551
typedef enum {
587
557
WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE,
588
558
WM_KERNEL_MASKNOCA_AFFINE,
589
559
WM_KERNEL_MASKNOCA_PROJECTIVE,
590
WM_KERNEL_COUNT
560
KERNEL_COUNT
591
561
} wm_kernel_t;
592
562
593
563
#define KERNEL(kernel_enum, kernel, masked) \
594
564
[kernel_enum] = {&kernel, sizeof(kernel), masked}
595
565
struct wm_kernel_info {
596
void *data;
566
const void *data;
597
567
unsigned int size;
598
568
Bool has_mask;
599
569
};
600
570
601
static struct wm_kernel_info wm_kernels[] = {
571
static const struct wm_kernel_info wm_kernels_gen4[] = {
602
572
KERNEL(WM_KERNEL_NOMASK_AFFINE,
603
573
ps_kernel_nomask_affine_static, FALSE),
604
574
KERNEL(WM_KERNEL_NOMASK_PROJECTIVE,
617
587
ps_kernel_masknoca_projective_static, TRUE),
618
588
};
619
589
620
static struct wm_kernel_info wm_kernels_gen5[] = {
590
static const struct wm_kernel_info wm_kernels_gen5[] = {
621
591
KERNEL(WM_KERNEL_NOMASK_AFFINE,
622
592
ps_kernel_nomask_affine_static_gen5, FALSE),
623
593
KERNEL(WM_KERNEL_NOMASK_PROJECTIVE,
636
606
ps_kernel_masknoca_projective_static_gen5, TRUE),
637
607
};
638
608
639
static struct wm_kernel_info wm_kernels_gen6[] = {
609
static const struct wm_kernel_info wm_kernels_gen6[] = {
640
610
KERNEL(WM_KERNEL_NOMASK_AFFINE,
641
611
ps_kernel_nomask_affine_static_gen6, FALSE),
642
612
KERNEL(WM_KERNEL_NOMASK_PROJECTIVE,
669
639
670
640
struct gen4_cc_unit_state {
671
641
/* Index by [src_blend][dst_blend] */
672
brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT]
673
[BRW_BLENDFACTOR_COUNT];
642
brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT][BRW_BLENDFACTOR_COUNT];
674
643
};
675
644
676
645
typedef struct gen4_composite_op {
681
650
sampler_state_extend_t mask_extend;
682
651
Bool is_affine;
683
652
wm_kernel_t wm_kernel;
653
int vertex_id;
684
654
} gen4_composite_op;
685
655
686
656
/** Private data for gen4 render accel implementation. */
689
659
drm_intel_bo *sf_state_bo;
690
660
drm_intel_bo *sf_mask_state_bo;
691
661
drm_intel_bo *cc_state_bo;
692
drm_intel_bo *wm_state_bo[WM_KERNEL_COUNT]
693
[SAMPLER_STATE_FILTER_COUNT]
694
[SAMPLER_STATE_EXTEND_COUNT]
695
[SAMPLER_STATE_FILTER_COUNT]
696
[SAMPLER_STATE_EXTEND_COUNT];
697
drm_intel_bo *wm_kernel_bo[WM_KERNEL_COUNT];
662
drm_intel_bo *wm_state_bo[KERNEL_COUNT]
663
[FILTER_COUNT] [EXTEND_COUNT]
664
[FILTER_COUNT] [EXTEND_COUNT];
665
drm_intel_bo *wm_kernel_bo[KERNEL_COUNT];
698
666
699
667
drm_intel_bo *cc_vp_bo;
700
668
drm_intel_bo *gen6_blend_bo;
701
669
drm_intel_bo *gen6_depth_stencil_bo;
702
drm_intel_bo *ps_sampler_state_bo[SAMPLER_STATE_FILTER_COUNT]
703
[SAMPLER_STATE_EXTEND_COUNT]
704
[SAMPLER_STATE_FILTER_COUNT]
705
[SAMPLER_STATE_EXTEND_COUNT];
670
drm_intel_bo *ps_sampler_state_bo[FILTER_COUNT]
671
[EXTEND_COUNT]
672
[FILTER_COUNT]
673
[EXTEND_COUNT];
706
674
gen4_composite_op composite_op;
707
675
};
708
676
709
static void gen6_emit_composite_state(ScrnInfoPtr scrn);
677
static void gen6_emit_composite_state(struct intel_screen_private *intel);
710
678
static void gen6_render_state_init(ScrnInfoPtr scrn);
711
679
712
680
/**
716
684
* calculate dA/dx and dA/dy. Hand these interpolation coefficients
717
685
* back to SF which then hands pixels off to WM.
718
686
*/
719
static drm_intel_bo *gen4_create_sf_state(ScrnInfoPtr scrn,
687
static drm_intel_bo *gen4_create_sf_state(intel_screen_private *intel,
720
688
drm_intel_bo * kernel_bo)
721
689
{
722
intel_screen_private *intel = intel_get_screen_private(scrn);
723
690
struct brw_sf_unit_state *sf_state;
724
691
drm_intel_bo *sf_state_bo;
725
692
754
721
sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
755
722
sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
756
723
sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
757
sf_state->thread4.stats_enable = 1;
758
724
sf_state->sf5.viewport_transform = FALSE; /* skip viewport */
759
725
sf_state->sf6.cull_mode = BRW_CULLMODE_NONE;
760
726
sf_state->sf6.scissor = 0;
767
733
return sf_state_bo;
768
734
}
769
735
770
static drm_intel_bo *sampler_border_color_create(ScrnInfoPtr scrn)
736
static drm_intel_bo *sampler_border_color_create(intel_screen_private *intel)
771
737
{
772
738
struct brw_sampler_legacy_border_color sampler_border_color;
773
739
778
744
sampler_border_color.color[2] = 0; /* B */
779
745
sampler_border_color.color[3] = 0; /* A */
780
746
781
return intel_bo_alloc_for_data(scrn,
747
return intel_bo_alloc_for_data(intel,
782
748
&sampler_border_color,
783
749
sizeof(sampler_border_color),
784
750
"gen4 render sampler border color");
850
816
sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */
851
817
}
852
818
853
static drm_intel_bo *gen4_create_sampler_state(ScrnInfoPtr scrn,
854
sampler_state_filter_t
855
src_filter,
856
sampler_state_extend_t
857
src_extend,
858
sampler_state_filter_t
859
mask_filter,
860
sampler_state_extend_t
861
mask_extend,
819
static drm_intel_bo *gen4_create_sampler_state(intel_screen_private *intel,
820
sampler_state_filter_t src_filter,
821
sampler_state_extend_t src_extend,
822
sampler_state_filter_t mask_filter,
823
sampler_state_extend_t mask_extend,
862
824
drm_intel_bo * border_color_bo)
863
825
{
864
intel_screen_private *intel = intel_get_screen_private(scrn);
865
826
drm_intel_bo *sampler_state_bo;
866
827
struct brw_sampler_state *sampler_state;
867
828
924
885
cc_state->cc6.dest_blend_factor = dst_blend;
925
886
}
926
887
927
static drm_intel_bo *gen4_create_wm_state(ScrnInfoPtr scrn,
888
static drm_intel_bo *gen4_create_wm_state(intel_screen_private *intel,
928
889
Bool has_mask,
929
890
drm_intel_bo * kernel_bo,
930
891
drm_intel_bo * sampler_bo)
931
892
{
932
intel_screen_private *intel = intel_get_screen_private(scrn);
933
struct brw_wm_unit_state *wm_state;
893
struct brw_wm_unit_state *state;
934
894
drm_intel_bo *wm_state_bo;
935
895
936
896
wm_state_bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 WM state",
937
sizeof(*wm_state), 4096);
897
sizeof(*state), 4096);
938
898
drm_intel_bo_map(wm_state_bo, TRUE);
939
wm_state = wm_state_bo->virtual;
899
state = wm_state_bo->virtual;
940
900
941
memset(wm_state, 0, sizeof(*wm_state));
942
wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
943
wm_state->thread0.kernel_start_pointer =
901
memset(state, 0, sizeof(*state));
902
state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
903
state->thread0.kernel_start_pointer =
944
904
intel_emit_reloc(wm_state_bo,
945
905
offsetof(struct brw_wm_unit_state, thread0),
946
kernel_bo, wm_state->thread0.grf_reg_count << 1,
906
kernel_bo, state->thread0.grf_reg_count << 1,
947
907
I915_GEM_DOMAIN_INSTRUCTION, 0) >> 6;
948
908
949
wm_state->thread1.single_program_flow = 0;
909
state->thread1.single_program_flow = 0;
950
910
951
911
/* scratch space is not used in our kernel */
952
wm_state->thread2.scratch_space_base_pointer = 0;
953
wm_state->thread2.per_thread_scratch_space = 0;
954
955
wm_state->thread3.const_urb_entry_read_length = 0;
956
wm_state->thread3.const_urb_entry_read_offset = 0;
957
958
wm_state->thread3.urb_entry_read_offset = 0;
912
state->thread2.scratch_space_base_pointer = 0;
913
state->thread2.per_thread_scratch_space = 0;
914
915
state->thread3.const_urb_entry_read_length = 0;
916
state->thread3.const_urb_entry_read_offset = 0;
917
918
state->thread3.urb_entry_read_offset = 0;
959
919
/* wm kernel use urb from 3, see wm_program in compiler module */
960
wm_state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */
961
962
wm_state->wm4.stats_enable = 1; /* statistic */
920
state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */
963
921
964
922
if (IS_GEN5(intel))
965
wm_state->wm4.sampler_count = 0; /* hardware requirement */
923
state->wm4.sampler_count = 0; /* hardware requirement */
966
924
else
967
wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
925
state->wm4.sampler_count = 1; /* 1-4 samplers used */
968
926
969
wm_state->wm4.sampler_state_pointer =
927
state->wm4.sampler_state_pointer =
970
928
intel_emit_reloc(wm_state_bo,
971
929
offsetof(struct brw_wm_unit_state, wm4),
972
930
sampler_bo,
973
wm_state->wm4.stats_enable +
974
(wm_state->wm4.sampler_count << 2),
931
state->wm4.sampler_count << 2,
975
932
I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
976
wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
977
wm_state->wm5.transposed_urb_read = 0;
978
wm_state->wm5.thread_dispatch_enable = 1;
933
state->wm5.max_threads = PS_MAX_THREADS - 1;
934
state->wm5.transposed_urb_read = 0;
935
state->wm5.thread_dispatch_enable = 1;
979
936
/* just use 16-pixel dispatch (4 subspans), don't need to change kernel
980
937
* start point
981
938
*/
982
wm_state->wm5.enable_16_pix = 1;
983
wm_state->wm5.enable_8_pix = 0;
984
wm_state->wm5.early_depth_test = 1;
939
state->wm5.enable_16_pix = 1;
940
state->wm5.enable_8_pix = 0;
941
state->wm5.early_depth_test = 1;
985
942
986
943
/* Each pair of attributes (src/mask coords) is two URB entries */
987
944
if (has_mask) {
988
wm_state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */
989
wm_state->thread3.urb_entry_read_length = 4;
945
state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */
946
state->thread3.urb_entry_read_length = 4;
990
947
} else {
991
wm_state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */
992
wm_state->thread3.urb_entry_read_length = 2;
948
state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */
949
state->thread3.urb_entry_read_length = 2;
993
950
}
994
951
995
952
/* binding table entry count is only used for prefetching, and it has to
996
* be set 0 for IGDNG
953
* be set 0 for Ironlake
997
954
*/
998
955
if (IS_GEN5(intel))
999
wm_state->thread1.binding_table_entry_count = 0;
956
state->thread1.binding_table_entry_count = 0;
1000
957
1001
958
drm_intel_bo_unmap(wm_state_bo);
1002
959
1003
960
return wm_state_bo;
1004
961
}
1005
962
1006
static drm_intel_bo *gen4_create_cc_viewport(ScrnInfoPtr scrn)
963
static drm_intel_bo *gen4_create_cc_viewport(intel_screen_private *intel)
1007
964
{
1008
intel_screen_private *intel = intel_get_screen_private(scrn);
1009
965
drm_intel_bo *bo;
1010
struct brw_cc_viewport cc_viewport;
966
struct brw_cc_viewport vp;
1011
967
1012
cc_viewport.min_depth = -1.e35;
1013
cc_viewport.max_depth = 1.e35;
968
vp.min_depth = -1.e35;
969
vp.max_depth = 1.e35;
1014
970
1015
971
bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 render unit state",
1016
sizeof(cc_viewport), 4096);
1017
drm_intel_bo_subdata(bo, 0, sizeof(cc_viewport), &cc_viewport);
972
sizeof(vp), 4096);
973
drm_intel_bo_subdata(bo, 0, sizeof(vp), &vp);
1018
974
1019
975
return bo;
1020
976
}
1021
977
1022
static drm_intel_bo *gen4_create_vs_unit_state(ScrnInfoPtr scrn)
978
static drm_intel_bo *gen4_create_vs_unit_state(intel_screen_private *intel)
1023
979
{
1024
intel_screen_private *intel = intel_get_screen_private(scrn);
1025
980
struct brw_vs_unit_state vs_state;
1026
981
memset(&vs_state, 0, sizeof(vs_state));
1027
982
1034
989
vs_state.vs6.vs_enable = 0;
1035
990
vs_state.vs6.vert_cache_disable = 1;
1036
991
1037
return intel_bo_alloc_for_data(scrn, &vs_state, sizeof(vs_state),
992
return intel_bo_alloc_for_data(intel, &vs_state, sizeof(vs_state),
1038
993
"gen4 render VS state");
1039
994
}
1040
995
1042
997
* Set up all combinations of cc state: each blendfactor for source and
1043
998
* dest.
1044
999
*/
1045
static drm_intel_bo *gen4_create_cc_unit_state(ScrnInfoPtr scrn)
1000
static drm_intel_bo *gen4_create_cc_unit_state(intel_screen_private *intel)
1046
1001
{
1047
intel_screen_private *intel = intel_get_screen_private(scrn);
1048
struct gen4_cc_unit_state *cc_state;
1049
1002
drm_intel_bo *cc_state_bo, *cc_vp_bo;
1050
1003
int i, j;
1051
1004
1052
cc_vp_bo = gen4_create_cc_viewport(scrn);
1005
cc_vp_bo = gen4_create_cc_viewport(intel);
1053
1006
1054
1007
cc_state_bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 CC state",
1055
sizeof(*cc_state), 4096);
1008
sizeof(struct gen4_cc_unit_state),
1009
4096);
1056
1010
drm_intel_bo_map(cc_state_bo, TRUE);
1057
cc_state = cc_state_bo->virtual;
1058
1011
for (i = 0; i < BRW_BLENDFACTOR_COUNT; i++) {
1059
1012
for (j = 0; j < BRW_BLENDFACTOR_COUNT; j++) {
1060
1013
cc_state_init(cc_state_bo,
1148
1101
1149
1102
memset(ss, 0, sizeof(*ss));
1150
1103
ss->ss0.surface_type = BRW_SURFACE_2D;
1151
if (is_dst) {
1152
uint32_t dst_format = 0;
1153
Bool ret;
1154
1155
ret = i965_get_dest_format(picture, &dst_format);
1156
assert(ret == TRUE);
1157
ss->ss0.surface_format = dst_format;
1158
} else {
1104
if (is_dst)
1105
ss->ss0.surface_format = i965_get_dest_format(picture);
1106
else
1159
1107
ss->ss0.surface_format = i965_get_card_format(picture);
1160
}
1161
1108
1162
1109
ss->ss0.data_return_format = BRW_SURFACERETURNFORMAT_FLOAT32;
1163
1110
ss->ss0.color_blend = 1;
1187
1134
return offset;
1188
1135
}
1189
1136
1190
static void i965_emit_composite_state(ScrnInfoPtr scrn)
1191
{
1192
intel_screen_private *intel = intel_get_screen_private(scrn);
1137
static void gen4_composite_vertex_elements(struct intel_screen_private *intel)
1138
{
1139
struct gen4_render_state *render_state = intel->gen4_render_state;
1140
gen4_composite_op *composite_op = &render_state->composite_op;
1141
Bool has_mask = intel->render_mask != NULL;
1142
Bool is_affine = composite_op->is_affine;
1143
/*
1144
* number of extra parameters per vertex
1145
*/
1146
int nelem = has_mask ? 2 : 1;
1147
/*
1148
* size of extra parameters:
1149
* 3 for homogenous (xyzw)
1150
* 2 for cartesian (xy)
1151
*/
1152
int selem = is_affine ? 2 : 3;
1153
uint32_t w_component;
1154
uint32_t src_format;
1155
int id;
1156
1157
id = has_mask << 1 | is_affine;
1158
1159
if (composite_op->vertex_id == id)
1160
return;
1161
1162
composite_op->vertex_id = id;
1163
1164
if (is_affine) {
1165
src_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
1166
w_component = BRW_VFCOMPONENT_STORE_1_FLT;
1167
} else {
1168
src_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
1169
w_component = BRW_VFCOMPONENT_STORE_SRC;
1170
}
1171
1172
if (IS_GEN5(intel)) {
1173
/*
1174
* The reason to add this extra vertex element in the header is that
1175
* Ironlake has different vertex header definition and origin method to
1176
* set destination element offset doesn't exist anymore, which means
1177
* hardware requires a predefined vertex element layout.
1178
*
1179
* haihao proposed this approach to fill the first vertex element, so
1180
* origin layout for Gen4 doesn't need to change, and origin shader
1181
* programs behavior is also kept.
1182
*
1183
* I think this is not bad. - zhenyu
1184
*/
1185
1186
OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS |
1187
((2 * (2 + nelem)) - 1));
1188
OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
1189
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1190
(0 << VE0_OFFSET_SHIFT));
1191
1192
OUT_BATCH((BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) |
1193
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) |
1194
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) |
1195
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
1196
} else {
1197
/* Set up our vertex elements, sourced from the single vertex buffer.
1198
* that will be set up later.
1199
*/
1200
OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS |
1201
((2 * (1 + nelem)) - 1));
1202
}
1203
1204
/* x,y */
1205
OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
1206
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1207
(0 << VE0_OFFSET_SHIFT));
1208
1209
if (IS_GEN5(intel))
1210
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1211
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1212
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1213
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1214
else
1215
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1216
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1217
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1218
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1219
(4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1220
/* u0, v0, w0 */
1221
OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
1222
(src_format << VE0_FORMAT_SHIFT) |
1223
((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
1224
1225
if (IS_GEN5(intel))
1226
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1227
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1228
(w_component << VE1_VFCOMPONENT_2_SHIFT) |
1229
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1230
else
1231
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1232
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1233
(w_component << VE1_VFCOMPONENT_2_SHIFT) |
1234
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1235
((4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
1236
/* u1, v1, w1 */
1237
if (has_mask) {
1238
OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
1239
(src_format << VE0_FORMAT_SHIFT) |
1240
(((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */
1241
1242
if (IS_GEN5(intel))
1243
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1244
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1245
(w_component << VE1_VFCOMPONENT_2_SHIFT) |
1246
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1247
else
1248
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1249
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1250
(w_component << VE1_VFCOMPONENT_2_SHIFT) |
1251
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1252
((4 + 4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
1253
}
1254
}
1255
1256
static void i965_emit_composite_state(struct intel_screen_private *intel)
1257
{
1193
1258
struct gen4_render_state *render_state = intel->gen4_render_state;
1194
1259
gen4_composite_op *composite_op = &render_state->composite_op;
1195
1260
int op = composite_op->op;
1201
1266
sampler_state_filter_t mask_filter = composite_op->mask_filter;
1202
1267
sampler_state_extend_t src_extend = composite_op->src_extend;
1203
1268
sampler_state_extend_t mask_extend = composite_op->mask_extend;
1204
Bool is_affine = composite_op->is_affine;
1205
1269
uint32_t src_blend, dst_blend;
1206
1270
1207
1271
intel->needs_render_state_emit = FALSE;
1266
1330
i965_get_blend_cntl(op, mask_picture, dest_picture->format,
1267
1331
&src_blend, &dst_blend);
1268
1332
1269
{
1270
/* Binding table pointers */
1271
OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
1272
OUT_BATCH(0); /* vs */
1273
OUT_BATCH(0); /* gs */
1274
OUT_BATCH(0); /* clip */
1275
OUT_BATCH(0); /* sf */
1276
/* Only the PS uses the binding table */
1277
OUT_BATCH(intel->surface_table);
1278
1279
/* The drawing rectangle clipping is always on. Set it to values that
1280
* shouldn't do any clipping.
1281
*/
1282
OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | 2);
1283
OUT_BATCH(0x00000000); /* ymin, xmin */
1284
OUT_BATCH(DRAW_YMAX(dest->drawable.height - 1) |
1285
DRAW_XMAX(dest->drawable.width - 1)); /* ymax, xmax */
1286
OUT_BATCH(0x00000000); /* yorigin, xorigin */
1287
1288
/* skip the depth buffer */
1289
/* skip the polygon stipple */
1290
/* skip the polygon stipple offset */
1291
/* skip the line stipple */
1292
1293
/* Set the pointers to the 3d pipeline state */
1294
OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5);
1295
OUT_RELOC(render_state->vs_state_bo,
1296
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1297
OUT_BATCH(BRW_GS_DISABLE); /* disable GS, resulting in passthrough */
1298
OUT_BATCH(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */
1299
if (mask) {
1300
OUT_RELOC(render_state->sf_mask_state_bo,
1301
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1302
} else {
1303
OUT_RELOC(render_state->sf_state_bo,
1304
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1305
}
1306
1307
OUT_RELOC(render_state->wm_state_bo[composite_op->wm_kernel]
1308
[src_filter][src_extend]
1309
[mask_filter][mask_extend],
1310
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1311
1312
OUT_RELOC(render_state->cc_state_bo,
1313
I915_GEM_DOMAIN_INSTRUCTION, 0,
1314
offsetof(struct gen4_cc_unit_state,
1315
cc_state[src_blend][dst_blend]));
1333
/* Binding table pointers */
1334
OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
1335
OUT_BATCH(0); /* vs */
1336
OUT_BATCH(0); /* gs */
1337
OUT_BATCH(0); /* clip */
1338
OUT_BATCH(0); /* sf */
1339
/* Only the PS uses the binding table */
1340
OUT_BATCH(intel->surface_table);
1341
1342
/* The drawing rectangle clipping is always on. Set it to values that
1343
* shouldn't do any clipping.
1344
*/
1345
OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | 2);
1346
OUT_BATCH(0x00000000); /* ymin, xmin */
1347
OUT_BATCH(DRAW_YMAX(dest->drawable.height - 1) |
1348
DRAW_XMAX(dest->drawable.width - 1)); /* ymax, xmax */
1349
OUT_BATCH(0x00000000); /* yorigin, xorigin */
1350
1351
/* skip the depth buffer */
1352
/* skip the polygon stipple */
1353
/* skip the polygon stipple offset */
1354
/* skip the line stipple */
1355
1356
/* Set the pointers to the 3d pipeline state */
1357
OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5);
1358
OUT_RELOC(render_state->vs_state_bo,
1359
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1360
OUT_BATCH(BRW_GS_DISABLE); /* disable GS, resulting in passthrough */
1361
OUT_BATCH(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */
1362
if (mask) {
1363
OUT_RELOC(render_state->sf_mask_state_bo,
1364
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1365
} else {
1366
OUT_RELOC(render_state->sf_state_bo,
1367
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1316
1368
}
1317
1369
1370
OUT_RELOC(render_state->wm_state_bo[composite_op->wm_kernel]
1371
[src_filter][src_extend]
1372
[mask_filter][mask_extend],
1373
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1374
1375
OUT_RELOC(render_state->cc_state_bo,
1376
I915_GEM_DOMAIN_INSTRUCTION, 0,
1377
offsetof(struct gen4_cc_unit_state,
1378
cc_state[src_blend][dst_blend]));
1379
1318
1380
{
1319
1381
int urb_vs_start, urb_vs_size;
1320
1382
int urb_gs_start, urb_gs_size;
1361
1423
(URB_CS_ENTRIES << 0));
1362
1424
}
1363
1425
1364
{
1365
/*
1366
* number of extra parameters per vertex
1367
*/
1368
int nelem = mask ? 2 : 1;
1369
/*
1370
* size of extra parameters:
1371
* 3 for homogenous (xyzw)
1372
* 2 for cartesian (xy)
1373
*/
1374
int selem = is_affine ? 2 : 3;
1375
uint32_t w_component;
1376
uint32_t src_format;
1377
1378
if (is_affine) {
1379
src_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
1380
w_component = BRW_VFCOMPONENT_STORE_1_FLT;
1381
} else {
1382
src_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
1383
w_component = BRW_VFCOMPONENT_STORE_SRC;
1384
}
1385
1386
if (IS_GEN5(intel)) {
1387
/*
1388
* The reason to add this extra vertex element in the header is that
1389
* IGDNG has different vertex header definition and origin method to
1390
* set destination element offset doesn't exist anymore, which means
1391
* hardware requires a predefined vertex element layout.
1392
*
1393
* haihao proposed this approach to fill the first vertex element, so
1394
* origin layout for Gen4 doesn't need to change, and origin shader
1395
* programs behavior is also kept.
1396
*
1397
* I think this is not bad. - zhenyu
1398
*/
1399
1400
OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS |
1401
((2 * (2 + nelem)) - 1));
1402
OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1403
VE0_VALID | (BRW_SURFACEFORMAT_R32G32_FLOAT <<
1404
VE0_FORMAT_SHIFT) | (0 <<
1405
VE0_OFFSET_SHIFT));
1406
1407
OUT_BATCH((BRW_VFCOMPONENT_STORE_0 <<
1408
VE1_VFCOMPONENT_0_SHIFT) |
1409
(BRW_VFCOMPONENT_STORE_0 <<
1410
VE1_VFCOMPONENT_1_SHIFT) |
1411
(BRW_VFCOMPONENT_STORE_0 <<
1412
VE1_VFCOMPONENT_2_SHIFT) |
1413
(BRW_VFCOMPONENT_STORE_0 <<
1414
VE1_VFCOMPONENT_3_SHIFT));
1415
} else {
1416
/* Set up our vertex elements, sourced from the single vertex buffer.
1417
* that will be set up later.
1418
*/
1419
OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS |
1420
((2 * (1 + nelem)) - 1));
1421
}
1422
1423
/* x,y */
1424
OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1425
VE0_VALID |
1426
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1427
(0 << VE0_OFFSET_SHIFT));
1428
1429
if (IS_GEN5(intel))
1430
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC <<
1431
VE1_VFCOMPONENT_0_SHIFT) |
1432
(BRW_VFCOMPONENT_STORE_SRC <<
1433
VE1_VFCOMPONENT_1_SHIFT) |
1434
(BRW_VFCOMPONENT_STORE_1_FLT <<
1435
VE1_VFCOMPONENT_2_SHIFT) |
1436
(BRW_VFCOMPONENT_STORE_1_FLT <<
1437
VE1_VFCOMPONENT_3_SHIFT));
1438
else
1439
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC <<
1440
VE1_VFCOMPONENT_0_SHIFT) |
1441
(BRW_VFCOMPONENT_STORE_SRC <<
1442
VE1_VFCOMPONENT_1_SHIFT) |
1443
(BRW_VFCOMPONENT_STORE_1_FLT <<
1444
VE1_VFCOMPONENT_2_SHIFT) |
1445
(BRW_VFCOMPONENT_STORE_1_FLT <<
1446
VE1_VFCOMPONENT_3_SHIFT) | (4 <<
1447
VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1448
/* u0, v0, w0 */
1449
OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (src_format << VE0_FORMAT_SHIFT) | ((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
1450
1451
if (IS_GEN5(intel))
1452
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC <<
1453
VE1_VFCOMPONENT_0_SHIFT) |
1454
(BRW_VFCOMPONENT_STORE_SRC <<
1455
VE1_VFCOMPONENT_1_SHIFT) | (w_component <<
1456
VE1_VFCOMPONENT_2_SHIFT)
1457
| (BRW_VFCOMPONENT_STORE_1_FLT <<
1458
VE1_VFCOMPONENT_3_SHIFT));
1459
else
1460
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (w_component << VE1_VFCOMPONENT_2_SHIFT) | (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | ((4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
1461
/* u1, v1, w1 */
1462
if (mask) {
1463
OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (src_format << VE0_FORMAT_SHIFT) | (((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */
1464
1465
if (IS_GEN5(intel))
1466
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC <<
1467
VE1_VFCOMPONENT_0_SHIFT) |
1468
(BRW_VFCOMPONENT_STORE_SRC <<
1469
VE1_VFCOMPONENT_1_SHIFT) |
1470
(w_component <<
1471
VE1_VFCOMPONENT_2_SHIFT) |
1472
(BRW_VFCOMPONENT_STORE_1_FLT <<
1473
VE1_VFCOMPONENT_3_SHIFT));
1474
else
1475
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (w_component << VE1_VFCOMPONENT_2_SHIFT) | (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | ((4 + 4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
1476
}
1477
}
1426
gen4_composite_vertex_elements(intel);
1478
1427
}
1479
1428
1480
1429
/**
1481
1430
* Returns whether the current set of composite state plus vertex buffer is
1482
1431
* expected to fit in the aperture.
1483
1432
*/
1484
static Bool i965_composite_check_aperture(ScrnInfoPtr scrn)
1433
static Bool i965_composite_check_aperture(intel_screen_private *intel)
1485
1434
{
1486
intel_screen_private *intel = intel_get_screen_private(scrn);
1487
1435
struct gen4_render_state *render_state = intel->gen4_render_state;
1488
1436
gen4_composite_op *composite_op = &render_state->composite_op;
1489
1437
drm_intel_bo *bo_table[] = {
1514
1462
render_state->gen6_blend_bo,
1515
1463
render_state->gen6_depth_stencil_bo,
1516
1464
};
1517
1465
1518
1466
if (INTEL_INFO(intel)->gen >= 60)
1519
1467
return drm_intel_bufmgr_check_aperture_space(gen6_bo_table,
1520
1468
ARRAY_SIZE(gen6_bo_table)) == 0;
1548
1496
priv->dst_bound = priv->src_bound = 0;
1549
1497
}
1550
1498
1499
static void
1500
i965_emit_composite_primitive_identity_source(intel_screen_private *intel,
1501
int srcX, int srcY,
1502
int maskX, int maskY,
1503
int dstX, int dstY,
1504
int w, int h)
1505
{
1506
OUT_VERTEX(dstX + w);
1507
OUT_VERTEX(dstY + h);
1508
OUT_VERTEX((srcX + w) * intel->scale_units[0][0]);
1509
OUT_VERTEX((srcY + h) * intel->scale_units[0][1]);
1510
1511
OUT_VERTEX(dstX);
1512
OUT_VERTEX(dstY + h);
1513
OUT_VERTEX(srcX * intel->scale_units[0][0]);
1514
OUT_VERTEX((srcY + h) * intel->scale_units[0][1]);
1515
1516
OUT_VERTEX(dstX);
1517
OUT_VERTEX(dstY);
1518
OUT_VERTEX(srcX * intel->scale_units[0][0]);
1519
OUT_VERTEX(srcY * intel->scale_units[0][1]);
1520
}
1521
1522
static void
1523
i965_emit_composite_primitive_affine_source(intel_screen_private *intel,
1524
int srcX, int srcY,
1525
int maskX, int maskY,
1526
int dstX, int dstY,
1527
int w, int h)
1528
{
1529
float src_x[3], src_y[3];
1530
1531
if (!intel_get_transformed_coordinates(srcX, srcY,
1532
intel->transform[0],
1533
&src_x[0],
1534
&src_y[0]))
1535
return;
1536
1537
if (!intel_get_transformed_coordinates(srcX, srcY + h,
1538
intel->transform[0],
1539
&src_x[1],
1540
&src_y[1]))
1541
return;
1542
1543
if (!intel_get_transformed_coordinates(srcX + w, srcY + h,
1544
intel->transform[0],
1545
&src_x[2],
1546
&src_y[2]))
1547
return;
1548
1549
OUT_VERTEX(dstX + w);
1550
OUT_VERTEX(dstY + h);
1551
OUT_VERTEX(src_x[2] * intel->scale_units[0][0]);
1552
OUT_VERTEX(src_y[2] * intel->scale_units[0][1]);
1553
1554
OUT_VERTEX(dstX);
1555
OUT_VERTEX(dstY + h);
1556
OUT_VERTEX(src_x[1] * intel->scale_units[0][0]);
1557
OUT_VERTEX(src_y[1] * intel->scale_units[0][1]);
1558
1559
OUT_VERTEX(dstX);
1560
OUT_VERTEX(dstY);
1561
OUT_VERTEX(src_x[0] * intel->scale_units[0][0]);
1562
OUT_VERTEX(src_y[0] * intel->scale_units[0][1]);
1563
}
1564
1565
static void
1566
i965_emit_composite_primitive_identity_source_mask(intel_screen_private *intel,
1567
int srcX, int srcY,
1568
int maskX, int maskY,
1569
int dstX, int dstY,
1570
int w, int h)
1571
{
1572
OUT_VERTEX(dstX + w);
1573
OUT_VERTEX(dstY + h);
1574
OUT_VERTEX((srcX + w) * intel->scale_units[0][0]);
1575
OUT_VERTEX((srcY + h) * intel->scale_units[0][1]);
1576
OUT_VERTEX((maskX + w) * intel->scale_units[1][0]);
1577
OUT_VERTEX((maskY + h) * intel->scale_units[1][1]);
1578
1579
OUT_VERTEX(dstX);
1580
OUT_VERTEX(dstY + h);
1581
OUT_VERTEX(srcX * intel->scale_units[0][0]);
1582
OUT_VERTEX((srcY + h) * intel->scale_units[0][1]);
1583
OUT_VERTEX(maskX * intel->scale_units[1][0]);
1584
OUT_VERTEX((maskY + h) * intel->scale_units[1][1]);
1585
1586
OUT_VERTEX(dstX);
1587
OUT_VERTEX(dstY);
1588
OUT_VERTEX(srcX * intel->scale_units[0][0]);
1589
OUT_VERTEX(srcY * intel->scale_units[0][1]);
1590
OUT_VERTEX(maskX * intel->scale_units[1][0]);
1591
OUT_VERTEX(maskY * intel->scale_units[1][1]);
1592
}
1593
1594
static void
1595
i965_emit_composite_primitive(intel_screen_private *intel,
1596
int srcX, int srcY,
1597
int maskX, int maskY,
1598
int dstX, int dstY,
1599
int w, int h)
1600
{
1601
float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3];
1602
Bool is_affine = intel->gen4_render_state->composite_op.is_affine;
1603
1604
if (! intel->render_source_is_solid) {
1605
if (is_affine) {
1606
if (!intel_get_transformed_coordinates(srcX, srcY,
1607
intel->transform[0],
1608
&src_x[0],
1609
&src_y[0]))
1610
return;
1611
1612
if (!intel_get_transformed_coordinates(srcX, srcY + h,
1613
intel->transform[0],
1614
&src_x[1],
1615
&src_y[1]))
1616
return;
1617
1618
if (!intel_get_transformed_coordinates(srcX + w, srcY + h,
1619
intel->transform[0],
1620
&src_x[2],
1621
&src_y[2]))
1622
return;
1623
} else {
1624
if (!intel_get_transformed_coordinates_3d(srcX, srcY,
1625
intel->transform[0],
1626
&src_x[0],
1627
&src_y[0],
1628
&src_w[0]))
1629
return;
1630
1631
if (!intel_get_transformed_coordinates_3d(srcX, srcY + h,
1632
intel->transform[0],
1633
&src_x[1],
1634
&src_y[1],
1635
&src_w[1]))
1636
return;
1637
1638
if (!intel_get_transformed_coordinates_3d(srcX + w, srcY + h,
1639
intel->transform[0],
1640
&src_x[2],
1641
&src_y[2],
1642
&src_w[2]))
1643
return;
1644
}
1645
}
1646
1647
if (intel->render_mask) {
1648
if (is_affine) {
1649
if (!intel_get_transformed_coordinates(maskX, maskY,
1650
intel->transform[1],
1651
&mask_x[0],
1652
&mask_y[0]))
1653
return;
1654
1655
if (!intel_get_transformed_coordinates(maskX, maskY + h,
1656
intel->transform[1],
1657
&mask_x[1],
1658
&mask_y[1]))
1659
return;
1660
1661
if (!intel_get_transformed_coordinates(maskX + w, maskY + h,
1662
intel->transform[1],
1663
&mask_x[2],
1664
&mask_y[2]))
1665
return;
1666
} else {
1667
if (!intel_get_transformed_coordinates_3d(maskX, maskY,
1668
intel->transform[1],
1669
&mask_x[0],
1670
&mask_y[0],
1671
&mask_w[0]))
1672
return;
1673
1674
if (!intel_get_transformed_coordinates_3d(maskX, maskY + h,
1675
intel->transform[1],
1676
&mask_x[1],
1677
&mask_y[1],
1678
&mask_w[1]))
1679
return;
1680
1681
if (!intel_get_transformed_coordinates_3d(maskX + w, maskY + h,
1682
intel->transform[1],
1683
&mask_x[2],
1684
&mask_y[2],
1685
&mask_w[2]))
1686
return;
1687
}
1688
}
1689
1690
OUT_VERTEX(dstX + w);
1691
OUT_VERTEX(dstY + h);
1692
OUT_VERTEX(src_x[2] * intel->scale_units[0][0]);
1693
OUT_VERTEX(src_y[2] * intel->scale_units[0][1]);
1694
if (!is_affine)
1695
OUT_VERTEX(src_w[2]);
1696
if (intel->render_mask) {
1697
OUT_VERTEX(mask_x[2] * intel->scale_units[1][0]);
1698
OUT_VERTEX(mask_y[2] * intel->scale_units[1][1]);
1699
if (!is_affine)
1700
OUT_VERTEX(mask_w[2]);
1701
}
1702
1703
OUT_VERTEX(dstX);
1704
OUT_VERTEX(dstY + h);
1705
OUT_VERTEX(src_x[1] * intel->scale_units[0][0]);
1706
OUT_VERTEX(src_y[1] * intel->scale_units[0][1]);
1707
if (!is_affine)
1708
OUT_VERTEX(src_w[1]);
1709
if (intel->render_mask) {
1710
OUT_VERTEX(mask_x[1] * intel->scale_units[1][0]);
1711
OUT_VERTEX(mask_y[1] * intel->scale_units[1][1]);
1712
if (!is_affine)
1713
OUT_VERTEX(mask_w[1]);
1714
}
1715
1716
OUT_VERTEX(dstX);
1717
OUT_VERTEX(dstY);
1718
OUT_VERTEX(src_x[0] * intel->scale_units[0][0]);
1719
OUT_VERTEX(src_y[0] * intel->scale_units[0][1]);
1720
if (!is_affine)
1721
OUT_VERTEX(src_w[0]);
1722
if (intel->render_mask) {
1723
OUT_VERTEX(mask_x[0] * intel->scale_units[1][0]);
1724
OUT_VERTEX(mask_y[0] * intel->scale_units[1][1]);
1725
if (!is_affine)
1726
OUT_VERTEX(mask_w[0]);
1727
}
1728
}
1729
1551
1730
Bool
1552
1731
i965_prepare_composite(int op, PicturePtr source_picture,
1553
1732
PicturePtr mask_picture, PicturePtr dest_picture,
1673
1852
composite_op->wm_kernel = WM_KERNEL_NOMASK_PROJECTIVE;
1674
1853
}
1675
1854
1855
intel->prim_emit = i965_emit_composite_primitive;
1856
if (!mask) {
1857
if (intel->transform[0] == NULL)
1858
intel->prim_emit = i965_emit_composite_primitive_identity_source;
1859
else if (composite_op->is_affine)
1860
intel->prim_emit = i965_emit_composite_primitive_affine_source;
1861
} else {
1862
if (intel->transform[0] == NULL && intel->transform[1] == NULL)
1863
intel->prim_emit = i965_emit_composite_primitive_identity_source_mask;
1864
}
1865
1676
1866
intel->floats_per_vertex =
1677
1867
2 + (mask ? 2 : 1) * (composite_op->is_affine ? 2: 3);
1678
1868
1679
if (!i965_composite_check_aperture(scrn)) {
1680
intel_batch_submit(scrn, FALSE);
1681
if (!i965_composite_check_aperture(scrn)) {
1869
if (!i965_composite_check_aperture(intel)) {
1870
intel_batch_submit(scrn);
1871
if (!i965_composite_check_aperture(intel)) {
1682
1872
intel_debug_fallback(scrn,
1683
1873
"Couldn't fit render operation "
1684
1874
"in aperture\n");
1697
1887
1698
1888
static void i965_select_vertex_buffer(struct intel_screen_private *intel)
1699
1889
{
1700
int vertex_size = intel->floats_per_vertex;
1890
int id = intel->gen4_render_state->composite_op.vertex_id;
1891
1892
if (intel->vertex_id & (1 << id))
1893
return;
1701
1894
1702
1895
/* Set up the pointer to our (single) vertex buffer */
1703
1896
OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3);
1706
1899
* frequently switching between vertex sizes, like rgb10text.
1707
1900
*/
1708
1901
if (INTEL_INFO(intel)->gen >= 60) {
1709
OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
1902
OUT_BATCH((id << GEN6_VB0_BUFFER_INDEX_SHIFT) |
1710
1903
GEN6_VB0_VERTEXDATA |
1711
(4*vertex_size << VB0_BUFFER_PITCH_SHIFT));
1904
(4*intel->floats_per_vertex << VB0_BUFFER_PITCH_SHIFT));
1712
1905
} else {
1713
OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
1906
OUT_BATCH((id << VB0_BUFFER_INDEX_SHIFT) |
1714
1907
VB0_VERTEXDATA |
1715
(4*vertex_size << VB0_BUFFER_PITCH_SHIFT));
1908
(4*intel->floats_per_vertex << VB0_BUFFER_PITCH_SHIFT));
1716
1909
}
1717
1910
OUT_RELOC(intel->vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
1718
1911
if (INTEL_INFO(intel)->gen >= 50)
1723
1916
OUT_BATCH(0);
1724
1917
OUT_BATCH(0); // ignore for VERTEXDATA, but still there
1725
1918
1726
intel->last_floats_per_vertex = vertex_size;
1919
intel->vertex_id |= 1 << id;
1727
1920
}
1728
1921
1729
1922
static void i965_bind_surfaces(struct intel_screen_private *intel)
1761
1954
{
1762
1955
ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum];
1763
1956
intel_screen_private *intel = intel_get_screen_private(scrn);
1764
struct gen4_render_state *render_state = intel->gen4_render_state;
1765
Bool has_mask;
1766
float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3];
1767
Bool is_affine = render_state->composite_op.is_affine;
1768
1769
if (is_affine) {
1770
if (!intel_get_transformed_coordinates(srcX, srcY,
1771
intel->transform[0],
1772
&src_x[0], &src_y[0]))
1773
return;
1774
if (!intel_get_transformed_coordinates(srcX, srcY + h,
1775
intel->transform[0],
1776
&src_x[1], &src_y[1]))
1777
return;
1778
if (!intel_get_transformed_coordinates(srcX + w, srcY + h,
1779
intel->transform[0],
1780
&src_x[2], &src_y[2]))
1781
return;
1782
} else {
1783
if (!intel_get_transformed_coordinates_3d(srcX, srcY,
1784
intel->transform[0],
1785
&src_x[0], &src_y[0],
1786
&src_w[0]))
1787
return;
1788
if (!intel_get_transformed_coordinates_3d(srcX, srcY + h,
1789
intel->transform[0],
1790
&src_x[1], &src_y[1],
1791
&src_w[1]))
1792
return;
1793
if (!intel_get_transformed_coordinates_3d(srcX + w, srcY + h,
1794
intel->transform[0],
1795
&src_x[2], &src_y[2],
1796
&src_w[2]))
1797
return;
1798
}
1799
1800
if (intel->render_mask) {
1801
has_mask = TRUE;
1802
if (is_affine) {
1803
if (!intel_get_transformed_coordinates(maskX, maskY,
1804
intel->
1805
transform[1],
1806
&mask_x[0],
1807
&mask_y[0]))
1808
return;
1809
if (!intel_get_transformed_coordinates(maskX, maskY + h,
1810
intel->
1811
transform[1],
1812
&mask_x[1],
1813
&mask_y[1]))
1814
return;
1815
if (!intel_get_transformed_coordinates
1816
(maskX + w, maskY + h, intel->transform[1],
1817
&mask_x[2], &mask_y[2]))
1818
return;
1819
} else {
1820
if (!intel_get_transformed_coordinates_3d(maskX, maskY,
1821
intel->
1822
transform[1],
1823
&mask_x[0],
1824
&mask_y[0],
1825
&mask_w[0]))
1826
return;
1827
if (!intel_get_transformed_coordinates_3d
1828
(maskX, maskY + h, intel->transform[1], &mask_x[1],
1829
&mask_y[1], &mask_w[1]))
1830
return;
1831
if (!intel_get_transformed_coordinates_3d
1832
(maskX + w, maskY + h, intel->transform[1],
1833
&mask_x[2], &mask_y[2], &mask_w[2]))
1834
return;
1835
}
1836
} else {
1837
has_mask = FALSE;
1838
}
1839
1840
if (!i965_composite_check_aperture(scrn))
1841
intel_batch_submit(scrn, FALSE);
1842
1957
1843
1958
intel_batch_start_atomic(scrn, 200);
1844
1959
if (intel->needs_render_state_emit) {
1845
1960
i965_bind_surfaces(intel);
1846
1961
1847
1962
if (INTEL_INFO(intel)->gen >= 60)
1848
gen6_emit_composite_state(scrn);
1963
gen6_emit_composite_state(intel);
1849
1964
else
1850
i965_emit_composite_state(scrn);
1965
i965_emit_composite_state(intel);
1851
1966
}
1852
1967
1853
if (intel->vertex_used &&
1854
intel->floats_per_vertex != intel->last_floats_per_vertex) {
1968
if (intel->floats_per_vertex != intel->last_floats_per_vertex) {
1855
1969
intel->vertex_index = (intel->vertex_used + intel->floats_per_vertex - 1) / intel->floats_per_vertex;
1856
1970
intel->vertex_used = intel->vertex_index * intel->floats_per_vertex;
1971
intel->last_floats_per_vertex = intel->floats_per_vertex;
1857
1972
}
1858
if (intel->floats_per_vertex != intel->last_floats_per_vertex ||
1859
intel_vertex_space(intel) < 3*4*intel->floats_per_vertex) {
1973
if (intel_vertex_space(intel) < 3*4*intel->floats_per_vertex) {
1860
1974
i965_vertex_flush(intel);
1861
1975
intel_next_vertex(intel);
1862
i965_select_vertex_buffer(intel);
1863
1976
intel->vertex_index = 0;
1864
1977
}
1978
i965_select_vertex_buffer(intel);
1865
1979
1866
1980
if (intel->vertex_offset == 0) {
1867
1981
OUT_BATCH(BRW_3DPRIMITIVE |
1878
1992
intel->vertex_count = intel->vertex_index;
1879
1993
}
1880
1994
1881
OUT_VERTEX(dstX + w);
1882
OUT_VERTEX(dstY + h);
1883
OUT_VERTEX(src_x[2] * intel->scale_units[0][0]);
1884
OUT_VERTEX(src_y[2] * intel->scale_units[0][1]);
1885
if (!is_affine)
1886
OUT_VERTEX(src_w[2]);
1887
if (has_mask) {
1888
OUT_VERTEX(mask_x[2] * intel->scale_units[1][0]);
1889
OUT_VERTEX(mask_y[2] * intel->scale_units[1][1]);
1890
if (!is_affine)
1891
OUT_VERTEX(mask_w[2]);
1892
}
1893
1894
/* rect (x1,y2) */
1895
OUT_VERTEX(dstX);
1896
OUT_VERTEX(dstY + h);
1897
OUT_VERTEX(src_x[1] * intel->scale_units[0][0]);
1898
OUT_VERTEX(src_y[1] * intel->scale_units[0][1]);
1899
if (!is_affine)
1900
OUT_VERTEX(src_w[1]);
1901
if (has_mask) {
1902
OUT_VERTEX(mask_x[1] * intel->scale_units[1][0]);
1903
OUT_VERTEX(mask_y[1] * intel->scale_units[1][1]);
1904
if (!is_affine)
1905
OUT_VERTEX(mask_w[1]);
1906
}
1907
1908
/* rect (x1,y1) */
1909
OUT_VERTEX(dstX);
1910
OUT_VERTEX(dstY);
1911
OUT_VERTEX(src_x[0] * intel->scale_units[0][0]);
1912
OUT_VERTEX(src_y[0] * intel->scale_units[0][1]);
1913
if (!is_affine)
1914
OUT_VERTEX(src_w[0]);
1915
if (has_mask) {
1916
OUT_VERTEX(mask_x[0] * intel->scale_units[1][0]);
1917
OUT_VERTEX(mask_y[0] * intel->scale_units[1][1]);
1918
if (!is_affine)
1919
OUT_VERTEX(mask_w[0]);
1920
}
1995
intel->prim_emit(intel,
1996
srcX, srcY,
1997
maskX, maskY,
1998
dstX, dstY,
1999
w, h);
1921
2000
intel->vertex_index += 3;
1922
2001
1923
2002
if (INTEL_INFO(intel)->gen < 50) {
1936
2015
intel->last_floats_per_vertex = 0;
1937
2016
intel->vertex_index = 0;
1938
2017
2018
intel->gen4_render_state->composite_op.vertex_id = -1;
2019
1939
2020
intel->gen6_render_state.num_sf_outputs = 0;
1940
2021
intel->gen6_render_state.samplers = NULL;
1941
2022
intel->gen6_render_state.blend = -1;
1942
intel->gen6_render_state.blend = -1;
1943
2023
intel->gen6_render_state.kernel = NULL;
1944
intel->gen6_render_state.vertex_size = 0;
1945
intel->gen6_render_state.vertex_type = 0;
1946
2024
intel->gen6_render_state.drawrect = -1;
2025
2026
assert(intel->surface_reloc == 0);
1947
2027
}
1948
2028
1949
2029
/**
1952
2032
void gen4_render_state_init(ScrnInfoPtr scrn)
1953
2033
{
1954
2034
intel_screen_private *intel = intel_get_screen_private(scrn);
1955
struct gen4_render_state *render_state;
2035
struct gen4_render_state *render;
2036
const struct wm_kernel_info *wm_kernels;
1956
2037
int i, j, k, l, m;
1957
2038
drm_intel_bo *sf_kernel_bo, *sf_kernel_mask_bo;
1958
2039
drm_intel_bo *border_color_bo;
1964
2045
sizeof(intel->surface_data), 4096);
1965
2046
intel->surface_used = 0;
1966
2047
2048
if (intel->gen4_render_state == NULL)
2049
intel->gen4_render_state = calloc(sizeof(*render), 1);
2050
1967
2051
if (INTEL_INFO(intel)->gen >= 60)
1968
2052
return gen6_render_state_init(scrn);
1969
2053
1970
if (intel->gen4_render_state == NULL)
1971
intel->gen4_render_state = calloc(sizeof(*render_state), 1);
1972
1973
render_state = intel->gen4_render_state;
1974
1975
render_state->vs_state_bo = gen4_create_vs_unit_state(scrn);
2054
render = intel->gen4_render_state;
2055
render->composite_op.vertex_id = -1;
2056
2057
render->vs_state_bo = gen4_create_vs_unit_state(intel);
1976
2058
1977
2059
/* Set up the two SF states (one for blending with a mask, one without) */
1978
2060
if (IS_GEN5(intel)) {
1979
sf_kernel_bo = intel_bo_alloc_for_data(scrn,
2061
sf_kernel_bo = intel_bo_alloc_for_data(intel,
1980
2062
sf_kernel_static_gen5,
1981
2063
sizeof
1982
2064
(sf_kernel_static_gen5),
1983
2065
"sf kernel gen5");
1984
2066
sf_kernel_mask_bo =
1985
intel_bo_alloc_for_data(scrn, sf_kernel_mask_static_gen5,
2067
intel_bo_alloc_for_data(intel, sf_kernel_mask_static_gen5,
1986
2068
sizeof(sf_kernel_mask_static_gen5),
1987
2069
"sf mask kernel");
1988
2070
} else {
1989
sf_kernel_bo = intel_bo_alloc_for_data(scrn,
2071
sf_kernel_bo = intel_bo_alloc_for_data(intel,
1990
2072
sf_kernel_static,
1991
2073
sizeof(sf_kernel_static),
1992
2074
"sf kernel");
1993
sf_kernel_mask_bo = intel_bo_alloc_for_data(scrn,
2075
sf_kernel_mask_bo = intel_bo_alloc_for_data(intel,
1994
2076
sf_kernel_mask_static,
1995
2077
sizeof
1996
2078
(sf_kernel_mask_static),
1997
2079
"sf mask kernel");
1998
2080
}
1999
render_state->sf_state_bo = gen4_create_sf_state(scrn, sf_kernel_bo);
2000
render_state->sf_mask_state_bo = gen4_create_sf_state(scrn,
2001
sf_kernel_mask_bo);
2081
render->sf_state_bo = gen4_create_sf_state(intel, sf_kernel_bo);
2082
render->sf_mask_state_bo = gen4_create_sf_state(intel, sf_kernel_mask_bo);
2002
2083
drm_intel_bo_unreference(sf_kernel_bo);
2003
2084
drm_intel_bo_unreference(sf_kernel_mask_bo);
2004
2085
2005
for (m = 0; m < WM_KERNEL_COUNT; m++) {
2006
if (IS_GEN5(intel))
2007
render_state->wm_kernel_bo[m] =
2008
intel_bo_alloc_for_data(scrn,
2009
wm_kernels_gen5[m].data,
2010
wm_kernels_gen5[m].size,
2011
"WM kernel gen5");
2012
else
2013
render_state->wm_kernel_bo[m] =
2014
intel_bo_alloc_for_data(scrn,
2015
wm_kernels[m].data,
2016
wm_kernels[m].size,
2017
"WM kernel");
2086
wm_kernels = IS_GEN5(intel) ? wm_kernels_gen5 : wm_kernels_gen4;
2087
for (m = 0; m < KERNEL_COUNT; m++) {
2088
render->wm_kernel_bo[m] =
2089
intel_bo_alloc_for_data(intel,
2090
wm_kernels[m].data,
2091
wm_kernels[m].size,
2092
"WM kernel");
2018
2093
}
2019
2094
2020
2095
/* Set up the WM states: each filter/extend type for source and mask, per
2021
2096
* kernel.
2022
2097
*/
2023
border_color_bo = sampler_border_color_create(scrn);
2024
for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++) {
2025
for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++) {
2026
for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++) {
2027
for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++) {
2098
border_color_bo = sampler_border_color_create(intel);
2099
for (i = 0; i < FILTER_COUNT; i++) {
2100
for (j = 0; j < EXTEND_COUNT; j++) {
2101
for (k = 0; k < FILTER_COUNT; k++) {
2102
for (l = 0; l < EXTEND_COUNT; l++) {
2028
2103
drm_intel_bo *sampler_state_bo;
2029
2104
2030
2105
sampler_state_bo =
2031
gen4_create_sampler_state(scrn,
2106
gen4_create_sampler_state(intel,
2032
2107
i, j,
2033
2108
k, l,
2034
2109
border_color_bo);
2035
2110
2036
for (m = 0; m < WM_KERNEL_COUNT; m++) {
2037
if (IS_GEN5(intel))
2038
render_state->
2039
wm_state_bo[m][i][j]
2040
[k][l] =
2041
gen4_create_wm_state
2042
(scrn,
2043
wm_kernels_gen5[m].
2044
has_mask,
2045
render_state->
2046
wm_kernel_bo[m],
2047
sampler_state_bo);
2048
else
2049
render_state->
2050
wm_state_bo[m][i][j]
2051
[k][l] =
2052
gen4_create_wm_state
2053
(scrn,
2054
wm_kernels[m].
2055
has_mask,
2056
render_state->
2057
wm_kernel_bo[m],
2058
sampler_state_bo);
2111
for (m = 0; m < KERNEL_COUNT; m++) {
2112
render->wm_state_bo[m][i][j][k][l] =
2113
gen4_create_wm_state
2114
(intel,
2115
wm_kernels[m]. has_mask,
2116
render->wm_kernel_bo[m],
2117
sampler_state_bo);
2059
2118
}
2060
drm_intel_bo_unreference
2061
(sampler_state_bo);
2119
drm_intel_bo_unreference(sampler_state_bo);
2062
2120
}
2063
2121
}
2064
2122
}
2065
2123
}
2066
2124
drm_intel_bo_unreference(border_color_bo);
2067
2125
2068
render_state->cc_state_bo = gen4_create_cc_unit_state(scrn);
2126
render->cc_state_bo = gen4_create_cc_unit_state(intel);
2069
2127
}
2070
2128
2071
2129
/**
2082
2140
drm_intel_bo_unreference(render_state->sf_state_bo);
2083
2141
drm_intel_bo_unreference(render_state->sf_mask_state_bo);
2084
2142
2085
for (i = 0; i < WM_KERNEL_COUNT; i++)
2143
for (i = 0; i < KERNEL_COUNT; i++)
2086
2144
drm_intel_bo_unreference(render_state->wm_kernel_bo[i]);
2087
2145
2088
for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++)
2089
for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++)
2090
for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++)
2091
for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++)
2092
for (m = 0; m < WM_KERNEL_COUNT; m++)
2146
for (i = 0; i < FILTER_COUNT; i++)
2147
for (j = 0; j < EXTEND_COUNT; j++)
2148
for (k = 0; k < FILTER_COUNT; k++)
2149
for (l = 0; l < EXTEND_COUNT; l++)
2150
for (m = 0; m < KERNEL_COUNT; m++)
2093
2151
drm_intel_bo_unreference
2094
2152
(render_state->
2095
2153
wm_state_bo[m][i][j][k]
2096
2154
[l]);
2097
2155
2098
for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++)
2099
for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++)
2100
for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++)
2101
for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++)
2156
for (i = 0; i < FILTER_COUNT; i++)
2157
for (j = 0; j < EXTEND_COUNT; j++)
2158
for (k = 0; k < FILTER_COUNT; k++)
2159
for (l = 0; l < EXTEND_COUNT; l++)
2102
2160
drm_intel_bo_unreference(render_state->ps_sampler_state_bo[i][j][k][l]);
2103
2161
2104
2162
drm_intel_bo_unreference(render_state->cc_state_bo);
2117
2175
#define GEN6_BLEND_STATE_PADDED_SIZE ALIGN(sizeof(struct gen6_blend_state), 64)
2118
2176
2119
2177
static drm_intel_bo *
2120
gen6_composite_create_cc_state(ScrnInfoPtr scrn)
2178
gen6_composite_create_cc_state(intel_screen_private *intel)
2121
2179
{
2122
intel_screen_private *intel = intel_get_screen_private(scrn);
2123
struct gen6_color_calc_state *cc_state;
2180
struct gen6_color_calc_state *state;
2124
2181
drm_intel_bo *cc_bo;
2125
2182
2126
2183
cc_bo = drm_intel_bo_alloc(intel->bufmgr,
2127
2184
"gen6 CC state",
2128
sizeof(*cc_state),
2185
sizeof(*state),
2129
2186
4096);
2130
2187
drm_intel_bo_map(cc_bo, TRUE);
2131
cc_state = cc_bo->virtual;
2132
memset(cc_state, 0, sizeof(*cc_state));
2133
cc_state->constant_r = 1.0;
2134
cc_state->constant_g = 0.0;
2135
cc_state->constant_b = 1.0;
2136
cc_state->constant_a = 1.0;
2188
state = cc_bo->virtual;
2189
memset(state, 0, sizeof(*state));
2190
state->constant_r = 1.0;
2191
state->constant_g = 0.0;
2192
state->constant_b = 1.0;
2193
state->constant_a = 1.0;
2137
2194
drm_intel_bo_unmap(cc_bo);
2138
2195
2139
2196
return cc_bo;
2140
2197
}
2141
2198
2142
2199
static drm_intel_bo *
2143
gen6_composite_create_blend_state(ScrnInfoPtr scrn)
2200
gen6_composite_create_blend_state(intel_screen_private *intel)
2144
2201
{
2145
intel_screen_private *intel = intel_get_screen_private(scrn);
2146
struct gen6_blend_state *blend_state;
2147
2202
drm_intel_bo *blend_bo;
2148
int src_blend, dst_blend;
2203
int src, dst;
2149
2204
2150
2205
blend_bo = drm_intel_bo_alloc(intel->bufmgr,
2151
2206
"gen6 BLEND state",
2154
2209
drm_intel_bo_map(blend_bo, TRUE);
2155
2210
memset(blend_bo->virtual, 0, blend_bo->size);
2156
2211
2157
for (src_blend = 0; src_blend < BRW_BLENDFACTOR_COUNT; src_blend++) {
2158
for (dst_blend = 0; dst_blend < BRW_BLENDFACTOR_COUNT; dst_blend++) {
2159
uint32_t blend_state_offset = ((src_blend * BRW_BLENDFACTOR_COUNT) + dst_blend) * GEN6_BLEND_STATE_PADDED_SIZE;
2160
2161
blend_state = (struct gen6_blend_state *)((char *)blend_bo->virtual + blend_state_offset);
2162
blend_state->blend0.dest_blend_factor = dst_blend;
2163
blend_state->blend0.source_blend_factor = src_blend;
2164
blend_state->blend0.blend_func = BRW_BLENDFUNCTION_ADD;
2165
blend_state->blend0.ia_blend_enable = 0;
2166
blend_state->blend0.blend_enable = 1;
2167
2168
blend_state->blend1.post_blend_clamp_enable = 1;
2169
blend_state->blend1.pre_blend_clamp_enable = 1;
2170
blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2171
blend_state->blend1.dither_enable = 0;
2172
blend_state->blend1.logic_op_enable = 0;
2173
blend_state->blend1.alpha_test_enable = 0;
2212
for (src = 0; src < BRW_BLENDFACTOR_COUNT; src++) {
2213
for (dst = 0; dst < BRW_BLENDFACTOR_COUNT; dst++) {
2214
uint32_t blend_state_offset = (src * BRW_BLENDFACTOR_COUNT + dst) * GEN6_BLEND_STATE_PADDED_SIZE;
2215
struct gen6_blend_state *blend;
2216
2217
blend = (struct gen6_blend_state *)((char *)blend_bo->virtual + blend_state_offset);
2218
blend->blend0.dest_blend_factor = dst;
2219
blend->blend0.source_blend_factor = src;
2220
blend->blend0.blend_func = BRW_BLENDFUNCTION_ADD;
2221
blend->blend0.blend_enable = 1;
2222
2223
blend->blend1.post_blend_clamp_enable = 1;
2224
blend->blend1.pre_blend_clamp_enable = 1;
2174
2225
}
2175
2226
}
2176
2227
2179
2230
}
2180
2231
2181
2232
static drm_intel_bo *
2182
gen6_composite_create_depth_stencil_state(ScrnInfoPtr scrn)
2233
gen6_composite_create_depth_stencil_state(intel_screen_private *intel)
2183
2234
{
2184
intel_screen_private *intel = intel_get_screen_private(scrn);
2185
struct gen6_depth_stencil_state *depth_stencil_state;
2235
struct gen6_depth_stencil_state *state;
2186
2236
drm_intel_bo *depth_stencil_bo;
2187
2237
2188
2238
depth_stencil_bo = drm_intel_bo_alloc(intel->bufmgr,
2189
2239
"gen6 DEPTH_STENCIL state",
2190
sizeof(*depth_stencil_state),
2240
sizeof(*state),
2191
2241
4096);
2192
2242
drm_intel_bo_map(depth_stencil_bo, TRUE);
2193
depth_stencil_state = depth_stencil_bo->virtual;
2194
memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
2243
state = depth_stencil_bo->virtual;
2244
memset(state, 0, sizeof(*state));
2195
2245
drm_intel_bo_unmap(depth_stencil_bo);
2196
2246
2197
2247
return depth_stencil_bo;
2370
2420
2371
2421
OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
2372
2422
OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
2373
(1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
2374
(1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
2423
(1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
2424
(1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
2375
2425
OUT_BATCH(0);
2376
2426
OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
2377
2427
OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
2410
2460
I915_GEM_DOMAIN_INSTRUCTION, 0,
2411
2461
0);
2412
2462
OUT_BATCH((1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
2413
(num_surfaces << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2463
(num_surfaces << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2414
2464
OUT_BATCH(0);
2415
2465
OUT_BATCH((6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
2416
2466
OUT_BATCH(((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
2440
2490
{
2441
2491
OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2));
2442
2492
OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) |
2443
(BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT));
2493
(BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT));
2444
2494
OUT_BATCH(0);
2445
2495
OUT_BATCH(0);
2446
2496
OUT_BATCH(0);
2454
2504
static void
2455
2505
gen6_composite_drawing_rectangle(intel_screen_private *intel,
2456
2506
PixmapPtr dest)
2457
2458
2507
{
2459
2508
uint32_t dw =
2460
2509
DRAW_YMAX(dest->drawable.height - 1) |
2482
2531
* texture coordinate 0: (u0, v0) if (is_affine is TRUE) else (u0, v0, w0)
2483
2532
* texture coordinate 1 if (has_mask is TRUE): same as above
2484
2533
*/
2534
gen4_composite_op *composite_op = &intel->gen4_render_state->composite_op;
2485
2535
int nelem = has_mask ? 2 : 1;
2486
2536
int selem = is_affine ? 2 : 3;
2487
2537
uint32_t w_component;
2488
2538
uint32_t src_format;
2489
2490
if (intel->gen6_render_state.vertex_size == nelem &&
2491
intel->gen6_render_state.vertex_type == selem)
2539
int id;
2540
2541
id = has_mask << 1 | is_affine;
2542
2543
if (composite_op->vertex_id == id)
2492
2544
return;
2493
2545
2494
intel->gen6_render_state.vertex_size = nelem;
2495
intel->gen6_render_state.vertex_type = selem;
2546
composite_op->vertex_id = id;
2496
2547
2497
2548
if (is_affine) {
2498
2549
src_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
2513
2564
OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS |
2514
2565
((2 * (2 + nelem)) + 1 - 2));
2515
2566
2516
OUT_BATCH((0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2517
GEN6_VE0_VALID |
2518
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2519
(0 << VE0_OFFSET_SHIFT));
2567
OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID |
2568
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2569
(0 << VE0_OFFSET_SHIFT));
2520
2570
OUT_BATCH((BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) |
2521
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) |
2522
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) |
2523
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
2571
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) |
2572
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) |
2573
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
2524
2574
2525
2575
/* x,y */
2526
OUT_BATCH((0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2527
GEN6_VE0_VALID |
2528
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2529
(0 << VE0_OFFSET_SHIFT)); /* offsets vb in bytes */
2576
OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID |
2577
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2578
(0 << VE0_OFFSET_SHIFT)); /* offsets vb in bytes */
2530
2579
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2531
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2532
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2533
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2580
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2581
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2582
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2534
2583
2535
2584
/* u0, v0, w0 */
2536
OUT_BATCH((0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2537
GEN6_VE0_VALID |
2538
(src_format << VE0_FORMAT_SHIFT) |
2539
((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
2585
OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID |
2586
(src_format << VE0_FORMAT_SHIFT) |
2587
((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
2540
2588
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2541
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2542
(w_component << VE1_VFCOMPONENT_2_SHIFT) |
2543
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2589
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2590
(w_component << VE1_VFCOMPONENT_2_SHIFT) |
2591
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2544
2592
2545
2593
/* u1, v1, w1 */
2546
2594
if (has_mask) {
2547
OUT_BATCH((0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2548
GEN6_VE0_VALID |
2549
(src_format << VE0_FORMAT_SHIFT) |
2550
(((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */
2595
OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2596
GEN6_VE0_VALID |
2597
(src_format << VE0_FORMAT_SHIFT) |
2598
(((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */
2551
2599
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2552
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2553
(w_component << VE1_VFCOMPONENT_2_SHIFT) |
2554
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2600
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2601
(w_component << VE1_VFCOMPONENT_2_SHIFT) |
2602
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2555
2603
}
2556
2604
}
2557
2605
2558
2606
static void
2559
gen6_emit_composite_state(ScrnInfoPtr scrn)
2607
gen6_emit_composite_state(struct intel_screen_private *intel)
2560
2608
{
2561
intel_screen_private *intel = intel_get_screen_private(scrn);
2562
struct gen4_render_state *render_state = intel->gen4_render_state;
2563
gen4_composite_op *composite_op = &render_state->composite_op;
2564
int op = composite_op->op;
2565
PicturePtr mask_picture = intel->render_mask_picture;
2566
PicturePtr dest_picture = intel->render_dest_picture;
2567
PixmapPtr mask = intel->render_mask;
2568
PixmapPtr dest = intel->render_dest;
2609
struct gen4_render_state *render = intel->gen4_render_state;
2610
gen4_composite_op *composite_op = &render->composite_op;
2569
2611
sampler_state_filter_t src_filter = composite_op->src_filter;
2570
2612
sampler_state_filter_t mask_filter = composite_op->mask_filter;
2571
2613
sampler_state_extend_t src_extend = composite_op->src_extend;
2572
2614
sampler_state_extend_t mask_extend = composite_op->mask_extend;
2573
2615
Bool is_affine = composite_op->is_affine;
2574
uint32_t src_blend, dst_blend;
2575
drm_intel_bo *ps_sampler_state_bo = render_state->ps_sampler_state_bo[src_filter][src_extend][mask_filter][mask_extend];
2616
Bool has_mask = intel->render_mask != NULL;
2617
uint32_t src, dst;
2618
drm_intel_bo *ps_sampler_state_bo = render->ps_sampler_state_bo[src_filter][src_extend][mask_filter][mask_extend];
2576
2619
2577
2620
intel->needs_render_state_emit = FALSE;
2578
2621
if (intel->needs_3d_invariant) {
2579
2622
gen6_composite_invariant_states(intel);
2580
2623
gen6_composite_viewport_state_pointers(intel,
2581
render_state->cc_vp_bo);
2624
render->cc_vp_bo);
2582
2625
gen6_composite_urb(intel);
2583
2626
2584
2627
gen6_composite_vs_state(intel);
2590
2633
intel->needs_3d_invariant = FALSE;
2591
2634
}
2592
2635
2593
i965_get_blend_cntl(op,
2594
mask_picture,
2595
dest_picture->format,
2596
&src_blend,
2597
&dst_blend);
2636
i965_get_blend_cntl(composite_op->op,
2637
intel->render_mask_picture,
2638
intel->render_dest_picture->format,
2639
&src, &dst);
2598
2640
2599
2641
if (intel->surface_reloc == 0)
2600
2642
gen6_composite_state_base_address(intel);
2601
2643
2602
2644
gen6_composite_cc_state_pointers(intel,
2603
((src_blend * BRW_BLENDFACTOR_COUNT) + dst_blend) * GEN6_BLEND_STATE_PADDED_SIZE);
2645
(src * BRW_BLENDFACTOR_COUNT + dst) * GEN6_BLEND_STATE_PADDED_SIZE);
2604
2646
gen6_composite_sampler_state_pointers(intel, ps_sampler_state_bo);
2605
gen6_composite_sf_state(intel, mask != 0);
2647
gen6_composite_sf_state(intel, has_mask);
2606
2648
gen6_composite_wm_state(intel,
2607
mask != 0,
2608
render_state->wm_kernel_bo[composite_op->wm_kernel]);
2649
has_mask,
2650
render->wm_kernel_bo[composite_op->wm_kernel]);
2609
2651
gen6_composite_binding_table_pointers(intel);
2610
2652
2611
gen6_composite_drawing_rectangle(intel, dest);
2612
gen6_composite_vertex_element_state(intel, mask != 0, is_affine);
2653
gen6_composite_drawing_rectangle(intel, intel->render_dest);
2654
gen6_composite_vertex_element_state(intel, has_mask, is_affine);
2613
2655
}
2614
2656
2615
2657
static void
2616
2658
gen6_render_state_init(ScrnInfoPtr scrn)
2617
2659
{
2618
2660
intel_screen_private *intel = intel_get_screen_private(scrn);
2619
struct gen4_render_state *render_state;
2661
struct gen4_render_state *render;
2620
2662
int i, j, k, l, m;
2621
2663
drm_intel_bo *border_color_bo;
2622
2664
2665
render= intel->gen4_render_state;
2666
render->composite_op.vertex_id = -1;
2667
2623
2668
intel->gen6_render_state.num_sf_outputs = 0;
2624
2669
intel->gen6_render_state.samplers = NULL;
2625
2670
intel->gen6_render_state.blend = -1;
2626
2671
intel->gen6_render_state.kernel = NULL;
2627
intel->gen6_render_state.vertex_size = 0;
2628
intel->gen6_render_state.vertex_type = 0;
2629
2672
intel->gen6_render_state.drawrect = -1;
2630
2673
2631
if (intel->gen4_render_state == NULL)
2632
intel->gen4_render_state = calloc(sizeof(*render_state), 1);
2633
2634
render_state = intel->gen4_render_state;
2635
2636
for (m = 0; m < WM_KERNEL_COUNT; m++) {
2637
render_state->wm_kernel_bo[m] =
2638
intel_bo_alloc_for_data(scrn,
2639
wm_kernels_gen6[m].data,
2640
wm_kernels_gen6[m].size,
2641
"WM kernel gen6");
2674
for (m = 0; m < KERNEL_COUNT; m++) {
2675
render->wm_kernel_bo[m] =
2676
intel_bo_alloc_for_data(intel,
2677
wm_kernels_gen6[m].data,
2678
wm_kernels_gen6[m].size,
2679
"WM kernel gen6");
2642
2680
}
2643
2681
2644
border_color_bo = sampler_border_color_create(scrn);
2682
border_color_bo = sampler_border_color_create(intel);
2645
2683
2646
for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++) {
2647
for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++) {
2648
for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++) {
2649
for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++) {
2650
render_state->ps_sampler_state_bo[i][j][k][l] =
2651
gen4_create_sampler_state(scrn,
2652
i, j,
2653
k, l,
2654
border_color_bo);
2684
for (i = 0; i < FILTER_COUNT; i++) {
2685
for (j = 0; j < EXTEND_COUNT; j++) {
2686
for (k = 0; k < FILTER_COUNT; k++) {
2687
for (l = 0; l < EXTEND_COUNT; l++) {
2688
render->ps_sampler_state_bo[i][j][k][l] =
2689
gen4_create_sampler_state(intel,
2690
i, j,
2691
k, l,
2692
border_color_bo);
2655
2693
}
2656
2694
}
2657
2695
}
2658
2696
}
2659
2697
2660
2698
drm_intel_bo_unreference(border_color_bo);
2661
render_state->cc_vp_bo = gen4_create_cc_viewport(scrn);
2662
render_state->cc_state_bo = gen6_composite_create_cc_state(scrn);
2663
render_state->gen6_blend_bo = gen6_composite_create_blend_state(scrn);
2664
render_state->gen6_depth_stencil_bo = gen6_composite_create_depth_stencil_state(scrn);
2699
render->cc_vp_bo = gen4_create_cc_viewport(intel);
2700
render->cc_state_bo = gen6_composite_create_cc_state(intel);
2701
render->gen6_blend_bo = gen6_composite_create_blend_state(intel);
2702
render->gen6_depth_stencil_bo = gen6_composite_create_depth_stencil_state(intel);
2665
2703
}
2666
2704
2667
2705
void i965_vertex_flush(struct intel_screen_private *intel)
Loggerhead is a web-based interface for Breezy
Version: 2.0.1