← Back to branch summary

~ubuntu-branches/ubuntu/precise/xserver-xorg-video-intel/precise

« back to all changes in this revision

Viewing changes to src/i965_video.c

  • Committer: Bazaar Package Importer
  • Author(s): Christopher James Halse Rogers, Robert Hooker, Christopher James Halse Rogers
  • Date: 2011-08-09 10:10:02 UTC
  • mfrom: (0.1.21 experimental)
  • Revision ID: james.westby@ubuntu.com-20110809101002-pguc3kc6pzh1cp5h
Tags: 2:2.15.901-1ubuntu1
[ Robert Hooker ]
* Merge from debian-experimental, remaining changes:
  - 101_copy-fb.patch
    + Plymouth integration patch
  - 120_check_privates.patch
    + Check for null privates pointer on render_dest_picture.
  - debian/xserver-xorg-video-intel.preinst.in:
  - debian/xserver-xorg-video-intel.postinst.in:
    + Remove obsolete /etc/modprobe.d/i915-kms.conf file on upgrades.
      KMS is the kernel default.
* Dropped patches:
  - 121_fdo-28798-fix.patch (upstream)

[ Christopher James Halse Rogers ]
* Refresh 101_copy-fb.patch.

Show diffs side-by-side

added added

removed removed

Lines of Context:
src/i965_video.c
149
149
#include "exa_wm_write.g6b"
150
150
};
151
151
 
 
152
/* programs for Ivybridge */
 
153
static const uint32_t ps_kernel_packed_static_gen7[][4] = {
 
154
#include "exa_wm_src_affine.g7b"
 
155
#include "exa_wm_src_sample_argb.g7b"
 
156
#include "exa_wm_yuv_rgb.g7b"
 
157
#include "exa_wm_write.g7b"
 
158
};
 
159
 
 
160
static const uint32_t ps_kernel_planar_static_gen7[][4] = {
 
161
#include "exa_wm_src_affine.g7b"
 
162
#include "exa_wm_src_sample_planar.g7b"
 
163
#include "exa_wm_yuv_rgb.g7b"
 
164
#include "exa_wm_write.g7b"
 
165
};
 
166
 
 
167
#ifndef MAX2
 
168
#define MAX2(a,b) ((a) > (b) ? (a) : (b))
 
169
#endif
 
170
 
 
171
#define SURFACE_STATE_PADDED_SIZE_I965  ALIGN(sizeof(struct brw_surface_state), 32)
 
172
#define SURFACE_STATE_PADDED_SIZE_GEN7  ALIGN(sizeof(struct gen7_surface_state), 32)
 
173
#define SURFACE_STATE_PADDED_SIZE       MAX2(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
 
174
#define SURFACE_STATE_OFFSET(index)     (SURFACE_STATE_PADDED_SIZE * index)
 
175
 
152
176
static uint32_t float_to_uint(float f)
153
177
{
154
178
        union {
475
499
        drm_intel_bo_unmap(surface_bo);
476
500
}
477
501
 
 
502
static void gen7_create_dst_surface_state(ScrnInfoPtr scrn,
 
503
                                        PixmapPtr pixmap,
 
504
                                        drm_intel_bo *surf_bo,
 
505
                                        uint32_t offset)
 
506
{
 
507
        intel_screen_private *intel = intel_get_screen_private(scrn);
 
508
        struct gen7_surface_state *dest_surf_state;
 
509
        drm_intel_bo *pixmap_bo = intel_get_pixmap_bo(pixmap);
 
510
 
 
511
        if (drm_intel_bo_map(surf_bo, TRUE) != 0)
 
512
                return;
 
513
 
 
514
        dest_surf_state = (struct gen7_surface_state *)((char *)surf_bo->virtual + offset);
 
515
        memset(dest_surf_state, 0, sizeof(*dest_surf_state));
 
516
 
 
517
        dest_surf_state->ss0.surface_type = BRW_SURFACE_2D;
 
518
        dest_surf_state->ss0.tiled_surface = intel_pixmap_tiled(pixmap);
 
519
        dest_surf_state->ss0.tile_walk = 0;     /* TileX */
 
520
 
 
521
        if (intel->cpp == 2) {
 
522
                dest_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 
523
        } else {
 
524
                dest_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 
525
        }
 
526
 
 
527
        dest_surf_state->ss1.base_addr =
 
528
                intel_emit_reloc(surf_bo, 
 
529
                                offset + offsetof(struct gen7_surface_state, ss1),
 
530
                                pixmap_bo, 0, 
 
531
                                I915_GEM_DOMAIN_SAMPLER, 0);
 
532
 
 
533
        dest_surf_state->ss2.height = pixmap->drawable.height - 1;
 
534
        dest_surf_state->ss2.width = pixmap->drawable.width - 1;
 
535
 
 
536
        dest_surf_state->ss3.pitch = intel_pixmap_pitch(pixmap) - 1;
 
537
 
 
538
        drm_intel_bo_unmap(surf_bo); 
 
539
}
 
540
 
 
541
static void gen7_create_src_surface_state(ScrnInfoPtr scrn,
 
542
                                        drm_intel_bo * src_bo,
 
543
                                        uint32_t src_offset,
 
544
                                        int src_width,
 
545
                                        int src_height,
 
546
                                        int src_pitch,
 
547
                                        uint32_t src_surf_format,
 
548
                                        drm_intel_bo *surface_bo,
 
549
                                        uint32_t offset)
 
550
{
 
551
        struct gen7_surface_state *src_surf_state;
 
552
 
 
553
        if (drm_intel_bo_map(surface_bo, TRUE) != 0)
 
554
                return;
 
555
 
 
556
        src_surf_state = (struct gen7_surface_state *)((char *)surface_bo->virtual + offset);
 
557
        memset(src_surf_state, 0, sizeof(*src_surf_state));
 
558
 
 
559
        src_surf_state->ss0.surface_type = BRW_SURFACE_2D;
 
560
        src_surf_state->ss0.surface_format = src_surf_format;
 
561
 
 
562
        if (src_bo) {
 
563
                src_surf_state->ss1.base_addr =
 
564
                        intel_emit_reloc(surface_bo,
 
565
                                        offset + offsetof(struct gen7_surface_state, ss1),
 
566
                                        src_bo, src_offset,
 
567
                                        I915_GEM_DOMAIN_SAMPLER, 0);
 
568
        } else {
 
569
                src_surf_state->ss1.base_addr = src_offset;
 
570
        }
 
571
 
 
572
        src_surf_state->ss2.width = src_width - 1;
 
573
        src_surf_state->ss2.height = src_height - 1;
 
574
 
 
575
        src_surf_state->ss3.pitch = src_pitch - 1;
 
576
 
 
577
        drm_intel_bo_unmap(surface_bo);
 
578
}
 
579
 
478
580
static void i965_create_binding_table(ScrnInfoPtr scrn,
479
581
                                drm_intel_bo *bind_bo,
480
582
                                int n_surf)
486
588
        if (drm_intel_bo_map(bind_bo, TRUE) != 0)
487
589
                return;
488
590
 
489
 
        binding_table = (uint32_t*)((char *)bind_bo->virtual + n_surf * ALIGN(sizeof(struct brw_surface_state), 32));
 
591
        binding_table = (uint32_t*)((char *)bind_bo->virtual + n_surf * SURFACE_STATE_PADDED_SIZE);
490
592
 
491
593
        for (i = 0; i < n_surf; i++)
492
 
                binding_table[i] = i * ALIGN(sizeof(struct brw_surface_state), 32);
 
594
                binding_table[i] = i * SURFACE_STATE_PADDED_SIZE;
493
595
 
494
596
        drm_intel_bo_unmap(bind_bo);
495
597
}
514
616
        return sampler_bo;
515
617
}
516
618
 
 
619
static drm_intel_bo *gen7_create_sampler_state(ScrnInfoPtr scrn)
 
620
{
 
621
        intel_screen_private *intel = intel_get_screen_private(scrn);
 
622
        drm_intel_bo *sampler_bo;
 
623
        struct gen7_sampler_state *sampler_state;
 
624
 
 
625
        if (intel_alloc_and_map(intel, "textured video sampler state", 4096,
 
626
                                &sampler_bo, &sampler_state) != 0)
 
627
                return NULL;
 
628
 
 
629
        sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 
630
        sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 
631
        sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 
632
        sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 
633
        sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 
634
 
 
635
        drm_intel_bo_unmap(sampler_bo);
 
636
        return sampler_bo;
 
637
}
 
638
 
517
639
static drm_intel_bo *i965_create_vs_state(ScrnInfoPtr scrn)
518
640
{
519
641
        intel_screen_private *intel = intel_get_screen_private(scrn);
863
985
        OUT_BATCH(0);           /* clip */
864
986
        OUT_BATCH(0);           /* sf */
865
987
        /* Only the PS uses the binding table */
866
 
        OUT_BATCH((n_src_surf + 1) * ALIGN(sizeof(struct brw_surface_state), 32));
 
988
        OUT_BATCH((n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
867
989
 
868
990
        /* Blend constant color (magenta is fun) */
869
991
        OUT_BATCH(BRW_3DSTATE_CONSTANT_COLOR | 3);
1056
1178
        surface_state_binding_table_bo = 
1057
1179
                drm_intel_bo_alloc(intel->bufmgr,
1058
1180
                                "surface state & binding table",
1059
 
                                (n_src_surf + 1) * (ALIGN(sizeof(struct brw_surface_state), 32) + sizeof(uint32_t)),
 
1181
                                (n_src_surf + 1) * (SURFACE_STATE_PADDED_SIZE + sizeof(uint32_t)),
1060
1182
                                4096);
1061
1183
 
1062
1184
        if (!surface_state_binding_table_bo)
1073
1195
                                        src_pitch[src_surf],
1074
1196
                                        src_surf_format,
1075
1197
                                        surface_state_binding_table_bo,
1076
 
                                        (src_surf + 1) * ALIGN(sizeof(struct brw_surface_state), 32));
 
1198
                                        (src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
1077
1199
        }
1078
1200
 
1079
1201
        i965_create_binding_table(scrn, surface_state_binding_table_bo, n_src_surf + 1);
1323
1445
 
1324
1446
        blend_state->blend1.logic_op_enable = 1;
1325
1447
        blend_state->blend1.logic_op_func = 0xc;
 
1448
        blend_state->blend1.pre_blend_clamp_enable = 1;
1326
1449
 
1327
1450
        drm_intel_bo_unmap(blend_bo);
1328
1451
        return blend_bo;
1351
1474
gen6_create_vidoe_objects(ScrnInfoPtr scrn)
1352
1475
{
1353
1476
        intel_screen_private *intel = intel_get_screen_private(scrn);
 
1477
        drm_intel_bo *(*create_sampler_state)(ScrnInfoPtr);
 
1478
        const uint32_t *packed_ps_kernel, *planar_ps_kernel;
 
1479
        unsigned int packed_ps_size, planar_ps_size;
 
1480
        
 
1481
        if (INTEL_INFO(intel)->gen >= 70) {
 
1482
                create_sampler_state = gen7_create_sampler_state;
 
1483
                packed_ps_kernel = &ps_kernel_packed_static_gen7[0][0];
 
1484
                packed_ps_size = sizeof(ps_kernel_packed_static_gen7);
 
1485
                planar_ps_kernel = &ps_kernel_planar_static_gen7[0][0];
 
1486
                planar_ps_size = sizeof(ps_kernel_planar_static_gen7);
 
1487
        } else {
 
1488
                create_sampler_state = i965_create_sampler_state;
 
1489
                packed_ps_kernel = &ps_kernel_packed_static_gen6[0][0];
 
1490
                packed_ps_size = sizeof(ps_kernel_packed_static_gen6);
 
1491
                planar_ps_kernel = &ps_kernel_planar_static_gen6[0][0];
 
1492
                planar_ps_size = sizeof(ps_kernel_planar_static_gen6);
 
1493
        }
1354
1494
 
1355
1495
        if (intel->video.gen4_sampler_bo == NULL)
1356
 
                intel->video.gen4_sampler_bo = i965_create_sampler_state(scrn);
 
1496
                intel->video.gen4_sampler_bo = create_sampler_state(scrn);
1357
1497
                
1358
1498
        if (intel->video.wm_prog_packed_bo == NULL)
1359
1499
                intel->video.wm_prog_packed_bo =
1360
1500
                        i965_create_program(scrn,
1361
 
                                        &ps_kernel_packed_static_gen6[0][0],
1362
 
                                        sizeof(ps_kernel_packed_static_gen6));
 
1501
                                        packed_ps_kernel,
 
1502
                                        packed_ps_size);
1363
1503
                
1364
1504
        if (intel->video.wm_prog_planar_bo == NULL)
1365
1505
                intel->video.wm_prog_planar_bo =
1366
1506
                        i965_create_program(scrn,
1367
 
                                        &ps_kernel_planar_static_gen6[0][0],
1368
 
                                        sizeof(ps_kernel_planar_static_gen6));
 
1507
                                        planar_ps_kernel,
 
1508
                                        planar_ps_size);
1369
1509
 
1370
1510
        if (intel->video.gen4_cc_vp_bo == NULL)
1371
1511
                intel->video.gen4_cc_vp_bo = i965_create_cc_vp_state(scrn);
1390
1530
}
1391
1531
 
1392
1532
static void
1393
 
gen6_upload_invarient_states(ScrnInfoPtr scrn)
1394
 
{
1395
 
        intel_screen_private *intel = intel_get_screen_private(scrn);
1396
 
 
1397
 
        OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
1398
 
        OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
1399
 
                BRW_PIPE_CONTROL_WC_FLUSH |
1400
 
                BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1401
 
                BRW_PIPE_CONTROL_NOWRITE);
1402
 
        OUT_BATCH(0); /* write address */
1403
 
        OUT_BATCH(0); /* write data */
1404
 
 
1405
 
        OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1406
 
 
1407
 
        OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
1408
 
        OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
1409
 
                GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
1410
 
        OUT_BATCH(0);
1411
 
 
1412
 
        OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
1413
 
        OUT_BATCH(1);
1414
 
 
1415
 
        /* Set system instruction pointer */
1416
 
        OUT_BATCH(BRW_STATE_SIP | 0);
1417
 
        OUT_BATCH(0);
1418
 
}
1419
 
 
1420
 
static void
1421
1533
gen6_upload_state_base_address(ScrnInfoPtr scrn, drm_intel_bo *surface_state_binding_table_bo)
1422
1534
{
1423
1535
        intel_screen_private *intel = intel_get_screen_private(scrn);
1435
1547
}
1436
1548
 
1437
1549
static void
1438
 
gen6_upload_viewport_state_pointers(ScrnInfoPtr scrn)
1439
 
{
1440
 
        intel_screen_private *intel = intel_get_screen_private(scrn);
1441
 
 
1442
 
        OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
1443
 
                GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
1444
 
                (4 - 2));
1445
 
        OUT_BATCH(0);
1446
 
        OUT_BATCH(0);
1447
 
        OUT_RELOC(intel->video.gen4_cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1448
 
}
1449
 
 
1450
 
static void
1451
 
gen6_upload_urb(ScrnInfoPtr scrn)
1452
 
{
1453
 
        intel_screen_private *intel = intel_get_screen_private(scrn);
1454
 
 
1455
 
        OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2));
1456
 
        OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
1457
 
                (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
1458
 
        OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
1459
 
                (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
1460
 
}
1461
 
 
1462
 
static void
1463
 
gen6_upload_cc_state_pointers(ScrnInfoPtr scrn)
1464
 
{
1465
 
        intel_screen_private *intel = intel_get_screen_private(scrn);
1466
 
 
1467
 
        OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
1468
 
        OUT_RELOC(intel->video.gen6_blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1469
 
        OUT_RELOC(intel->video.gen6_depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1470
 
        OUT_RELOC(intel->video.gen4_cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1471
 
}
1472
 
 
1473
 
static void
1474
 
gen6_upload_sampler_state_pointers(ScrnInfoPtr scrn)
1475
 
{
1476
 
        intel_screen_private *intel = intel_get_screen_private(scrn);
1477
 
 
1478
 
        OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
1479
 
                GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
1480
 
                (4 - 2));
1481
 
        OUT_BATCH(0); /* VS */
1482
 
        OUT_BATCH(0); /* GS */
1483
 
        OUT_RELOC(intel->video.gen4_sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1484
 
}
1485
 
 
1486
 
static void
1487
 
gen6_upload_binding_table(ScrnInfoPtr scrn, uint32_t ps_binding_table_offset)
1488
 
{
1489
 
        intel_screen_private *intel = intel_get_screen_private(scrn);
1490
 
 
1491
 
        /* Binding table pointers */
1492
 
        OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS |
1493
 
                GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
1494
 
                (4 - 2));
1495
 
        OUT_BATCH(0);           /* vs */
1496
 
        OUT_BATCH(0);           /* gs */
1497
 
        /* Only the PS uses the binding table */
1498
 
        OUT_BATCH(ps_binding_table_offset);
1499
 
}
1500
 
 
1501
 
static void
1502
 
gen6_upload_depth_buffer_state(ScrnInfoPtr scrn)
1503
 
{
1504
 
        intel_screen_private *intel = intel_get_screen_private(scrn);
1505
 
 
1506
 
        OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2));
1507
 
        OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) |
1508
 
                (BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT));
1509
 
        OUT_BATCH(0);
1510
 
        OUT_BATCH(0);
1511
 
        OUT_BATCH(0);
1512
 
        OUT_BATCH(0);
1513
 
        OUT_BATCH(0);
1514
 
 
1515
 
        OUT_BATCH(BRW_3DSTATE_CLEAR_PARAMS | (2 - 2));
1516
 
        OUT_BATCH(0);
1517
 
}
1518
 
 
1519
 
static void
1520
1550
gen6_upload_drawing_rectangle(ScrnInfoPtr scrn, PixmapPtr pixmap)
1521
1551
{
1522
1552
        intel_screen_private *intel = intel_get_screen_private(scrn);
1528
1558
}
1529
1559
 
1530
1560
static void 
1531
 
gen6_upload_vs_state(ScrnInfoPtr scrn)
1532
 
{
1533
 
        intel_screen_private *intel = intel_get_screen_private(scrn);
1534
 
 
1535
 
        /* disable VS constant buffer */
1536
 
        OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
1537
 
        OUT_BATCH(0);
1538
 
        OUT_BATCH(0);
1539
 
        OUT_BATCH(0);
1540
 
        OUT_BATCH(0);
1541
 
        
1542
 
        OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
1543
 
        OUT_BATCH(0); /* without VS kernel */
1544
 
        OUT_BATCH(0);
1545
 
        OUT_BATCH(0);
1546
 
        OUT_BATCH(0);
1547
 
        OUT_BATCH(0); /* pass-through */
1548
 
}
1549
 
 
1550
 
static void 
1551
 
gen6_upload_gs_state(ScrnInfoPtr scrn)
1552
 
{
1553
 
        intel_screen_private *intel = intel_get_screen_private(scrn);
1554
 
 
1555
 
        /* disable GS constant buffer */
1556
 
        OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
1557
 
        OUT_BATCH(0);
1558
 
        OUT_BATCH(0);
1559
 
        OUT_BATCH(0);
1560
 
        OUT_BATCH(0);
1561
 
        
1562
 
        OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
1563
 
        OUT_BATCH(0); /* without GS kernel */
1564
 
        OUT_BATCH(0);
1565
 
        OUT_BATCH(0);
1566
 
        OUT_BATCH(0);
1567
 
        OUT_BATCH(0);
1568
 
        OUT_BATCH(0); /* pass-through */
1569
 
}
1570
 
 
1571
 
static void 
1572
 
gen6_upload_clip_state(ScrnInfoPtr scrn)
1573
 
{
1574
 
        intel_screen_private *intel = intel_get_screen_private(scrn);
1575
 
 
1576
 
        OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
1577
 
        OUT_BATCH(0);
1578
 
        OUT_BATCH(0); /* pass-through */
1579
 
        OUT_BATCH(0);
1580
 
}
1581
 
 
1582
 
static void 
1583
 
gen6_upload_sf_state(ScrnInfoPtr scrn)
1584
 
{
1585
 
        intel_screen_private *intel = intel_get_screen_private(scrn);
1586
 
 
1587
 
        OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
1588
 
        OUT_BATCH((1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
1589
 
                (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
1590
 
                (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
1591
 
        OUT_BATCH(0);
1592
 
        OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
1593
 
        OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
1594
 
        OUT_BATCH(0);
1595
 
        OUT_BATCH(0);
1596
 
        OUT_BATCH(0);
1597
 
        OUT_BATCH(0);
1598
 
        OUT_BATCH(0); /* DW9 */
1599
 
        OUT_BATCH(0);
1600
 
        OUT_BATCH(0);
1601
 
        OUT_BATCH(0);
1602
 
        OUT_BATCH(0);
1603
 
        OUT_BATCH(0); /* DW14 */
1604
 
        OUT_BATCH(0);
1605
 
        OUT_BATCH(0);
1606
 
        OUT_BATCH(0);
1607
 
        OUT_BATCH(0);
1608
 
        OUT_BATCH(0); /* DW19 */
1609
 
}
1610
 
 
1611
 
static void 
1612
1561
gen6_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed)
1613
1562
{
1614
1563
        intel_screen_private *intel = intel_get_screen_private(scrn);
1672
1621
                (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1673
1622
}
1674
1623
 
1675
 
static void
1676
 
gen6_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo *surface_state_binding_table_bo, int n_src_surf, PixmapPtr pixmap)
 
1624
static void 
 
1625
gen6_upload_vertex_buffer(ScrnInfoPtr scrn, drm_intel_bo *vertex_bo, uint32_t end_address_offset)
 
1626
{
 
1627
        intel_screen_private *intel = intel_get_screen_private(scrn);
 
1628
 
 
1629
        /* Set up the pointer to our vertex buffer */
 
1630
        OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | (5 - 2));
 
1631
        /* four 32-bit floats per vertex */
 
1632
        OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
 
1633
                GEN6_VB0_VERTEXDATA | 
 
1634
                ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
 
1635
        OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
 
1636
        OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, end_address_offset);
 
1637
        OUT_BATCH(0);   /* reserved */
 
1638
}
 
1639
 
 
1640
static void
 
1641
gen6_upload_primitive(ScrnInfoPtr scrn)
 
1642
{
 
1643
        intel_screen_private *intel = intel_get_screen_private(scrn);
 
1644
 
 
1645
        OUT_BATCH(BRW_3DPRIMITIVE | 
 
1646
                BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL | 
 
1647
                (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) | 
 
1648
                (0 << 9) | /* Internal Vertex Count */
 
1649
                (6 - 2));
 
1650
        OUT_BATCH(3);   /* vertex count per instance */
 
1651
        OUT_BATCH(0);   /* start vertex offset */
 
1652
        OUT_BATCH(1);   /* single instance */
 
1653
        OUT_BATCH(0);   /* start instance location */
 
1654
        OUT_BATCH(0);   /* index buffer offset, ignored */
 
1655
}
 
1656
 
 
1657
static void
 
1658
gen6_emit_video_setup(ScrnInfoPtr scrn,
 
1659
                drm_intel_bo *surface_state_binding_table_bo, int n_src_surf,
 
1660
                PixmapPtr pixmap,
 
1661
                drm_intel_bo *vertex_bo, uint32_t end_address_offset)
1677
1662
{
1678
1663
        intel_screen_private *intel = intel_get_screen_private(scrn);
1679
1664
 
1681
1666
        IntelEmitInvarientState(scrn);
1682
1667
        intel->last_3d = LAST_3D_VIDEO;
1683
1668
 
1684
 
        gen6_upload_invarient_states(scrn);
 
1669
        gen6_upload_invariant_states(intel);
1685
1670
        gen6_upload_state_base_address(scrn, surface_state_binding_table_bo);
1686
 
        gen6_upload_viewport_state_pointers(scrn);
1687
 
        gen6_upload_urb(scrn);
1688
 
        gen6_upload_cc_state_pointers(scrn);
1689
 
        gen6_upload_sampler_state_pointers(scrn);
1690
 
        gen6_upload_vs_state(scrn);
1691
 
        gen6_upload_gs_state(scrn);
1692
 
        gen6_upload_clip_state(scrn);
1693
 
        gen6_upload_sf_state(scrn);
 
1671
        gen6_upload_viewport_state_pointers(intel, intel->video.gen4_cc_vp_bo);
 
1672
        gen6_upload_urb(intel);
 
1673
        gen6_upload_cc_state_pointers(intel, intel->video.gen6_blend_bo, intel->video.gen4_cc_bo, intel->video.gen6_depth_stencil_bo, 0);
 
1674
        gen6_upload_sampler_state_pointers(intel, intel->video.gen4_sampler_bo);
 
1675
        gen6_upload_vs_state(intel);
 
1676
        gen6_upload_gs_state(intel);
 
1677
        gen6_upload_clip_state(intel);
 
1678
        gen6_upload_sf_state(intel, 1, 0);
1694
1679
        gen6_upload_wm_state(scrn, n_src_surf == 1 ? TRUE : FALSE);
1695
 
        gen6_upload_binding_table(scrn, (n_src_surf + 1) * ALIGN(sizeof(struct brw_surface_state), 32));;
1696
 
        gen6_upload_depth_buffer_state(scrn);
1697
 
        gen6_upload_drawing_rectangle(scrn, pixmap);
1698
 
        gen6_upload_vertex_element_state(scrn);
 
1680
        gen6_upload_binding_table(intel, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
 
1681
        gen6_upload_depth_buffer_state(intel);
 
1682
        gen6_upload_drawing_rectangle(scrn, pixmap);
 
1683
        gen6_upload_vertex_element_state(scrn);
 
1684
        gen6_upload_vertex_buffer(scrn, vertex_bo, end_address_offset);
 
1685
        gen6_upload_primitive(scrn);
 
1686
}
 
1687
 
 
1688
static void 
 
1689
gen7_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed)
 
1690
{
 
1691
        intel_screen_private *intel = intel_get_screen_private(scrn);
 
1692
 
 
1693
        /* disable WM constant buffer */
 
1694
        OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
 
1695
        OUT_BATCH(0);
 
1696
        OUT_BATCH(0);
 
1697
        OUT_BATCH(0);
 
1698
        OUT_BATCH(0);
 
1699
        OUT_BATCH(0);
 
1700
        OUT_BATCH(0);
 
1701
 
 
1702
        OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2));
 
1703
        OUT_BATCH(GEN7_WM_DISPATCH_ENABLE |
 
1704
                GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
 
1705
        OUT_BATCH(0);
 
1706
 
 
1707
        OUT_BATCH(GEN7_3DSTATE_PS | (8 - 2));
 
1708
 
 
1709
        if (is_packed) {
 
1710
                OUT_RELOC(intel->video.wm_prog_packed_bo,
 
1711
                        I915_GEM_DOMAIN_INSTRUCTION, 0,
 
1712
                        0);
 
1713
                OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
 
1714
                        (2 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 
1715
        } else {
 
1716
                OUT_RELOC(intel->video.wm_prog_planar_bo,
 
1717
                        I915_GEM_DOMAIN_INSTRUCTION, 0,
 
1718
                        0);
 
1719
                OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
 
1720
                        (7 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 
1721
        }
 
1722
 
 
1723
        OUT_BATCH(0); /* scratch space base offset */
 
1724
        OUT_BATCH(
 
1725
                ((86 - 1) << GEN7_PS_MAX_THREADS_SHIFT) |
 
1726
                GEN7_PS_ATTRIBUTE_ENABLE |
 
1727
                GEN7_PS_16_DISPATCH_ENABLE);
 
1728
        OUT_BATCH(
 
1729
                (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
 
1730
        OUT_BATCH(0); /* kernel 1 pointer */
 
1731
        OUT_BATCH(0); /* kernel 2 pointer */
 
1732
}
 
1733
 
 
1734
static void 
 
1735
gen7_upload_vertex_buffer(ScrnInfoPtr scrn, drm_intel_bo *vertex_bo, uint32_t end_address_offset)
 
1736
{
 
1737
        intel_screen_private *intel = intel_get_screen_private(scrn);
 
1738
 
 
1739
        /* Set up the pointer to our vertex buffer */
 
1740
        OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | (5 - 2));
 
1741
        /* four 32-bit floats per vertex */
 
1742
        OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
 
1743
                GEN6_VB0_VERTEXDATA | 
 
1744
                GEN7_VB0_ADDRESS_MODIFYENABLE |
 
1745
                ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
 
1746
        OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
 
1747
        OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, end_address_offset);
 
1748
        OUT_BATCH(0);   /* reserved */
 
1749
}
 
1750
 
 
1751
static void
 
1752
gen7_upload_primitive(ScrnInfoPtr scrn)
 
1753
{
 
1754
        intel_screen_private *intel = intel_get_screen_private(scrn);
 
1755
 
 
1756
        OUT_BATCH(BRW_3DPRIMITIVE | (7 - 2));
 
1757
        OUT_BATCH(_3DPRIM_RECTLIST |
 
1758
                GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
 
1759
        OUT_BATCH(3); /* vertex count per instance */
 
1760
        OUT_BATCH(0); /* start vertex offset */
 
1761
        OUT_BATCH(1); /* single instance */
 
1762
        OUT_BATCH(0); /* start instance location */
 
1763
        OUT_BATCH(0);
 
1764
}
 
1765
 
 
1766
static void
 
1767
gen7_emit_video_setup(ScrnInfoPtr scrn,
 
1768
                drm_intel_bo *surface_state_binding_table_bo, int n_src_surf,
 
1769
                PixmapPtr pixmap,
 
1770
                drm_intel_bo *vertex_bo, uint32_t end_address_offset)
 
1771
{
 
1772
        intel_screen_private *intel = intel_get_screen_private(scrn);
 
1773
 
 
1774
        assert(n_src_surf == 1 || n_src_surf == 6);
 
1775
        IntelEmitInvarientState(scrn);
 
1776
        intel->last_3d = LAST_3D_VIDEO;
 
1777
 
 
1778
        gen6_upload_invariant_states(intel);
 
1779
        gen6_upload_state_base_address(scrn, surface_state_binding_table_bo);
 
1780
        gen7_upload_viewport_state_pointers(intel, intel->video.gen4_cc_vp_bo);
 
1781
        gen7_upload_urb(intel);
 
1782
        gen7_upload_cc_state_pointers(intel, intel->video.gen6_blend_bo, intel->video.gen4_cc_bo, intel->video.gen6_depth_stencil_bo, 0);
 
1783
        gen7_upload_sampler_state_pointers(intel, intel->video.gen4_sampler_bo);
 
1784
        gen7_upload_bypass_states(intel);
 
1785
        gen6_upload_vs_state(intel);
 
1786
        gen6_upload_clip_state(intel);
 
1787
        gen7_upload_sf_state(intel, 1, 0);
 
1788
        gen7_upload_wm_state(scrn, n_src_surf == 1 ? TRUE : FALSE);
 
1789
        gen7_upload_binding_table(intel, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
 
1790
        gen7_upload_depth_buffer_state(intel);
 
1791
        gen6_upload_drawing_rectangle(scrn, pixmap);
 
1792
        gen6_upload_vertex_element_state(scrn);
 
1793
        gen7_upload_vertex_buffer(scrn, vertex_bo, end_address_offset);
 
1794
        gen7_upload_primitive(scrn);
1699
1795
}
1700
1796
 
1701
1797
void Gen6DisplayVideoTextured(ScrnInfoPtr scrn,
1718
1814
        int src_height[6];
1719
1815
        int src_pitch[6];
1720
1816
        drm_intel_bo *surface_state_binding_table_bo;
 
1817
        void (*create_dst_surface_state)(ScrnInfoPtr,
 
1818
                                        PixmapPtr, 
 
1819
                                        drm_intel_bo *, 
 
1820
                                        uint32_t);
 
1821
        void (*create_src_surface_state)(ScrnInfoPtr,
 
1822
                                        drm_intel_bo *,
 
1823
                                        uint32_t, int, 
 
1824
                                        int, int, uint32_t, 
 
1825
                                        drm_intel_bo *, uint32_t);
 
1826
        void (*emit_video_setup)(ScrnInfoPtr,
 
1827
                                drm_intel_bo *, int,
 
1828
                                PixmapPtr,
 
1829
                                drm_intel_bo *, uint32_t);
 
1830
 
 
1831
        if (INTEL_INFO(intel)->gen >= 70) {
 
1832
                create_dst_surface_state = gen7_create_dst_surface_state;
 
1833
                create_src_surface_state = gen7_create_src_surface_state;
 
1834
                emit_video_setup = gen7_emit_video_setup;
 
1835
        } else {
 
1836
                create_dst_surface_state = i965_create_dst_surface_state;
 
1837
                create_src_surface_state = i965_create_src_surface_state;
 
1838
                emit_video_setup = gen6_emit_video_setup;
 
1839
        }
1721
1840
 
1722
1841
        src_surf_base[0] = adaptor_priv->YBufOffset;
1723
1842
        src_surf_base[1] = adaptor_priv->YBufOffset;
1753
1872
        surface_state_binding_table_bo = 
1754
1873
                drm_intel_bo_alloc(intel->bufmgr,
1755
1874
                                "surface state & binding table",
1756
 
                                (n_src_surf + 1) * (ALIGN(sizeof(struct brw_surface_state), 32) + sizeof(uint32_t)),
 
1875
                                (n_src_surf + 1) * (SURFACE_STATE_PADDED_SIZE + sizeof(uint32_t)),
1757
1876
                                4096);
1758
1877
 
1759
1878
        if (!surface_state_binding_table_bo)
1760
1879
                return;
1761
1880
                                
1762
 
        i965_create_dst_surface_state(scrn, pixmap, surface_state_binding_table_bo, 0);
 
1881
        create_dst_surface_state(scrn, pixmap, surface_state_binding_table_bo, 0);
1763
1882
 
1764
1883
        for (src_surf = 0; src_surf < n_src_surf; src_surf++) {
1765
 
                i965_create_src_surface_state(scrn,
 
1884
                create_src_surface_state(scrn,
1766
1885
                                        adaptor_priv->buf,
1767
1886
                                        src_surf_base[src_surf],
1768
1887
                                        src_width[src_surf],
1770
1889
                                        src_pitch[src_surf],
1771
1890
                                        src_surf_format,
1772
1891
                                        surface_state_binding_table_bo,
1773
 
                                        (src_surf + 1) * ALIGN(sizeof(struct brw_surface_state), 32));
 
1892
                                        (src_surf + 1) * SURFACE_STATE_PADDED_SIZE);
1774
1893
        }
1775
1894
 
1776
1895
        i965_create_binding_table(scrn, surface_state_binding_table_bo, n_src_surf + 1);
1853
1972
                        intel_batch_submit(scrn);
1854
1973
 
1855
1974
                intel_batch_start_atomic(scrn, 200);
1856
 
                gen6_emit_video_setup(scrn, surface_state_binding_table_bo, n_src_surf, pixmap);
1857
 
 
1858
 
                /* Set up the pointer to our vertex buffer */
1859
 
                OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | (5 - 2));
1860
 
                /* four 32-bit floats per vertex */
1861
 
                OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
1862
 
                        GEN6_VB0_VERTEXDATA | 
1863
 
                        ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1864
 
                OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
1865
 
                OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, i * 4);
1866
 
                OUT_BATCH(0);   /* reserved */
1867
 
 
1868
 
                OUT_BATCH(BRW_3DPRIMITIVE | 
1869
 
                        BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL | 
1870
 
                        (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) | 
1871
 
                        (0 << 9) | /* Internal Vertex Count */
1872
 
                        (6 - 2));
1873
 
                OUT_BATCH(3);   /* vertex count per instance */
1874
 
                OUT_BATCH(0);   /* start vertex offset */
1875
 
                OUT_BATCH(1);   /* single instance */
1876
 
                OUT_BATCH(0);   /* start instance location */
1877
 
                OUT_BATCH(0);   /* index buffer offset, ignored */
1878
 
 
 
1975
                emit_video_setup(scrn, surface_state_binding_table_bo, n_src_surf, pixmap, vb_bo, i * 4);
1879
1976
                intel_batch_end_atomic(scrn);
 
1977
 
1880
1978
                drm_intel_bo_unreference(vb_bo);
1881
1979
        }
1882
1980