~ubuntu-branches/ubuntu/precise/xserver-xorg-video-mach64-lts-quantal/precise-proposed : revision 1

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/*

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*

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* Permission to use, copy, modify, distribute, and sell this software and its

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* documentation for any purpose is hereby granted without fee, provided that

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* the above copyright notice appear in all copies and that both that copyright

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* notice and this permission notice appear in supporting documentation, and

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* that the name of Marc Aurele La France not be used in advertising or

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* publicity pertaining to distribution of the software without specific,

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* written prior permission. Marc Aurele La France makes no representations

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* about the suitability of this software for any purpose. It is provided

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* "as-is" without express or implied warranty.

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*

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* MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,

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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO

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* EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR

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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,

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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER

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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR

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* PERFORMANCE OF THIS SOFTWARE.

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*

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* Acknowledgements:

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* Jake Richter, Panacea Inc., Londonderry, New Hampshire, U.S.A.

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* Kevin E. Martin, martin@cs.unc.edu

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* Tiago Gons, tiago@comosjn.hobby.nl

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* Rickard E. Faith, faith@cs.unc.edu

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* Scott Laird, lair@kimbark.uchicago.edu

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*

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* The intent here is to list all I/O ports for VGA (and its predecessors),

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* ATI VGA Wonder, 8514/A, ATI Mach8, ATI Mach32 and ATI Mach64 video adapters,

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* not just the ones in use by the ATI driver.

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*/

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#ifndef ___ATIREGS_H___

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#define ___ATIREGS_H___ 1

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#include "atiutil.h"

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/* I/O decoding definitions */

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#define SPARSE_IO_BASE 0x03fcu

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#define SPARSE_IO_SELECT 0xfc00u

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#define BLOCK_IO_BASE 0xff00u

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#define BLOCK_IO_SELECT 0x00fcu

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#define MM_IO_SELECT 0x03fcu

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#define BLOCK_SELECT 0x0400u

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#define DWORD_SELECT (BLOCK_SELECT | MM_IO_SELECT)

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#define IO_BYTE_SELECT 0x0003u

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#define SPARSE_IO_PORT (SPARSE_IO_BASE | IO_BYTE_SELECT)

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#define BLOCK_IO_PORT (BLOCK_IO_BASE | IO_BYTE_SELECT)

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#define IOPortTag(_SparseIOSelect, _BlockIOSelect) \

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(SetBits(_SparseIOSelect, SPARSE_IO_SELECT) | \

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SetBits(_BlockIOSelect, DWORD_SELECT))

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#define SparseIOTag(_IOSelect) IOPortTag(_IOSelect, 0)

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#define BlockIOTag(_IOSelect) IOPortTag(0, _IOSelect)

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/* MDA/[M]CGA/EGA/VGA I/O ports */

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#define GENVS 0x0102u /* Write (and Read on uC only) */

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#define R_GENLPS 0x03b9u /* Read */

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#define GENHP 0x03bfu

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#define ATTRX 0x03c0u

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#define ATTRD 0x03c1u

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#define GENS0 0x03c2u /* Read */

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#define GENMO 0x03c2u /* Write */

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#define GENENB 0x03c3u /* Read */

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#define SEQX 0x03c4u

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#define SEQD 0x03c5u

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#define VGA_DAC_MASK 0x03c6u

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#define VGA_DAC_READ 0x03c7u

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#define VGA_DAC_WRITE 0x03c8u

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#define VGA_DAC_DATA 0x03c9u

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#define R_GENFC 0x03cau /* Read */

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/* ? 0x03cbu */

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#define R_GENMO 0x03ccu /* Read */

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/* ? 0x03cdu */

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#define GRAX 0x03ceu

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#define GRAD 0x03cfu

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#define GENB 0x03d9u

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#define GENLPS 0x03dcu /* Write */

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#define KCX 0x03ddu

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#define KCD 0x03deu

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#define GENENA 0x46e8u /* Write */

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/* I/O port base numbers */

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#define MonochromeIOBase 0x03b0u

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#define ColourIOBase 0x03d0u

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/* Other MDA/[M]CGA/EGA/VGA I/O ports */

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/* ?(_IOBase) ((_IOBase) + 0x00u) */ /* CRTX synonym */

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/* ?(_IOBase) ((_IOBase) + 0x01u) */ /* CRTD synonym */

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/* ?(_IOBase) ((_IOBase) + 0x02u) */ /* CRTX synonym */

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/* ?(_IOBase) ((_IOBase) + 0x03u) */ /* CRTD synonym */

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#define CRTX(_IOBase) ((_IOBase) + 0x04u)

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#define CRTD(_IOBase) ((_IOBase) + 0x05u)

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/* ?(_IOBase) ((_IOBase) + 0x06u) */

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/* ?(_IOBase) ((_IOBase) + 0x07u) */

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#define GENMC(_IOBase) ((_IOBase) + 0x08u)

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/* ?(_IOBase) ((_IOBase) + 0x09u) */ /* R_GENLPS/GENB */

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#define GENS1(_IOBase) ((_IOBase) + 0x0au) /* Read */

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#define GENFC(_IOBase) ((_IOBase) + 0x0au) /* Write */

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#define GENLPC(_IOBase) ((_IOBase) + 0x0bu)

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/* ?(_IOBase) ((_IOBase) + 0x0cu) */ /* /GENLPS */

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/* ?(_IOBase) ((_IOBase) + 0x0du) */ /* /KCX */

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/* ?(_IOBase) ((_IOBase) + 0x0eu) */ /* /KCD */

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/* ?(_IOBase) ((_IOBase) + 0x0fu) */ /* GENHP/ */

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/* 8514/A VESA approved register definitions */

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#define DISP_STAT 0x02e8u /* Read */

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#define SENSE 0x0001u /* Presumably belong here */

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#define VBLANK 0x0002u

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#define HORTOG 0x0004u

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#define H_TOTAL 0x02e8u /* Write */

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#define IBM_DAC_MASK 0x02eau

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#define IBM_DAC_READ 0x02ebu

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#define IBM_DAC_WRITE 0x02ecu

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#define IBM_DAC_DATA 0x02edu

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#define H_DISP 0x06e8u /* Write */

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#define H_SYNC_STRT 0x0ae8u /* Write */

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#define H_SYNC_WID 0x0ee8u /* Write */

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#define HSYNCPOL_POS 0x0000u

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#define HSYNCPOL_NEG 0x0020u

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#define H_POLARITY_POS HSYNCPOL_POS /* Sigh */

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#define H_POLARITY_NEG HSYNCPOL_NEG /* Sigh */

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#define V_TOTAL 0x12e8u /* Write */

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#define V_DISP 0x16e8u /* Write */

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#define V_SYNC_STRT 0x1ae8u /* Write */

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#define V_SYNC_WID 0x1ee8u /* Write */

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#define VSYNCPOL_POS 0x0000u

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#define VSYNCPOL_NEG 0x0020u

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#define V_POLARITY_POS VSYNCPOL_POS /* Sigh */

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#define V_POLARITY_NEG VSYNCPOL_NEG /* Sigh */

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#define DISP_CNTL 0x22e8u /* Write */

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#define ODDBNKENAB 0x0001u

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#define MEMCFG_2 0x0000u

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#define MEMCFG_4 0x0002u

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#define MEMCFG_6 0x0004u

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#define MEMCFG_8 0x0006u

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#define DBLSCAN 0x0008u

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#define INTERLACE 0x0010u

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#define DISPEN_NC 0x0000u

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#define DISPEN_ENAB 0x0020u

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#define DISPEN_DISAB 0x0040u

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#define R_H_TOTAL 0x26e8u /* Read */

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/* ? 0x2ae8u */

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/* ? 0x2ee8u */

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/* ? 0x32e8u */

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/* ? 0x36e8u */

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/* ? 0x3ae8u */

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/* ? 0x3ee8u */

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#define SUBSYS_STAT 0x42e8u /* Read */

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#define VBLNKFLG 0x0001u

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#define PICKFLAG 0x0002u

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#define INVALIDIO 0x0004u

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#define GPIDLE 0x0008u

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#define MONITORID_MASK 0x0070u

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/* MONITORID_? 0x0000u */

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#define MONITORID_8507 0x0010u

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#define MONITORID_8514 0x0020u

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/* MONITORID_? 0x0030u */

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/* MONITORID_? 0x0040u */

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#define MONITORID_8503 0x0050u

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#define MONITORID_8512 0x0060u

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#define MONITORID_8513 0x0060u

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#define MONITORID_NONE 0x0070u

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#define _8PLANE 0x0080u

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#define SUBSYS_CNTL 0x42e8u /* Write */

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#define RVBLNKFLG 0x0001u

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#define RPICKFLAG 0x0002u

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#define RINVALIDIO 0x0004u

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#define RGPIDLE 0x0008u

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#define IVBLNKFLG 0x0100u

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#define IPICKFLAG 0x0200u

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#define IINVALIDIO 0x0400u

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#define IGPIDLE 0x0800u

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#define CHPTEST_NC 0x0000u

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#define CHPTEST_NORMAL 0x1000u

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#define CHPTEST_ENAB 0x2000u

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#define GPCTRL_NC 0x0000u

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#define GPCTRL_ENAB 0x4000u

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#define GPCTRL_RESET 0x8000u

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#define ROM_PAGE_SEL 0x46e8u /* Write */

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#define ADVFUNC_CNTL 0x4ae8u /* Write */

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#define DISABPASSTHRU 0x0001u

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#define CLOKSEL 0x0004u

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/* ? 0x4ee8u */

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#define EXT_CONFIG_0 0x52e8u /* C & T 82C480 */

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#define EXT_CONFIG_1 0x56e8u /* C & T 82C480 */

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#define EXT_CONFIG_2 0x5ae8u /* C & T 82C480 */

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#define EXT_CONFIG_3 0x5ee8u /* C & T 82C480 */

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/* ? 0x62e8u */

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/* ? 0x66e8u */

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/* ? 0x6ae8u */

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/* ? 0x6ee8u */

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/* ? 0x72e8u */

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/* ? 0x76e8u */

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/* ? 0x7ae8u */

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/* ? 0x7ee8u */

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#define CUR_Y 0x82e8u

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#define CUR_X 0x86e8u

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#define DESTY_AXSTP 0x8ae8u /* Write */

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#define DESTX_DIASTP 0x8ee8u /* Write */

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#define ERR_TERM 0x92e8u

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#define MAJ_AXIS_PCNT 0x96e8u /* Write */

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#define GP_STAT 0x9ae8u /* Read */

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#define GE_STAT 0x9ae8u /* Alias */

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#define DATARDY 0x0100u

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#define DATA_READY DATARDY /* Alias */

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#define GPBUSY 0x0200u

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#define CMD 0x9ae8u /* Write */

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#define WRTDATA 0x0001u

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#define PLANAR 0x0002u

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#define LASTPIX 0x0004u

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#define LINETYPE 0x0008u

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#define DRAW 0x0010u

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#define INC_X 0x0020u

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#define YMAJAXIS 0x0040u

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#define INC_Y 0x0080u

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#define PCDATA 0x0100u

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#define _16BIT 0x0200u

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#define CMD_NOP 0x0000u

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#define CMD_OP_MSK 0xf000u

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#define BYTSEQ 0x1000u

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#define CMD_LINE 0x2000u

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#define CMD_RECT 0x4000u

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#define CMD_RECTV1 0x6000u

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#define CMD_RECTV2 0x8000u

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#define CMD_LINEAF 0xa000u

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#define CMD_BITBLT 0xc000u

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#define SHORT_STROKE 0x9ee8u /* Write */

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#define SSVDRAW 0x0010u

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#define VECDIR_000 0x0000u

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#define VECDIR_045 0x0020u

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#define VECDIR_090 0x0040u

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#define VECDIR_135 0x0060u

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#define VECDIR_180 0x0080u

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#define VECDIR_225 0x00a0u

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#define VECDIR_270 0x00c0u

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#define VECDIR_315 0x00e0u

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#define BKGD_COLOR 0xa2e8u /* Write */

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#define FRGD_COLOR 0xa6e8u /* Write */

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#define WRT_MASK 0xaae8u /* Write */

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#define RD_MASK 0xaee8u /* Write */

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#define COLOR_CMP 0xb2e8u /* Write */

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#define BKGD_MIX 0xb6e8u /* Write */

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/* 0x001fu See MIX_* definitions below */

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#define BSS_BKGDCOL 0x0000u

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#define BSS_FRGDCOL 0x0020u

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#define BSS_PCDATA 0x0040u

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#define BSS_BITBLT 0x0060u

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#define FRGD_MIX 0xbae8u /* Write */

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/* 0x001fu See MIX_* definitions below */

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#define FSS_BKGDCOL 0x0000u

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#define FSS_FRGDCOL 0x0020u

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#define FSS_PCDATA 0x0040u

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#define FSS_BITBLT 0x0060u

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#define MULTIFUNC_CNTL 0xbee8u /* Write */

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#define MIN_AXIS_PCNT 0x0000u

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#define SCISSORS_T 0x1000u

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#define SCISSORS_L 0x2000u

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#define SCISSORS_B 0x3000u

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#define SCISSORS_R 0x4000u

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#define M32_MEM_CNTL 0x5000u

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#define HORCFG_4 0x0000u

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#define HORCFG_5 0x0001u

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#define HORCFG_8 0x0002u

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#define HORCFG_10 0x0003u

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#define VRTCFG_2 0x0000u

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#define VRTCFG_4 0x0004u

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#define VRTCFG_6 0x0008u

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#define VRTCFG_8 0x000cu

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#define BUFSWP 0x0010u

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#define PATTERN_L 0x8000u

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#define PATTERN_H 0x9000u

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#define PIX_CNTL 0xa000u

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#define PLANEMODE 0x0004u

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#define COLCMPOP_F 0x0000u

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#define COLCMPOP_T 0x0008u

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#define COLCMPOP_GE 0x0010u

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#define COLCMPOP_LT 0x0018u

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#define COLCMPOP_NE 0x0020u

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#define COLCMPOP_EQ 0x0028u

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#define COLCMPOP_LE 0x0030u

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#define COLCMPOP_GT 0x0038u

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#define MIXSEL_FRGDMIX 0x0000u

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#define MIXSEL_PATT 0x0040u

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#define MIXSEL_EXPPC 0x0080u

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#define MIXSEL_EXPBLT 0x00c0u

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/* ? 0xc2e8u */

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/* ? 0xc6e8u */

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/* ? 0xcae8u */

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/* ? 0xcee8u */

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/* ? 0xd2e8u */

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/* ? 0xd6e8u */

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/* ? 0xdae8u */

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/* ? 0xdee8u */

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#define PIX_TRANS 0xe2e8u

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/* ? 0xe6e8u */

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/* ? 0xeae8u */

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/* ? 0xeee8u */

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/* ? 0xf2e8u */

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/* ? 0xf6e8u */

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/* ? 0xfae8u */

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/* ? 0xfee8u */

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/* ATI Mach8 & Mach32 register definitions */

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#define OVERSCAN_COLOR_8 0x02eeu /* Write */ /* Mach32 */

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#define OVERSCAN_BLUE_24 0x02efu /* Write */ /* Mach32 */

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#define OVERSCAN_GREEN_24 0x06eeu /* Write */ /* Mach32 */

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#define OVERSCAN_RED_24 0x06efu /* Write */ /* Mach32 */

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#define CURSOR_OFFSET_LO 0x0aeeu /* Write */ /* Mach32 */

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#define CURSOR_OFFSET_HI 0x0eeeu /* Write */ /* Mach32 */

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#define CONFIG_STATUS_1 0x12eeu /* Read */

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#define CLK_MODE 0x0001u /* Mach8 */

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#define BUS_16 0x0002u /* Mach8 */

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#define MC_BUS 0x0004u /* Mach8 */

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#define EEPROM_ENA 0x0008u /* Mach8 */

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#define DRAM_ENA 0x0010u /* Mach8 */

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#define MEM_INSTALLED 0x0060u /* Mach8 */

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#define ROM_ENA 0x0080u /* Mach8 */

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#define ROM_PAGE_ENA 0x0100u /* Mach8 */

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#define ROM_LOCATION 0xfe00u /* Mach8 */

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#define _8514_ONLY 0x0001u /* Mach32 */

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#define BUS_TYPE 0x000eu /* Mach32 */

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#define ISA_16_BIT 0x0000u /* Mach32 */

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#define EISA 0x0002u /* Mach32 */

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#define MICRO_C_16_BIT 0x0004u /* Mach32 */

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#define MICRO_C_8_BIT 0x0006u /* Mach32 */

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#define LOCAL_386SX 0x0008u /* Mach32 */

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#define LOCAL_386DX 0x000au /* Mach32 */

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#define LOCAL_486 0x000cu /* Mach32 */

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#define PCI 0x000eu /* Mach32 */

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#define MEM_TYPE 0x0070u /* Mach32 */

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#define CHIP_DIS 0x0080u /* Mach32 */

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#define TST_VCTR_ENA 0x0100u /* Mach32 */

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#define DACTYPE 0x0e00u /* Mach32 */

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#define MC_ADR_DECODE 0x1000u /* Mach32 */

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#define CARD_ID 0xe000u /* Mach32 */

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#define HORZ_CURSOR_POSN 0x12eeu /* Write */ /* Mach32 */

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#define CONFIG_STATUS_2 0x16eeu /* Read */

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#define SHARE_CLOCK 0x0001u /* Mach8 */

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#define HIRES_BOOT 0x0002u /* Mach8 */

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#define EPROM_16_ENA 0x0004u /* Mach8 */

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#define WRITE_PER_BIT 0x0008u /* Mach8 */

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#define FLASH_ENA 0x0010u /* Mach8 */

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#define SLOW_SEQ_EN 0x0001u /* Mach32 */

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#define MEM_ADDR_DIS 0x0002u /* Mach32 */

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#define ISA_16_ENA 0x0004u /* Mach32 */

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#define KOR_TXT_MODE_ENA 0x0008u /* Mach32 */

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#define LOCAL_BUS_SUPPORT 0x0030u /* Mach32 */

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#define LOCAL_BUS_CONFIG_2 0x0040u /* Mach32 */

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#define LOCAL_BUS_RD_DLY_ENA 0x0080u /* Mach32 */

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#define LOCAL_DAC_EN 0x0100u /* Mach32 */

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#define LOCAL_RDY_EN 0x0200u /* Mach32 */

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#define EEPROM_ADR_SEL 0x0400u /* Mach32 */

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#define GE_STRAP_SEL 0x0800u /* Mach32 */

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#define VESA_RDY 0x1000u /* Mach32 */

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#define Z4GB 0x2000u /* Mach32 */

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#define LOC2_MDRAM 0x4000u /* Mach32 */

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#define VERT_CURSOR_POSN 0x16eeu /* Write */ /* Mach32 */

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#define FIFO_TEST_DATA 0x1aeeu /* Read */ /* Mach32 */

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#define CURSOR_COLOR_0 0x1aeeu /* Write */ /* Mach32 */

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#define CURSOR_COLOR_1 0x1aefu /* Write */ /* Mach32 */

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#define HORZ_CURSOR_OFFSET 0x1eeeu /* Write */ /* Mach32 */

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#define VERT_CURSOR_OFFSET 0x1eefu /* Write */ /* Mach32 */

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#define PCI_CNTL 0x22eeu /* Mach32-PCI */

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#define CRT_PITCH 0x26eeu /* Write */

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#define CRT_OFFSET_LO 0x2aeeu /* Write */

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#define CRT_OFFSET_HI 0x2eeeu /* Write */

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#define LOCAL_CNTL 0x32eeu /* Mach32 */

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#define FIFO_OPT 0x36eeu /* Write */ /* Mach8 */

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#define MISC_OPTIONS 0x36eeu /* Mach32 */

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#define W_STATE_ENA 0x0000u /* Mach32 */

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#define HOST_8_ENA 0x0001u /* Mach32 */

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#define MEM_SIZE_ALIAS 0x000cu /* Mach32 */

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#define MEM_SIZE_512K 0x0000u /* Mach32 */

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#define MEM_SIZE_1M 0x0004u /* Mach32 */

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#define MEM_SIZE_2M 0x0008u /* Mach32 */

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#define MEM_SIZE_4M 0x000cu /* Mach32 */

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#define DISABLE_VGA 0x0010u /* Mach32 */

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#define _16_BIT_IO 0x0020u /* Mach32 */

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#define DISABLE_DAC 0x0040u /* Mach32 */

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#define DLY_LATCH_ENA 0x0080u /* Mach32 */

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#define TEST_MODE 0x0100u /* Mach32 */

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#define BLK_WR_ENA 0x0400u /* Mach32 */

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#define _64_DRAW_ENA 0x0800u /* Mach32 */

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#define FIFO_TEST_TAG 0x3aeeu /* Read */ /* Mach32 */

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#define EXT_CURSOR_COLOR_0 0x3aeeu /* Write */ /* Mach32 */

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#define EXT_CURSOR_COLOR_1 0x3eeeu /* Write */ /* Mach32 */

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#define MEM_BNDRY 0x42eeu /* Mach32 */

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#define MEM_PAGE_BNDRY 0x000fu /* Mach32 */

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#define MEM_BNDRY_ENA 0x0010u /* Mach32 */

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#define SHADOW_CTL 0x46eeu /* Write */

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#define CLOCK_SEL 0x4aeeu

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/* DISABPASSTHRU 0x0001u See ADVFUNC_CNTL */

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#define VFIFO_DEPTH_1 0x0100u /* Mach32 */

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#define VFIFO_DEPTH_2 0x0200u /* Mach32 */

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#define VFIFO_DEPTH_3 0x0300u /* Mach32 */

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#define VFIFO_DEPTH_4 0x0400u /* Mach32 */

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#define VFIFO_DEPTH_5 0x0500u /* Mach32 */

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#define VFIFO_DEPTH_6 0x0600u /* Mach32 */

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#define VFIFO_DEPTH_7 0x0700u /* Mach32 */

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#define VFIFO_DEPTH_8 0x0800u /* Mach32 */

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#define VFIFO_DEPTH_9 0x0900u /* Mach32 */

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#define VFIFO_DEPTH_A 0x0a00u /* Mach32 */

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#define VFIFO_DEPTH_B 0x0b00u /* Mach32 */

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#define VFIFO_DEPTH_C 0x0c00u /* Mach32 */

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#define VFIFO_DEPTH_D 0x0d00u /* Mach32 */

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#define VFIFO_DEPTH_E 0x0e00u /* Mach32 */

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#define VFIFO_DEPTH_F 0x0f00u /* Mach32 */

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#define COMPOSITE_SYNC 0x1000u

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/* ? 0x4eeeu */

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#define ROM_ADDR_1 0x52eeu

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#define BIOS_BASE_SEGMENT 0x007fu /* Mach32 */

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/* ? 0xff80u */ /* Mach32 */

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#define ROM_ADDR_2 0x56eeu /* Sick ... */

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#define SHADOW_SET 0x5aeeu /* Write */

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#define MEM_CFG 0x5eeeu /* Mach32 */

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#define MEM_APERT_SEL 0x0003u /* Mach32 */

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#define MEM_APERT_PAGE 0x000cu /* Mach32 */

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#define MEM_APERT_LOC 0xfff0u /* Mach32 */

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#define EXT_GE_STATUS 0x62eeu /* Read */ /* Mach32 */

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#define HORZ_OVERSCAN 0x62eeu /* Write */ /* Mach32 */

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#define VERT_OVERSCAN 0x66eeu /* Write */ /* Mach32 */

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#define MAX_WAITSTATES 0x6aeeu

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#define GE_OFFSET_LO 0x6eeeu /* Write */

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#define BOUNDS_LEFT 0x72eeu /* Read */

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#define GE_OFFSET_HI 0x72eeu /* Write */

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#define BOUNDS_TOP 0x76eeu /* Read */

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#define GE_PITCH 0x76eeu /* Write */

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#define BOUNDS_RIGHT 0x7aeeu /* Read */

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#define EXT_GE_CONFIG 0x7aeeu /* Write */ /* Mach32 */

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#define MONITOR_ALIAS 0x0007u /* Mach32 */

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/* MONITOR_? 0x0000u */ /* Mach32 */

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#define MONITOR_8507 0x0001u /* Mach32 */

445

#define MONITOR_8514 0x0002u /* Mach32 */

446

/* MONITOR_? 0x0003u */ /* Mach32 */

447

/* MONITOR_? 0x0004u */ /* Mach32 */

448

#define MONITOR_8503 0x0005u /* Mach32 */

449

#define MONITOR_8512 0x0006u /* Mach32 */

450

#define MONITOR_8513 0x0006u /* Mach32 */

451

#define MONITOR_NONE 0x0007u /* Mach32 */

452

#define ALIAS_ENA 0x0008u /* Mach32 */

453

#define PIXEL_WIDTH_4 0x0000u /* Mach32 */

454

#define PIXEL_WIDTH_8 0x0010u /* Mach32 */

455

#define PIXEL_WIDTH_16 0x0020u /* Mach32 */

456

#define PIXEL_WIDTH_24 0x0030u /* Mach32 */

457

#define RGB16_555 0x0000u /* Mach32 */

458

#define RGB16_565 0x0040u /* Mach32 */

459

#define RGB16_655 0x0080u /* Mach32 */

460

#define RGB16_664 0x00c0u /* Mach32 */

461

#define MULTIPLEX_PIXELS 0x0100u /* Mach32 */

462

#define RGB24 0x0000u /* Mach32 */

463

#define RGBx24 0x0200u /* Mach32 */

464

#define BGR24 0x0400u /* Mach32 */

465

#define xBGR24 0x0600u /* Mach32 */

466

#define DAC_8_BIT_EN 0x4000u /* Mach32 */

467

#define ORDER_16BPP_565 RGB16_565 /* Mach32 */

468

#define BOUNDS_BOTTOM 0x7eeeu /* Read */

469

#define MISC_CNTL 0x7eeeu /* Write */ /* Mach32 */

470

#define PATT_DATA_INDEX 0x82eeu

471

/* ? 0x86eeu */

472

/* ? 0x8aeeu */

473

#define R_EXT_GE_CONFIG 0x8eeeu /* Read */ /* Mach32 */

474

#define PATT_DATA 0x8eeeu /* Write */

475

#define R_MISC_CNTL 0x92eeu /* Read */ /* Mach32 */

476

#define BRES_COUNT 0x96eeu

477

#define EXT_FIFO_STATUS 0x9aeeu /* Read */

478

#define LINEDRAW_INDEX 0x9aeeu /* Write */

479

/* ? 0x9eeeu */

480

#define LINEDRAW_OPT 0xa2eeu

481

#define BOUNDS_RESET 0x0100u

482

#define CLIP_MODE_0 0x0000u /* Clip exception disabled */

483

#define CLIP_MODE_1 0x0200u /* Line segments */

484

#define CLIP_MODE_2 0x0400u /* Polygon boundary lines */

485

#define CLIP_MODE_3 0x0600u /* Patterned lines */

486

#define DEST_X_START 0xa6eeu /* Write */

487

#define DEST_X_END 0xaaeeu /* Write */

488

#define DEST_Y_END 0xaeeeu /* Write */

489

#define R_H_TOTAL_DISP 0xb2eeu /* Read */ /* Mach32 */

490

#define SRC_X_STRT 0xb2eeu /* Write */

491

#define R_H_SYNC_STRT 0xb6eeu /* Read */ /* Mach32 */

492

#define ALU_BG_FN 0xb6eeu /* Write */

493

#define R_H_SYNC_WID 0xbaeeu /* Read */ /* Mach32 */

494

#define ALU_FG_FN 0xbaeeu /* Write */

495

#define SRC_X_END 0xbeeeu /* Write */

496

#define R_V_TOTAL 0xc2eeu /* Read */

497

#define SRC_Y_DIR 0xc2eeu /* Write */

498

#define R_V_DISP 0xc6eeu /* Read */ /* Mach32 */

499

#define EXT_SHORT_STROKE 0xc6eeu /* Write */

500

#define R_V_SYNC_STRT 0xcaeeu /* Read */ /* Mach32 */

501

#define SCAN_X 0xcaeeu /* Write */

502

#define VERT_LINE_CNTR 0xceeeu /* Read */ /* Mach32 */

503

#define DP_CONFIG 0xceeeu /* Write */

504

#define READ_WRITE 0x0001u

505

#define DATA_WIDTH 0x0200u

506

#define DATA_ORDER 0x1000u

507

#define FG_COLOR_SRC_FG 0x2000u

508

#define FG_COLOR_SRC_BLIT 0x6000u

509

#define R_V_SYNC_WID 0xd2eeu /* Read */

510

#define PATT_LENGTH 0xd2eeu /* Write */

511

#define PATT_INDEX 0xd6eeu /* Write */

512

#define READ_SRC_X 0xdaeeu /* Read */ /* Mach32 */

513

#define EXT_SCISSOR_L 0xdaeeu /* Write */

514

#define READ_SRC_Y 0xdeeeu /* Read */ /* Mach32 */

515

#define EXT_SCISSOR_T 0xdeeeu /* Write */

516

#define EXT_SCISSOR_R 0xe2eeu /* Write */

517

#define EXT_SCISSOR_B 0xe6eeu /* Write */

518

/* ? 0xeaeeu */

519

#define DEST_COMP_FN 0xeeeeu /* Write */

520

#define DEST_COLOR_CMP_MASK 0xf2eeu /* Write */ /* Mach32 */

521

/* ? 0xf6eeu */

522

#define CHIP_ID 0xfaeeu /* Read */ /* Mach32 */

523

#define CHIP_CODE_0 0x001fu /* Mach32 */

524

#define CHIP_CODE_1 0x03e0u /* Mach32 */

525

#define CHIP_CLASS 0x0c00u /* Mach32 */

526

#define CHIP_REV 0xf000u /* Mach32 */

527

#define LINEDRAW 0xfeeeu /* Write */

528

529

/* ATI Mach64 register definitions */

530

#define CRTC_H_TOTAL_DISP IOPortTag(0x00u, 0x00u)

531

#define CRTC_H_TOTAL 0x000001fful

532

/* ? 0x0000fe00ul */

533

#define CRTC_H_DISP 0x01ff0000ul

534

/* ? 0xfe000000ul */

535

#define CRTC_H_SYNC_STRT_WID IOPortTag(0x01u, 0x01u)

536

#define CRTC_H_SYNC_STRT 0x000000fful

537

#define CRTC_H_SYNC_DLY 0x00000700ul

538

/* ? 0x00000800ul */

539

#define CRTC_H_SYNC_STRT_HI 0x00001000ul

540

/* ? 0x0000e000ul */

541

#define CRTC_H_SYNC_WID 0x001f0000ul

542

#define CRTC_H_SYNC_POL 0x00200000ul

543

/* ? 0xffc00000ul */

544

#define CRTC_V_TOTAL_DISP IOPortTag(0x02u, 0x02u)

545

#define CRTC_V_TOTAL 0x000007fful

546

/* ? 0x0000f800ul */

547

#define CRTC_V_DISP 0x07ff0000ul

548

/* ? 0xf8000000ul */

549

#define CRTC_V_SYNC_STRT_WID IOPortTag(0x03u, 0x03u)

550

#define CRTC_V_SYNC_STRT 0x000007fful

551

/* ? 0x0000f800ul */

552

#define CRTC_V_SYNC_WID 0x001f0000ul

553

#define CRTC_V_SYNC_END_VGA 0x000f0000ul

554

#define CRTC_V_SYNC_POL 0x00200000ul

555

/* ? 0xffc00000ul */

556

#define CRTC_VLINE_CRNT_VLINE IOPortTag(0x04u, 0x04u)

557

#define CRTC_VLINE 0x000007fful

558

/* ? 0x0000f800ul */

559

#define CRTC_CRNT_VLINE 0x07ff0000ul

560

/* ? 0xf8000000ul */

561

#define CRTC_OFF_PITCH IOPortTag(0x05u, 0x05u)

562

#define CRTC_OFFSET 0x000ffffful

563

#define CRTC_OFFSET_VGA 0x0003fffful

564

#define CRTC_OFFSET_LOCK 0x00100000ul /* XC/XL */

565

/* ? 0x00200000ul */

566

#define CRTC_PITCH 0xffc00000ul

567

#define CRTC_INT_CNTL IOPortTag(0x06u, 0x06u)

568

#define CRTC_VBLANK 0x00000001ul

569

#define CRTC_VBLANK_INT_EN 0x00000002ul

570

#define CRTC_VBLANK_INT 0x00000004ul

571

#define CRTC_VLINE_INT_EN 0x00000008ul

572

#define CRTC_VLINE_INT 0x00000010ul

573

#define CRTC_VLINE_SYNC 0x00000020ul

574

#define CRTC_FRAME 0x00000040ul

575

#define CRTC_SNAPSHOT_INT_EN 0x00000080ul /* GTPro */

576

#define CRTC_SNAPSHOT_INT 0x00000100ul /* GTPro */

577

#define CRTC_I2C_INT_EN 0x00000200ul /* GTPro */

578

#define CRTC_I2C_INT 0x00000400ul /* GTPro */

579

#define CRTC2_VBLANK 0x00000800ul /* LTPro */

580

#define CRTC2_VBLANK_INT_EN 0x00001000ul /* LTPro */

581

#define CRTC2_VBLANK_INT 0x00002000ul /* LTPro */

582

#define CRTC2_VLINE_INT_EN 0x00004000ul /* LTPro */

583

#define CRTC2_VLINE_INT 0x00008000ul /* LTPro */

584

#define CRTC_CAPBUF0_INT_EN 0x00010000ul /* VT/GT */

585

#define CRTC_CAPBUF0_INT 0x00020000ul /* VT/GT */

586

#define CRTC_CAPBUF1_INT_EN 0x00040000ul /* VT/GT */

587

#define CRTC_CAPBUF1_INT 0x00080000ul /* VT/GT */

588

#define CRTC_OVERLAY_EOF_INT_EN 0x00100000ul /* VT/GT */

589

#define CRTC_OVERLAY_EOF_INT 0x00200000ul /* VT/GT */

590

#define CRTC_ONESHOT_CAP_INT_EN 0x00400000ul /* VT/GT */

591

#define CRTC_ONESHOT_CAP_INT 0x00800000ul /* VT/GT */

592

#define CRTC_BUSMASTER_EOL_INT_EN 0x01000000ul /* VTB/GTB/LT */

593

#define CRTC_BUSMASTER_EOL_INT 0x02000000ul /* VTB/GTB/LT */

594

#define CRTC_GP_INT_EN 0x04000000ul /* VTB/GTB/LT */

595

#define CRTC_GP_INT 0x08000000ul /* VTB/GTB/LT */

596

#define CRTC2_VLINE_SYNC 0x10000000ul /* LTPro */

597

#define CRTC_SNAPSHOT2_INT_EN 0x20000000ul /* LTPro */

598

#define CRTC_SNAPSHOT2_INT 0x40000000ul /* LTPro */

599

#define CRTC_VBLANK_BIT2_INT 0x80000000ul /* GTPro */

600

#define CRTC_INT_ENS /* *** UPDATE ME *** */ \

601

( \

602

CRTC_VBLANK_INT_EN | \

603

CRTC_VLINE_INT_EN | \

604

CRTC_SNAPSHOT_INT_EN | \

605

CRTC_I2C_INT_EN | \

606

CRTC2_VBLANK_INT_EN | \

607

CRTC2_VLINE_INT_EN | \

608

CRTC_CAPBUF0_INT_EN | \

609

CRTC_CAPBUF1_INT_EN | \

610

CRTC_OVERLAY_EOF_INT_EN | \

611

CRTC_ONESHOT_CAP_INT_EN | \

612

CRTC_BUSMASTER_EOL_INT_EN | \

613

CRTC_GP_INT_EN | \

614

CRTC_SNAPSHOT2_INT_EN | \

615

0 \

616

)

617

#define CRTC_INT_ACKS /* *** UPDATE ME *** */ \

618

( \

619

CRTC_VBLANK_INT | \

620

CRTC_VLINE_INT | \

621

CRTC_SNAPSHOT_INT | \

622

CRTC_I2C_INT | \

623

CRTC2_VBLANK_INT | \

624

CRTC2_VLINE_INT | \

625

CRTC_CAPBUF0_INT | \

626

CRTC_CAPBUF1_INT | \

627

CRTC_OVERLAY_EOF_INT | \

628

CRTC_ONESHOT_CAP_INT | \

629

CRTC_BUSMASTER_EOL_INT | \

630

CRTC_GP_INT | \

631

CRTC_SNAPSHOT2_INT | \

632

CRTC_VBLANK_BIT2_INT | \

633

0 \

634

)

635

#define CRTC_GEN_CNTL IOPortTag(0x07u, 0x07u)

636

#define CRTC_DBL_SCAN_EN 0x00000001ul

637

#define CRTC_INTERLACE_EN 0x00000002ul

638

#define CRTC_HSYNC_DIS 0x00000004ul

639

#define CRTC_VSYNC_DIS 0x00000008ul

640

#define CRTC_CSYNC_EN 0x00000010ul

641

#define CRTC_PIX_BY_2_EN 0x00000020ul

642

#define CRTC2_DBL_SCAN_EN 0x00000020ul /* LTPro */

643

#define CRTC_DISPLAY_DIS 0x00000040ul

644

#define CRTC_VGA_XOVERSCAN 0x00000080ul

645

#define CRTC_PIX_WIDTH 0x00000700ul

646

#define CRTC_BYTE_PIX_ORDER 0x00000800ul

647

#define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */

648

#define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */

649

#define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */

650

#define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */

651

#define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */

652

#define CRTC_FIFO_LWM 0x000f0000ul

653

#define CRTC_HVSYNC_IO_DRIVE 0x00010000ul /* XC/XL */

654

#define CRTC2_PIX_WIDTH 0x000e0000ul /* LTPro */

655

#define CRTC_VGA_128KAP_PAGING 0x00100000ul /* VT/GT */

656

#define CRTC_DISPREQ_ONLY 0x00200000ul /* VT/GT */

657

#define CRTC_VFC_SYNC_TRISTATE 0x00200000ul /* VTB/GTB/LT */

658

#define CRTC2_EN 0x00200000ul /* LTPro */

659

#define CRTC_LOCK_REGS 0x00400000ul /* VT/GT */

660

#define CRTC_SYNC_TRISTATE 0x00800000ul /* VT/GT */

661

#define CRTC_EXT_DISP_EN 0x01000000ul

662

#define CRTC_EN 0x02000000ul

663

#define CRTC_DISP_REQ_EN 0x04000000ul

664

#define CRTC_VGA_LINEAR 0x08000000ul

665

#define CRTC_VSYNC_FALL_EDGE 0x10000000ul

666

#define CRTC_VGA_TEXT_132 0x20000000ul

667

#define CRTC_CNT_EN 0x40000000ul

668

#define CRTC_CUR_B_TEST 0x80000000ul

669

#define CRTC_INT_ENS_X /* *** UPDATE ME *** */ \

670

( \

671

CRTC_VSYNC_INT_EN | \

672

CRTC2_VSYNC_INT_EN | \

673

0 \

674

)

675

#define CRTC_INT_ACKS_X /* *** UPDATE ME *** */ \

676

( \

677

CRTC_VSYNC_INT | \

678

CRTC2_VSYNC_INT | \

679

0 \

680

)

681

#define DSP_CONFIG BlockIOTag(0x08u) /* VTB/GTB/LT */

682

#define DSP_XCLKS_PER_QW 0x00003ffful

683

/* ? 0x00004000ul */

684

#define DSP_FLUSH_WB 0x00008000ul

685

#define DSP_LOOP_LATENCY 0x000f0000ul

686

#define DSP_PRECISION 0x00700000ul

687

/* ? 0xff800000ul */

688

#define DSP_ON_OFF BlockIOTag(0x09u) /* VTB/GTB/LT */

689

#define DSP_OFF 0x000007fful

690

/* ? 0x0000f800ul */

691

#define DSP_ON 0x07ff0000ul

692

/* ? 0xf8000000ul */

693

#define TIMER_CONFIG BlockIOTag(0x0au) /* VTB/GTB/LT */

694

#define MEM_BUF_CNTL BlockIOTag(0x0bu) /* VTB/GTB/LT */

695

#define Z_WB_FLUSH 0x00000007ul

696

#define Z_WB_FLUSH_P 0x0000000ful /* GTPro */

697

#define VID_WB_FLUSH_P 0x000000f0ul /* GTPro */

698

#define VID_WB_FLUSH_MSB 0x00000100ul

699

#define GUI_WB_FLUSH_P 0x00001f00ul /* GTPro */

700

#define HST_WB_FLUSH_P 0x0000e000ul /* GTPro */

701

#define SCL_MIN_BURST_LEN 0x001f0000ul

702

#define SCL_THRESH 0x003f0000ul /* GTPro */

703

/* ? 0x00400000ul */

704

#define INVALIDATE_RB_CACHE 0x00800000ul

705

#define HST_WB_FLUSH 0x03000000ul

706

#define VID_WB_FLUSH 0x1c000000ul

707

#define GUI_WB_FLUSH 0xe0000000ul

708

#define SHARED_CNTL BlockIOTag(0x0cu) /* VTB/GTB/LT */

709

#define SHARED_MEM_CONFIG BlockIOTag(0x0du) /* VTB/GTB/LT */

710

#define MEM_ADDR_CONFIG BlockIOTag(0x0du) /* GTPro */

711

#define SHARED_CNTL_CTD BlockIOTag(0x0eu) /* CTD */

712

/* ? 0x00fffffful */

713

#define CTD_FIFO5 0x01000000ul

714

/* ? 0xfe000000ul */

715

#define CRT_TRAP BlockIOTag(0x0eu) /* VTB/GTB/LT */

716

#define DSTN_CONTROL BlockIOTag(0x0fu) /* LT */

717

#define I2C_CNTL_0 BlockIOTag(0x0fu) /* GTPro */

718

#define I2C_CNTL_STAT 0x0000000ful

719

#define I2C_CNTL_DONE 0x00000001ul

720

#define I2C_CNTL_NACK 0x00000002ul

721

#define I2C_CNTL_HALT 0x00000004ul

722

#define I2C_CNTL_FULL 0x00000008ul

723

/* ? 0x00000010ul */

724

#define I2C_CNTL_HPTR_RST 0x00000020ul

725

/* ? 0x000000c0ul */

726

#define I2C_CNTL_START 0x00000100ul

727

#define I2C_CNTL_STOP 0x00000200ul

728

#define I2C_CNTL_GO 0x00000400ul

729

#define I2C_CNTL_RECEIVE 0x00000800ul

730

#define I2C_CNTL_ABORT 0x00001000ul

731

#define I2C_CNTL_INT_EN 0x00002000ul

732

#define I2C_CNTL_SCL 0x00004000ul

733

#define I2C_CNTL_SDA 0x00008000ul

734

#define I2C_CNTL_M_FACTOR 0x00ff0000ul

735

#define I2C_CNTL_N_FACTOR 0xff000000ul

736

#define OVR_CLR IOPortTag(0x08u, 0x10u)

737

#define OVR_CLR_8 0x000000fful

738

#define OVR_CLR_B 0x0000ff00ul

739

#define OVR_CLR_G 0x00ff0000ul

740

#define OVR_CLR_R 0xff000000ul

741

#define OVR_WID_LEFT_RIGHT IOPortTag(0x09u, 0x11u)

742

#define OVR_WID_LEFT 0x0000003ful /* 0x0f on <LT */

743

/* ? 0x0000ffc0ul */

744

#define OVR_WID_RIGHT 0x003f0000ul /* 0x0f0000 on <LT */

745

/* ? 0xffc00000ul */

746

#define OVR_WID_TOP_BOTTOM IOPortTag(0x0au, 0x12u)

747

#define OVR_WID_TOP 0x000001fful /* 0x00ff on <LT */

748

/* ? 0x0000fe00ul */

749

#define OVR_WID_BOTTOM 0x01ff0000ul /* 0x00ff0000 on <LT */

750

/* ? 0xfe000000ul */

751

#define VGA_DSP_CONFIG BlockIOTag(0x13u) /* VTB/GTB/LT */

752

#define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW

753

/* ? 0x000fc000ul */

754

#define VGA_DSP_PREC_PCLKBY2 0x00700000ul

755

/* ? 0x00800000ul */

756

#define VGA_DSP_PREC_PCLK 0x07000000ul

757

/* ? 0xf8000000ul */

758

#define VGA_DSP_ON_OFF BlockIOTag(0x14u) /* VTB/GTB/LT */

759

#define VGA_DSP_OFF DSP_OFF

760

/* ? 0x0000f800ul */

761

#define VGA_DSP_ON DSP_ON

762

/* ? 0xf8000000ul */

763

#define DSP2_CONFIG BlockIOTag(0x15u) /* LTPro */

764

#define DSP2_ON_OFF BlockIOTag(0x16u) /* LTPro */

765

#define EXT_CRTC_GEN_CNTL BlockIOTag(0x17u) /* VT-A4 (W) */

766

#define CRTC2_OFF_PITCH BlockIOTag(0x17u) /* LTPro */

767

#define CUR_CLR0 IOPortTag(0x0bu, 0x18u)

768

#define CUR_CLR1 IOPortTag(0x0cu, 0x19u)

769

/* These are for both CUR_CLR0 and CUR_CLR1 */

770

#define CUR_CLR_I 0x000000fful

771

#define CUR_CLR_B 0x0000ff00ul

772

#define CUR_CLR_G 0x00ff0000ul

773

#define CUR_CLR_R 0xff000000ul

774

#define CUR_CLR (CUR_CLR_R | CUR_CLR_G | CUR_CLR_B)

775

#define CUR_OFFSET IOPortTag(0x0du, 0x1au)

776

#define CUR_HORZ_VERT_POSN IOPortTag(0x0eu, 0x1bu)

777

#define CUR_HORZ_POSN 0x000007fful

778

/* ? 0x0000f800ul */

779

#define CUR_VERT_POSN 0x07ff0000ul

780

/* ? 0xf8000000ul */

781

#define CUR_HORZ_VERT_OFF IOPortTag(0x0fu, 0x1cu)

782

#define CUR_HORZ_OFF 0x0000007ful

783

/* ? 0x0000ff80ul */

784

#define CUR_VERT_OFF 0x007f0000ul

785

/* ? 0xff800000ul */

786

#define CONFIG_PANEL BlockIOTag(0x1du) /* LT */

787

#define PANEL_FORMAT 0x00000007ul

788

/* ? 0x00000008ul */

789

#define PANEL_TYPE 0x000000f0ul

790

#define NO_OF_GREY 0x00000700ul

791

#define MOD_GEN 0x00001800ul

792

#define EXT_LVDS_CLK 0x00001800ul /* LTPro */

793

#define BLINK_RATE 0x00006000ul

794

#define BLINK_RATE_PRO 0x00002000ul /* LTPro */

795

#define DONT_SHADOW_HEND 0x00004000ul /* LTPro */

796

#define DONT_USE_F32KHZ 0x00008000ul

797

#define LCD_IO_DRIVE 0x00008000ul /* XC/XL */

798

#define FP_POL 0x00010000ul

799

#define LP_POL 0x00020000ul

800

#define DTMG_POL 0x00040000ul

801

#define SCK_POL 0x00080000ul

802

#define DITHER_SEL 0x00300000ul

803

#define INVERSE_VIDEO_EN 0x00400000ul

804

#define BL_CLK_SEL 0x01800000ul

805

#define BL_LEVEL 0x0e000000ul

806

#define BL_CLK_SEL_PRO 0x00800000ul /* LTPro */

807

#define BL_LEVEL_PRO 0x03000000ul /* LTPro */

808

#define BIAS_LEVEL_PRO 0x0c000000ul /* LTPro */

809

#define HSYNC_DELAY 0xf0000000ul

810

#define TV_OUT_INDEX BlockIOTag(0x1du) /* LTPro */

811

#define TV_REG_INDEX 0x000000fful

812

#define TV_ON 0x00000100ul

813

/* ? 0xfffffe00ul */

814

#define GP_IO IOPortTag(0x1eu, 0x1eu) /* VT/GT */

815

#define GP_IO_0 0x00000001ul

816

#define GP_IO_1 0x00000002ul

817

#define GP_IO_2 0x00000004ul

818

#define GP_IO_3 0x00000008ul

819

#define GP_IO_4 0x00000010ul

820

#define GP_IO_5 0x00000020ul

821

#define GP_IO_6 0x00000040ul

822

#define GP_IO_7 0x00000080ul

823

#define GP_IO_8 0x00000100ul

824

#define GP_IO_9 0x00000200ul

825

#define GP_IO_A 0x00000400ul

826

#define GP_IO_B 0x00000800ul

827

#define GP_IO_C 0x00001000ul

828

#define GP_IO_D 0x00002000ul

829

#define GP_IO_E 0x00004000ul

830

#define GP_IO_F 0x00008000ul

831

#define GP_IO_DIR_0 0x00010000ul

832

#define GP_IO_DIR_1 0x00020000ul

833

#define GP_IO_DIR_2 0x00040000ul

834

#define GP_IO_DIR_3 0x00080000ul

835

#define GP_IO_DIR_4 0x00100000ul

836

#define GP_IO_DIR_5 0x00200000ul

837

#define GP_IO_DIR_6 0x00400000ul

838

#define GP_IO_DIR_7 0x00800000ul

839

#define GP_IO_DIR_8 0x01000000ul

840

#define GP_IO_DIR_9 0x02000000ul

841

#define GP_IO_DIR_A 0x04000000ul

842

#define GP_IO_DIR_B 0x08000000ul

843

#define GP_IO_DIR_C 0x10000000ul

844

#define GP_IO_DIR_D 0x20000000ul

845

#define GP_IO_DIR_E 0x40000000ul

846

#define GP_IO_DIR_F 0x80000000ul

847

#define GP_IO_CNTL BlockIOTag(0x1fu) /* VT/GT */

848

#define GP_IO_MODE 0x0000000ful

849

/* ? 0x7ffffff0ul */

850

#define GP_IO_EN 0x80000000ul

851

#define HW_DEBUG BlockIOTag(0x1fu) /* VTB/GTB/LT */

852

#define FAST_SRCCOPY_DIS 0x00000001ul

853

#define BYPASS_SUBPIC_DBF 0x00000001ul /* XL/XC */

854

#define SRC_AUTONA_FIX_DIS 0x00000002ul

855

#define SYNC_PD_EN 0x00000002ul /* Mobility */

856

#define DISP_QW_FIX_DIS 0x00000004ul

857

#define GUIDST_WB_EXP_DIS 0x00000008ul

858

#define CYC_ALL_FIX_DIS 0x00000008ul /* GTPro */

859

#define AGPPLL_FIX_EN 0x00000008ul /* Mobility */

860

#define SRC_AUTONA_ALWAYS_EN 0x00000010ul

861

#define GUI_BEATS_HOST_P 0x00000010ul /* GTPro */

862

#define DRV_CNTL_DQMB_WEB 0x00000020ul

863

#define FAST_FILL_SCISSOR_DIS 0x00000020ul /* GT2c/VT4 */

864

#define INTER_BLIT_FIX_DIS 0x00000020ul /* GTPro */

865

#define DRV_CNTL_MA 0x00000040ul

866

#define AUTO_BLKWRT_COLOR_DIS 0x00000040ul /* GT2c/VT4 */

867

#define INTER_PRIM_DIS 0x00000040ul /* GTPro */

868

#define DRV_CNTL_MD 0x00000080ul

869

#define CHG_DEV_ID 0x00000100ul

870

#define SRC_TRACK_DST_FIX_DIS 0x00000200ul

871

#define HCLK_FB_SKEW 0x00000380ul /* GT2c/VT4 */

872

#define SRC_TRACK_DST_FIX_DIS_P 0x00000080ul /* GTPro */

873

#define AUTO_BLKWRT_COLOR_DIS_P 0x00000100ul /* GTPro */

874

#define INTER_LINE_OVERLAP_DIS 0x00000200ul /* GTPro */

875

#define MEM_OE_PULLBACK 0x00000400ul

876

#define DBL_BUFFER_EN 0x00000400ul /* GTPro */

877

#define MEM_WE_FIX_DIS 0x00000800ul

878

#define MEM_OE_PULLBACK_B 0x00000800ul /* GT2c/VT4 */

879

#define CMDFIFO_SIZE_EN 0x00000800ul /* GTPro */

880

#define RD_EN_FIX_DIS 0x00001000ul

881

#define MEM_WE_FIX_DIS_B 0x00001000ul

882

#define AUTO_FF_DIS 0x00001000ul /* GTPro */

883

#define CMDFIFO_SIZE_DIS 0x00002000ul /* GT2c/VT4 */

884

#define AUTO_BLKWRT_DIS 0x00002000ul /* GTPro */

885

#define GUI_BEATS_HOST 0x00004000ul /* GT2c/VT4 */

886

#define ORED_INVLD_RB_CACHE 0x00004000ul /* GTPro */

887

#define BLOCK_DBL_BUF 0x00008000ul /* GTPro */

888

#define R2W_TURNAROUND_DELAY 0x00020000ul /* GT2c/VT4 */

889

#define ENA_32BIT_DATA_BUS 0x00040000ul /* GT2c/VT4 */

890

#define HCLK_FB_SKEW_P 0x00070000ul /* GTPro */

891

#define ENA_FLASH_ROM 0x00080000ul /* GT2c/VT4 */

892

#define DISABLE_SWITCH_FIX 0x00080000ul /* GTPro */

893

#define MCLK_START_EN 0x00080000ul /* LTPro */

894

#define SEL_VBLANK_BDL_BUF 0x00100000ul /* GTPro */

895

#define CMDFIFO_64EN 0x00200000ul /* GTPro */

896

#define BM_FIX_DIS 0x00400000ul /* GTPro */

897

#define Z_SWITCH_EN 0x00800000ul /* LTPro */

898

#define FLUSH_HOST_WB 0x01000000ul /* GTPro */

899

#define HW_DEBUG_WRITE_MSK_FIX_DIS 0x02000000ul /* LTPro */

900

#define Z_NO_WRITE_EN 0x04000000ul /* LTPro */

901

#define DISABLE_PCLK_RESET_P 0x08000000ul /* LTPro */

902

#define PM_D3_SUPPORT_ENABLE_P 0x10000000ul /* LTPro */

903

#define STARTCYCLE_FIX_ENABLE 0x20000000ul /* LTPro */

904

#define DONT_RST_CHAREN 0x20000000ul /* XL/XC */

905

#define C3_FIX_ENABLE 0x40000000ul /* LTPro */

906

#define BM_HOSTRA_EN 0x40000000ul /* XL/XC */

907

#define PKGBGAb 0x80000000ul /* XL/XC */

908

#define AUTOEXP_HORZ_FIX 0x80000000ul /* Mobility */

909

#define SCRATCH_REG0 IOPortTag(0x10u, 0x20u)

910

#define SCRATCH_REG1 IOPortTag(0x11u, 0x21u)

911

/* BIOS_BASE_SEGMENT 0x0000007ful */ /* As above */

912

/* ? 0x00000f80ul */

913

#define BIOS_INIT_DAC_SUBTYPE 0x0000f000ul

914

/* ? 0xffff0000ul */

915

#define SCRATCH_REG2 BlockIOTag(0x22u) /* LT */

916

#define SCRATCH_REG3 BlockIOTag(0x23u) /* GTPro */

917

/* Not described here 0x07fffffful */

918

#define DISPLAY_SWITCH_DISABLE 0x08000000ul

919

/* Not described here 0xf0000000ul */

920

#define CLOCK_CNTL IOPortTag(0x12u, 0x24u)

921

#define CLOCK_BIT 0x00000004ul /* For ICS2595 */

922

#define CLOCK_PULSE 0x00000008ul /* For ICS2595 */

923

#define CLOCK_SELECT 0x0000000ful

924

#define CLOCK_DIVIDER 0x00000030ul

925

#define CLOCK_STROBE 0x00000040ul

926

#define CLOCK_DATA 0x00000080ul

927

/* ? 0x00000100ul */

928

#define PLL_WR_EN 0x00000200ul /* For internal PLL */

929

#define PLL_ADDR 0x0000fc00ul /* For internal PLL */

930

#define PLL_DATA 0x00ff0000ul /* For internal PLL */

931

/* ? 0xff000000ul */

932

#define CONFIG_STAT64_1 BlockIOTag(0x25u) /* GTPro */

933

#define CFG_SUBSYS_DEV_ID 0x000000fful

934

#define CFG_SUBSYS_VEN_ID 0x00ffff00ul

935

/* ? 0x1f000000ul */

936

#define CFG_DIMM_TYPE 0xe0000000ul

937

#define CFG_PCI_SUBSYS_DEV_ID 0x0000fffful /* XC/XL */

938

#define CFG_PCI_SUBSYS_VEN_ID 0xffff0000ul /* XC/XL */

939

#define CONFIG_STAT64_2 BlockIOTag(0x26u) /* GTPro */

940

#define CFG_DIMM_TYPE_3 0x00000001ul

941

/* ? 0x0000001eul */

942

#define CFG_ROMWRTEN 0x00000020ul

943

#define CFG_AGPVCOGAIN 0x000000c0ul

944

#define CFG_PCI_TYPE 0x00000100ul

945

#define CFG_AGPSKEW 0x00000e00ul

946

#define CFG_X1CLKSKEW 0x00007000ul

947

#define CFG_PANEL_ID_P 0x000f8000ul /* LTPro */

948

/* ? 0x00100000ul */

949

#define CFG_PREFETCH_EN 0x00200000ul

950

#define CFG_ID_DISABLE 0x00400000ul

951

#define CFG_PRE_TESTEN 0x00800000ul

952

/* ? 0x01000000ul */

953

#define CFG_PCI5VEN 0x02000000ul /* LTPro */

954

#define CFG_VGA_DISABLE 0x04000000ul

955

#define CFG_ENINTB 0x08000000ul

956

/* ? 0x10000000ul */

957

#define CFG_ROM_REMAP_2 0x20000000ul

958

#define CFG_IDSEL 0x40000000ul

959

/* ? 0x80000000ul */

960

#define TV_OUT_DATA BlockIOTag(0x27u) /* LTPro */

961

#define BUS_CNTL IOPortTag(0x13u, 0x28u)

962

#define BUS_WS 0x0000000ful

963

#define BUS_DBL_RESYNC 0x00000001ul /* VTB/GTB/LT */

964

#define BUS_MSTR_RESET 0x00000002ul /* VTB/GTB/LT */

965

#define BUS_FLUSH_BUF 0x00000004ul /* VTB/GTB/LT */

966

#define BUS_STOP_REQ_DIS 0x00000008ul /* VTB/GTB/LT */

967

#define BUS_ROM_WS 0x000000f0ul

968

#define BUS_APER_REG_DIS 0x00000010ul /* VTB/GTB/LT */

969

#define BUS_EXTRA_PIPE_DIS 0x00000020ul /* VTB/GTB/LT */

970

#define BUS_MASTER_DIS 0x00000040ul /* VTB/GTB/LT */

971

#define BUS_ROM_WRT_EN 0x00000080ul /* GTPro */

972

#define BUS_ROM_PAGE 0x00000f00ul

973

#define BUS_MINOR_REV_ID 0x00000700ul /* LTPro */

974

/* First silicom - Prototype (A11) 0x00000000ul */

975

/* Metal mask spin (A12 & A13) 0x00000100ul */

976

/* All layer spin (A21) 0x00000200ul */

977

/* Fast metal spin (A22) - Prod. 0x00000300ul */

978

/* All layer spin (A31) 0x00000700ul */

979

/* ? 0x00000800ul */ /* LTPro */

980

#define BUS_CHIP_HIDDEN_REV 0x00000300ul /* XC/XL */

981

/* ? 0x00001c00ul */ /* XC/XL */

982

#define BUS_ROM_DIS 0x00001000ul

983

#define BUS_IO_16_EN 0x00002000ul /* GX */

984

#define BUS_PCI_READ_RETRY_EN 0x00002000ul /* VTB/GTB/LT */

985

#define BUS_DAC_SNOOP_EN 0x00004000ul

986

#define BUS_PCI_RETRY_EN 0x00008000ul /* VT/GT */

987

#define BUS_PCI_WRT_RETRY_EN 0x00008000ul /* VTB/GTB/LT */

988

#define BUS_FIFO_WS 0x000f0000ul

989

#define BUS_RETRY_WS 0x000f0000ul /* VTB/GTB/LT */

990

#define BUS_FIFO_ERR_INT_EN 0x00100000ul

991

#define BUS_MSTR_RD_MULT 0x00100000ul /* VTB/GTB/LT */

992

#define BUS_FIFO_ERR_INT 0x00200000ul

993

#define BUS_MSTR_RD_LINE 0x00200000ul /* VTB/GTB/LT */

994

#define BUS_HOST_ERR_INT_EN 0x00400000ul

995

#define BUS_SUSPEND 0x00400000ul /* GTPro */

996

#define BUS_HOST_ERR_INT 0x00800000ul

997

#define BUS_LAT16X 0x00800000ul /* GTPro */

998

#define BUS_PCI_DAC_WS 0x07000000ul

999

#define BUS_RD_DISCARD_EN 0x01000000ul /* VTB/GTB/LT */

1000

#define BUS_RD_ABORT_EN 0x02000000ul /* VTB/GTB/LT */

1001

#define BUS_MSTR_WS 0x04000000ul /* VTB/GTB/LT */

1002

#define BUS_PCI_DAC_DLY 0x08000000ul

1003

#define BUS_EXT_REG_EN 0x08000000ul /* VT/GT */

1004

#define BUS_PCI_MEMW_WS 0x10000000ul

1005

#define BUS_MSTR_DISCONNECT_EN 0x10000000ul /* VTB/GTB/LT */

1006

#define BUS_PCI_BURST_DEC 0x20000000ul /* GX/CX */

1007

#define BUS_BURST 0x20000000ul /* 264xT */

1008

#define BUS_WRT_BURST 0x20000000ul /* VTB/GTB/LT */

1009

#define BUS_RDY_READ_DLY 0xc0000000ul

1010

#define BUS_READ_BURST 0x40000000ul /* VTB/GTB/LT */

1011

#define BUS_RDY_READ_DLY_B 0x80000000ul /* VTB/GTB/LT */

1012

#define LCD_INDEX BlockIOTag(0x29u) /* LTPro */

1013

#define LCD_REG_INDEX 0x0000003ful

1014

/* ? 0x000000c0ul */

1015

#define LCD_DISPLAY_DIS 0x00000100ul

1016

#define LCD_SRC_SEL 0x00000200ul

1017

#define LCD_SRC_SEL_CRTC1 0x00000000ul

1018

#define LCD_SRC_SEL_CRTC2 0x00000200ul

1019

#define LCD_CRTC2_DISPLAY_DIS 0x00000400ul

1020

#define LCD_GUI_ACTIVE 0x00000800ul /* XC/XL */

1021

/* ? 0x00fff000ul */

1022

#define LCD_MONDET_SENSE 0x01000000ul /* XC/XL */

1023

#define LCD_MONDET_INT_POL 0x02000000ul /* XC/XL */

1024

#define LCD_MONDET_INT_EN 0x04000000ul /* XC/XL */

1025

#define LCD_MONDET_INT 0x08000000ul /* XC/XL */

1026

#define LCD_MONDET_EN 0x10000000ul /* XC/XL */

1027

#define LCD_EN_PL 0x20000000ul /* XC/XL */

1028

/* ? 0xc0000000ul */

1029

#define HFB_PITCH_ADDR BlockIOTag(0x2au) /* LT */

1030

#define LCD_DATA BlockIOTag(0x2au) /* LTPro */

1031

#define EXT_MEM_CNTL BlockIOTag(0x2bu) /* VTB/GTB/LT */

1032

#define MEM_CNTL IOPortTag(0x14u, 0x2cu)

1033

#define CTL_MEM_SIZE 0x00000007ul

1034

/* ? 0x00000008ul */

1035

#define CTL_MEM_REFRESH 0x00000078ul /* VT/GT */

1036

#define CTL_MEM_SIZEB 0x0000000ful /* VTB/GTB/LT */

1037

#define CTL_MEM_RD_LATCH_EN 0x00000010ul

1038

#define CTL_MEM_RD_LATCH_DLY 0x00000020ul

1039

#define CTL_MEM_LATENCY 0x00000030ul /* VTB/GTB/LT */

1040

#define CTL_MEM_SD_LATCH_EN 0x00000040ul

1041

#define CTL_MEM_SD_LATCH_DLY 0x00000080ul

1042

#define CTL_MEM_LATCH 0x000000c0ul /* VTB/GTB/LT */

1043

#define CTL_MEM_WDOE_CNTL 0x000000c0ul /* XC/XL */

1044

#define CTL_MEM_FULL_PLS 0x00000100ul

1045

#define CTL_MEM_CYC_LNTH_AUX 0x00000180ul /* VT/GT */

1046

#define CTL_MEM_TRP 0x00000300ul /* VTB/GTB/LT */

1047

#define CTL_MEM_CYC_LNTH 0x00000600ul

1048

#define CTL_MEM_REFRESH_RATE 0x00001800ul /* 264xT */

1049

#define CTL_MEM_TRCD 0x00000c00ul /* VTB/GTB/LT */

1050

#define CTL_MEM_WR_RDY_SEL 0x00000800ul /* GX/CX */

1051

#define CTL_MEM_EXT_RMW_CYC_EN 0x00001000ul /* GX/CX */

1052

#define CTL_MEM_TCRD 0x00001000ul /* VTB/GTB/LT */

1053

#define CTL_MEM_DLL_RESET 0x00002000ul /* VT/GT */

1054

#define CTL_MEM_TR2W 0x00002000ul /* GTPro */

1055

#define CTL_MEM_ACTV_PRE 0x0000c000ul /* VT/GT */

1056

#define CTL_MEM_CAS_PHASE 0x00004000ul /* GTPro */

1057

#define CTL_MEM_OE_PULLBACK 0x00008000ul /* GTPro */

1058

#define CTL_MEM_TWR 0x0000c000ul /* XC/XL */

1059

#define CTL_MEM_BNDRY 0x00030000ul

1060

#define CTL_MEM_BNDRY_0K 0x00000000ul

1061

#define CTL_MEM_BNDRY_256K 0x00010000ul

1062

#define CTL_MEM_BNDRY_512K 0x00020000ul

1063

#define CTL_MEM_BNDRY_1024K 0x00030000ul

1064

#define CTL_MEM_DLL_GAIN_CNTL 0x00030000ul /* VT/GT */

1065

#define CTL_MEM_BNDRY_EN 0x00040000ul

1066

#define CTL_MEM_SDRAM_RESET 0x00040000ul /* VT/GT */

1067

#define CTL_MEM_TRAS 0x00070000ul /* VTB/GTB/LT */

1068

#define CTL_MEM_TILE_SELECT 0x00180000ul /* VT/GT */

1069

#define CTL_MEM_REFRESH_DIS 0x00080000ul /* VTB/GTB/LT */

1070

#define CTL_MEM_LOW_LATENCY_MODE 0x00200000ul /* VT/GT */

1071

#define CTL_MEM_CDE_PULLBACK 0x00400000ul /* VT/GT */

1072

#define CTL_MEM_REFRESH_RATE_B 0x00f00000ul /* VTB/GTB/LT */

1073

#define CTL_MEM_PIX_WIDTH 0x07000000ul

1074

#define CTL_MEM_LOWER_APER_ENDIAN 0x03000000ul /* VTB/GTB/LT */

1075

#define CTL_MEM_OE_SELECT 0x18000000ul /* VT/GT */

1076

#define CTL_MEM_UPPER_APER_ENDIAN 0x0c000000ul /* VTB/GTB/LT */

1077

/* ? 0xe0000000ul */

1078

#define CTL_MEM_PAGE_SIZE 0x30000000ul /* VTB/GTB/LT */

1079

#define MEM_VGA_WP_SEL IOPortTag(0x15u, 0x2du)

1080

#define MEM_VGA_WPS0 0x0000fffful

1081

#define MEM_VGA_WPS1 0xffff0000ul

1082

#define MEM_VGA_RP_SEL IOPortTag(0x16u, 0x2eu)

1083

#define MEM_VGA_RPS0 0x0000fffful

1084

#define MEM_VGA_RPS1 0xffff0000ul

1085

#define LT_GIO BlockIOTag(0x2fu) /* LT */

1086

#define I2C_CNTL_1 BlockIOTag(0x2fu) /* GTPro */

1087

#define I2C_DATA_PORT 0x000000fful

1088

#define I2C_DATA_COUNT 0x0000ff00ul

1089

#define I2C_ADDR_COUNT 0x00070000ul

1090

/* ? 0x00380000ul */

1091

#define I2C_SEL 0x00400000ul

1092

/* ? 0x00800000ul */

1093

#define I2C_TIME_LIMIT 0xff000000ul

1094

#define DAC_REGS IOPortTag(0x17u, 0x30u) /* 4 separate bytes */

1095

#define M64_DAC_WRITE (DAC_REGS + 0)

1096

#define M64_DAC_DATA (DAC_REGS + 1)

1097

#define M64_DAC_MASK (DAC_REGS + 2)

1098

#define M64_DAC_READ (DAC_REGS + 3)

1099

#define DAC_CNTL IOPortTag(0x18u, 0x31u)

1100

#define DAC_EXT_SEL 0x00000003ul

1101

#define DAC_EXT_SEL_RS2 0x000000001ul

1102

#define DAC_EXT_SEL_RS3 0x000000002ul

1103

#define DAC_RANGE_CTL 0x00000003ul /* VTB/GTB/LT */

1104

#define DAC_BLANKING 0x00000004ul /* 264xT */

1105

#define DAC_CMP_DIS 0x00000008ul /* 264xT */

1106

#define DAC1_CLK_SEL 0x00000010ul /* LTPro */

1107

#define DAC_PALETTE_ACCESS_CNTL 0x00000020ul /* LTPro */

1108

#define DAC_PALETTE2_SNOOP_EN 0x00000040ul /* LTPro */

1109

#define DAC_CMP_OUTPUT 0x00000080ul /* 264xT */

1110

#define DAC_8BIT_EN 0x00000100ul

1111

#define DAC_PIX_DLY 0x00000600ul

1112

#define DAC_DIRECT 0x00000400ul /* VTB/GTB/LT */

1113

#define DAC_BLANK_ADJ 0x00001800ul

1114

#define DAC_PAL_CLK_SEL 0x00000800ul /* VTB/GTB/LT */

1115

#define DAC_CRT_SENSE 0x00000800ul /* XC/XL */

1116

#define DAC_CRT_DETECTION_ON 0x00001000ul /* XC/XL */

1117

#define DAC_VGA_ADR_EN 0x00002000ul

1118

#define DAC_FEA_CON_EN 0x00004000ul /* 264xT */

1119

#define DAC_PDMN 0x00008000ul /* 264xT */

1120

#define DAC_TYPE 0x00070000ul

1121

/* ? 0x00f80000ul */

1122

#define DAC_MON_ID_STATE0 0x01000000ul /* GX-E+/CX */

1123

#define DAC_GIO_STATE_1 0x01000000ul /* 264xT */

1124

#define DAC_MON_ID_STATE1 0x02000000ul /* GX-E+/CX */

1125

#define DAC_GIO_STATE_0 0x02000000ul /* 264xT */

1126

#define DAC_MON_ID_STATE2 0x04000000ul /* GX-E+/CX */

1127

#define DAC_GIO_STATE_4 0x04000000ul /* 264xT */

1128

#define DAC_MON_ID_DIR0 0x08000000ul /* GX-E+/CX */

1129

#define DAC_GIO_DIR_1 0x08000000ul /* 264xT */

1130

#define DAC_MON_ID_DIR1 0x10000000ul /* GX-E+/CX */

1131

#define DAC_GIO_DIR_0 0x10000000ul /* 264xT */

1132

#define DAC_MON_ID_DIR2 0x20000000ul /* GX-E+/CX */

1133

#define DAC_GIO_DIR_4 0x20000000ul /* 264xT */

1134

#define DAC_MAN_CMP_STATE 0x40000000ul /* GX-E+ */

1135

#define DAC_RW_WS 0x80000000ul /* VT/GT */

1136

#define HORZ_STRETCHING BlockIOTag(0x32u) /* LT */

1137

#define HORZ_STRETCH_BLEND 0x00000ffful

1138

#define HORZ_STRETCH_RATIO 0x0000fffful

1139

#define HORZ_STRETCH_LOOP 0x00070000ul

1140

#define HORZ_STRETCH_LOOP09 0x00000000ul

1141

#define HORZ_STRETCH_LOOP11 0x00010000ul

1142

#define HORZ_STRETCH_LOOP12 0x00020000ul

1143

#define HORZ_STRETCH_LOOP14 0x00030000ul

1144

#define HORZ_STRETCH_LOOP15 0x00040000ul

1145

/* ? 0x00050000ul */

1146

/* ? 0x00060000ul */

1147

/* ? 0x00070000ul */

1148

/* ? 0x00080000ul */

1149

#define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */

1150

/* ? 0x10000000ul */

1151

#define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */

1152

#define HORZ_STRETCH_MODE 0x40000000ul

1153

#define HORZ_STRETCH_EN 0x80000000ul

1154

#define EXT_DAC_REGS BlockIOTag(0x32u) /* GTPro */

1155

#define EXT_DAC_REG_SEL 0x0000000ful

1156

/* ? 0x000000f0ul */

1157

#define EXT_DAC_DATA 0x0000ff00ul

1158

#define EXT_DAC_EN 0x00010000ul

1159

#define EXT_DAC_WID 0x00020000ul

1160

/* ? 0xfffc0000ul */

1161

#define VERT_STRETCHING BlockIOTag(0x33u) /* LT */

1162

#define VERT_STRETCH_RATIO0 0x000003fful

1163

#define VERT_STRETCH_RATIO1 0x000ffc00ul

1164

#define VERT_STRETCH_RATIO2 0x3ff00000ul

1165

#define VERT_STRETCH_USE0 0x40000000ul

1166

#define VERT_STRETCH_EN 0x80000000ul

1167

#define GEN_TEST_CNTL IOPortTag(0x19u, 0x34u)

1168

#define GEN_EE_DATA_OUT 0x00000001ul /* GX/CX */

1169

#define GEN_GIO2_DATA_OUT 0x00000001ul /* 264xT */

1170

#define GEN_EE_CLOCK 0x00000002ul /* GX/CX */

1171

/* ? 0x00000002ul */ /* 264xT */

1172

#define GEN_EE_CHIP_SEL 0x00000004ul /* GX/CX */

1173

#define GEN_GIO3_DATA_OUT 0x00000004ul /* 264xT */

1174

#define GEN_EE_DATA_IN 0x00000008ul /* GX/CX */

1175

#define GEN_GIO2_DATA_IN 0x00000008ul /* 264xT */

1176

#define GEN_EE_EN 0x00000010ul /* GX/CX */

1177

#define GEN_GIO2_ENABLE 0x00000010ul /* 264xT */

1178

#define GEN_ICON2_ENABLE 0x00000010ul /* XC/XL */

1179

#define GEN_OVR_OUTPUT_EN 0x00000020ul /* GX/CX */

1180

#define GEN_GIO2_WRITE 0x00000020ul /* 264xT */

1181

#define GEN_CUR2_ENABLE 0x00000020ul /* XC/XL */

1182

#define GEN_OVR_POLARITY 0x00000040ul /* GX/CX */

1183

#define GEN_ICON_ENABLE 0x00000040ul /* XC/XL */

1184

#define GEN_CUR_EN 0x00000080ul

1185

#define GEN_GUI_EN 0x00000100ul /* GX/CX */

1186

#define GEN_GUI_RESETB 0x00000100ul /* 264xT */

1187

#define GEN_BLOCK_WR_EN 0x00000200ul /* GX */

1188

/* ? 0x00000200ul */ /* CX/264xT */

1189

#define GEN_SOFT_RESET 0x00000200ul /* VTB/GTB/LT */

1190

#define GEN_MEM_TRISTATE 0x00000400ul /* GTPro */

1191

/* ? 0x00000800ul */

1192

#define GEN_TEST_VECT_MODE 0x00003000ul /* VT/GT */

1193

/* ? 0x0000c000ul */

1194

#define GEN_TEST_FIFO_EN 0x00010000ul /* GX/CX */

1195

#define GEN_TEST_GUI_REGS_EN 0x00020000ul /* GX/CX */

1196

#define GEN_TEST_VECT_EN 0x00040000ul /* GX/CX */

1197

#define GEN_TEST_CRC_STR 0x00080000ul /* GX-C/-D */

1198

/* ? 0x00080000ul */ /* GX-E+/CX */

1199

#define GEN_TEST_MODE_T 0x000f0000ul /* 264xT */

1200

#define GEN_TEST_MODE 0x00700000ul /* GX/CX */

1201

#define GEN_TEST_CNT_EN 0x00100000ul /* 264xT */

1202

#define GEN_TEST_CRC_EN 0x00200000ul /* 264xT */

1203

/* ? 0x00400000ul */ /* 264xT */

1204

/* ? 0x00800000ul */

1205

#define GEN_TEST_MEM_WR 0x01000000ul /* GX-C/-D */

1206

#define GEN_TEST_MEM_STROBE 0x02000000ul /* GX-C/-D */

1207

#define GEN_TEST_DST_SS_EN 0x04000000ul /* GX/CX */

1208

#define GEN_TEST_DST_SS_STROBE 0x08000000ul /* GX/CX */

1209

#define GEN_TEST_SRC_SS_EN 0x10000000ul /* GX/CX */

1210

#define GEN_TEST_SRC_SS_STROBE 0x20000000ul /* GX/CX */

1211

#define GEN_TEST_CNT_VALUE 0x3f000000ul /* 264xT */

1212

#define GEN_TEST_CC_EN 0x40000000ul /* GX/CX */

1213

#define GEN_TEST_CC_STROBE 0x80000000ul /* GX/CX */

1214

/* ? 0xc0000000ul */ /* 264xT */

1215

#define GEN_DEBUG_MODE 0xff000000ul /* VTB/GTB/LT */

1216

#define LCD_GEN_CTRL BlockIOTag(0x35u) /* LT */

1217

#define CRT_ON 0x00000001ul

1218

#define LCD_ON 0x00000002ul

1219

#define HORZ_DIVBY2_EN 0x00000004ul

1220

#define TRISTATE_MEM_EN 0x00000008ul

1221

#define DONT_DS_ICON 0x00000008ul /* LTPro */

1222

#define LOCK_8DOT 0x00000010ul

1223

#define ICON_ENABLE 0x00000020ul

1224

#define DONT_SHADOW_VPAR 0x00000040ul

1225

#define TOGGLE_EN 0x00000080ul

1226

#define V2CLK_PM_EN 0x00000080ul /* LTPro */

1227

#define RST_FM 0x00000100ul

1228

#define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */

1229

#define DIS_HOR_CRT_DIVBY2 0x00000400ul

1230

#define SCLK_SEL 0x00000800ul

1231

#define SCLK_DELAY 0x0000f000ul

1232

#define MCLK_PM_EN 0x00010000ul

1233

#define TVCLK_PM_EN 0x00010000ul /* LTPro */

1234

#define VCLK_DAC_PM_EN 0x00020000ul

1235

#define VCLK_LCD_OFF 0x00040000ul

1236

#define SLOWDOWN_XMCLK 0x00080000ul

1237

#define SELECT_WAIT_4MS 0x00080000ul /* LTPro */

1238

#define XTALIN_PM_EN 0x00080000ul /* XC/XL */

1239

#define LCD_CLK_RATIO 0x00100000ul

1240

#define V2CLK_DAC_PM_EN 0x00100000ul /* LTPro */

1241

#define LVDS_EN 0x00200000ul

1242

#define LVDS_PLL_EN 0x00400000ul

1243

#define LVDS_PLL_RESET 0x00800000ul

1244

#define LVDS_RESERVED_BITS 0x07000000ul

1245

#define CRTC_RW_SELECT 0x08000000ul /* LTPro */

1246

#define USE_SHADOWED_VEND 0x10000000ul

1247

#define USE_SHADOWED_ROWCUR 0x20000000ul

1248

#define SHADOW_EN 0x40000000ul

1249

#define SHADOW_RW_EN 0x80000000ul

1250

#define CUSTOM_MACRO_CNTL BlockIOTag(0x35u) /* GTPro */

1251

#define POWER_MANAGEMENT BlockIOTag(0x36u) /* LT */

1252

#define PWR_MGT_ON 0x00000001ul

1253

#define PWR_MGT_MODE 0x00000006ul

1254

#define AUTO_PWRUP_EN 0x00000008ul

1255

#define ACTIVITY_PIN_ON 0x00000010ul

1256

#define STANDBY_POL 0x00000020ul

1257

#define SUSPEND_POL 0x00000040ul

1258

#define SELF_REFRESH 0x00000080ul

1259

#define ACTIVITY_PIN_EN 0x00000100ul

1260

#define KEYBD_SNOOP 0x00000200ul

1261

#define USE_F32KHZ 0x00000400ul /* LTPro */

1262

#define DONT_USE_XTALIN 0x00000400ul /* XC/XL */

1263

#define TRISTATE_MEM_EN_P 0x00000800ul /* LTPro */

1264

#define LCDENG_TEST_MODE 0x0000f000ul

1265

#define STANDBY_COUNT 0x000f0000ul

1266

#define SUSPEND_COUNT 0x00f00000ul

1267

#define BAISON 0x01000000ul

1268

#define BLON 0x02000000ul

1269

#define DIGON 0x04000000ul

1270

#define PM_D3_SUPPORT_ENABLE 0x08000000ul /* XC/XL */

1271

#define STANDBY_NOW 0x10000000ul

1272

#define SUSPEND_NOW 0x20000000ul

1273

#define PWR_MGT_STATUS 0xc0000000ul

1274

#define CONFIG_CNTL IOPortTag(0x1au, 0x37u)

1275

#define CFG_MEM_AP_SIZE 0x00000003ul

1276

#define CFG_MEM_VGA_AP_EN 0x00000004ul

1277

/* ? 0x00000008ul */

1278

#define CFG_MEM_AP_LOC 0x00003ff0ul

1279

/* ? 0x0000c000ul */

1280

#define CFG_CARD_ID 0x00070000ul

1281

#define CFG_VGA_DIS 0x00080000ul

1282

/* ? 0x00f00000ul */

1283

#define CFG_CDE_WINDOW 0x3f000000ul /* VT/GT */

1284

/* ? 0xc0000000ul */

1285

#define CONFIG_CHIP_ID IOPortTag(0x1bu, 0x38u) /* Read */

1286

#define CFG_CHIP_TYPE0 0x000000fful

1287

#define CFG_CHIP_TYPE1 0x0000ff00ul

1288

#define CFG_CHIP_TYPE 0x0000fffful

1289

#define CFG_CHIP_CLASS 0x00ff0000ul

1290

#define CFG_CHIP_REV 0xff000000ul

1291

#define CFG_CHIP_VERSION 0x07000000ul /* 264xT */

1292

#define CFG_CHIP_FOUNDRY 0x38000000ul /* 264xT */

1293

#define CFG_CHIP_REVISION 0xc0000000ul /* 264xT */

1294

#define CONFIG_STATUS64_0 IOPortTag(0x1cu, 0x39u) /* Read (R/W (264xT)) */

1295

#define CFG_BUS_TYPE 0x00000007ul /* GX/CX */

1296

#define CFG_MEM_TYPE_T 0x00000007ul /* 264xT */

1297

#define CFG_MEM_TYPE 0x00000038ul /* GX/CX */

1298

#define CFG_DUAL_CAS_EN_T 0x00000008ul /* 264xT */

1299

#define CFG_ROM_128K_EN 0x00000008ul /* VTB/GTB/LT */

1300

#define CFG_ROM_REMAP 0x00000008ul /* GTPro */

1301

#define CFG_VGA_EN_T 0x00000010ul /* VT/GT */

1302

#define CFG_CLOCK_EN 0x00000020ul /* 264xT */

1303

#define CFG_DUAL_CAS_EN 0x00000040ul /* GX/CX */

1304

#define CFG_VMC_SENSE 0x00000040ul /* VT/GT */

1305

#define CFG_SHARED_MEM_EN 0x00000040ul /* VTB/GTB/LT */

1306

#define CFG_LOCAL_BUS_OPTION 0x00000180ul /* GX/CX */

1307

#define CFG_VFC_SENSE 0x00000080ul /* VT/GT */

1308

#define CFG_INIT_DAC_TYPE 0x00000e00ul /* GX/CX */

1309

#define CFG_INIT_CARD_ID 0x00007000ul /* GX-C/-D */

1310

#define CFG_BLK_WR_SIZE 0x00001000ul /* GX-E+ */

1311

#define CFG_INT_QSF_EN 0x00002000ul /* GX-E+ */

1312

/* ? 0x00004000ul */ /* GX-E+ */

1313

/* ? 0x00007000ul */ /* CX */

1314

#define CFG_TRI_BUF_DIS 0x00008000ul /* GX/CX */

1315

#define CFG_BOARD_ID 0x0000ff00ul /* VT/GT */

1316

#define CFG_EXT_RAM_ADDR 0x003f0000ul /* GX/CX */

1317

#define CFG_PANEL_ID 0x001f0000ul /* LT */

1318

#define CFG_MACROVISION_EN 0x00200000ul /* GTPro */

1319

#define CFG_ROM_DIS 0x00400000ul /* GX/CX */

1320

#define CFG_PCI33EN 0x00400000ul /* GTPro */

1321

#define CFG_VGA_EN 0x00800000ul /* GX/CX */

1322

#define CFG_FULLAGP 0x00800000ul /* GTPro */

1323

#define CFG_ARITHMOS_ENABLE 0x00800000ul /* XC/XL */

1324

#define CFG_LOCAL_BUS_CFG 0x01000000ul /* GX/CX */

1325

#define CFG_CHIP_EN 0x02000000ul /* GX/CX */

1326

#define CFG_LOCAL_READ_DLY_DIS 0x04000000ul /* GX/CX */

1327

#define CFG_ROM_OPTION 0x08000000ul /* GX/CX */

1328

#define CFG_BUS_OPTION 0x10000000ul /* GX/CX */

1329

#define CFG_LOCAL_DAC_WR_EN 0x20000000ul /* GX/CX */

1330

#define CFG_VLB_RDY_DIS 0x40000000ul /* GX/CX */

1331

#define CFG_AP_4GBYTE_DIS 0x80000000ul /* GX/CX */

1332

#define CONFIG_STATUS64_1 IOPortTag(0x1du, 0x3au) /* Read */

1333

#define CFG_PCI_DAC_CFG 0x00000001ul /* GX/CX */

1334

/* ? 0x0000001eul */ /* GX/CX */

1335

#define CFG_1C8_IO_SEL 0x00000020ul /* GX/CX */

1336

/* ? 0xffffffc0ul */ /* GX/CX */

1337

#define CRC_SIG 0xfffffffful /* 264xT */

1338

#define MPP_CONFIG BlockIOTag(0x3bu) /* VTB/GTB/LT */

1339

#define MPP_PRESCALE 0x00000007ul

1340

/* ? 0x00000008ul */

1341

#define MPP_NSTATES 0x00000030ul

1342

/* ? 0x00000000ul */

1343

#define MPP_NSTATES_2 0x00000010ul

1344

#define MPP_NSTATES_4 0x00000020ul

1345

#define MPP_NSTATES_8 0x00000030ul

1346

#define MPP_FORMAT 0x000000c0ul

1347

#define MPP_FORMAT_DO8 0x00000000ul

1348

#define MPP_FORMAT_DO16 0x00000040ul

1349

#define MPP_FORMAT_DA8 0x00000080ul

1350

#define MPP_FORMAT_DA16 0x000000c0ul

1351

#define MPP_WAIT_STATE 0x00000700ul

1352

#define MPP_CHKRDY_EN 0x00000800ul

1353

#define MPP_INSERT_WAIT 0x00001000ul

1354

#define MPP_TRISTATE_ADDR 0x00002000ul

1355

/* ? 0x00004000ul */

1356

#define MPP_READ_EARLY 0x00008000ul

1357

#define MPP_RW_MODE 0x00030000ul

1358

#define MPP_INT_MASK 0x000c0000ul

1359

#define MPP_AUTO_INC_EN 0x00300000ul

1360

#define MPP_CHKREQ_EN 0x00400000ul

1361

#define MPP_CHKREQ_MODE 0x00800000ul

1362

#define MPP_BUFFER_SIZE 0x03000000ul

1363

#define MPP_BUFFER_MODE 0x0c000000ul

1364

#define MPP_BUFFER_MODE_NORMAL 0x00000000ul

1365

#define MPP_BUFFER_MODE_PREFETCH 0x04000000ul

1366

#define MPP_BUFFER_MODE_BUS_MASTER 0x08000000ul

1367

/* ? 0x0c000000ul */

1368

/* ? 0x30000000ul */

1369

#define MPP_BUSY 0x40000000ul

1370

#define MPP_EN 0x80000000ul

1371

#define MPP_STROBE_SEQ BlockIOTag(0x3cu) /* VTB/GTB/LT */

1372

#define MPP_STB0_SEQ 0x000000fful

1373

#define MPP_STB1_SEQ 0x0000ff00ul

1374

/* ? 0xffff0000ul */

1375

#define MPP_ADDR BlockIOTag(0x3du) /* VTB/GTB/LT */

1376

#define MPP_DATA BlockIOTag(0x3eu) /* VTB/GTB/LT */

1377

#define TVO_CNTL BlockIOTag(0x3fu) /* VTB/GTB/LT */

1378

#define TVO_H_TOT_PIX 0x00000007ul

1379

#define TVO_PC_OVR_DIS 0x00000008ul

1380

#define TVO_H_TOT_EDGE 0x00000010ul

1381

/* ? 0x00000060ul */

1382

#define TVO_VBLANK_ONLY 0x00000080ul

1383

/* ? 0x0000ff00ul */

1384

#define TVO_MPEG_CLR_SRC 0x00030000ul

1385

/* ? 0x1ffc0000ul */

1386

#define TVO_MPEG_CLK_EN 0x20000000ul

1387

#define TVO_OVERRIDE_EN 0x40000000ul

1388

#define TVO_EN 0x80000000ul

1389

/* GP_IO IOPortTag(0x1eu, 0x1eu) */ /* See above */

1390

/* CRTC_H_TOTAL_DISP IOPortTag(0x1fu, 0x00u) */ /* Duplicate */

1391

#define DST_OFF_PITCH BlockIOTag(0x40u)

1392

#define DST_OFFSET 0x000ffffful

1393

/* ? 0x00300000ul */

1394

#define DST_PITCH 0xffc00000ul

1395

#define DST_X BlockIOTag(0x41u)

1396

#define DST_Y BlockIOTag(0x42u)

1397

#define DST_Y_X BlockIOTag(0x43u)

1398

#define DST_WIDTH BlockIOTag(0x44u)

1399

#define DST_HEIGHT BlockIOTag(0x45u)

1400

#define DST_HEIGHT_WIDTH BlockIOTag(0x46u)

1401

#define DST_X_WIDTH BlockIOTag(0x47u)

1402

#define DST_BRES_LNTH BlockIOTag(0x48u)

1403

#define DST_BRES_ERR BlockIOTag(0x49u)

1404

#define DST_BRES_INC BlockIOTag(0x4au)

1405

#define DST_BRES_DEC BlockIOTag(0x4bu)

1406

#define DST_CNTL BlockIOTag(0x4cu)

1407

#define DST_X_DIR 0x00000001ul

1408

#define DST_Y_DIR 0x00000002ul

1409

#define DST_Y_MAJOR 0x00000004ul

1410

#define DST_X_TILE 0x00000008ul

1411

#define DST_Y_TILE 0x00000010ul

1412

#define DST_LAST_PEL 0x00000020ul

1413

#define DST_POLYGON_EN 0x00000040ul

1414

#define DST_24_ROT_EN 0x00000080ul

1415

#define DST_24_ROT 0x00000700ul

1416

#define DST_BRES_SIGN 0x00000800ul /* GX/CX */

1417

#define DST_BRES_ZERO 0x00000800ul /* CT */

1418

#define DST_POLYGON_RTEDGE_DIS 0x00001000ul /* CT */

1419

#define TRAIL_X_DIR 0x00002000ul /* GT */

1420

#define TRAP_FILL_DIR 0x00004000ul /* GT */

1421

#define TRAIL_BRES_SIGN 0x00008000ul /* GT */

1422

/* ? 0x00010000ul */

1423

#define BRES_SIGN_AUTO 0x00020000ul /* GT */

1424

/* ? 0x00040000ul */

1425

#define ALPHA_OVERLAP_ENB 0x00080000ul /* GTPro */

1426

#define SUB_PIX_ON 0x00100000ul /* GTPro */

1427

/* ? 0xffe00000ul */

1428

/* DST_Y_X BlockIOTag(0x4du) */ /* Duplicate */

1429

#define TRAIL_BRES_ERR BlockIOTag(0x4eu) /* GT */

1430

#define TRAIL_BRES_INC BlockIOTag(0x4fu) /* GT */

1431

#define TRAIL_BRES_DEC BlockIOTag(0x50u) /* GT */

1432

#define LEAD_BRES_LNTH BlockIOTag(0x51u) /* GT */

1433

#define Z_OFF_PITCH BlockIOTag(0x52u) /* GT */

1434

#define Z_CNTL BlockIOTag(0x53u) /* GT */

1435

#define ALPHA_TST_CNTL BlockIOTag(0x54u) /* GTPro */

1436

/* ? BlockIOTag(0x55u) */

1437

#define SECONDARY_STW_EXP BlockIOTag(0x56u) /* GTPro */

1438

#define SECONDARY_S_X_INC BlockIOTag(0x57u) /* GTPro */

1439

#define SECONDARY_S_Y_INC BlockIOTag(0x58u) /* GTPro */

1440

#define SECONDARY_S_START BlockIOTag(0x59u) /* GTPro */

1441

#define SECONDARY_W_X_INC BlockIOTag(0x5au) /* GTPro */

1442

#define SECONDARY_W_Y_INC BlockIOTag(0x5bu) /* GTPro */

1443

#define SECONDARY_W_START BlockIOTag(0x5cu) /* GTPro */

1444

#define SECONDARY_T_X_INC BlockIOTag(0x5du) /* GTPro */

1445

#define SECONDARY_T_Y_INC BlockIOTag(0x5eu) /* GTPro */

1446

#define SECONDARY_T_START BlockIOTag(0x5fu) /* GTPro */

1447

#define SRC_OFF_PITCH BlockIOTag(0x60u)

1448

#define SRC_OFFSET 0x000ffffful

1449

/* ? 0x00300000ul */

1450

#define SRC_PITCH 0xffc00000ul

1451

#define SRC_X BlockIOTag(0x61u)

1452

#define SRC_Y BlockIOTag(0x62u)

1453

#define SRC_Y_X BlockIOTag(0x63u)

1454

#define SRC_WIDTH1 BlockIOTag(0x64u)

1455

#define SRC_HEIGHT1 BlockIOTag(0x65u)

1456

#define SRC_HEIGHT1_WIDTH1 BlockIOTag(0x66u)

1457

#define SRC_X_START BlockIOTag(0x67u)

1458

#define SRC_Y_START BlockIOTag(0x68u)

1459

#define SRC_Y_X_START BlockIOTag(0x69u)

1460

#define SRC_WIDTH2 BlockIOTag(0x6au)

1461

#define SRC_HEIGHT2 BlockIOTag(0x6bu)

1462

#define SRC_HEIGHT2_WIDTH2 BlockIOTag(0x6cu)

1463

#define SRC_CNTL BlockIOTag(0x6du)

1464

#define SRC_PATT_EN 0x00000001ul

1465

#define SRC_PATT_ROT_EN 0x00000002ul

1466

#define SRC_LINEAR_EN 0x00000004ul

1467

#define SRC_BYTE_ALIGN 0x00000008ul

1468

#define SRC_LINE_X_DIR 0x00000010ul

1469

#define SRC_8X8X8_BRUSH 0x00000020ul /* VTB/GTB */

1470

#define FAST_FILL_EN 0x00000040ul /* VTB/GTB */

1471

#define SRC_TRACK_DST 0x00000080ul /* VTB/GTB */

1472

#define BUS_MASTER_EN 0x00000100ul /* VTB/GTB */

1473

#define BUS_MASTER_SYNC 0x00000200ul /* VTB/GTB */

1474

#define BUS_MASTER_OP 0x00000c00ul /* VTB/GTB */

1475

#define SRC_8X8X8_BRUSH_LOADED 0x00001000ul /* VTB/GTB */

1476

#define COLOR_REG_WRITE_EN 0x00002000ul /* VTB/GTB */

1477

#define BLOCK_WRITE_EN 0x00004000ul /* VTB/GTB */

1478

/* ? 0xffff8000ul */

1479

/* ? BlockIOTag(0x6eu) */

1480

/* ? BlockIOTag(0x6fu) */

1481

#define SCALE_Y_OFF BlockIOTag(0x70u) /* GT */

1482

#define SCALE_OFF BlockIOTag(0x70u) /* GTPro */

1483

#define SECONDARY_SCALE_OFF BlockIOTag(0x70u) /* GTPro */

1484

#define TEX_0_OFF BlockIOTag(0x70u) /* GT */

1485

#define TEX_1_OFF BlockIOTag(0x71u) /* GT */

1486

#define TEX_2_OFF BlockIOTag(0x72u) /* GT */

1487

#define TEX_3_OFF BlockIOTag(0x73u) /* GT */

1488

#define TEX_4_OFF BlockIOTag(0x74u) /* GT */

1489

#define TEX_5_OFF BlockIOTag(0x75u) /* GT */

1490

#define TEX_6_OFF BlockIOTag(0x76u) /* GT */

1491

#define SCALE_WIDTH BlockIOTag(0x77u) /* GT */

1492

#define TEX_7_OFF BlockIOTag(0x77u) /* GT */

1493

#define SCALE_HEIGHT BlockIOTag(0x78u) /* GT */

1494

#define TEX_8_OFF BlockIOTag(0x78u) /* GT */

1495

#define TEX_9_OFF BlockIOTag(0x79u) /* GT */

1496

#define TEX_10_OFF BlockIOTag(0x7au) /* GT */

1497

#define S_Y_INC BlockIOTag(0x7bu) /* GT */

1498

#define SCALE_Y_PITCH BlockIOTag(0x7bu) /* GT */

1499

#define SCALE_X_INC BlockIOTag(0x7cu) /* GT */

1500

#define RED_X_INC BlockIOTag(0x7cu) /* GT */

1501

#define GREEN_X_INC BlockIOTag(0x7du) /* GT */

1502

#define SCALE_Y_INC BlockIOTag(0x7du) /* GT */

1503

#define SCALE_VACC BlockIOTag(0x7eu) /* GT */

1504

#define SCALE_3D_CNTL BlockIOTag(0x7fu) /* GT */

1505

#define HOST_DATA_0 BlockIOTag(0x80u)

1506

#define HOST_DATA_1 BlockIOTag(0x81u)

1507

#define HOST_DATA_2 BlockIOTag(0x82u)

1508

#define HOST_DATA_3 BlockIOTag(0x83u)

1509

#define HOST_DATA_4 BlockIOTag(0x84u)

1510

#define HOST_DATA_5 BlockIOTag(0x85u)

1511

#define HOST_DATA_6 BlockIOTag(0x86u)

1512

#define HOST_DATA_7 BlockIOTag(0x87u)

1513

#define HOST_DATA_8 BlockIOTag(0x88u)

1514

#define HOST_DATA_9 BlockIOTag(0x89u)

1515

#define HOST_DATA_A BlockIOTag(0x8au)

1516

#define HOST_DATA_B BlockIOTag(0x8bu)

1517

#define HOST_DATA_C BlockIOTag(0x8cu)

1518

#define HOST_DATA_D BlockIOTag(0x8du)

1519

#define HOST_DATA_E BlockIOTag(0x8eu)

1520

#define HOST_DATA_F BlockIOTag(0x8fu)

1521

#define HOST_CNTL BlockIOTag(0x90u)

1522

#define HOST_BYTE_ALIGN 0x00000001ul

1523

#define HOST_BIG_ENDIAN_EN 0x00000002ul /* GX-E/CT */

1524

/* ? 0xfffffffcul */

1525

#define BM_HOSTDATA BlockIOTag(0x91u) /* VTB/GTB */

1526

#define BM_ADDR BlockIOTag(0x92u) /* VTB/GTB */

1527

#define BM_DATA BlockIOTag(0x92u) /* VTB/GTB */

1528

#define BM_GUI_TABLE_CMD BlockIOTag(0x93u) /* GTPro */

1529

/* ? BlockIOTag(0x94u) */

1530

/* ? BlockIOTag(0x95u) */

1531

/* ? BlockIOTag(0x96u) */

1532

/* ? BlockIOTag(0x97u) */

1533

/* ? BlockIOTag(0x98u) */

1534

/* ? BlockIOTag(0x99u) */

1535

/* ? BlockIOTag(0x9au) */

1536

/* ? BlockIOTag(0x9bu) */

1537

/* ? BlockIOTag(0x9cu) */

1538

/* ? BlockIOTag(0x9du) */

1539

/* ? BlockIOTag(0x9eu) */

1540

/* ? BlockIOTag(0x9fu) */

1541

#define PAT_REG0 BlockIOTag(0xa0u)

1542

#define PAT_REG1 BlockIOTag(0xa1u)

1543

#define PAT_CNTL BlockIOTag(0xa2u)

1544

#define PAT_MONO_EN 0x00000001ul

1545

#define PAT_CLR_4x2_EN 0x00000002ul

1546

#define PAT_CLR_8x1_EN 0x00000004ul

1547

/* ? 0xfffffff8ul */

1548

/* ? BlockIOTag(0xa3u) */

1549

/* ? BlockIOTag(0xa4u) */

1550

/* ? BlockIOTag(0xa5u) */

1551

/* ? BlockIOTag(0xa6u) */

1552

/* ? BlockIOTag(0xa7u) */

1553

#define SC_LEFT BlockIOTag(0xa8u)

1554

#define SC_RIGHT BlockIOTag(0xa9u)

1555

#define SC_LEFT_RIGHT BlockIOTag(0xaau)

1556

#define SC_TOP BlockIOTag(0xabu)

1557

#define SC_BOTTOM BlockIOTag(0xacu)

1558

#define SC_TOP_BOTTOM BlockIOTag(0xadu)

1559

#define USR1_DST_OFF_PITCH BlockIOTag(0xaeu) /* LTPro */

1560

#define USR2_DST_OFF_PITCH BlockIOTag(0xafu) /* LTPro */

1561

#define DP_BKGD_CLR BlockIOTag(0xb0u)

1562

#define DP_FRGD_CLR BlockIOTag(0xb1u)

1563

#define DP_WRITE_MASK BlockIOTag(0xb2u)

1564

#define DP_CHAIN_MASK BlockIOTag(0xb3u)

1565

#define DP_CHAIN_1BPP 0x00000000ul /* Irrelevant */

1566

#define DP_CHAIN_4BPP 0x00008888ul

1567

#define DP_CHAIN_8BPP 0x00008080ul

1568

#define DP_CHAIN_8BPP_332 0x00009292ul

1569

#define DP_CHAIN_15BPP_1555 0x00004210ul

1570

#define DP_CHAIN_16BPP_565 0x00008410ul

1571

#define DP_CHAIN_24BPP_888 0x00008080ul

1572

#define DP_CHAIN_32BPP_8888 0x00008080ul

1573

/* ? 0xffff0000ul */

1574

#define DP_PIX_WIDTH BlockIOTag(0xb4u)

1575

#define DP_DST_PIX_WIDTH 0x0000000ful

1576

#define COMPOSITE_PIX_WIDTH 0x000000f0ul /* GTPro */

1577

#define DP_SRC_PIX_WIDTH 0x00000f00ul

1578

/* ? 0x00001000ul */

1579

#define DP_HOST_TRIPLE_EN 0x00002000ul /* GT2c/VT4 */

1580

#define DP_SRC_AUTONA_FIX_DIS 0x00004000ul /* GTB */

1581

#define DP_FAST_SRCCOPY_DIS 0x00008000ul /* GTB */

1582

#define DP_HOST_PIX_WIDTH 0x000f0000ul

1583

#define DP_CI4_RGB_INDEX 0x00f00000ul /* GTB */

1584

#define DP_BYTE_PIX_ORDER 0x01000000ul

1585

#define DP_CONVERSION_TEMP 0x02000000ul /* GTB */

1586

#define DP_CI4_RGB_LOW_NIBBLE 0x04000000ul /* GTB */

1587

#define DP_C14_RGB_HIGH_NIBBLE 0x08000000ul /* GTB */

1588

#define DP_SCALE_PIX_WIDTH 0xf0000000ul /* GTB */

1589

#define DP_MIX BlockIOTag(0xb5u)

1590

#define DP_BKGD_MIX 0x0000001ful

1591

/* ? 0x0000ffe0ul */

1592

#define DP_FRGD_MIX 0x001f0000ul

1593

/* ? 0xffe00000ul */

1594

#define DP_SRC BlockIOTag(0xb6u)

1595

#define DP_BKGD_SRC 0x00000007ul

1596

/* ? 0x000000feul */

1597

#define DP_FRGD_SRC 0x00000700ul

1598

/* ? 0x0000fe00ul */

1599

#define DP_MONO_SRC 0x00030000ul

1600

#define DP_MONO_SRC_ALLONES 0x00000000ul

1601

#define DP_MONO_SRC_PATTERN 0x00010000ul

1602

#define DP_MONO_SRC_HOST 0x00020000ul

1603

#define DP_MONO_SRC_BLIT 0x00030000ul

1604

/* ? 0xfffc0000ul */

1605

#define DP_FRGD_CLR_MIX BlockIOTag(0xb7u) /* VTB/GTB */

1606

#define DP_FRGD_BKGD_CLR BlockIOTag(0xb8u) /* VTB/GTB */

1607

/* ? BlockIOTag(0xb9u) */

1608

#define DST_X_Y BlockIOTag(0xbau) /* VTB/GTB */

1609

#define DST_WIDTH_HEIGHT BlockIOTag(0xbbu) /* VTB/GTB */

1610

#define USR_DST_PITCH BlockIOTag(0xbcu) /* GTPro */

1611

/* ? BlockIOTag(0xbdu) */

1612

#define DP_SET_GUI_ENGINE2 BlockIOTag(0xbeu) /* GTPro */

1613

#define DP_SET_GUI_ENGINE BlockIOTag(0xbfu) /* VTB/GTB */

1614

#define CLR_CMP_CLR BlockIOTag(0xc0u)

1615

#define CLR_CMP_MSK BlockIOTag(0xc1u)

1616

#define CLR_CMP_CNTL BlockIOTag(0xc2u)

1617

#define CLR_CMP_FN 0x00000007ul

1618

#define CLR_CMP_FN_FALSE 0x00000000ul

1619

#define CLR_CMP_FN_TRUE 0x00000001ul

1620

/* ? 0x00000002ul */

1621

/* ? 0x00000003ul */

1622

#define CLR_CMP_FN_NOT_EQUAL 0x00000004ul

1623

#define CLR_CMP_FN_EQUAL 0x00000005ul

1624

/* ? 0x00000006ul */

1625

/* ? 0x00000007ul */

1626

/* ? 0x00fffff8ul */

1627

#define CLR_CMP_SRC 0x03000000ul

1628

#define CLR_CMP_SRC_DST 0x00000000ul

1629

#define CLR_CMP_SRC_2D 0x01000000ul

1630

#define CLR_CMP_SRC_TEXEL 0x02000000ul

1631

/* ? 0x03000000ul */

1632

/* ? 0xfc000000ul */

1633

/* ? BlockIOTag(0xc3u) */

1634

#define FIFO_STAT BlockIOTag(0xc4u)

1635

#define FIFO_STAT_BITS 0x0000fffful

1636

/* ? 0x7fff0000ul */

1637

#define FIFO_ERR 0x80000000ul

1638

/* ? BlockIOTag(0xc5u) */

1639

/* ? BlockIOTag(0xc6u) */

1640

/* ? BlockIOTag(0xc7u) */

1641

#define CONTEXT_MASK BlockIOTag(0xc8u)

1642

/* ? BlockIOTag(0xc9u) */

1643

/* ? BlockIOTag(0xcau) */

1644

#define CONTEXT_LOAD_CNTL BlockIOTag(0xcbu)

1645

#define CONTEXT_LOAD_PTR 0x00007ffful

1646

/* ? 0x00008000ul */

1647

#define CONTEXT_LOAD_CMD 0x00030000ul

1648

#define CONTEXT_LOAD_NONE 0x00000000ul

1649

#define CONTEXT_LOAD_ONLY 0x00010000ul

1650

#define CONTEXT_LOAD_FILL 0x00020000ul

1651

#define CONTEXT_LOAD_LINE 0x00030000ul

1652

/* ? 0x7ffc0000ul */

1653

#define CONTEXT_LOAD_DIS 0x80000000ul

1654

#define GUI_TRAJ_CNTL BlockIOTag(0xccu)

1655

/* ? BlockIOTag(0xcdu) */

1656

#define GUI_STAT BlockIOTag(0xceu)

1657

#define GUI_ACTIVE 0x00000001ul

1658

/* ? 0x000000feul */

1659

#define DSTX_LT_SCISSOR_LEFT 0x00000100ul

1660

#define DSTX_GT_SCISSOR_RIGHT 0x00000200ul

1661

#define DSTY_LT_SCISSOR_TOP 0x00000400ul

1662

#define DSTY_GT_SCISSOR_BOTTOM 0x00000800ul

1663

/* ? 0x0000f000ul */

1664

#define GUI_FIFO 0x03ff0000ul /* VTB/GTB */

1665

/* ? 0xfc000000ul */

1666

/* ? BlockIOTag(0xcfu) */

1667

#define S_X_INC2 BlockIOTag(0xd0u) /* GTB */

1668

#define TEX_PALETTE_INDEX BlockIOTag(0xd0u) /* GTPro */

1669

#define S_Y_INC2 BlockIOTag(0xd1u) /* GTB */

1670

#define STW_EXP BlockIOTag(0xd1u) /* GTPro */

1671

#define S_XY_INC2 BlockIOTag(0xd2u) /* GTB */

1672

#define LOG_MAX_INC BlockIOTag(0xd2u) /* GTPro */

1673

#define S_XINC_START BlockIOTag(0xd3u) /* GTB */

1674

/* S_Y_INC BlockIOTag(0xd4u) */ /* Duplicate */

1675

/* SCALE_Y_PITCH BlockIOTag(0xd4u) */ /* Duplicate */

1676

#define S_START BlockIOTag(0xd5u) /* GTB */

1677

#define T_X_INC2 BlockIOTag(0xd6u) /* GTB */

1678

#define W_X_INC BlockIOTag(0xd6u) /* GTPro */

1679

#define T_Y_INC2 BlockIOTag(0xd7u) /* GTB */

1680

#define W_Y_INC BlockIOTag(0xd7u) /* GTPro */

1681

#define T_XY_INC2 BlockIOTag(0xd8u) /* GTB */

1682

#define W_START BlockIOTag(0xd8u) /* GTPro */

1683

#define T_XINC_START BlockIOTag(0xd9u) /* GTB */

1684

#define T_Y_INC BlockIOTag(0xdau) /* GTB */

1685

#define SECONDARY_SCALE_PITCH BlockIOTag(0xdau) /* GTPro */

1686

#define T_START BlockIOTag(0xdbu) /* GTB */

1687

#define TEX_SIZE_PITCH BlockIOTag(0xdcu) /* GTB */

1688

#define TEX_CNTL BlockIOTag(0xddu) /* GTPro */

1689

#define SECONDARY_TEX_OFFSET BlockIOTag(0xdeu) /* GTPro */

1690

#define TEX_PAL_WR BlockIOTag(0xdfu) /* GTB */

1691

#define TEX_PALETTE BlockIOTag(0xdfu) /* GTPro */

1692

#define SCALE_PITCH_BOTH BlockIOTag(0xe0u) /* GTPro */

1693

#define SECONDARY_SCALE_OFF_ACC BlockIOTag(0xe1u) /* GTPro */

1694

#define SCALE_OFF_ACC BlockIOTag(0xe2u) /* GTPro */

1695

#define SCALE_DST_Y_X BlockIOTag(0xe3u) /* GTPro */

1696

/* ? BlockIOTag(0xe4u) */

1697

/* ? BlockIOTag(0xe5u) */

1698

#define COMPOSITE_SHADOW_ID BlockIOTag(0xe6u) /* GTPro */

1699

#define SECONDARY_SCALE_X_INC BlockIOTag(0xe7u) /* GTPro */

1700

#define SPECULAR_RED_X_INC BlockIOTag(0xe7u) /* GTPro */

1701

#define SPECULAR_RED_Y_INC BlockIOTag(0xe8u) /* GTPro */

1702

#define SPECULAR_RED_START BlockIOTag(0xe9u) /* GTPro */

1703

#define SECONDARY_SCALE_HACC BlockIOTag(0xe9u) /* GTPro */

1704

#define SPECULAR_GREEN_X_INC BlockIOTag(0xeau) /* GTPro */

1705

#define SPECULAR_GREEN_Y_INC BlockIOTag(0xebu) /* GTPro */

1706

#define SPECULAR_GREEN_START BlockIOTag(0xecu) /* GTPro */

1707

#define SPECULAR_BLUE_X_INC BlockIOTag(0xedu) /* GTPro */

1708

#define SPECULAR_BLUE_Y_INC BlockIOTag(0xeeu) /* GTPro */

1709

#define SPECULAR_BLUE_START BlockIOTag(0xefu) /* GTPro */

1710

/* SCALE_X_INC BlockIOTag(0xf0u) */ /* Duplicate */

1711

/* RED_X_INC BlockIOTag(0xf0u) */ /* Duplicate */

1712

#define RED_Y_INC BlockIOTag(0xf1u) /* GTB */

1713

#define SCALE_HACC BlockIOTag(0xf2u) /* GTB */

1714

#define RED_START BlockIOTag(0xf2u) /* GTB */

1715

/* GREEN_X_INC BlockIOTag(0xf3u) */ /* Duplicate */

1716

/* SCALE_Y_INC BlockIOTag(0xf3u) */ /* Duplicate */

1717

#define GREEN_Y_INC BlockIOTag(0xf4u) /* GTB */

1718

#define SECONDARY_SCALE_Y_INC BlockIOTag(0xf4u) /* GTPro */

1719

#define SECONDARY_SCALE_VACC BlockIOTag(0xf5u) /* GTPro */

1720

#define GREEN_START BlockIOTag(0xf5u) /* GTB */

1721

#define BLUE_X_INC BlockIOTag(0xf6u) /* GTB */

1722

#define SCALE_XUV_INC BlockIOTag(0xf6u) /* GTB */

1723

#define BLUE_Y_INC BlockIOTag(0xf7u) /* GTB */

1724

#define BLUE_START BlockIOTag(0xf8u) /* GTB */

1725

#define SCALE_UV_HACC BlockIOTag(0xf8u) /* GTB */

1726

#define Z_X_INC BlockIOTag(0xf9u) /* GTB */

1727

#define Z_Y_INC BlockIOTag(0xfau) /* GTB */

1728

#define Z_START BlockIOTag(0xfbu) /* GTB */

1729

#define ALPHA_FOG_X_INC BlockIOTag(0xfcu) /* GTB */

1730

#define ALPHA_FOG_Y_INC BlockIOTag(0xfdu) /* GTB */

1731

#define ALPHA_FOG_START BlockIOTag(0xfeu) /* GTB */

1732

/* ? BlockIOTag(0xffu) */

1733

#define OVERLAY_Y_X_START BlockIOTag(0x100u)

1734

#define OVERLAY_Y_START 0x000003fful

1735

/* ? 0x0000fc00ul */

1736

#define OVERLAY_X_START 0x03ff0000ul

1737

/* ? 0x7c000000ul */

1738

#define OVERLAY_LOCK_START 0x80000000ul

1739

#define OVERLAY_Y_X_END BlockIOTag(0x101u)

1740

#define OVERLAY_Y_END 0x000003fful

1741

/* ? 0x0000fc00ul */

1742

#define OVERLAY_X_END 0x03ff0000ul

1743

/* ? 0x7c000000ul */

1744

#define OVERLAY_LOCK_END 0x80000000ul

1745

#define OVERLAY_VIDEO_KEY_CLR BlockIOTag(0x102u)

1746

#define OVERLAY_VIDEO_KEY_MSK BlockIOTag(0x103u)

1747

#define OVERLAY_GRAPHICS_KEY_CLR BlockIOTag(0x104u)

1748

#define OVERLAY_GRAPHICS_KEY_MSK BlockIOTag(0x105u)

1749

#define OVERLAY_KEY_CNTL BlockIOTag(0x106u)

1750

#define OVERLAY_VIDEO_FN 0x00000007ul

1751

/* ? 0x00000008ul */

1752

#define OVERLAY_GRAPHICS_FN 0x00000070ul

1753

/* ? 0x00000080ul */

1754

#define OVERLAY_CMP_MIX 0x00000100ul

1755

/* ? 0xfffffe00ul */

1756

/* ? BlockIOTag(0x107u) */

1757

#define OVERLAY_SCALE_INC BlockIOTag(0x108u)

1758

#define OVERLAY_SCALE_CNTL BlockIOTag(0x109u)

1759

#define SCALE_PIX_EXPAND 0x00000001ul

1760

#define SCALE_Y2R_TEMP 0x00000002ul

1761

#define SCALE_HORZ_MODE 0x00000004ul

1762

#define SCALE_VERT_MODE 0x00000008ul

1763

#define SCALE_SIGNED_UV 0x00000010ul

1764

#define SCALE_GAMMA_SEL 0x00000060ul

1765

/* ? 0x03ffff80ul */

1766

#define SCALE_BANDWIDTH 0x04000000ul

1767

#define SCALE_DIS_LIMIT 0x08000000ul

1768

/* ? 0x10000000ul */

1769

#define SCALE_CLK_FORCE_ON 0x20000000ul

1770

#define OVERLAY_EN 0x40000000ul

1771

#define SCALE_EN 0x80000000ul

1772

#define SCALER_HEIGHT_WIDTH BlockIOTag(0x10au)

1773

#define SCALER_TEST BlockIOTag(0x10bu)

1774

/* ? 0x00000001ul */

1775

#define SCALE_Y2R_DIS 0x00000002ul

1776

/* ? 0xfffffffcul */

1777

#define SCALER_THRESHOLD BlockIOTag(0x10cu)

1778

#define SCALER_BUF0_OFFSET BlockIOTag(0x10du) /* VTB/GTB */

1779

#define SCALER_BUF1_OFFSET BlockIOTag(0x10eu) /* VTB/GTB */

1780

#define SCALER_BUF_PITCH BlockIOTag(0x10fu) /* VTB/GTB */

1781

#define CAPTURE_Y_X BlockIOTag(0x110u)

1782

#define CAPTURE_START_END BlockIOTag(0x110u) /* VTB/GTB */

1783

#define CAPTURE_HEIGHT_WIDTH BlockIOTag(0x111u)

1784

#define CAPTURE_X_WIDTH BlockIOTag(0x111u) /* VTB/GTB */

1785

#define VIDEO_FORMAT BlockIOTag(0x112u)

1786

#define VIDEO_IN 0x0000000ful

1787

/* ? 0x00000000ul */

1788

/* ? 0x00000001ul */

1789

/* ? 0x00000002ul */

1790

/* ? 0x00000003ul */

1791

/* ? 0x00000004ul */

1792

/* ? 0x00000005ul */

1793

/* ? 0x00000006ul */

1794

/* ? 0x00000007ul */

1795

/* ? 0x00000008ul */

1796

/* ? 0x00000009ul */

1797

/* ? 0x0000000aul */

1798

#define VIDEO_IN_VYUY422 0x0000000bul

1799

#define VIDEO_IN_YVYU422 0x0000000cul

1800

/* ? 0x0000000dul */

1801

/* ? 0x0000000eul */

1802

/* ? 0x0000000ful */

1803

#define VIDEO_SIGNED_UV 0x00000010ul

1804

/* ? 0x0000ffe0ul */

1805

#define SCALER_IN 0x000f0000ul

1806

/* ? 0x00000000ul */

1807

/* ? 0x00010000ul */

1808

/* ? 0x00020000ul */

1809

#define SCALER_IN_15BPP 0x00030000ul

1810

#define SCALER_IN_16BPP 0x00040000ul

1811

/* ? 0x00050000ul */

1812

#define SCALER_IN_32BPP 0x00060000ul

1813

/* ? 0x00070000ul */

1814

/* ? 0x00080000ul */

1815

#define SCALER_IN_YUV9 0x00090000ul

1816

#define SCALER_IN_YUV12 0x000a0000ul

1817

#define SCALER_IN_VYUY422 0x000b0000ul

1818

#define SCALER_IN_YVYU422 0x000c0000ul

1819

/* ? 0x000d0000ul */

1820

/* ? 0x000e0000ul */

1821

/* ? 0x000f0000ul */

1822

/* ? 0x0ff00000ul */

1823

#define HOST_BYTE_SHIFT_EN 0x10000000ul

1824

#define HOST_YUV_APER 0x20000000ul

1825

#define HOST_MEM_MODE 0xc0000000ul

1826

#define HOST_MEM_MODE_NORMAL 0x00000000ul

1827

#define HOST_MEM_MODE_Y 0x40000000ul

1828

#define HOST_MEM_MODE_U 0x80000000ul

1829

#define HOST_MEM_MODE_V 0xc0000000ul

1830

#define VIDEO_CONFIG BlockIOTag(0x113u)

1831

#define VBI_START_END BlockIOTag(0x113u) /* VTB/GTB */

1832

#define CAPTURE_CONFIG BlockIOTag(0x114u)

1833

#define CAP_INPUT_MODE 0x00000001ul

1834

#define CAP_START_FIELD 0x00000002ul

1835

#define CAP_BUF_MODE 0x00000004ul

1836

#define CAP_START_BUF 0x00000008ul

1837

#define CAP_BUF_TYPE 0x00000030ul

1838

#define CAP_BUF_FIELD 0x00000000ul

1839

#define CAP_BUF_ALTERNATING 0x00000010ul

1840

#define CAP_BUF_FRAME 0x00000020ul

1841

/* ? 0x00000030ul */

1842

#define CAP_FIELD_FLIP 0x00000040ul

1843

#define CAP_CCIR656_EN 0x00000080ul

1844

/* ? 0x00000f00ul */

1845

#define CAP_MIRROR_EN 0x00001000ul

1846

#define ONESHOT_MIRROR_EN 0x00002000ul

1847

#define ONESHOT_MODE 0x00004000ul

1848

/* ? 0x00008000ul */

1849

#define CAP_HORZ_DOWN 0x00030000ul

1850

#define CAP_VERT_DOWN 0x000c0000ul

1851

#define ONESHOT_HORZ_DOWN 0x00300000ul

1852

#define ONESHOT_VERT_DOWN 0x00c00000ul

1853

/* ? 0x0f000000ul */

1854

#define OVL_BUF_MODE 0x10000000ul

1855

#define OVL_BUF_NEXT 0x20000000ul

1856

/* ? 0xc0000000ul */

1857

#define TRIG_CNTL BlockIOTag(0x115u)

1858

#define CAP_TRIGGER 0x00000003ul

1859

#define CAP_TRIGGER_NEXT 0x00000001ul

1860

/* ? 0x0000001cul */

1861

#define OVL_CUR_BUF 0x00000020ul

1862

#define OVL_BUF_STATUS 0x00000040ul

1863

#define CAP_BUF_STATUS 0x00000080ul

1864

/* ? 0x7fffff00ul */

1865

#define CAPTURE_EN 0x80000000ul

1866

#define VIDEO_SYNC_TEST BlockIOTag(0x116u)

1867

#define OVERLAY_EXCLUSIVE_HORZ BlockIOTag(0x116u) /* VTB/GTB */

1868

#define EXCLUSIVE_HORZ_START 0x000000fful

1869

#define EXCLUSIVE_HORZ_END 0x0000ff00ul

1870

#define EXCLUSIVE_HORZ_PORCH 0x00ff0000ul

1871

/* ? 0x7f000000ul */

1872

#define EXCLUSIVE_EN 0x80000000ul

1873

#define EXT_CRTC_GEN_CNTL_R BlockIOTag(0x117u) /* VT-A4 (R) */

1874

#define OVERLAY_EXCLUSIVE_VERT BlockIOTag(0x117u) /* VTB/GTB */

1875

#define EXCLUSIVE_VERT_START 0x000003fful

1876

/* ? 0x0000fc00ul */

1877

#define EXCLUSIVE_VERT_END 0x03ff0000ul

1878

/* ? 0xfc000000ul */

1879

#define VMC_CONFIG BlockIOTag(0x118u)

1880

#define VBI_WIDTH BlockIOTag(0x118u) /* VTB/GTB */

1881

#define VMC_STATUS BlockIOTag(0x119u)

1882

#define CAPTURE_DEBUG BlockIOTag(0x119u) /* VTB/GTB */

1883

#define VMC_CMD BlockIOTag(0x11au)

1884

#define VIDEO_SYNC_TEST_B BlockIOTag(0x11au) /* VTB/GTB */

1885

#define VMC_ARG0 BlockIOTag(0x11bu)

1886

#define VMC_ARG1 BlockIOTag(0x11cu)

1887

#define SNAPSHOT_VH_COUNTS BlockIOTag(0x11cu) /* GTPro */

1888

#define VMC_SNOOP_ARG0 BlockIOTag(0x11du)

1889

#define SNAPSHOT_F_COUNT BlockIOTag(0x11du) /* GTPro */

1890

#define VMC_SNOOP_ARG1 BlockIOTag(0x11eu)

1891

#define N_VIF_COUNT BlockIOTag(0x11eu) /* GTPro */

1892

#define SNAPSHOT_VIF_COUNT BlockIOTag(0x11fu) /* GTPro */

1893

#define BUF0_OFFSET BlockIOTag(0x120u)

1894

#define CAPTURE_BUF0_OFFSET BlockIOTag(0x120u) /* VTB/GTB */

1895

#define CAPTURE_BUF1_OFFSET BlockIOTag(0x121u) /* VTB/GTB */

1896

#define ONESHOT_BUF_OFFSET BlockIOTag(0x122u) /* VTB/GTB */

1897

#define BUF0_PITCH BlockIOTag(0x123u)

1898

/* ? BlockIOTag(0x124u) */

1899

/* ? BlockIOTag(0x125u) */

1900

#define BUF1_OFFSET BlockIOTag(0x126u)

1901

/* ? BlockIOTag(0x127u) */

1902

/* ? BlockIOTag(0x128u) */

1903

#define BUF1_PITCH BlockIOTag(0x129u)

1904

/* ? BlockIOTag(0x12au) */

1905

#define BUF0_CAP_ODD_OFFSET BlockIOTag(0x12bu)

1906

#define BUF1_CAP_ODD_OFFSET BlockIOTag(0x12cu)

1907

#define SNAPSHOT2_VH_COUNTS BlockIOTag(0x12cu) /* LTPro */

1908

#define SNAPSHOT2_F_COUNT BlockIOTag(0x12du) /* LTPro */

1909

#define N_VIF2_COUNT BlockIOTag(0x12eu) /* LTPro */

1910

#define SNAPSHOT2_VIF_COUNT BlockIOTag(0x12fu) /* LTPro */

1911

#define VMC_STRM_DATA_0 BlockIOTag(0x130u)

1912

/* MPP_CONFIG BlockIOTag(0x130u) */ /* See 0x3bu */

1913

#define VMC_STRM_DATA_1 BlockIOTag(0x131u)

1914

/* MPP_STROBE_SEQ BlockIOTag(0x131u) */ /* See 0x3cu */

1915

#define VMC_STRM_DATA_2 BlockIOTag(0x132u)

1916

/* MPP_ADDR BlockIOTag(0x132u) */ /* See 0x3du */

1917

#define VMC_STRM_DATA_3 BlockIOTag(0x133u)

1918

/* MPP_DATA BlockIOTag(0x133u) */ /* See 0x3eu */

1919

#define VMC_STRM_DATA_4 BlockIOTag(0x134u)

1920

#define VMC_STRM_DATA_5 BlockIOTag(0x135u)

1921

#define VMC_STRM_DATA_6 BlockIOTag(0x136u)

1922

#define VMC_STRM_DATA_7 BlockIOTag(0x137u)

1923

#define VMC_STRM_DATA_8 BlockIOTag(0x138u)

1924

#define VMC_STRM_DATA_9 BlockIOTag(0x139u)

1925

#define VMC_STRM_DATA_A BlockIOTag(0x13au)

1926

#define VMC_STRM_DATA_B BlockIOTag(0x13bu)

1927

#define VMC_STRM_DATA_C BlockIOTag(0x13cu)

1928

#define VMC_STRM_DATA_D BlockIOTag(0x13du)

1929

#define VMC_STRM_DATA_E BlockIOTag(0x13eu)

1930

#define VMC_STRM_DATA_F BlockIOTag(0x13fu)

1931

/* TVO_CNTL BlockIOTag(0x140u) */ /* See 0x3fu */

1932

/* ? BlockIOTag(0x141u) */

1933

/* ? BlockIOTag(0x142u) */

1934

/* ? BlockIOTag(0x143u) */

1935

/* ? BlockIOTag(0x144u) */

1936

/* ? BlockIOTag(0x145u) */

1937

/* ? BlockIOTag(0x146u) */

1938

/* ? BlockIOTag(0x147u) */

1939

/* ? BlockIOTag(0x148u) */

1940

/* ? BlockIOTag(0x149u) */

1941

/* ? BlockIOTag(0x14au) */

1942

/* ? BlockIOTag(0x14bu) */

1943

/* ? BlockIOTag(0x14cu) */

1944

/* ? BlockIOTag(0x14du) */

1945

/* ? BlockIOTag(0x14eu) */

1946

/* ? BlockIOTag(0x14fu) */

1947

/* ? BlockIOTag(0x150u) */

1948

#define CRT_HORZ_VERT_LOAD BlockIOTag(0x151u) /* VTB/GTB */

1949

#define AGP_BASE BlockIOTag(0x152u) /* GTPro */

1950

#define AGP_CNTL BlockIOTag(0x153u) /* GTPro */

1951

#define AGP_MODE_1X 0x00000001ul

1952

#define AGP_MODE_2X 0x00000002ul

1953

#define AGP_MODE_MASK 0x00000003ul

1954

#define AGP_APER_SIZE_MASK 0x0000003ful

1955

#define AGP_APER_SIZE_4MB 0x0000003ful

1956

#define AGP_APER_SIZE_8MB 0x0000003eul

1957

#define AGP_APER_SIZE_16MB 0x0000003cul

1958

#define AGP_APER_SIZE_32MB 0x00000038ul

1959

#define AGP_APER_SIZE_64MB 0x00000030ul

1960

#define AGP_APER_SIZE_128MB 0x00000020ul

1961

#define AGP_APER_SIZE_256MB 0x00000000ul

1962

#define HIGH_PRIORITY_READ_EN 0x00010000ul

1963

#define AGP_TRDY_MODE 0x00020000ul

1964

#define SCALER_COLOUR_CNTL BlockIOTag(0x154u) /* GTPro */

1965

#define SCALE_BRIGHTNESS 0x0000007ful

1966

/* ? 0x00000080ul */

1967

#define SCALE_SATURATION_U 0x00001f00ul

1968

/* ? 0x0000e000ul */

1969

#define SCALE_SATURATION_V 0x001f0000ul

1970

#define SCALE_VERT_ADJ_UV 0x0fe00000ul

1971

#define SCALE_HORZ_ADJ_UV 0xf0000000ul

1972

#define SCALER_H_COEFF0 BlockIOTag(0x155u) /* GTPro */

1973

#define SCALER_H_COEFF1 BlockIOTag(0x156u) /* GTPro */

1974

#define SCALER_H_COEFF2 BlockIOTag(0x157u) /* GTPro */

1975

#define SCALER_H_COEFF3 BlockIOTag(0x158u) /* GTPro */

1976

#define SCALER_H_COEFF4 BlockIOTag(0x159u) /* GTPro */

1977

/* ? BlockIOTag(0x15au) */

1978

/* ? BlockIOTag(0x15bu) */

1979

#define GUI_CMDFIFO_DEBUG BlockIOTag(0x15cu) /* GT2c/VT4 */

1980

#define GUI_CMDFIFO_DATA BlockIOTag(0x15du) /* GT2c/VT4 */

1981

#define GUI_CNTL BlockIOTag(0x15eu) /* GT2c/VT4 */

1982

#define CMDFIFO_SIZE_MODE 0x00000003ul

1983

/* ? 0x0000fffcul */

1984

#define IDCT_PRSR_MODE 0x00010000ul /* XL/XC */

1985

#define IDCT_BLOCK_GUI_INITIATOR 0x00020000ul /* XL/XC */

1986

/* ? 0xfffc0000ul */

1987

/* ? BlockIOTag(0x15fu) */

1988

#define BM_FRAME_BUF_OFFSET BlockIOTag(0x160u) /* VTB/GTB */

1989

#define BM_SYSTEM_MEM_ADDR BlockIOTag(0x161u) /* VTB/GTB */

1990

#define BM_COMMAND BlockIOTag(0x162u) /* VTB/GTB */

1991

#define BM_STATUS BlockIOTag(0x163u) /* VTB/GTB */

1992

/* ? BlockIOTag(0x164u) */

1993

/* ? BlockIOTag(0x165u) */

1994

/* ? BlockIOTag(0x166u) */

1995

/* ? BlockIOTag(0x167u) */

1996

/* ? BlockIOTag(0x168u) */

1997

/* ? BlockIOTag(0x169u) */

1998

/* ? BlockIOTag(0x16au) */

1999

/* ? BlockIOTag(0x16bu) */

2000

/* ? BlockIOTag(0x16cu) */

2001

/* ? BlockIOTag(0x16du) */

2002

#define BM_GUI_TABLE BlockIOTag(0x16eu) /* VTB/GTB */

2003

#define BM_SYSTEM_TABLE BlockIOTag(0x16fu) /* VTB/GTB */

2004

/* ? BlockIOTag(0x170u) */

2005

/* ? BlockIOTag(0x171u) */

2006

/* ? BlockIOTag(0x172u) */

2007

/* ? BlockIOTag(0x173u) */

2008

/* ? BlockIOTag(0x174u) */

2009

#define SCALER_BUF0_OFFSET_U BlockIOTag(0x175u) /* GTPro */

2010

#define SCALER_BUF0_OFFSET_V BlockIOTag(0x176u) /* GTPro */

2011

#define SCALER_BUF1_OFFSET_U BlockIOTag(0x177u) /* GTPro */

2012

#define SCALER_BUF1_OFFSET_V BlockIOTag(0x178u) /* GTPro */

2013

/* ? BlockIOTag(0x179u) */

2014

/* ? BlockIOTag(0x17au) */

2015

/* ? BlockIOTag(0x17bu) */

2016

/* ? BlockIOTag(0x17cu) */

2017

/* ? BlockIOTag(0x17du) */

2018

/* ? BlockIOTag(0x17eu) */

2019

/* ? BlockIOTag(0x17fu) */

2020

/* ? BlockIOTag(0x180u) */

2021

/* ? BlockIOTag(0x181u) */

2022

/* ? BlockIOTag(0x182u) */

2023

/* ? BlockIOTag(0x183u) */

2024

/* ? BlockIOTag(0x184u) */

2025

/* ? BlockIOTag(0x185u) */

2026

/* ? BlockIOTag(0x186u) */

2027

/* ? BlockIOTag(0x187u) */

2028

/* ? BlockIOTag(0x188u) */

2029

/* ? BlockIOTag(0x189u) */

2030

/* ? BlockIOTag(0x18au) */

2031

/* ? BlockIOTag(0x18bu) */

2032

/* ? BlockIOTag(0x18cu) */

2033

/* ? BlockIOTag(0x18du) */

2034

/* ? BlockIOTag(0x18eu) */

2035

/* ? BlockIOTag(0x18fu) */

2036

#define VERTEX_1_S BlockIOTag(0x190u) /* GTPro */

2037

#define VERTEX_1_T BlockIOTag(0x191u) /* GTPro */

2038

#define VERTEX_1_W BlockIOTag(0x192u) /* GTPro */

2039

#define VERTEX_1_SPEC_ARGB BlockIOTag(0x193u) /* GTPro */

2040

#define VERTEX_1_Z BlockIOTag(0x194u) /* GTPro */

2041

#define VERTEX_1_ARGB BlockIOTag(0x195u) /* GTPro */

2042

#define VERTEX_1_X_Y BlockIOTag(0x196u) /* GTPro */

2043

#define ONE_OVER_AREA BlockIOTag(0x197u) /* GTPro */

2044

#define VERTEX_2_S BlockIOTag(0x198u) /* GTPro */

2045

#define VERTEX_2_T BlockIOTag(0x199u) /* GTPro */

2046

#define VERTEX_2_W BlockIOTag(0x19au) /* GTPro */

2047

#define VERTEX_2_SPEC_ARGB BlockIOTag(0x19bu) /* GTPro */

2048

#define VERTEX_2_Z BlockIOTag(0x19cu) /* GTPro */

2049

#define VERTEX_2_ARGB BlockIOTag(0x19du) /* GTPro */

2050

#define VERTEX_2_X_Y BlockIOTag(0x19eu) /* GTPro */

2051

/* ONE_OVER_AREA BlockIOTag(0x19fu) */ /* Duplicate */

2052

#define VERTEX_3_S BlockIOTag(0x1a0u) /* GTPro */

2053

#define VERTEX_3_T BlockIOTag(0x1a1u) /* GTPro */

2054

#define VERTEX_3_W BlockIOTag(0x1a2u) /* GTPro */

2055

#define VERTEX_3_SPEC_ARGB BlockIOTag(0x1a3u) /* GTPro */

2056

#define VERTEX_3_Z BlockIOTag(0x1a4u) /* GTPro */

2057

#define VERTEX_3_ARGB BlockIOTag(0x1a5u) /* GTPro */

2058

#define VERTEX_3_X_Y BlockIOTag(0x1a6u) /* GTPro */

2059

/* ONE_OVER_AREA BlockIOTag(0x1a7u) */ /* Duplicate */

2060

#define VERTEX_3_SECONDARY_S BlockIOTag(0x1a8u) /* GTPro */

2061

#define VERTEX_3_SECONDARY_T BlockIOTag(0x1a9u) /* GTPro */

2062

#define VERTEX_3_SECONDARY_W BlockIOTag(0x1aau) /* GTPro */

2063

/* VERTEX_1_S BlockIOTag(0x1abu) */ /* Duplicate */

2064

/* VERTEX_1_T BlockIOTag(0x1acu) */ /* Duplicate */

2065

/* VERTEX_1_W BlockIOTag(0x1adu) */ /* Duplicate */

2066

/* VERTEX_2_S BlockIOTag(0x1aeu) */ /* Duplicate */

2067

/* VERTEX_2_T BlockIOTag(0x1afu) */ /* Duplicate */

2068

/* VERTEX_2_W BlockIOTag(0x1b0u) */ /* Duplicate */

2069

/* VERTEX_3_S BlockIOTag(0x1b1u) */ /* Duplicate */

2070

/* VERTEX_3_T BlockIOTag(0x1b2u) */ /* Duplicate */

2071

/* VERTEX_3_W BlockIOTag(0x1b3u) */ /* Duplicate */

2072

/* VERTEX_1_SPEC_ARGB BlockIOTag(0x1b4u) */ /* Duplicate */

2073

/* VERTEX_2_SPEC_ARGB BlockIOTag(0x1b5u) */ /* Duplicate */

2074

/* VERTEX_3_SPEC_ARGB BlockIOTag(0x1b6u) */ /* Duplicate */

2075

/* VERTEX_1_Z BlockIOTag(0x1b7u) */ /* Duplicate */

2076

/* VERTEX_2_Z BlockIOTag(0x1b8u) */ /* Duplicate */

2077

/* VERTEX_3_Z BlockIOTag(0x1b9u) */ /* Duplicate */

2078

/* VERTEX_1_ARGB BlockIOTag(0x1bau) */ /* Duplicate */

2079

/* VERTEX_2_ARGB BlockIOTag(0x1bbu) */ /* Duplicate */

2080

/* VERTEX_3_ARGB BlockIOTag(0x1bcu) */ /* Duplicate */

2081

/* VERTEX_1_X_Y BlockIOTag(0x1bdu) */ /* Duplicate */

2082

/* VERTEX_2_X_Y BlockIOTag(0x1beu) */ /* Duplicate */

2083

/* VERTEX_3_X_Y BlockIOTag(0x1bfu) */ /* Duplicate */

2084

#define ONE_OVER_AREA_UC BlockIOTag(0x1c0u) /* GTPro */

2085

#define SETUP_CNTL BlockIOTag(0x1c1u) /* GTPro */

2086

/* ? BlockIOTag(0x1c2u) */

2087

/* ? BlockIOTag(0x1c3u) */

2088

/* ? BlockIOTag(0x1c4u) */

2089

/* ? BlockIOTag(0x1c5u) */

2090

/* ? BlockIOTag(0x1c6u) */

2091

/* ? BlockIOTag(0x1c7u) */

2092

/* ? BlockIOTag(0x1c8u) */

2093

/* ? BlockIOTag(0x1c9u) */

2094

#define VERTEX_1_SECONDARY_S BlockIOTag(0x1cau) /* GTPro */

2095

#define VERTEX_1_SECONDARY_T BlockIOTag(0x1cbu) /* GTPro */

2096

#define VERTEX_1_SECONDARY_W BlockIOTag(0x1ccu) /* GTPro */

2097

#define VERTEX_2_SECONDARY_S BlockIOTag(0x1cdu) /* GTPro */

2098

#define VERTEX_2_SECONDARY_T BlockIOTag(0x1ceu) /* GTPro */

2099

#define VERTEX_2_SECONDARY_W BlockIOTag(0x1cfu) /* GTPro */

2100

/* ? BlockIOTag(0x1d0u) */

2101

/* ? BlockIOTag(0x1d1u) */

2102

/* ? BlockIOTag(0x1d2u) */

2103

/* ? BlockIOTag(0x1d3u) */

2104

/* ? BlockIOTag(0x1d4u) */

2105

/* ? BlockIOTag(0x1d5u) */

2106

/* ? BlockIOTag(0x1d6u) */

2107

/* ? BlockIOTag(0x1d7u) */

2108

/* ? BlockIOTag(0x1d8u) */

2109

/* ? BlockIOTag(0x1d9u) */

2110

/* ? BlockIOTag(0x1dau) */

2111

/* ? BlockIOTag(0x1dbu) */

2112

/* ? BlockIOTag(0x1dcu) */

2113

/* ? BlockIOTag(0x1ddu) */

2114

/* ? BlockIOTag(0x1deu) */

2115

/* ? BlockIOTag(0x1dfu) */

2116

/* ? BlockIOTag(0x1e0u) */

2117

/* ? BlockIOTag(0x1e1u) */

2118

/* ? BlockIOTag(0x1e2u) */

2119

/* ? BlockIOTag(0x1e3u) */

2120

/* ? BlockIOTag(0x1e4u) */

2121

/* ? BlockIOTag(0x1e5u) */

2122

/* ? BlockIOTag(0x1e6u) */

2123

/* ? BlockIOTag(0x1e7u) */

2124

/* ? BlockIOTag(0x1e8u) */

2125

/* ? BlockIOTag(0x1e9u) */

2126

/* ? BlockIOTag(0x1eau) */

2127

/* ? BlockIOTag(0x1ebu) */

2128

/* ? BlockIOTag(0x1ecu) */

2129

/* ? BlockIOTag(0x1edu) */

2130

/* ? BlockIOTag(0x1eeu) */

2131

/* ? BlockIOTag(0x1efu) */

2132

/* ? BlockIOTag(0x1f0u) */

2133

/* ? BlockIOTag(0x1f1u) */

2134

/* ? BlockIOTag(0x1f2u) */

2135

/* ? BlockIOTag(0x1f3u) */

2136

/* ? BlockIOTag(0x1f4u) */

2137

/* ? BlockIOTag(0x1f5u) */

2138

/* ? BlockIOTag(0x1f6u) */

2139

/* ? BlockIOTag(0x1f7u) */

2140

/* ? BlockIOTag(0x1f8u) */

2141

/* ? BlockIOTag(0x1f9u) */

2142

/* ? BlockIOTag(0x1fau) */

2143

/* ? BlockIOTag(0x1fbu) */

2144

/* ? BlockIOTag(0x1fcu) */

2145

/* ? BlockIOTag(0x1fdu) */

2146

/* ? BlockIOTag(0x1feu) */

2147

/* ? BlockIOTag(0x1ffu) */

2148

2149

/* Definitions for MEM_CNTL's CTL_MEM_?????_APER_ENDIAN fields */

2150

#define CTL_MEM_APER_BYTE_ENDIAN 0x00u

2151

#define CTL_MEM_APER_WORD_ENDIAN 0x01u

2152

#define CTL_MEM_APER_LONG_ENDIAN 0x02u

2153

/* ? 0x03u */

2154

2155

/* Definitions for an ICS2595's programme word */

2156

#define ICS2595_CLOCK 0x000001f0ul

2157

#define ICS2595_FB_DIV 0x0001fe00ul /* Feedback divider */

2158

#define ICS2595_POST_DIV 0x000c0000ul /* Post-divider */

2159

#define ICS2595_STOP 0x00300000ul /* Stop bits */

2160

#define ICS2595_TOGGLE (ICS2595_POST_DIV | ICS2595_STOP)

2161

2162

/* Definitions for internal PLL registers on a 264xT */

2163

#define PLL_MPLL_CNTL 0x00u

2164

#define MPLL_PC_GAIN 0x07u

2165

#define MPLL_VC_GAIN 0x18u

2166

#define MPLL_D_CYC 0x60u

2167

#define MPLL_RANGE 0x80u

2168

#define VPLL_CNTL 0x01u

2169

#define VPLL_PC_GAIN 0x07u

2170

#define VPLL_VC_GAIN 0x18u

2171

#define VPLL_D_CYC 0x60u

2172

#define VPLL_RANGE 0x80u

2173

#define PLL_REF_DIV 0x02u

2174

#define PLL_GEN_CNTL 0x03u

2175

#define PLL_OVERRIDE 0x01u

2176

#define PLL_SLEEP 0x01u /* GTPro */

2177

#define PLL_MCLK_RESET 0x02u

2178

#define PLL_OSC_EN 0x04u

2179

#define PLL_EXT_CLK_EN 0x08u

2180

#define PLL_MCLK_SRC_SEL 0x70u

2181

#define PLL_EXT_CLK_CNTL 0x80u /* CT/ET */

2182

#define PLL_DLL_PWDN 0x80u /* VTB/GTB/LT */

2183

#define PLL_MCLK_FB_DIV 0x04u

2184

#define PLL_VCLK_CNTL 0x05u

2185

#define PLL_VCLK_SRC_SEL 0x03u

2186

#define PLL_VCLK_RESET 0x04u

2187

#define PLL_VCLK_INVERT 0x08u

2188

#define PLL_ECP_DIV 0x30u /* VT/GT */

2189

#define PLL_ERATE_GT_XRATE 0x40u /* VT/GT */

2190

#define PLL_SCALER_LOCK_EN 0x80u /* VT/GT */

2191

#define PLL_VCLK_POST_DIV 0x06u

2192

#define PLL_VCLK0_POST_DIV 0x03u

2193

#define PLL_VCLK1_POST_DIV 0x0cu

2194

#define PLL_VCLK2_POST_DIV 0x30u

2195

#define PLL_VCLK3_POST_DIV 0xc0u

2196

#define PLL_VCLK0_FB_DIV 0x07u

2197

#define PLL_VCLK1_FB_DIV 0x08u

2198

#define PLL_VCLK2_FB_DIV 0x09u

2199

#define PLL_VCLK3_FB_DIV 0x0au

2200

#define PLL_XCLK_CNTL 0x0bu /* VT/GT */

2201

#define PLL_XCLK_MCLK_RATIO 0x03u

2202

#define PLL_XCLK_SRC_SEL 0x07u /* VTB/GTB/LT */

2203

#define PLL_MFB_TIMES_4_2B 0x08u

2204

#define PLL_VCLK0_XDIV 0x10u

2205

#define PLL_VCLK1_XDIV 0x20u

2206

#define PLL_VCLK2_XDIV 0x40u

2207

#define PLL_VCLK3_XDIV 0x80u

2208

#define PLL_FCP_CNTL 0x0cu /* VT/GT */

2209

#define PLL_FCP_POST_DIV 0x0fu

2210

#define PLL_FCP_SRC_SEL 0x70u

2211

#define PLL_DCLK_BY2_EN 0x80u

2212

#define PLL_DLL_CNTL 0x0cu /* VTB/GTB/LT */

2213

#define PLL_DLL_REF_SRC 0x03u

2214

#define PLL_DLL_FB_SRC 0x0cu

2215

#define PLL_DLL_GAIN 0x30u

2216

#define PLL_DLL_RESET 0x40u

2217

#define PLL_DLL_HCLK_OUT_EN 0x80u

2218

#define PLL_VFC_CNTL 0x0du /* VT/GT */

2219

#define PLL_DCLK_INVB 0x01u

2220

#define PLL_DCLKBY2_EN 0x02u

2221

#define PLL_VFC_2PHASE 0x04u

2222

#define PLL_VFC_DELAY 0x18u

2223

#define PLL_VFC_DCLKBY2_SHIFT 0x20u

2224

/* ? 0x40u */

2225

#define PLL_TST_SRC_SEL_BIT5 0x80u /* VTB/GTB/LT */

2226

#define PLL_TEST_CNTL 0x0eu

2227

#define PLL_TST_SRC_SEL 0x1fu

2228

#define PLL_TST_DIVIDERS 0x20u

2229

#define PLL_TST_MASK_READ 0x40u

2230

#define PLL_TST_ANALOG_MON_EN 0x80u

2231

#define PLL_TEST_COUNT 0x0fu

2232

#define PLL_LVDSPLL_CNTL0 0x10u /* LT */

2233

#define PLL_FPDI_NS_TIMING 0x01u

2234

#define PLL_CURR_LEVEL 0x0eu

2235

#define PLL_LVDS_TEST_MODE 0xf0u

2236

#define PLL_LVDSPLL_CNTL1 0x11u /* LT */

2237

#define PLL_LPPL_RANGE 0x01u

2238

#define PLL_LPLL_DUTY 0x06u

2239

#define PLL_LPLL_VC_GAIN 0x18u

2240

#define PLL_LPLL_CP_GAIN 0xe0u

2241

#define PLL_AGP1_CNTL 0x12u /* GTPro */

2242

#define PLL_AGP2_CNTL 0x13u /* GTPro */

2243

#define PLL_DLL2_CNTL 0x14u /* GTPro */

2244

#define PLL_SCLK_FB_DIV 0x15u /* GTPro */

2245

#define PLL_SPLL_CNTL1 0x16u /* GTPro */

2246

#define PLL_SPLL_CNTL2 0x17u /* GTPro */

2247

#define PLL_APLL_STRAPS 0x18u /* GTPro */

2248

#define PLL_EXT_VPLL_CNTL 0x19u /* GTPro */

2249

#define PLL_EXT_VPLL_REF_SRC 0x03u

2250

#define PLL_EXT_VPLL_EN 0x04u

2251

#define PLL_EXT_VPLL_VGA_EN 0x08u

2252

#define PLL_EXT_VPLL_INSYNC 0x10u

2253

/* ? 0x60u */

2254

#define PLL_EXT_V2PLL_EN 0x80u

2255

#define PLL_EXT_VPLL_REF_DIV 0x1au /* GTPro */

2256

#define PLL_EXT_VPLL_FB_DIV 0x1bu /* GTPro */

2257

#define PLL_EXT_VPLL_MSB 0x1cu /* GTPro */

2258

#define PLL_HTOTAL_CNTL 0x1du /* GTPro */

2259

#define PLL_BYTE_CLK_CNTL 0x1eu /* GTPro */

2260

#define PLL_TV_REF_DIV 0x1fu /* LTPro */

2261

#define PLL_TV_FB_DIV 0x20u /* LTPro */

2262

#define PLL_TV_CNTL 0x21u /* LTPro */

2263

#define PLL_TV_GEN_CNTL 0x22u /* LTPro */

2264

#define PLL_V2_CNTL 0x23u /* LTPro */

2265

#define PLL_V2_GEN_CNTL 0x24u /* LTPro */

2266

#define PLL_V2_REF_DIV 0x25u /* LTPro */

2267

#define PLL_V2_FB_DIV 0x26u /* LTPro */

2268

#define PLL_V2_MSB 0x27u /* LTPro */

2269

#define PLL_HTOTAL2_CNTL 0x28u /* LTPro */

2270

#define PLL_YCLK_CNTL 0x29u /* XC/XL */

2271

#define PM_DYN_CLK_CNTL 0x2au /* XC/XL */

2272

/* ? 0x2bu */

2273

/* ? 0x2cu */

2274

/* ? 0x2du */

2275

/* ? 0x2eu */

2276

/* ? 0x2fu */

2277

/* ? 0x30u */

2278

/* ? 0x31u */

2279

/* ? 0x32u */

2280

/* ? 0x33u */

2281

/* ? 0x34u */

2282

/* ? 0x35u */

2283

/* ? 0x36u */

2284

/* ? 0x37u */

2285

/* ? 0x38u */

2286

/* ? 0x39u */

2287

/* ? 0x3au */

2288

/* ? 0x3bu */

2289

/* ? 0x3cu */

2290

/* ? 0x3du */

2291

/* ? 0x3eu */

2292

/* ? 0x3fu */

2293

2294

/* Definitions for an LTPro's 32-bit LCD registers */

2295

#define LCD_CONFIG_PANEL 0x00u /* See LT's CONFIG_PANEL (0x1d) */

2296

#define LCD_GEN_CNTL 0x01u /* See LT's LCD_GEN_CTRL (0x35) */

2297

#define LCD_DSTN_CONTROL 0x02u /* See LT's DSTN_CONTROL (0x1f) */

2298

#define LCD_HFB_PITCH_ADDR 0x03u /* See LT's HFB_PITCH_ADDR (0x2a) */

2299

#define LCD_HORZ_STRETCHING 0x04u /* See LT's HORZ_STRETCHING (0x32) */

2300

#define LCD_VERT_STRETCHING 0x05u /* See LT's VERT_STRETCHING (0x33) */

2301

#define LCD_EXT_VERT_STRETCH 0x06u

2302

#define VERT_STRETCH_RATIO3 0x000003fful

2303

#define FORCE_DAC_DATA 0x000000fful

2304

#define FORCE_DAC_DATA_SEL 0x00000300ul

2305

#define VERT_STRETCH_MODE 0x00000400ul

2306

#define VERT_PANEL_SIZE 0x003ff800ul

2307

#define AUTO_VERT_RATIO 0x00400000ul

2308

#define USE_AUTO_FP_POS 0x00800000ul

2309

#define USE_AUTO_LCD_VSYNC 0x01000000ul

2310

/* ? 0xfe000000ul */

2311

#define LCD_LT_GIO 0x07u /* See LT's LT_GIO (0x2f) */

2312

#define LCD_POWER_MANAGEMENT 0x08u /* See LT's POWER_MANAGEMENT (0x36) */

2313

#define LCD_ZVGPIO 0x09u

2314

#define LCD_ICON_CLR0 0x0au /* Mobility */

2315

#define LCD_ICON_CLR1 0x0bu /* Mobility */

2316

#define LCD_ICON_OFFSET 0x0cu /* Mobility */

2317

#define LCD_ICON_HORZ_VERT_POSN 0x0du /* Mobility */

2318

#define LCD_ICON_HORZ_VERT_OFF 0x0eu /* Mobility */

2319

#define LCD_ICON2_CLR0 0x0fu /* Mobility */

2320

#define LCD_ICON2_CLR1 0x10u /* Mobility */

2321

#define LCD_ICON2_OFFSET 0x11u /* Mobility */

2322

#define LCD_ICON2_HORZ_VERT_POSN 0x12u /* Mobility */

2323

#define LCD_ICON2_HORZ_VERT_OFF 0x13u /* Mobility */

2324

#define LCD_MISC_CNTL 0x14u /* XC/XL */

2325

#define BL_MOD_LEVEL 0x000000fful

2326

#define BIAS_MOD_LEVEL 0x0000ff00ul

2327

#define BLMOD_EN 0x00010000ul

2328

#define BIASMOD_EN 0x00020000ul

2329

/* ? 0x00040000ul */

2330

#define PWRSEQ_MODE 0x00080000ul

2331

#define APC_EN 0x00100000ul

2332

#define MONITOR_DET_EN 0x00200000ul

2333

#define FORCE_DAC_DATA_SEL_X 0x00c00000ul

2334

#define FORCE_DAC_DATA_X 0xff000000ul

2335

#define LCD_TMDS_CNTL 0x15u /* XC/XL */

2336

#define LCD_SCRATCH_PAD_4M 0x15u /* Mobility */

2337

#define LCD_TMDS_SYNC_CHAR_SETA 0x16u /* XC/XL */

2338

#define LCD_SCRATCH_PAD_5M 0x16u /* Mobility */

2339

#define LCD_TMDS_SYNC_CHAR_SETB 0x17u /* XC/XL */

2340

#define LCD_SCRATCH_PAD_6M 0x17u /* Mobility */

2341

#define LCD_TMDS_SRC 0x18u /* XC/XL */

2342

#define LCD_SCRATCH_PAD_7M 0x18u /* Mobility */

2343

#define LCD_PLTSTBLK_CNTL 0x19u /* XC/XL */

2344

#define LCD_SCRATCH_PAD_8M 0x19u /* Mobility */

2345

#define LCD_SYNC_GEN_CNTL 0x1au /* XC/XL */

2346

#define LCD_PATTERN_GEN_SEED 0x1bu /* XC/XL */

2347

#define LCD_APC_CNTL 0x1cu /* XC/XL */

2348

#define LCD_POWER_MANAGEMENT_2 0x1du /* XC/XL */

2349

#define LCD_XCLK_DISP_PM_EN 0x00000001ul

2350

#define LCD_XCLK_DISP2_PM_EN 0x00000002ul /* Mobility */

2351

#define LCD_XCLK_VID_PM_EN 0x00000004ul

2352

#define LCD_XCLK_SCL_PM_EN 0x00000008ul

2353

#define LCD_XCLK_GUI_PM_EN 0x00000010ul

2354

#define LCD_XCLK_SUB_PM_EN 0x00000020ul

2355

/* ? 0x000000c0ul */

2356

#define LCD_MCLK_PM_EN 0x00000100ul

2357

#define LCD_SS_EN 0x00000200ul

2358

#define LCD_BLON_DIGON_EN 0x00000400ul

2359

/* ? 0x00000800ul */

2360

#define LCD_PM_DYN_XCLK_SYNC 0x00003000ul

2361

#define LCD_SEL_W4MS 0x00004000ul

2362

/* ? 0x00008000ul */

2363

#define LCD_PM_DYN_XCLK_EN 0x00010000ul

2364

#define LCD_PM_XCLK_ALWAYS 0x00020000ul

2365

#define LCD_PM_DYN_XCLK_STATUS 0x00040000ul

2366

#define LCD_PCI_ACC_DIS 0x00080000ul

2367

#define LCD_PM_DYN_XCLK_DISP 0x00100000ul

2368

#define LCD_PM_DYN_XCLK_DISP2 0x00200000ul /* Mobility */

2369

#define LCD_PM_DYN_XCLK_VID 0x00400000ul

2370

#define LCD_PM_DYN_XCLK_HFB 0x00800000ul

2371

#define LCD_PM_DYN_XCLK_SCL 0x01000000ul

2372

#define LCD_PM_DYN_XCLK_SUB 0x02000000ul

2373

#define LCD_PM_DYN_XCLK_GUI 0x04000000ul

2374

#define LCD_PM_DYN_XCLK_HOST 0x08000000ul

2375

/* ? 0xf0000000ul */

2376

#define LCD_PRI_ERR_PATTERN 0x1eu /* XC/XL */

2377

#define LCD_CUR_ERR_PATTERN 0x1fu /* XC/XL */

2378

#define LCD_PLTSTBLK_RPT 0x20u /* XC/XL */

2379

#define LCD_SYNC_RPT 0x21u /* XC/XL */

2380

#define LCD_CRC_PATTERN_RPT 0x22u /* XC/XL */

2381

#define LCD_PL_TRANSMITTER_CNTL 0x23u /* XC/XL */

2382

#define LCD_PL_PLL_CNTL 0x24u /* XC/XL */

2383

#define LCD_ALPHA_BLENDING 0x25u /* Mobility */

2384

#define LCD_PORTRAIT_GEN_CNTL 0x26u /* Mobility */

2385

#define LCD_APC_CTRL_IO 0x27u /* Mobility */

2386

#define LCD_TEST_IO 0x28u /* XC/XL */

2387

/* ? 0x29u */

2388

#define LCD_DP1_MEM_ACCESS 0x2au /* XC/XL */

2389

#define LCD_DP0_MEM_ACCESS 0x2bu /* XC/XL */

2390

#define LCD_DP0_DEBUG_A 0x2cu /* XC/XL */

2391

#define LCD_DP0_DEBUG_B 0x2du /* XC/XL */

2392

#define LCD_DP1_DEBUG_A 0x2eu /* XC/XL */

2393

#define LCD_DP1_DEBUG_B 0x2fu /* XC/XL */

2394

#define LCD_DPCTRL_DEBUG_A 0x30u /* XC/XL */

2395

#define LCD_DPCTRL_DEBUG_B 0x31u /* XC/XL */

2396

#define LCD_MEMBLK_DEBUG 0x32u /* XC/XL */

2397

#define LCD_APC_LUT_AB 0x33u /* Mobility */

2398

#define LCD_SCRATCH_PAD_4X 0x33u /* XL/XC */

2399

#define LCD_APC_LUT_CD 0x34u /* Mobility */

2400

#define LCD_SCRATCH_PAD_5X 0x34u /* XL/XC */

2401

#define LCD_APC_LUT_EF 0x35u /* Mobility */

2402

#define LCD_SCRATCH_PAD_6X 0x35u /* XL/XC */

2403

#define LCD_APC_LUT_GH 0x36u /* Mobility */

2404

#define LCD_SCRATCH_PAD_7X 0x36u /* XL/XC */

2405

#define LCD_APC_LUT_IJ 0x37u /* Mobility */

2406

#define LCD_SCRATCH_PAD_8X 0x37u /* XL/XC */

2407

#define LCD_APC_LUT_KL 0x38u /* Mobility */

2408

#define LCD_APC_LUT_MN 0x39u /* Mobility */

2409

#define LCD_APC_LUT_OP 0x3au /* Mobility */

2410

/* ? 0x3bu */

2411

/* ? 0x3cu */

2412

/* ? 0x3du */

2413

/* ? 0x3eu */

2414

/* ? 0x3fu */

2415

2416

/* Definitions for an LTPro's TV registers */

2417

/* ? 0x00u */

2418

/* ? 0x01u */

2419

/* ? 0x02u */

2420

/* ? 0x03u */

2421

/* ? 0x04u */

2422

/* ? 0x05u */

2423

/* ? 0x06u */

2424

/* ? 0x07u */

2425

/* ? 0x08u */

2426

/* ? 0x09u */

2427

/* ? 0x0au */

2428

/* ? 0x0bu */

2429

/* ? 0x0cu */

2430

/* ? 0x0du */

2431

/* ? 0x0eu */

2432

/* ? 0x0fu */

2433

#define TV_MASTER_CNTL 0x10u

2434

/* ? 0x11u */

2435

#define TV_RGB_CNTL 0x12u

2436

/* ? 0x13u */

2437

#define TV_SYNC_CNTL 0x14u

2438

/* ? 0x15u */

2439

/* ? 0x16u */

2440

/* ? 0x17u */

2441

/* ? 0x18u */

2442

/* ? 0x19u */

2443

/* ? 0x1au */

2444

/* ? 0x1bu */

2445

/* ? 0x1cu */

2446

/* ? 0x1du */

2447

/* ? 0x1eu */

2448

/* ? 0x1fu */

2449

#define TV_HTOTAL 0x20u

2450

#define TV_HDISP 0x21u

2451

#define TV_HSIZE 0x22u

2452

#define TV_HSTART 0x23u

2453

#define TV_HCOUNT 0x24u

2454

#define TV_VTOTAL 0x25u

2455

#define TV_VDISP 0x26u

2456

#define TV_VCOUNT 0x27u

2457

#define TV_FTOTAL 0x28u

2458

#define TV_FCOUNT 0x29u

2459

#define TV_FRESTART 0x2au

2460

#define TV_HRESTART 0x2bu

2461

#define TV_VRESTART 0x2cu

2462

/* ? 0x2du */

2463

/* ? 0x2eu */

2464

/* ? 0x2fu */

2465

/* ? 0x30u */

2466

/* ? 0x31u */

2467

/* ? 0x32u */

2468

/* ? 0x33u */

2469

/* ? 0x34u */

2470

/* ? 0x35u */

2471

/* ? 0x36u */

2472

/* ? 0x37u */

2473

/* ? 0x38u */

2474

/* ? 0x39u */

2475

/* ? 0x3au */

2476

/* ? 0x3bu */

2477

/* ? 0x3cu */

2478

/* ? 0x3du */

2479

/* ? 0x3eu */

2480

/* ? 0x3fu */

2481

/* ? 0x40u */

2482

/* ? 0x41u */

2483

/* ? 0x42u */

2484

/* ? 0x43u */

2485

/* ? 0x44u */

2486

/* ? 0x45u */

2487

/* ? 0x46u */

2488

/* ? 0x47u */

2489

/* ? 0x48u */

2490

/* ? 0x49u */

2491

/* ? 0x4au */

2492

/* ? 0x4bu */

2493

/* ? 0x4cu */

2494

/* ? 0x4du */

2495

/* ? 0x4eu */

2496

/* ? 0x4fu */

2497

/* ? 0x50u */

2498

/* ? 0x51u */

2499

/* ? 0x52u */

2500

/* ? 0x53u */

2501

/* ? 0x54u */

2502

/* ? 0x55u */

2503

/* ? 0x56u */

2504

/* ? 0x57u */

2505

/* ? 0x58u */

2506

/* ? 0x59u */

2507

/* ? 0x5au */

2508

/* ? 0x5bu */

2509

/* ? 0x5cu */

2510

/* ? 0x5du */

2511

/* ? 0x5eu */

2512

/* ? 0x5fu */

2513

#define TV_HOST_READ_DATA 0x60u

2514

#define TV_HOST_WRITE_DATA 0x61u

2515

#define TV_HOST_RD_WT_CNTL 0x62u

2516

/* ? 0x63u */

2517

/* ? 0x64u */

2518

/* ? 0x65u */

2519

/* ? 0x66u */

2520

/* ? 0x67u */

2521

/* ? 0x68u */

2522

/* ? 0x69u */

2523

/* ? 0x6au */

2524

/* ? 0x6bu */

2525

/* ? 0x6cu */

2526

/* ? 0x6du */

2527

/* ? 0x6eu */

2528

/* ? 0x6fu */

2529

#define TV_VSCALER_CNTL 0x70u

2530

#define TV_TIMING_CNTL 0x71u

2531

#define TV_GAMMA_CNTL 0x72u

2532

#define TV_Y_FALL_CNTL 0x73u

2533

#define TV_Y_RISE_CNTL 0x74u

2534

#define TV_Y_SAW_TOOTH_CNTL 0x75u

2535

/* ? 0x76u */

2536

/* ? 0x77u */

2537

/* ? 0x78u */

2538

/* ? 0x79u */

2539

/* ? 0x7au */

2540

/* ? 0x7bu */

2541

/* ? 0x7cu */

2542

/* ? 0x7du */

2543

/* ? 0x7eu */

2544

/* ? 0x7fu */

2545

#define TV_MODULATOR_CNTL1 0x80u

2546

#define TV_MODULATOR_CNTL2 0x81u

2547

/* ? 0x82u */

2548

/* ? 0x83u */

2549

/* ? 0x84u */

2550

/* ? 0x85u */

2551

/* ? 0x86u */

2552

/* ? 0x87u */

2553

/* ? 0x88u */

2554

/* ? 0x89u */

2555

/* ? 0x8au */

2556

/* ? 0x8bu */

2557

/* ? 0x8cu */

2558

/* ? 0x8du */

2559

/* ? 0x8eu */

2560

/* ? 0x8fu */

2561

#define TV_PRE_DAC_MUX_CNTL 0x90u

2562

/* ? 0x91u */

2563

/* ? 0x92u */

2564

/* ? 0x93u */

2565

/* ? 0x94u */

2566

/* ? 0x95u */

2567

/* ? 0x96u */

2568

/* ? 0x97u */

2569

/* ? 0x98u */

2570

/* ? 0x99u */

2571

/* ? 0x9au */

2572

/* ? 0x9bu */

2573

/* ? 0x9cu */

2574

/* ? 0x9du */

2575

/* ? 0x9eu */

2576

/* ? 0x9fu */

2577

#define TV_DAC_CNTL 0xa0u

2578

/* ? 0xa1u */

2579

/* ? 0xa2u */

2580

/* ? 0xa3u */

2581

/* ? 0xa4u */

2582

/* ? 0xa5u */

2583

/* ? 0xa6u */

2584

/* ? 0xa7u */

2585

/* ? 0xa8u */

2586

/* ? 0xa9u */

2587

/* ? 0xaau */

2588

/* ? 0xabu */

2589

/* ? 0xacu */

2590

/* ? 0xadu */

2591

/* ? 0xaeu */

2592

/* ? 0xafu */

2593

#define TV_CRC_CNTL 0xb0u

2594

#define TV_VIDEO_PORT_SIG 0xb1u

2595

/* ? 0xb2u */

2596

/* ? 0xb3u */

2597

/* ? 0xb4u */

2598

/* ? 0xb5u */

2599

/* ? 0xb6u */

2600

/* ? 0xb7u */

2601

#define TV_VBI_CC_CNTL 0xb8u

2602

#define TV_VBI_EDS_CNTL 0xb9u

2603

#define TV_VBI_20BIT_CNTL 0xbau

2604

/* ? 0xbbu */

2605

/* ? 0xbcu */

2606

#define TV_VBI_DTO_CNTL 0xbdu

2607

#define TV_VBI_LEVEL_CNTL 0xbeu

2608

/* ? 0xbfu */

2609

#define TV_UV_ADR 0xc0u

2610

#define TV_FIFO_TEST_CNTL 0xc1u

2611

/* ? 0xc2u */

2612

/* ? 0xc3u */

2613

/* ? 0xc4u */

2614

/* ? 0xc5u */

2615

/* ? 0xc6u */

2616

/* ? 0xc7u */

2617

/* ? 0xc8u */

2618

/* ? 0xc9u */

2619

/* ? 0xcau */

2620

/* ? 0xcbu */

2621

/* ? 0xccu */

2622

/* ? 0xcdu */

2623

/* ? 0xceu */

2624

/* ? 0xcfu */

2625

/* ? 0xd0u */

2626

/* ? 0xd1u */

2627

/* ? 0xd2u */

2628

/* ? 0xd3u */

2629

/* ? 0xd4u */

2630

/* ? 0xd5u */

2631

/* ? 0xd6u */

2632

/* ? 0xd7u */

2633

/* ? 0xd8u */

2634

/* ? 0xd9u */

2635

/* ? 0xdau */

2636

/* ? 0xdbu */

2637

/* ? 0xdcu */

2638

/* ? 0xddu */

2639

/* ? 0xdeu */

2640

/* ? 0xdfu */

2641

/* ? 0xe0u */

2642

/* ? 0xe1u */

2643

/* ? 0xe2u */

2644

/* ? 0xe3u */

2645

/* ? 0xe4u */

2646

/* ? 0xe5u */

2647

/* ? 0xe6u */

2648

/* ? 0xe7u */

2649

/* ? 0xe8u */

2650

/* ? 0xe9u */

2651

/* ? 0xeau */

2652

/* ? 0xebu */

2653

/* ? 0xecu */

2654

/* ? 0xedu */

2655

/* ? 0xeeu */

2656

/* ? 0xefu */

2657

/* ? 0xf0u */

2658

/* ? 0xf1u */

2659

/* ? 0xf2u */

2660

/* ? 0xf3u */

2661

/* ? 0xf4u */

2662

/* ? 0xf5u */

2663

/* ? 0xf6u */

2664

/* ? 0xf7u */

2665

/* ? 0xf8u */

2666

/* ? 0xf9u */

2667

/* ? 0xfau */

2668

/* ? 0xfbu */

2669

/* ? 0xfcu */

2670

/* ? 0xfdu */

2671

/* ? 0xfeu */

2672

/* ? 0xffu */

2673

2674

/* Some ImpacTV definitions */

2675

#define IT_SDA_GET 0x40u

2676

#define IT_SDA_SET 0x20u

2677

#define IT_SDA_DIR 0x10u

2678

#define IT_SCL_GET 0x04u

2679

#define IT_SCL_SET 0x02u

2680

#define IT_SCL_DIR 0x01u

2681

2682

#define IT_I2C_CNTL 0x0015u

2683

2684

/* Miscellaneous */

2685

2686

/* Current X, Y & Dest X, Y mask */

2687

#define COORD_MASK 0x07ffu

2688

2689

/* Pixel widths */

2690

#define PIX_WIDTH_1BPP 0x00u

2691

#define PIX_WIDTH_4BPP 0x01u /* CRTC2: 8bpp */

2692

#define PIX_WIDTH_8BPP 0x02u /* CRTC2: Undefined */

2693

#define PIX_WIDTH_15BPP 0x03u

2694

#define PIX_WIDTH_16BPP 0x04u

2695

#define PIX_WIDTH_24BPP 0x05u

2696

#define PIX_WIDTH_32BPP 0x06u

2697

#define PIX_WIDTH_YUV422 0x07u /* CRTC2 only */

2698

2699

/* Source definitions */

2700

#define SRC_BKGD 0x00u

2701

#define SRC_FRGD 0x01u

2702

#define SRC_HOST 0x02u

2703

#define SRC_BLIT 0x03u

2704

#define SRC_PATTERN 0x04u

2705

#define SRC_SCALER_3D 0x05u

2706

/* ? 0x06u */

2707

/* ? 0x07u */

2708

2709

/* The Mixes */

2710

#define MIX_MASK 0x001fu

2711

2712

#define MIX_NOT_DST 0x0000u

2713

#define MIX_0 0x0001u

2714

#define MIX_1 0x0002u

2715

#define MIX_DST 0x0003u

2716

#define MIX_NOT_SRC 0x0004u

2717

#define MIX_XOR 0x0005u

2718

#define MIX_XNOR 0x0006u

2719

#define MIX_SRC 0x0007u

2720

#define MIX_NAND 0x0008u

2721

#define MIX_NOT_SRC_OR_DST 0x0009u

2722

#define MIX_SRC_OR_NOT_DST 0x000au

2723

#define MIX_OR 0x000bu

2724

#define MIX_AND 0x000cu

2725

#define MIX_SRC_AND_NOT_DST 0x000du

2726

#define MIX_NOT_SRC_AND_DST 0x000eu

2727

#define MIX_NOR 0x000fu

2728

2729

#define MIX_MIN 0x0010u

2730

#define MIX_DST_MINUS_SRC 0x0011u

2731

#define MIX_SRC_MINUS_DST 0x0012u

2732

#define MIX_PLUS 0x0013u

2733

#define MIX_MAX 0x0014u

2734

#define MIX_HALF__DST_MINUS_SRC 0x0015u

2735

#define MIX_HALF__SRC_MINUS_DST 0x0016u

2736

#define MIX_AVERAGE 0x0017u

2737

#define MIX_DST_MINUS_SRC_SAT 0x0018u

2738

#define MIX_SRC_MINUS_DST_SAT 0x001au

2739

#define MIX_HALF__DST_MINUS_SRC_SAT 0x001cu

2740

#define MIX_HALF__SRC_MINUS_DST_SAT 0x001eu

2741

#define MIX_AVERAGE_SAT 0x001fu

2742

#define MIX_FN_PAINT MIX_SRC

2743

2744

/* Video/Graphics mix functions for overlay */

2745

#define OVERLAY_MIX_FALSE 0x00u

2746

#define OVERLAY_MIX_TRUE 0x01u

2747

/* ? 0x02u */

2748

/* ? 0x03u */

2749

#define OVERLAY_MIX_NOT_EQUAL 0x04u

2750

#define OVERLAY_MIX_EQUAL 0x05u

2751

/* ? 0x06u */

2752

/* ? 0x07u */

2753

2754

/* 3D Engine for render acceleration (from Mach64 DRI driver) */

2755

2756

/* SCALE_3D_CNTL */

2757

#define MACH64_SCALE_PIX_EXPAND_ZERO_EXTEND (0 << 0)

2758

#define MACH64_SCALE_PIX_EXPAND_DYNAMIC_RANGE (1 << 0)

2759

#define MACH64_SCALE_DITHER_ERROR_DIFFUSE (0 << 1)

2760

#define MACH64_SCALE_DITHER_2D_TABLE (1 << 1)

2761

#define MACH64_DITHER_EN (1 << 2)

2762

#define MACH64_DITHER_INIT_CURRENT (O << 3)

2763

#define MACH64_DITHER_INIT_RESET (1 << 3)

2764

#define MACH64_ROUND_EN (1 << 4)

2765

2766

#define MACH64_TEX_CACHE_DIS (1 << 5)

2767

2768

#define MACH64_SCALE_3D_FCN_MASK (3 << 6)

2769

#define MACH64_SCALE_3D_FCN_NOP (0 << 6)

2770

#define MACH64_SCALE_3D_FCN_SCALE (1 << 6)

2771

#define MACH64_SCALE_3D_FCN_TEXTURE (2 << 6)

2772

#define MACH64_SCALE_3D_FCN_SHADE (3 << 6)

2773

#define MACH64_TEXTURE_DISABLE (1 << 6)

2774

2775

#define MACH64_EDGE_ANTI_ALIAS (1 << 8)

2776

#define MACH64_TEX_CACHE_SPLIT (1 << 9)

2777

#define MACH64_APPLE_YUV_MODE (1 << 10)

2778

2779

#define MACH64_ALPHA_FOG_EN_MASK (3 << 11)

2780

#define MACH64_ALPHA_FOG_DIS (0 << 11)

2781

#define MACH64_ALPHA_FOG_EN_ALPHA (1 << 11)

2782

#define MACH64_ALPHA_FOG_EN_FOG (2 << 11)

2783

2784

#define MACH64_ALPHA_BLEND_SAT (1 << 13)

2785

#define MACH64_RED_DITHER_MAX (1 << 14)

2786

#define MACH64_SIGNED_DST_CLAMP (1 << 15)

2787

2788

#define MACH64_ALPHA_BLEND_SRC_MASK (7 << 16)

2789

#define MACH64_ALPHA_BLEND_SRC_ZERO (0 << 16)

2790

#define MACH64_ALPHA_BLEND_SRC_ONE (1 << 16)

2791

#define MACH64_ALPHA_BLEND_SRC_DSTCOLOR (2 << 16)

2792

#define MACH64_ALPHA_BLEND_SRC_INVDSTCOLOR (3 << 16)

2793

#define MACH64_ALPHA_BLEND_SRC_SRCALPHA (4 << 16)

2794

#define MACH64_ALPHA_BLEND_SRC_INVSRCALPHA (5 << 16)

2795

#define MACH64_ALPHA_BLEND_SRC_DSTALPHA (6 << 16)

2796

#define MACH64_ALPHA_BLEND_SRC_INVDSTALPHA (7 << 16)

2797

#define MACH64_ALPHA_BLEND_DST_MASK (7 << 19)

2798

#define MACH64_ALPHA_BLEND_DST_ZERO (0 << 19)

2799

#define MACH64_ALPHA_BLEND_DST_ONE (1 << 19)

2800

#define MACH64_ALPHA_BLEND_DST_SRCCOLOR (2 << 19)

2801

#define MACH64_ALPHA_BLEND_DST_INVSRCCOLOR (3 << 19)

2802

#define MACH64_ALPHA_BLEND_DST_SRCALPHA (4 << 19)

2803

#define MACH64_ALPHA_BLEND_DST_INVSRCALPHA (5 << 19)

2804

#define MACH64_ALPHA_BLEND_DST_DSTALPHA (6 << 19)

2805

#define MACH64_ALPHA_BLEND_DST_INVDSTALPHA (7 << 19)

2806

2807

#define MACH64_TEX_LIGHT_FCN_MASK (3 << 22)

2808

#define MACH64_TEX_LIGHT_FCN_REPLACE (0 << 22)

2809

#define MACH64_TEX_LIGHT_FCN_MODULATE (1 << 22)

2810

#define MACH64_TEX_LIGHT_FCN_ALPHA_DECAL (2 << 22)

2811

2812

#define MACH64_MIP_MAP_DISABLE (1 << 24)

2813

2814

#define MACH64_BILINEAR_TEX_EN (1 << 25)

2815

#define MACH64_TEX_BLEND_FCN_MASK (3 << 26)

2816

#define MACH64_TEX_BLEND_FCN_NEAREST (0 << 26)

2817

#define MACH64_TEX_BLEND_FCN_LINEAR (2 << 26)

2818

#define MACH64_TEX_BLEND_FCN_TRILINEAR (3 << 26)

2819

2820

#define MACH64_TEX_AMASK_AEN (1 << 28)

2821

#define MACH64_TEX_AMASK_BLEND_EDGE (1 << 29)

2822

#define MACH64_TEX_MAP_AEN (1 << 30)

2823

#define MACH64_SRC_3D_HOST_FIFO (1 << 31)

2824

2825

/* TEX_CNTL */

2826

#define MACH64_LOD_BIAS_SHIFT 0

2827

#define MACH64_LOD_BIAS_MASK (0xf << 0)

2828

#define MACH64_COMP_FACTOR_SHIFT 4

2829

#define MACH64_COMP_FACTOR_MASK (0xf << 4)

2830

2831

#define MACH64_TEXTURE_COMPOSITE (1 << 8)

2832

2833

#define MACH64_COMP_COMBINE_BLEND (0 << 9)

2834

#define MACH64_COMP_COMBINE_MODULATE (1 << 9)

2835

#define MACH64_COMP_BLEND_NEAREST (0 << 11)

2836

#define MACH64_COMP_BLEND_BILINEAR (1 << 11)

2837

#define MACH64_COMP_FILTER_NEAREST (0 << 12)

2838

#define MACH64_COMP_FILTER_BILINEAR (1 << 12)

2839

#define MACH64_COMP_ALPHA (1 << 13)

2840

2841

#define MACH64_TEXTURE_TILING (1 << 14)

2842

#define MACH64_COMPOSITE_TEX_TILING (1 << 15)

2843

#define MACH64_TEX_COLLISION_DISABLE (1 << 16)

2844

2845

#define MACH64_TEXTURE_CLAMP_S (1 << 17)

2846

#define MACH64_TEXTURE_CLAMP_T (1 << 18)

2847

#define MACH64_TEX_ST_MULT_W (0 << 19)

2848

#define MACH64_TEX_ST_DIRECT (1 << 19)

2849

#define MACH64_TEX_SRC_LOCAL (0 << 20)

2850

#define MACH64_TEX_SRC_AGP (1 << 20)

2851

#define MACH64_TEX_UNCOMPRESSED (0 << 21)

2852

#define MACH64_TEX_VQ_COMPRESSED (1 << 21)

2853

#define MACH64_COMP_TEX_UNCOMPRESSED (0 << 22)

2854

#define MACH64_COMP_TEX_VQ_COMPRESSED (1 << 22)

2855

#define MACH64_TEX_CACHE_FLUSH (1 << 23)

2856

#define MACH64_SEC_TEX_CLAMP_S (1 << 24)

2857

#define MACH64_SEC_TEX_CLAMP_T (1 << 25)

2858

#define MACH64_TEX_WRAP_S (1 << 28)

2859

#define MACH64_TEX_WRAP_T (1 << 29)

2860

#define MACH64_TEX_CACHE_SIZE_4K (1 << 30)

2861

#define MACH64_TEX_CACHE_SIZE_2K (1 << 30)

2862

#define MACH64_SECONDARY_STW (1 << 31)

2863

2864

/* DP_PIX_WIDTH (superset of PIX_WIDTH_?BPP) */

2865

#define MACH64_DATATYPE_CI8 2

2866

#define MACH64_DATATYPE_ARGB1555 3

2867

#define MACH64_DATATYPE_RGB565 4

2868

#define MACH64_DATATYPE_ARGB8888 6

2869

#define MACH64_DATATYPE_RGB332 7

2870

#define MACH64_DATATYPE_Y8 8

2871

#define MACH64_DATATYPE_RGB8 9

2872

#define MACH64_DATATYPE_VYUY422 11

2873

#define MACH64_DATATYPE_YVYU422 12

2874

#define MACH64_DATATYPE_AYUV444 14

2875

#define MACH64_DATATYPE_ARGB4444 15

2876

2877

/* Extract texture level from TEX_SIZE_PITCH and shift appropriately for

2878

* addition to TEX_0_OFF.

2879

*/

2880

#define TEX_LEVEL(_tex_size_pitch) (((_tex_size_pitch) & 0xf0) >> 2)

2881

2882

#endif /* ___ATIREGS_H___ */