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- Committer: Bazaar Package Importer
- Author(s): Matthias Klose
- Date: 2011-03-15 16:14:08 UTC
- Revision ID: james.westby@ubuntu.com-20110315161408-o3sk4typcfgzuiqb
Tags: 7.2-1ubuntu10
* Update with changes from the Linaro 7.2-2011.03-0 release (Ulrich Weigand).
* Configure with --with-pkgversion, don't run post-patches.
* Configure with --with-pkgversion, don't run post-patches.
- files added:
- .pc/linaro-gdb.patch
- .pc/linaro-gdb.patch/gdb
- .pc/linaro-gdb.patch/gdb/features
- .pc/linaro-gdb.patch/gdb/testsuite
- .pc/linaro-gdb.patch/gdb/testsuite/gdb.asm
- .pc/linaro-gdb.patch/gdb/testsuite/gdb.base
- .pc/linaro-gdb.patch/gdb/testsuite/gdb.dwarf2
- .pc/linaro-gdb.patch/gdb/testsuite/gdb.python
- .pc/linaro-gdb.patch/gdb/testsuite/gdb.threads
- .pc/linaro-gdb.patch/gdb/testsuite/gdb.xml
- .pc/linaro-gdb.patch/gdb/testsuite/lib
- .pc/linaro-gdb.patch/libiberty
- debian/gdb-mutliarch
- debian/gdb-mutliarch/usr
- debian/gdb-mutliarch/usr/share
- debian/gdb-mutliarch/usr/share/man
- debian/gdb-mutliarch/usr/share/man/man1
- debian/gdb-mutliarch/usr/share/man/man1/gdb64.1.gz
- files modified:
- .pc/applied-patches
added
removed
gdb/arm-tdep.c
29
29
#include "gdb_string.h"
30
30
#include "dis-asm.h" /* For register styles. */
31
31
#include "regcache.h"
32
#include "reggroups.h"
32
33
#include "doublest.h"
33
34
#include "value.h"
34
35
#include "arch-utils.h"
42
43
#include "prologue-value.h"
43
44
#include "target-descriptions.h"
44
45
#include "user-regs.h"
46
#include "observer.h"
45
47
46
48
#include "arm-tdep.h"
47
49
#include "gdb/sim-arm.h"
346
348
function. This function should be called for addresses unrelated to
347
349
any executing frame; otherwise, prefer arm_frame_is_thumb. */
348
350
349
static int
351
int
350
352
arm_pc_is_thumb (CORE_ADDR memaddr)
351
353
{
352
354
struct obj_section *sec;
430
432
}
431
433
432
434
/* Return 1 if PC is the start of a compiler helper function which
433
can be safely ignored during prologue skipping. */
435
can be safely ignored during prologue skipping. IS_THUMB is true
436
if the function is known to be a Thumb function due to the way it
437
is being called. */
434
438
static int
435
skip_prologue_function (CORE_ADDR pc)
439
skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
436
440
{
441
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
437
442
struct minimal_symbol *msym;
438
const char *name;
439
443
440
444
msym = lookup_minimal_symbol_by_pc (pc);
441
if (msym == NULL || SYMBOL_VALUE_ADDRESS (msym) != pc)
442
return 0;
443
444
name = SYMBOL_LINKAGE_NAME (msym);
445
if (name == NULL)
446
return 0;
447
448
/* The GNU linker's Thumb call stub to foo is named
449
__foo_from_thumb. */
450
if (strstr (name, "_from_thumb") != NULL)
451
name += 2;
452
453
/* On soft-float targets, __truncdfsf2 is called to convert promoted
454
arguments to their argument types in non-prototyped
455
functions. */
456
if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
457
return 1;
458
if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
459
return 1;
445
if (msym != NULL
446
&& SYMBOL_VALUE_ADDRESS (msym) == pc
447
&& SYMBOL_LINKAGE_NAME (msym) != NULL)
448
{
449
const char *name = SYMBOL_LINKAGE_NAME (msym);
450
451
/* The GNU linker's Thumb call stub to foo is named
452
__foo_from_thumb. */
453
if (strstr (name, "_from_thumb") != NULL)
454
name += 2;
455
456
/* On soft-float targets, __truncdfsf2 is called to convert promoted
457
arguments to their argument types in non-prototyped
458
functions. */
459
if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
460
return 1;
461
if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
462
return 1;
463
464
/* Internal functions related to thread-local storage. */
465
if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
466
return 1;
467
if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
468
return 1;
469
}
470
else
471
{
472
/* If we run against a stripped glibc, we may be unable to identify
473
special functions by name. Check for one important case,
474
__aeabi_read_tp, by comparing the *code* against the default
475
implementation (this is hand-written ARM assembler in glibc). */
476
477
if (!is_thumb
478
&& read_memory_unsigned_integer (pc, 4, byte_order_for_code)
479
== 0xe3e00a0f /* mov r0, #0xffff0fff */
480
&& read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
481
== 0xe240f01f) /* sub pc, r0, #31 */
482
return 1;
483
}
460
484
461
485
return 0;
462
486
}
470
494
#define BranchDest(addr,instr) \
471
495
((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
472
496
497
/* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
498
the first 16-bit of instruction, and INSN2 is the second 16-bit of
499
instruction. */
500
#define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
501
((bits ((insn1), 0, 3) << 12) \
502
| (bits ((insn1), 10, 10) << 11) \
503
| (bits ((insn2), 12, 14) << 8) \
504
| bits ((insn2), 0, 7))
505
506
/* Extract the immediate from instruction movw/movt of encoding A. INSN is
507
the 32-bit instruction. */
508
#define EXTRACT_MOVW_MOVT_IMM_A(insn) \
509
((bits ((insn), 16, 19) << 12) \
510
| bits ((insn), 0, 11))
511
512
/* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
513
514
static unsigned int
515
thumb_expand_immediate (unsigned int imm)
516
{
517
unsigned int count = imm >> 7;
518
519
if (count < 8)
520
switch (count / 2)
521
{
522
case 0:
523
return imm & 0xff;
524
case 1:
525
return (imm & 0xff) | ((imm & 0xff) << 16);
526
case 2:
527
return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
528
case 3:
529
return (imm & 0xff) | ((imm & 0xff) << 8)
530
| ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
531
}
532
533
return (0x80 | (imm & 0x7f)) << (32 - count);
534
}
535
536
/* Return 1 if the 16-bit Thumb instruction INST might change
537
control flow, 0 otherwise. */
538
539
static int
540
thumb_instruction_changes_pc (unsigned short inst)
541
{
542
if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
543
return 1;
544
545
if ((inst & 0xf000) == 0xd000) /* conditional branch */
546
return 1;
547
548
if ((inst & 0xf800) == 0xe000) /* unconditional branch */
549
return 1;
550
551
if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
552
return 1;
553
554
if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
555
return 1;
556
557
if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
558
return 1;
559
560
return 0;
561
}
562
563
/* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
564
might change control flow, 0 otherwise. */
565
566
static int
567
thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
568
{
569
if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
570
{
571
/* Branches and miscellaneous control instructions. */
572
573
if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
574
{
575
/* B, BL, BLX. */
576
return 1;
577
}
578
else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
579
{
580
/* SUBS PC, LR, #imm8. */
581
return 1;
582
}
583
else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
584
{
585
/* Conditional branch. */
586
return 1;
587
}
588
589
return 0;
590
}
591
592
if ((inst1 & 0xfe50) == 0xe810)
593
{
594
/* Load multiple or RFE. */
595
596
if (bit (inst1, 7) && !bit (inst1, 8))
597
{
598
/* LDMIA or POP */
599
if (bit (inst2, 15))
600
return 1;
601
}
602
else if (!bit (inst1, 7) && bit (inst1, 8))
603
{
604
/* LDMDB */
605
if (bit (inst2, 15))
606
return 1;
607
}
608
else if (bit (inst1, 7) && bit (inst1, 8))
609
{
610
/* RFEIA */
611
return 1;
612
}
613
else if (!bit (inst1, 7) && !bit (inst1, 8))
614
{
615
/* RFEDB */
616
return 1;
617
}
618
619
return 0;
620
}
621
622
if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
623
{
624
/* MOV PC or MOVS PC. */
625
return 1;
626
}
627
628
if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
629
{
630
/* LDR PC. */
631
if (bits (inst1, 0, 3) == 15)
632
return 1;
633
if (bit (inst1, 7))
634
return 1;
635
if (bit (inst2, 11))
636
return 1;
637
if ((inst2 & 0x0fc0) == 0x0000)
638
return 1;
639
640
return 0;
641
}
642
643
if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
644
{
645
/* TBB. */
646
return 1;
647
}
648
649
if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
650
{
651
/* TBH. */
652
return 1;
653
}
654
655
return 0;
656
}
657
473
658
/* Analyze a Thumb prologue, looking for a recognizable stack frame
474
659
and frame pointer. Scan until we encounter a store that could
475
660
clobber the stack frame unexpectedly, or an unknown instruction.
488
673
struct pv_area *stack;
489
674
struct cleanup *back_to;
490
675
CORE_ADDR offset;
676
CORE_ADDR unrecognized_pc = 0;
491
677
492
678
for (i = 0; i < 16; i++)
493
679
regs[i] = pv_register (i, 0);
625
811
constant = read_memory_unsigned_integer (loc, 4, byte_order);
626
812
regs[bits (insn, 8, 10)] = pv_constant (constant);
627
813
}
628
else if ((insn & 0xe000) == 0xe000 && cache == NULL)
814
else if ((insn & 0xe000) == 0xe000)
629
815
{
630
/* Only recognize 32-bit instructions for prologue skipping. */
631
816
unsigned short inst2;
632
817
633
818
inst2 = read_memory_unsigned_integer (start + 2, 2,
654
839
if (bit (inst2, 12) == 0)
655
840
nextpc = nextpc & 0xfffffffc;
656
841
657
if (!skip_prologue_function (nextpc))
658
break;
659
}
660
else if ((insn & 0xfe50) == 0xe800 /* stm{db,ia} Rn[!], { registers } */
661
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
662
;
663
else if ((insn & 0xfe50) == 0xe840 /* strd Rt, Rt2, [Rn, #imm] */
664
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
665
;
842
if (!skip_prologue_function (gdbarch, nextpc,
843
bit (inst2, 12) != 0))
844
break;
845
}
846
847
else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, { registers } */
848
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
849
{
850
pv_t addr = regs[bits (insn, 0, 3)];
851
int regno;
852
853
if (pv_area_store_would_trash (stack, addr))
854
break;
855
856
/* Calculate offsets of saved registers. */
857
for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
858
if (inst2 & (1 << regno))
859
{
860
addr = pv_add_constant (addr, -4);
861
pv_area_store (stack, addr, 4, regs[regno]);
862
}
863
864
if (insn & 0x0020)
865
regs[bits (insn, 0, 3)] = addr;
866
}
867
868
else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, [Rn, #+/-imm]{!} */
869
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
870
{
871
int regno1 = bits (inst2, 12, 15);
872
int regno2 = bits (inst2, 8, 11);
873
pv_t addr = regs[bits (insn, 0, 3)];
874
875
offset = inst2 & 0xff;
876
if (insn & 0x0080)
877
addr = pv_add_constant (addr, offset);
878
else
879
addr = pv_add_constant (addr, -offset);
880
881
if (pv_area_store_would_trash (stack, addr))
882
break;
883
884
pv_area_store (stack, addr, 4, regs[regno1]);
885
pv_area_store (stack, pv_add_constant (addr, 4),
886
4, regs[regno2]);
887
888
if (insn & 0x0020)
889
regs[bits (insn, 0, 3)] = addr;
890
}
891
892
else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
893
&& (inst2 & 0x0c00) == 0x0c00
894
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
895
{
896
int regno = bits (inst2, 12, 15);
897
pv_t addr = regs[bits (insn, 0, 3)];
898
899
offset = inst2 & 0xff;
900
if (inst2 & 0x0200)
901
addr = pv_add_constant (addr, offset);
902
else
903
addr = pv_add_constant (addr, -offset);
904
905
if (pv_area_store_would_trash (stack, addr))
906
break;
907
908
pv_area_store (stack, addr, 4, regs[regno]);
909
910
if (inst2 & 0x0100)
911
regs[bits (insn, 0, 3)] = addr;
912
}
913
914
else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
915
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
916
{
917
int regno = bits (inst2, 12, 15);
918
pv_t addr;
919
920
offset = inst2 & 0xfff;
921
addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
922
923
if (pv_area_store_would_trash (stack, addr))
924
break;
925
926
pv_area_store (stack, addr, 4, regs[regno]);
927
}
928
929
else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
930
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
931
/* Ignore stores of argument registers to the stack. */
932
;
933
934
else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
935
&& (inst2 & 0x0d00) == 0x0c00
936
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
937
/* Ignore stores of argument registers to the stack. */
938
;
939
666
940
else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], { registers } */
667
&& (inst2 & 0x8000) == 0x0000
668
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
669
;
941
&& (inst2 & 0x8000) == 0x0000
942
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
943
/* Ignore block loads from the stack, potentially copying
944
parameters from memory. */
945
;
946
947
else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2, [Rn, #+/-imm] */
948
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
949
/* Similarly ignore dual loads from the stack. */
950
;
951
952
else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
953
&& (inst2 & 0x0d00) == 0x0c00
954
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
955
/* Similarly ignore single loads from the stack. */
956
;
957
958
else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
959
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
960
/* Similarly ignore single loads from the stack. */
961
;
962
670
963
else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
671
964
&& (inst2 & 0x8000) == 0x0000)
672
/* Since we only recognize this for prologue skipping, do not bother
673
to compute the constant. */
674
regs[bits (inst2, 8, 11)] = regs[bits (insn, 0, 3)];
675
else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm12 */
676
&& (inst2 & 0x8000) == 0x0000)
677
/* Since we only recognize this for prologue skipping, do not bother
678
to compute the constant. */
679
regs[bits (inst2, 8, 11)] = regs[bits (insn, 0, 3)];
680
else if ((insn & 0xfbf0) == 0xf2a0 /* sub.w Rd, Rn, #imm8 */
681
&& (inst2 & 0x8000) == 0x0000)
682
/* Since we only recognize this for prologue skipping, do not bother
683
to compute the constant. */
684
regs[bits (inst2, 8, 11)] = regs[bits (insn, 0, 3)];
685
else if ((insn & 0xff50) == 0xf850 /* ldr.w Rd, [Rn, #imm]{!} */
686
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
687
;
688
else if ((insn & 0xff50) == 0xe950 /* ldrd Rt, Rt2, [Rn, #imm]{!} */
689
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
690
;
691
else if ((insn & 0xff50) == 0xf800 /* strb.w or strh.w */
692
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
693
;
965
{
966
unsigned int imm = ((bits (insn, 10, 10) << 11)
967
| (bits (inst2, 12, 14) << 8)
968
| bits (inst2, 0, 7));
969
970
regs[bits (inst2, 8, 11)]
971
= pv_add_constant (regs[bits (insn, 0, 3)],
972
thumb_expand_immediate (imm));
973
}
974
975
else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
976
&& (inst2 & 0x8000) == 0x0000)
977
{
978
unsigned int imm = ((bits (insn, 10, 10) << 11)
979
| (bits (inst2, 12, 14) << 8)
980
| bits (inst2, 0, 7));
981
982
regs[bits (inst2, 8, 11)]
983
= pv_add_constant (regs[bits (insn, 0, 3)], imm);
984
}
985
986
else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
987
&& (inst2 & 0x8000) == 0x0000)
988
{
989
unsigned int imm = ((bits (insn, 10, 10) << 11)
990
| (bits (inst2, 12, 14) << 8)
991
| bits (inst2, 0, 7));
992
993
regs[bits (inst2, 8, 11)]
994
= pv_add_constant (regs[bits (insn, 0, 3)],
995
- (CORE_ADDR) thumb_expand_immediate (imm));
996
}
997
998
else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
999
&& (inst2 & 0x8000) == 0x0000)
1000
{
1001
unsigned int imm = ((bits (insn, 10, 10) << 11)
1002
| (bits (inst2, 12, 14) << 8)
1003
| bits (inst2, 0, 7));
1004
1005
regs[bits (inst2, 8, 11)]
1006
= pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
1007
}
1008
1009
else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1010
{
1011
unsigned int imm = ((bits (insn, 10, 10) << 11)
1012
| (bits (inst2, 12, 14) << 8)
1013
| bits (inst2, 0, 7));
1014
1015
regs[bits (inst2, 8, 11)]
1016
= pv_constant (thumb_expand_immediate (imm));
1017
}
1018
1019
else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
1020
{
1021
unsigned int imm
1022
= EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
1023
1024
regs[bits (inst2, 8, 11)] = pv_constant (imm);
1025
}
1026
1027
else if (insn == 0xea5f /* mov.w Rd,Rm */
1028
&& (inst2 & 0xf0f0) == 0)
1029
{
1030
int dst_reg = (inst2 & 0x0f00) >> 8;
1031
int src_reg = inst2 & 0xf;
1032
regs[dst_reg] = regs[src_reg];
1033
}
1034
1035
else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1036
{
1037
/* Constant pool loads. */
1038
unsigned int constant;
1039
CORE_ADDR loc;
1040
1041
offset = bits (insn, 0, 11);
1042
if (insn & 0x0080)
1043
loc = start + 4 + offset;
1044
else
1045
loc = start + 4 - offset;
1046
1047
constant = read_memory_unsigned_integer (loc, 4, byte_order);
1048
regs[bits (inst2, 12, 15)] = pv_constant (constant);
1049
}
1050
1051
else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1052
{
1053
/* Constant pool loads. */
1054
unsigned int constant;
1055
CORE_ADDR loc;
1056
1057
offset = bits (insn, 0, 7) << 2;
1058
if (insn & 0x0080)
1059
loc = start + 4 + offset;
1060
else
1061
loc = start + 4 - offset;
1062
1063
constant = read_memory_unsigned_integer (loc, 4, byte_order);
1064
regs[bits (inst2, 12, 15)] = pv_constant (constant);
1065
1066
constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
1067
regs[bits (inst2, 8, 11)] = pv_constant (constant);
1068
}
1069
1070
else if (thumb2_instruction_changes_pc (insn, inst2))
1071
{
1072
/* Don't scan past anything that might change control flow. */
1073
break;
1074
}
694
1075
else
695
1076
{
696
/* We don't know what this instruction is. We're finished
697
scanning. NOTE: Recognizing more safe-to-ignore
698
instructions here will improve support for optimized
699
code. */
700
break;
1077
/* The optimizer might shove anything into the prologue,
1078
so we just skip what we don't recognize. */
1079
unrecognized_pc = start;
701
1080
}
702
1081
703
1082
start += 2;
704
1083
}
1084
else if (thumb_instruction_changes_pc (insn))
1085
{
1086
/* Don't scan past anything that might change control flow. */
1087
break;
1088
}
705
1089
else
706
1090
{
707
/* We don't know what this instruction is. We're finished
708
scanning. NOTE: Recognizing more safe-to-ignore
709
instructions here will improve support for optimized
710
code. */
711
break;
1091
/* The optimizer might shove anything into the prologue,
1092
so we just skip what we don't recognize. */
1093
unrecognized_pc = start;
712
1094
}
713
1095
714
1096
start += 2;
718
1100
fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
719
1101
paddress (gdbarch, start));
720
1102
1103
if (unrecognized_pc == 0)
1104
unrecognized_pc = start;
1105
721
1106
if (cache == NULL)
722
1107
{
723
1108
do_cleanups (back_to);
724
return start;
1109
return unrecognized_pc;
725
1110
}
726
1111
727
1112
if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
754
1139
cache->saved_regs[i].addr = offset;
755
1140
756
1141
do_cleanups (back_to);
757
return start;
1142
return unrecognized_pc;
1143
}
1144
1145
1146
/* Try to analyze the instructions starting from PC, which load symbol
1147
__stack_chk_guard. Return the address of instruction after loading this
1148
symbol, set the dest register number to *BASEREG, and set the size of
1149
instructions for loading symbol in OFFSET. Return 0 if instructions are
1150
not recognized. */
1151
1152
static CORE_ADDR
1153
arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
1154
unsigned int *destreg, int *offset)
1155
{
1156
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1157
int is_thumb = arm_pc_is_thumb (pc);
1158
unsigned int low, high, address;
1159
1160
address = 0;
1161
if (is_thumb)
1162
{
1163
unsigned short insn1
1164
= read_memory_unsigned_integer (pc, 2, byte_order_for_code);
1165
1166
if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
1167
{
1168
*destreg = bits (insn1, 8, 10);
1169
*offset = 2;
1170
address = bits (insn1, 0, 7);
1171
}
1172
else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
1173
{
1174
unsigned short insn2
1175
= read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
1176
1177
low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1178
1179
insn1
1180
= read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
1181
insn2
1182
= read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
1183
1184
/* movt Rd, #const */
1185
if ((insn1 & 0xfbc0) == 0xf2c0)
1186
{
1187
high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
1188
*destreg = bits (insn2, 8, 11);
1189
*offset = 8;
1190
address = (high << 16 | low);
1191
}
1192
}
1193
}
1194
else
1195
{
1196
unsigned int insn
1197
= read_memory_unsigned_integer (pc, 4, byte_order_for_code);
1198
1199
if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1200
{
1201
address = bits (insn, 0, 11);
1202
*destreg = bits (insn, 12, 15);
1203
*offset = 4;
1204
}
1205
else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1206
{
1207
low = EXTRACT_MOVW_MOVT_IMM_A (insn);
1208
1209
insn
1210
= read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
1211
1212
if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1213
{
1214
high = EXTRACT_MOVW_MOVT_IMM_A (insn);
1215
*destreg = bits (insn, 12, 15);
1216
*offset = 8;
1217
address = (high << 16 | low);
1218
}
1219
}
1220
}
1221
1222
return address;
1223
}
1224
1225
/* Try to skip a sequence of instructions used for stack protector. If PC
1226
points to the first instruction of this sequence, return the address of first
1227
instruction after this sequence, otherwise, return original PC.
1228
1229
On arm, this sequence of instructions is composed of mainly three steps,
1230
Step 1: load symbol __stack_chk_guard,
1231
Step 2: load from address of __stack_chk_guard,
1232
Step 3: store it to somewhere else.
1233
1234
Usually, instructions on step 2 and step 3 are the same on various ARM
1235
architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1236
on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1237
instructions in step 1 vary from different ARM architectures. On ARMv7,
1238
they are,
1239
1240
movw Rn, #:lower16:__stack_chk_guard
1241
movt Rn, #:upper16:__stack_chk_guard
1242
1243
On ARMv5t, it is,
1244
1245
ldr Rn, .Label
1246
....
1247
.Lable:
1248
.word __stack_chk_guard
1249
1250
Since ldr/str is a very popular instruction, we can't use them as
1251
'fingerprint' or 'signature' of stack protector sequence. Here we choose
1252
sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1253
stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1254
1255
static CORE_ADDR
1256
arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
1257
{
1258
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
1259
unsigned int address, basereg;
1260
struct minimal_symbol *stack_chk_guard;
1261
int offset;
1262
int is_thumb = arm_pc_is_thumb (pc);
1263
CORE_ADDR addr;
1264
1265
/* Try to parse the instructions in Step 1. */
1266
addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
1267
&basereg, &offset);
1268
if (!addr)
1269
return pc;
1270
1271
stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
1272
/* If name of symbol doesn't start with '__stack_chk_guard', this
1273
instruction sequence is not for stack protector. If symbol is
1274
removed, we conservatively think this sequence is for stack protector. */
1275
if (stack_chk_guard
1276
&& strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard), "__stack_chk_guard",
1277
strlen ("__stack_chk_guard")) != 0)
1278
return pc;
1279
1280
if (is_thumb)
1281
{
1282
unsigned int destreg;
1283
unsigned short insn
1284
= read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
1285
1286
/* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1287
if ((insn & 0xf800) != 0x6800)
1288
return pc;
1289
if (bits (insn, 3, 5) != basereg)
1290
return pc;
1291
destreg = bits (insn, 0, 2);
1292
1293
insn = read_memory_unsigned_integer (pc + offset + 2, 2,
1294
byte_order_for_code);
1295
/* Step 3: str Rd, [Rn, #immed], encoding T1. */
1296
if ((insn & 0xf800) != 0x6000)
1297
return pc;
1298
if (destreg != bits (insn, 0, 2))
1299
return pc;
1300
}
1301
else
1302
{
1303
unsigned int destreg;
1304
unsigned int insn
1305
= read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
1306
1307
/* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1308
if ((insn & 0x0e500000) != 0x04100000)
1309
return pc;
1310
if (bits (insn, 16, 19) != basereg)
1311
return pc;
1312
destreg = bits (insn, 12, 15);
1313
/* Step 3: str Rd, [Rn, #immed], encoding A1. */
1314
insn = read_memory_unsigned_integer (pc + offset + 4,
1315
4, byte_order_for_code);
1316
if ((insn & 0x0e500000) != 0x04000000)
1317
return pc;
1318
if (bits (insn, 12, 15) != destreg)
1319
return pc;
1320
}
1321
/* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1322
on arm. */
1323
if (is_thumb)
1324
return pc + offset + 4;
1325
else
1326
return pc + offset + 8;
758
1327
}
759
1328
760
1329
/* Advance the PC across any function entry prologue instructions to
790
1359
= skip_prologue_using_sal (gdbarch, func_addr);
791
1360
struct symtab *s = find_pc_symtab (func_addr);
792
1361
1362
if (post_prologue_pc)
1363
post_prologue_pc
1364
= arm_skip_stack_protector (post_prologue_pc, gdbarch);
1365
1366
793
1367
/* GCC always emits a line note before the prologue and another
794
1368
one after, even if the two are at the same address or on the
795
1369
same line. Take advantage of this so that we do not need to
938
1512
if (find_pc_partial_function (block_addr, NULL, &prologue_start,
939
1513
&prologue_end))
940
1514
{
941
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
942
943
if (sal.line == 0) /* no line info, use current PC */
944
prologue_end = prev_pc;
945
else if (sal.end < prologue_end) /* next line begins after fn end */
946
prologue_end = sal.end; /* (probably means no prologue) */
1515
/* See comment in arm_scan_prologue for an explanation of
1516
this heuristics. */
1517
if (prologue_end > prologue_start + 64)
1518
{
1519
prologue_end = prologue_start + 64;
1520
}
947
1521
}
948
1522
else
949
1523
/* We're in the boondocks: we have no idea where the start of the
1230
1804
the stack. */
1231
1805
CORE_ADDR dest = BranchDest (current_pc, insn);
1232
1806
1233
if (skip_prologue_function (dest))
1807
if (skip_prologue_function (gdbarch, dest, 0))
1234
1808
continue;
1235
1809
else
1236
1810
break;
1459
2033
if (cache->prev_sp == 0)
1460
2034
return;
1461
2035
2036
/* Use function start address as part of the frame ID. If we cannot
2037
identify the start address (due to missing symbol information),
2038
fall back to just using the current PC. */
1462
2039
func = get_frame_func (this_frame);
2040
if (!func)
2041
func = pc;
2042
1463
2043
id = frame_id_build (cache->prev_sp, func);
1464
2044
*this_id = id;
1465
2045
}
1529
2109
default_frame_sniffer
1530
2110
};
1531
2111
2112
/* Maintain a list of ARM exception table entries per objfile, similar to the
2113
list of mapping symbols. We only cache entries for standard ARM-defined
2114
personality routines; the cache will contain only the frame unwinding
2115
instructions associated with the entry (not the descriptors). */
2116
2117
static const struct objfile_data *arm_exidx_data_key;
2118
2119
struct arm_exidx_entry
2120
{
2121
bfd_vma addr;
2122
gdb_byte *entry;
2123
};
2124
typedef struct arm_exidx_entry arm_exidx_entry_s;
2125
DEF_VEC_O(arm_exidx_entry_s);
2126
2127
struct arm_exidx_data
2128
{
2129
VEC(arm_exidx_entry_s) **section_maps;
2130
};
2131
2132
static void
2133
arm_exidx_data_free (struct objfile *objfile, void *arg)
2134
{
2135
struct arm_exidx_data *data = arg;
2136
unsigned int i;
2137
2138
for (i = 0; i < objfile->obfd->section_count; i++)
2139
VEC_free (arm_exidx_entry_s, data->section_maps[i]);
2140
}
2141
2142
static inline int
2143
arm_compare_exidx_entries (const struct arm_exidx_entry *lhs,
2144
const struct arm_exidx_entry *rhs)
2145
{
2146
return lhs->addr < rhs->addr;
2147
}
2148
2149
static struct obj_section *
2150
arm_obj_section_from_vma (struct objfile *objfile, bfd_vma vma)
2151
{
2152
struct obj_section *osect;
2153
2154
ALL_OBJFILE_OSECTIONS (objfile, osect)
2155
if (bfd_get_section_flags (objfile->obfd,
2156
osect->the_bfd_section) & SEC_ALLOC)
2157
{
2158
bfd_vma start, size;
2159
start = bfd_get_section_vma (objfile->obfd, osect->the_bfd_section);
2160
size = bfd_get_section_size (osect->the_bfd_section);
2161
2162
if (start <= vma && vma < start + size)
2163
return osect;
2164
}
2165
2166
return NULL;
2167
}
2168
2169
/* Parse contents of exception table and exception index sections
2170
of OBJFILE, and fill in the exception table entry cache.
2171
2172
For each entry that refers to a standard ARM-defined personality
2173
routine, extract the frame unwinding instructions (from either
2174
the index or the table section). The unwinding instructions
2175
are normalized by:
2176
- extracting them from the rest of the table data
2177
- converting to host endianness
2178
- appending the implicit 0xb0 ("Finish") code
2179
2180
The extracted and normalized instructions are stored for later
2181
retrieval by the arm_find_exidx_entry routine. */
2182
2183
static void
2184
arm_exidx_new_objfile (struct objfile *objfile)
2185
{
2186
struct cleanup *cleanups = make_cleanup (null_cleanup, NULL);
2187
struct arm_exidx_data *data;
2188
asection *exidx, *extab;
2189
bfd_vma exidx_vma = 0, extab_vma = 0;
2190
bfd_size_type exidx_size = 0, extab_size = 0;
2191
gdb_byte *exidx_data = NULL, *extab_data = NULL;
2192
LONGEST i;
2193
2194
/* If we've already touched this file, do nothing. */
2195
if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
2196
return;
2197
2198
/* Read contents of exception table and index. */
2199
exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx");
2200
if (exidx)
2201
{
2202
exidx_vma = bfd_section_vma (objfile->obfd, exidx);
2203
exidx_size = bfd_get_section_size (exidx);
2204
exidx_data = xmalloc (exidx_size);
2205
make_cleanup (xfree, exidx_data);
2206
2207
if (!bfd_get_section_contents (objfile->obfd, exidx,
2208
exidx_data, 0, exidx_size))
2209
{
2210
do_cleanups (cleanups);
2211
return;
2212
}
2213
}
2214
2215
extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
2216
if (extab)
2217
{
2218
extab_vma = bfd_section_vma (objfile->obfd, extab);
2219
extab_size = bfd_get_section_size (extab);
2220
extab_data = xmalloc (extab_size);
2221
make_cleanup (xfree, extab_data);
2222
2223
if (!bfd_get_section_contents (objfile->obfd, extab,
2224
extab_data, 0, extab_size))
2225
{
2226
do_cleanups (cleanups);
2227
return;
2228
}
2229
}
2230
2231
/* Allocate exception table data structure. */
2232
data = OBSTACK_ZALLOC (&objfile->objfile_obstack, struct arm_exidx_data);
2233
set_objfile_data (objfile, arm_exidx_data_key, data);
2234
data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2235
objfile->obfd->section_count,
2236
VEC(arm_exidx_entry_s) *);
2237
2238
/* Fill in exception table. */
2239
for (i = 0; i < exidx_size / 8; i++)
2240
{
2241
struct arm_exidx_entry new_exidx_entry;
2242
bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
2243
bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
2244
bfd_vma addr = 0, word = 0;
2245
int n_bytes = 0, n_words = 0;
2246
struct obj_section *sec;
2247
gdb_byte *entry = NULL;
2248
2249
/* Extract address of start of function. */
2250
idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2251
idx += exidx_vma + i * 8;
2252
2253
/* Find section containing function and compute section offset. */
2254
sec = arm_obj_section_from_vma (objfile, idx);
2255
if (sec == NULL)
2256
continue;
2257
idx -= bfd_get_section_vma (objfile->obfd, sec->the_bfd_section);
2258
2259
/* Determine address of exception table entry. */
2260
if (val == 1)
2261
{
2262
/* EXIDX_CANTUNWIND -- no exception table entry present. */
2263
}
2264
else if ((val & 0xff000000) == 0x80000000)
2265
{
2266
/* Exception table entry embedded in .ARM.exidx
2267
-- must be short form. */
2268
word = val;
2269
n_bytes = 3;
2270
}
2271
else if (!(val & 0x80000000))
2272
{
2273
/* Exception table entry in .ARM.extab. */
2274
addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2275
addr += exidx_vma + i * 8 + 4;
2276
2277
if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2278
{
2279
word = bfd_h_get_32 (objfile->obfd,
2280
extab_data + addr - extab_vma);
2281
addr += 4;
2282
2283
if ((word & 0xff000000) == 0x80000000)
2284
{
2285
/* Short form. */
2286
n_bytes = 3;
2287
}
2288
else if ((word & 0xff000000) == 0x81000000
2289
|| (word & 0xff000000) == 0x82000000)
2290
{
2291
/* Long form. */
2292
n_bytes = 2;
2293
n_words = ((word >> 16) & 0xff);
2294
}
2295
else if (!(word & 0x80000000))
2296
{
2297
bfd_vma pers;
2298
struct obj_section *pers_sec;
2299
int gnu_personality = 0;
2300
2301
/* Custom personality routine. */
2302
pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2303
pers = UNMAKE_THUMB_ADDR (pers + addr - 4);
2304
2305
/* Check whether we've got one of the variants of the
2306
GNU personality routines. */
2307
pers_sec = arm_obj_section_from_vma (objfile, pers);
2308
if (pers_sec)
2309
{
2310
static const char *personality[] =
2311
{
2312
"__gcc_personality_v0",
2313
"__gxx_personality_v0",
2314
"__gcj_personality_v0",
2315
"__gnu_objc_personality_v0",
2316
NULL
2317
};
2318
2319
CORE_ADDR pc = pers + obj_section_offset (pers_sec);
2320
int k;
2321
2322
for (k = 0; personality[k]; k++)
2323
if (lookup_minimal_symbol_by_pc_name
2324
(pc, personality[k], objfile))
2325
{
2326
gnu_personality = 1;
2327
break;
2328
}
2329
}
2330
2331
/* If so, the next word contains a word count in the high
2332
byte, followed by the same unwind instructions as the
2333
pre-defined forms. */
2334
if (gnu_personality
2335
&& addr + 4 <= extab_vma + extab_size)
2336
{
2337
word = bfd_h_get_32 (objfile->obfd,
2338
extab_data + addr - extab_vma);
2339
addr += 4;
2340
n_bytes = 3;
2341
n_words = ((word >> 24) & 0xff);
2342
}
2343
}
2344
}
2345
}
2346
2347
/* Sanity check address. */
2348
if (n_words)
2349
if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2350
n_words = n_bytes = 0;
2351
2352
/* The unwind instructions reside in WORD (only the N_BYTES least
2353
significant bytes are valid), followed by N_WORDS words in the
2354
extab section starting at ADDR. */
2355
if (n_bytes || n_words)
2356
{
2357
gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack,
2358
n_bytes + n_words * 4 + 1);
2359
2360
while (n_bytes--)
2361
*p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2362
2363
while (n_words--)
2364
{
2365
word = bfd_h_get_32 (objfile->obfd,
2366
extab_data + addr - extab_vma);
2367
addr += 4;
2368
2369
*p++ = (gdb_byte) ((word >> 24) & 0xff);
2370
*p++ = (gdb_byte) ((word >> 16) & 0xff);
2371
*p++ = (gdb_byte) ((word >> 8) & 0xff);
2372
*p++ = (gdb_byte) (word & 0xff);
2373
}
2374
2375
/* Implied "Finish" to terminate the list. */
2376
*p++ = 0xb0;
2377
}
2378
2379
/* Push entry onto vector. They are guaranteed to always
2380
appear in order of increasing addresses. */
2381
new_exidx_entry.addr = idx;
2382
new_exidx_entry.entry = entry;
2383
VEC_safe_push (arm_exidx_entry_s,
2384
data->section_maps[sec->the_bfd_section->index],
2385
&new_exidx_entry);
2386
}
2387
2388
do_cleanups (cleanups);
2389
}
2390
2391
/* Search for the exception table entry covering MEMADDR. If one is found,
2392
return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2393
set *START to the start of the region covered by this entry. */
2394
2395
static gdb_byte *
2396
arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start)
2397
{
2398
struct obj_section *sec;
2399
2400
sec = find_pc_section (memaddr);
2401
if (sec != NULL)
2402
{
2403
struct arm_exidx_data *data;
2404
VEC(arm_exidx_entry_s) *map;
2405
struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 };
2406
unsigned int idx;
2407
2408
data = objfile_data (sec->objfile, arm_exidx_data_key);
2409
if (data != NULL)
2410
{
2411
map = data->section_maps[sec->the_bfd_section->index];
2412
if (!VEC_empty (arm_exidx_entry_s, map))
2413
{
2414
struct arm_exidx_entry *map_sym;
2415
2416
idx = VEC_lower_bound (arm_exidx_entry_s, map, &map_key,
2417
arm_compare_exidx_entries);
2418
2419
/* VEC_lower_bound finds the earliest ordered insertion
2420
point. If the following symbol starts at this exact
2421
address, we use that; otherwise, the preceding
2422
exception table entry covers this address. */
2423
if (idx < VEC_length (arm_exidx_entry_s, map))
2424
{
2425
map_sym = VEC_index (arm_exidx_entry_s, map, idx);
2426
if (map_sym->addr == map_key.addr)
2427
{
2428
if (start)
2429
*start = map_sym->addr + obj_section_addr (sec);
2430
return map_sym->entry;
2431
}
2432
}
2433
2434
if (idx > 0)
2435
{
2436
map_sym = VEC_index (arm_exidx_entry_s, map, idx - 1);
2437
if (start)
2438
*start = map_sym->addr + obj_section_addr (sec);
2439
return map_sym->entry;
2440
}
2441
}
2442
}
2443
}
2444
2445
return NULL;
2446
}
2447
2448
/* Given the current frame THIS_FRAME, and its associated frame unwinding
2449
instruction list from the ARM exception table entry ENTRY, allocate and
2450
return a prologue cache structure describing how to unwind this frame.
2451
2452
Return NULL if the unwinding instruction list contains a "spare",
2453
"reserved" or "refuse to unwind" instruction as defined in section
2454
"9.3 Frame unwinding instructions" of the "Exception Handling ABI
2455
for the ARM Architecture" document. */
2456
2457
static struct arm_prologue_cache *
2458
arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
2459
{
2460
CORE_ADDR vsp = 0;
2461
int vsp_valid = 0;
2462
2463
struct arm_prologue_cache *cache;
2464
cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
2465
cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2466
2467
for (;;)
2468
{
2469
gdb_byte insn;
2470
2471
/* Whenever we reload SP, we actually have to retrieve its
2472
actual value in the current frame. */
2473
if (!vsp_valid)
2474
{
2475
if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2476
{
2477
int reg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2478
vsp = get_frame_register_unsigned (this_frame, reg);
2479
}
2480
else
2481
{
2482
CORE_ADDR addr = cache->saved_regs[ARM_SP_REGNUM].addr;
2483
vsp = get_frame_memory_unsigned (this_frame, addr, 4);
2484
}
2485
2486
vsp_valid = 1;
2487
}
2488
2489
/* Decode next unwind instruction. */
2490
insn = *entry++;
2491
2492
if ((insn & 0xc0) == 0)
2493
{
2494
int offset = insn & 0x3f;
2495
vsp += (offset << 2) + 4;
2496
}
2497
else if ((insn & 0xc0) == 0x40)
2498
{
2499
int offset = insn & 0x3f;
2500
vsp -= (offset << 2) + 4;
2501
}
2502
else if ((insn & 0xf0) == 0x80)
2503
{
2504
int mask = ((insn & 0xf) << 8) | *entry++;
2505
int i;
2506
2507
/* The special case of an all-zero mask identifies
2508
"Refuse to unwind". We return NULL to fall back
2509
to the prologue analyzer. */
2510
if (mask == 0)
2511
return NULL;
2512
2513
/* Pop registers r4..r15 under mask. */
2514
for (i = 0; i < 12; i++)
2515
if (mask & (1 << i))
2516
{
2517
cache->saved_regs[4 + i].addr = vsp;
2518
vsp += 4;
2519
}
2520
2521
/* Special-case popping SP -- we need to reload vsp. */
2522
if (mask & (1 << (ARM_SP_REGNUM - 4)))
2523
vsp_valid = 0;
2524
}
2525
else if ((insn & 0xf0) == 0x90)
2526
{
2527
int reg = insn & 0xf;
2528
2529
/* Reserved cases. */
2530
if (reg == ARM_SP_REGNUM || reg == ARM_PC_REGNUM)
2531
return NULL;
2532
2533
/* Set SP from another register and mark VSP for reload. */
2534
cache->saved_regs[ARM_SP_REGNUM] = cache->saved_regs[reg];
2535
vsp_valid = 0;
2536
}
2537
else if ((insn & 0xf0) == 0xa0)
2538
{
2539
int count = insn & 0x7;
2540
int pop_lr = (insn & 0x8) != 0;
2541
int i;
2542
2543
/* Pop r4..r[4+count]. */
2544
for (i = 0; i <= count; i++)
2545
{
2546
cache->saved_regs[4 + i].addr = vsp;
2547
vsp += 4;
2548
}
2549
2550
/* If indicated by flag, pop LR as well. */
2551
if (pop_lr)
2552
{
2553
cache->saved_regs[ARM_LR_REGNUM].addr = vsp;
2554
vsp += 4;
2555
}
2556
}
2557
else if (insn == 0xb0)
2558
{
2559
/* We could only have updated PC by popping into it; if so, it
2560
will show up as address. Otherwise, copy LR into PC. */
2561
if (!trad_frame_addr_p (cache->saved_regs, ARM_PC_REGNUM))
2562
cache->saved_regs[ARM_PC_REGNUM]
2563
= cache->saved_regs[ARM_LR_REGNUM];
2564
2565
/* We're done. */
2566
break;
2567
}
2568
else if (insn == 0xb1)
2569
{
2570
int mask = *entry++;
2571
int i;
2572
2573
/* All-zero mask and mask >= 16 is "spare". */
2574
if (mask == 0 || mask >= 16)
2575
return NULL;
2576
2577
/* Pop r0..r3 under mask. */
2578
for (i = 0; i < 4; i++)
2579
if (mask & (1 << i))
2580
{
2581
cache->saved_regs[i].addr = vsp;
2582
vsp += 4;
2583
}
2584
}
2585
else if (insn == 0xb2)
2586
{
2587
ULONGEST offset = 0;
2588
unsigned shift = 0;
2589
2590
do
2591
{
2592
offset |= (*entry & 0x7f) << shift;
2593
shift += 7;
2594
}
2595
while (*entry++ & 0x80);
2596
2597
vsp += 0x204 + (offset << 2);
2598
}
2599
else if (insn == 0xb3)
2600
{
2601
int start = *entry >> 4;
2602
int count = (*entry++) & 0xf;
2603
int i;
2604
2605
/* Only registers D0..D15 are valid here. */
2606
if (start + count >= 16)
2607
return NULL;
2608
2609
/* Pop VFP double-precision registers D[start]..D[start+count]. */
2610
for (i = 0; i <= count; i++)
2611
{
2612
cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2613
vsp += 8;
2614
}
2615
2616
/* Add an extra 4 bytes for FSTMFDX-style stack. */
2617
vsp += 4;
2618
}
2619
else if ((insn & 0xf8) == 0xb8)
2620
{
2621
int count = insn & 0x7;
2622
int i;
2623
2624
/* Pop VFP double-precision registers D[8]..D[8+count]. */
2625
for (i = 0; i <= count; i++)
2626
{
2627
cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2628
vsp += 8;
2629
}
2630
2631
/* Add an extra 4 bytes for FSTMFDX-style stack. */
2632
vsp += 4;
2633
}
2634
else if (insn == 0xc6)
2635
{
2636
int start = *entry >> 4;
2637
int count = (*entry++) & 0xf;
2638
int i;
2639
2640
/* Only registers WR0..WR15 are valid. */
2641
if (start + count >= 16)
2642
return NULL;
2643
2644
/* Pop iwmmx registers WR[start]..WR[start+count]. */
2645
for (i = 0; i <= count; i++)
2646
{
2647
cache->saved_regs[ARM_WR0_REGNUM + start + i].addr = vsp;
2648
vsp += 8;
2649
}
2650
}
2651
else if (insn == 0xc7)
2652
{
2653
int mask = *entry++;
2654
int i;
2655
2656
/* All-zero mask and mask >= 16 is "spare". */
2657
if (mask == 0 || mask >= 16)
2658
return NULL;
2659
2660
/* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2661
for (i = 0; i < 4; i++)
2662
if (mask & (1 << i))
2663
{
2664
cache->saved_regs[ARM_WCGR0_REGNUM + i].addr = vsp;
2665
vsp += 4;
2666
}
2667
}
2668
else if ((insn & 0xf8) == 0xc0)
2669
{
2670
int count = insn & 0x7;
2671
int i;
2672
2673
/* Pop iwmmx registers WR[10]..WR[10+count]. */
2674
for (i = 0; i <= count; i++)
2675
{
2676
cache->saved_regs[ARM_WR0_REGNUM + 10 + i].addr = vsp;
2677
vsp += 8;
2678
}
2679
}
2680
else if (insn == 0xc8)
2681
{
2682
int start = *entry >> 4;
2683
int count = (*entry++) & 0xf;
2684
int i;
2685
2686
/* Only registers D0..D31 are valid. */
2687
if (start + count >= 16)
2688
return NULL;
2689
2690
/* Pop VFP double-precision registers
2691
D[16+start]..D[16+start+count]. */
2692
for (i = 0; i <= count; i++)
2693
{
2694
cache->saved_regs[ARM_D0_REGNUM + 16 + start + i].addr = vsp;
2695
vsp += 8;
2696
}
2697
}
2698
else if (insn == 0xc9)
2699
{
2700
int start = *entry >> 4;
2701
int count = (*entry++) & 0xf;
2702
int i;
2703
2704
/* Pop VFP double-precision registers D[start]..D[start+count]. */
2705
for (i = 0; i <= count; i++)
2706
{
2707
cache->saved_regs[ARM_D0_REGNUM + start + i].addr = vsp;
2708
vsp += 8;
2709
}
2710
}
2711
else if ((insn & 0xf8) == 0xd0)
2712
{
2713
int count = insn & 0x7;
2714
int i;
2715
2716
/* Pop VFP double-precision registers D[8]..D[8+count]. */
2717
for (i = 0; i <= count; i++)
2718
{
2719
cache->saved_regs[ARM_D0_REGNUM + 8 + i].addr = vsp;
2720
vsp += 8;
2721
}
2722
}
2723
else
2724
{
2725
/* Everything else is "spare". */
2726
return NULL;
2727
}
2728
}
2729
2730
/* If we restore SP from a register, assume this was the frame register.
2731
Otherwise just fall back to SP as frame register. */
2732
if (trad_frame_realreg_p (cache->saved_regs, ARM_SP_REGNUM))
2733
cache->framereg = cache->saved_regs[ARM_SP_REGNUM].realreg;
2734
else
2735
cache->framereg = ARM_SP_REGNUM;
2736
2737
/* Determine offset to previous frame. */
2738
cache->framesize
2739
= vsp - get_frame_register_unsigned (this_frame, cache->framereg);
2740
2741
/* We already got the previous SP. */
2742
cache->prev_sp = vsp;
2743
2744
return cache;
2745
}
2746
2747
/* Unwinding via ARM exception table entries. Note that the sniffer
2748
already computes a filled-in prologue cache, which is then used
2749
with the same arm_prologue_this_id and arm_prologue_prev_register
2750
routines also used for prologue-parsing based unwinding. */
2751
2752
static int
2753
arm_exidx_unwind_sniffer (const struct frame_unwind *self,
2754
struct frame_info *this_frame,
2755
void **this_prologue_cache)
2756
{
2757
struct gdbarch *gdbarch = get_frame_arch (this_frame);
2758
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2759
CORE_ADDR addr_in_block, exidx_region, func_start;
2760
struct arm_prologue_cache *cache;
2761
gdb_byte *entry;
2762
2763
/* See if we have an ARM exception table entry covering this address. */
2764
addr_in_block = get_frame_address_in_block (this_frame);
2765
entry = arm_find_exidx_entry (addr_in_block, &exidx_region);
2766
if (!entry)
2767
return 0;
2768
2769
/* The ARM exception table does not describe unwind information
2770
for arbitrary PC values, but is guaranteed to be correct only
2771
at call sites. We have to decide here whether we want to use
2772
ARM exception table information for this frame, or fall back
2773
to using prologue parsing. (Note that if we have DWARF CFI,
2774
this sniffer isn't even called -- CFI is always preferred.)
2775
2776
Before we make this decision, however, we check whether we
2777
actually have *symbol* information for the current frame.
2778
If not, prologue parsing would not work anyway, so we might
2779
as well use the exception table and hope for the best. */
2780
if (find_pc_partial_function (addr_in_block, NULL, &func_start, NULL))
2781
{
2782
int exc_valid = 0;
2783
2784
/* If the next frame is "normal", we are at a call site in this
2785
frame, so exception information is guaranteed to be valid. */
2786
if (get_next_frame (this_frame)
2787
&& get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
2788
exc_valid = 1;
2789
2790
/* We also assume exception information is valid if we're currently
2791
blocked in a system call. The system library is supposed to
2792
ensure this, so that e.g. pthread cancellation works. */
2793
if (arm_frame_is_thumb (this_frame))
2794
{
2795
LONGEST insn;
2796
2797
if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
2798
byte_order_for_code, &insn)
2799
&& (insn & 0xff00) == 0xdf00 /* svc */)
2800
exc_valid = 1;
2801
}
2802
else
2803
{
2804
LONGEST insn;
2805
2806
if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
2807
byte_order_for_code, &insn)
2808
&& (insn & 0x0f000000) == 0x0f000000 /* svc */)
2809
exc_valid = 1;
2810
}
2811
2812
/* Bail out if we don't know that exception information is valid. */
2813
if (!exc_valid)
2814
return 0;
2815
2816
/* The ARM exception index does not mark the *end* of the region
2817
covered by the entry, and some functions will not have any entry.
2818
To correctly recognize the end of the covered region, the linker
2819
should have inserted dummy records with a CANTUNWIND marker.
2820
2821
Unfortunately, current versions of GNU ld do not reliably do
2822
this, and thus we may have found an incorrect entry above.
2823
As a (temporary) sanity check, we only use the entry if it
2824
lies *within* the bounds of the function. Note that this check
2825
might reject perfectly valid entries that just happen to cover
2826
multiple functions; therefore this check ought to be removed
2827
once the linker is fixed. */
2828
if (func_start > exidx_region)
2829
return 0;
2830
}
2831
2832
/* Decode the list of unwinding instructions into a prologue cache.
2833
Note that this may fail due to e.g. a "refuse to unwind" code. */
2834
cache = arm_exidx_fill_cache (this_frame, entry);
2835
if (!cache)
2836
return 0;
2837
2838
*this_prologue_cache = cache;
2839
return 1;
2840
}
2841
2842
struct frame_unwind arm_exidx_unwind = {
2843
NORMAL_FRAME,
2844
arm_prologue_this_id,
2845
arm_prologue_prev_register,
2846
NULL,
2847
arm_exidx_unwind_sniffer
2848
};
2849
1532
2850
static struct arm_prologue_cache *
1533
2851
arm_make_stub_cache (struct frame_info *this_frame)
1534
2852
{
1686
3004
}
1687
3005
}
1688
3006
3007
/* Return true if we are in the function's epilogue, i.e. after the
3008
instruction that destroyed the function's stack frame. */
3009
3010
static int
3011
thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3012
{
3013
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3014
unsigned int insn, insn2;
3015
int found_return = 0, found_stack_adjust = 0;
3016
CORE_ADDR func_start, func_end;
3017
CORE_ADDR scan_pc;
3018
gdb_byte buf[4];
3019
3020
if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3021
return 0;
3022
3023
/* The epilogue is a sequence of instructions along the following lines:
3024
3025
- add stack frame size to SP or FP
3026
- [if frame pointer used] restore SP from FP
3027
- restore registers from SP [may include PC]
3028
- a return-type instruction [if PC wasn't already restored]
3029
3030
In a first pass, we scan forward from the current PC and verify the
3031
instructions we find as compatible with this sequence, ending in a
3032
return instruction.
3033
3034
However, this is not sufficient to distinguish indirect function calls
3035
within a function from indirect tail calls in the epilogue in some cases.
3036
Therefore, if we didn't already find any SP-changing instruction during
3037
forward scan, we add a backward scanning heuristic to ensure we actually
3038
are in the epilogue. */
3039
3040
scan_pc = pc;
3041
while (scan_pc < func_end && !found_return)
3042
{
3043
if (target_read_memory (scan_pc, buf, 2))
3044
break;
3045
3046
scan_pc += 2;
3047
insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3048
3049
if ((insn & 0xff80) == 0x4700) /* bx <Rm> */
3050
found_return = 1;
3051
else if (insn == 0x46f7) /* mov pc, lr */
3052
found_return = 1;
3053
else if (insn == 0x46bd) /* mov sp, r7 */
3054
found_stack_adjust = 1;
3055
else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3056
found_stack_adjust = 1;
3057
else if ((insn & 0xfe00) == 0xbc00) /* pop <registers> */
3058
{
3059
found_stack_adjust = 1;
3060
if (insn & 0x0100) /* <registers> include PC. */
3061
found_return = 1;
3062
}
3063
else if ((insn & 0xe000) == 0xe000) /* 32-bit Thumb-2 instruction */
3064
{
3065
if (target_read_memory (scan_pc, buf, 2))
3066
break;
3067
3068
scan_pc += 2;
3069
insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code);
3070
3071
if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3072
{
3073
found_stack_adjust = 1;
3074
if (insn2 & 0x8000) /* <registers> include PC. */
3075
found_return = 1;
3076
}
3077
else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3078
&& (insn2 & 0x0fff) == 0x0b04)
3079
{
3080
found_stack_adjust = 1;
3081
if ((insn2 & 0xf000) == 0xf000) /* <Rt> is PC. */
3082
found_return = 1;
3083
}
3084
else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3085
&& (insn2 & 0x0e00) == 0x0a00)
3086
found_stack_adjust = 1;
3087
else
3088
break;
3089
}
3090
else
3091
break;
3092
}
3093
3094
if (!found_return)
3095
return 0;
3096
3097
/* Since any instruction in the epilogue sequence, with the possible
3098
exception of return itself, updates the stack pointer, we need to
3099
scan backwards for at most one instruction. Try either a 16-bit or
3100
a 32-bit instruction. This is just a heuristic, so we do not worry
3101
too much about false positives.*/
3102
3103
if (!found_stack_adjust)
3104
{
3105
if (pc - 4 < func_start)
3106
return 0;
3107
if (target_read_memory (pc - 4, buf, 4))
3108
return 0;
3109
3110
insn = extract_unsigned_integer (buf, 2, byte_order_for_code);
3111
insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code);
3112
3113
if (insn2 == 0x46bd) /* mov sp, r7 */
3114
found_stack_adjust = 1;
3115
else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3116
found_stack_adjust = 1;
3117
else if ((insn2 & 0xff00) == 0xbc00) /* pop <registers> without PC */
3118
found_stack_adjust = 1;
3119
else if (insn == 0xe8bd) /* ldm.w sp!, <registers> */
3120
found_stack_adjust = 1;
3121
else if (insn == 0xf85d /* ldr.w <Rt>, [sp], #4 */
3122
&& (insn2 & 0x0fff) == 0x0b04)
3123
found_stack_adjust = 1;
3124
else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, <list> */
3125
&& (insn2 & 0x0e00) == 0x0a00)
3126
found_stack_adjust = 1;
3127
}
3128
3129
return found_stack_adjust;
3130
}
3131
3132
/* Return true if we are in the function's epilogue, i.e. after the
3133
instruction that destroyed the function's stack frame. */
3134
3135
static int
3136
arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
3137
{
3138
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
3139
unsigned int insn;
3140
int found_return, found_stack_adjust;
3141
CORE_ADDR func_start, func_end;
3142
3143
if (arm_pc_is_thumb (pc))
3144
return thumb_in_function_epilogue_p (gdbarch, pc);
3145
3146
if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
3147
return 0;
3148
3149
/* We are in the epilogue if the previous instruction was a stack
3150
adjustment and the next instruction is a possible return (bx, mov
3151
pc, or pop). We could have to scan backwards to find the stack
3152
adjustment, or forwards to find the return, but this is a decent
3153
approximation. First scan forwards. */
3154
3155
found_return = 0;
3156
insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
3157
if (bits (insn, 28, 31) != INST_NV)
3158
{
3159
if ((insn & 0x0ffffff0) == 0x012fff10)
3160
/* BX. */
3161
found_return = 1;
3162
else if ((insn & 0x0ffffff0) == 0x01a0f000)
3163
/* MOV PC. */
3164
found_return = 1;
3165
else if ((insn & 0x0fff0000) == 0x08bd0000
3166
&& (insn & 0x0000c000) != 0)
3167
/* POP (LDMIA), including PC or LR. */
3168
found_return = 1;
3169
}
3170
3171
if (!found_return)
3172
return 0;
3173
3174
/* Scan backwards. This is just a heuristic, so do not worry about
3175
false positives from mode changes. */
3176
3177
if (pc < func_start + 4)
3178
return 0;
3179
3180
insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code);
3181
if (bits (insn, 28, 31) != INST_NV)
3182
{
3183
if ((insn & 0x0df0f000) == 0x0080d000)
3184
/* ADD SP (register or immediate). */
3185
found_stack_adjust = 1;
3186
else if ((insn & 0x0df0f000) == 0x0040d000)
3187
/* SUB SP (register or immediate). */
3188
found_stack_adjust = 1;
3189
else if ((insn & 0x0ffffff0) == 0x01a0d000)
3190
/* MOV SP. */
3191
found_return = 1;
3192
else if ((insn & 0x0fff0000) == 0x08bd0000)
3193
/* POP (LDMIA). */
3194
found_stack_adjust = 1;
3195
}
3196
3197
if (found_stack_adjust)
3198
return 1;
3199
3200
return 0;
3201
}
3202
3203
1689
3204
/* When arguments must be pushed onto the stack, they go on in reverse
1690
3205
order. The code below implements a FILO (stack) to do this. */
1691
3206
3004
4519
else
3005
4520
nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
3006
4521
}
4522
else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
4523
{
4524
if (bits (inst1, 3, 6) == 0x0f)
4525
nextpc = pc_val;
4526
else
4527
nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
4528
4529
nextpc = MAKE_THUMB_ADDR (nextpc);
4530
}
3007
4531
else if ((inst1 & 0xf500) == 0xb100)
3008
4532
{
3009
4533
/* CBNZ or CBZ. */
6412
7936
return osabi;
6413
7937
}
6414
7938
7939
static int
7940
arm_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
7941
struct reggroup *group)
7942
{
7943
/* FPS register's type is INT, but belongs to float_reggroup. Beside
7944
this, FPS register belongs to save_regroup, restore_reggroup, and
7945
all_reggroup, of course. */
7946
if (regnum == ARM_FPS_REGNUM)
7947
return (group == float_reggroup
7948
|| group == save_reggroup
7949
|| group == restore_reggroup
7950
|| group == all_reggroup);
7951
else
7952
return default_register_reggroup_p (gdbarch, regnum, group);
7953
}
7954
6415
7955
6416
7956
/* Initialize the current architecture based on INFO. If possible,
6417
7957
re-use an architecture from ARCHES, which is a list of
6818
8358
/* Advance PC across function entry code. */
6819
8359
set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
6820
8360
8361
/* Detect whether PC is in function epilogue. */
8362
set_gdbarch_in_function_epilogue_p (gdbarch, arm_in_function_epilogue_p);
8363
6821
8364
/* Skip trampolines. */
6822
8365
set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
6823
8366
6830
8373
arm_remote_breakpoint_from_pc);
6831
8374
6832
8375
/* Information about registers, etc. */
6833
set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
6834
8376
set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
6835
8377
set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
6836
8378
set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
6837
8379
set_gdbarch_register_type (gdbarch, arm_register_type);
8380
set_gdbarch_register_reggroup_p (gdbarch, arm_register_reggroup_p);
6838
8381
6839
8382
/* This "info float" is FPA-specific. Use the generic version if we
6840
8383
do not have FPA. */
6874
8417
/* Add some default predicates. */
6875
8418
frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
6876
8419
dwarf2_append_unwinders (gdbarch);
8420
frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind);
6877
8421
frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
6878
8422
6879
8423
/* Now we have tuned the configuration, set a few final things,
6884
8428
if (tdep->arm_abi == ARM_ABI_AUTO)
6885
8429
tdep->arm_abi = ARM_ABI_APCS;
6886
8430
8431
/* Watchpoints are not steppable. */
8432
set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
8433
6887
8434
/* We used to default to FPA for generic ARM, but almost nobody
6888
8435
uses that now, and we now provide a way for the user to force
6889
8436
the model. So default to the most useful variant. */
6976
8523
arm_objfile_data_key
6977
8524
= register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
6978
8525
8526
/* Add ourselves to objfile event chain. */
8527
observer_attach_new_objfile (arm_exidx_new_objfile);
8528
arm_exidx_data_key
8529
= register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
8530
6979
8531
/* Register an ELF OS ABI sniffer for ARM binaries. */
6980
8532
gdbarch_register_osabi_sniffer (bfd_arch_arm,
6981
8533
bfd_target_elf_flavour,
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