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Viewing changes to intel/intel_decode.c

  • Committer: Package Import Robot
  • Author(s): Maarten Lankhorst
  • Date: 2013-04-22 11:06:19 UTC
  • mfrom: (65.1.10 raring)
  • Revision ID: package-import@ubuntu.com-20130422110619-bdujabi7bls3ze3l
Tags: 2.4.43-0ubuntu0.1
https://launchpad.net/bugs/1171340
Copy package from raring, and re-enable libdrm-nouveau1a. (LP: #1171340)

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Lines of Context:
intel/intel_decode.c
139
139
}
140
140
 
141
141
static int
 
142
decode_MI_SET_CONTEXT(struct drm_intel_decode *ctx)
 
143
{
 
144
        uint32_t data = ctx->data[1];
 
145
        if (ctx->gen > 7)
 
146
                return 1;
 
147
 
 
148
        instr_out(ctx, 0, "MI_SET_CONTEXT\n");
 
149
        instr_out(ctx, 1, "gtt offset = 0x%x%s%s\n",
 
150
                  data & ~0xfff,
 
151
                  data & (1<<1)? ", Force Restore": "",
 
152
                  data & (1<<0)? ", Restore Inhibit": "");
 
153
 
 
154
        return 2;
 
155
}
 
156
 
 
157
static int
 
158
decode_MI_WAIT_FOR_EVENT(struct drm_intel_decode *ctx)
 
159
{
 
160
        const char *cc_wait;
 
161
        int cc_shift = 0;
 
162
        uint32_t data = ctx->data[0];
 
163
 
 
164
        if (ctx->gen <= 5)
 
165
                cc_shift = 9;
 
166
        else
 
167
                cc_shift = 16;
 
168
 
 
169
        switch ((data >> cc_shift) & 0x1f) {
 
170
        case 1:
 
171
                cc_wait = ", cc wait 1";
 
172
                break;
 
173
        case 2:
 
174
                cc_wait = ", cc wait 2";
 
175
                break;
 
176
        case 3:
 
177
                cc_wait = ", cc wait 3";
 
178
                break;
 
179
        case 4:
 
180
                cc_wait = ", cc wait 4";
 
181
                break;
 
182
        case 5:
 
183
                cc_wait = ", cc wait 4";
 
184
                break;
 
185
        default:
 
186
                cc_wait = "";
 
187
                break;
 
188
        }
 
189
 
 
190
        if (ctx->gen <= 5) {
 
191
                instr_out(ctx, 0, "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
 
192
                          data & (1<<18)? ", pipe B start vblank wait": "",
 
193
                          data & (1<<17)? ", pipe A start vblank wait": "",
 
194
                          data & (1<<16)? ", overlay flip pending wait": "",
 
195
                          data & (1<<14)? ", pipe B hblank wait": "",
 
196
                          data & (1<<13)? ", pipe A hblank wait": "",
 
197
                          cc_wait,
 
198
                          data & (1<<8)? ", plane C pending flip wait": "",
 
199
                          data & (1<<7)? ", pipe B vblank wait": "",
 
200
                          data & (1<<6)? ", plane B pending flip wait": "",
 
201
                          data & (1<<5)? ", pipe B scan line wait": "",
 
202
                          data & (1<<4)? ", fbc idle wait": "",
 
203
                          data & (1<<3)? ", pipe A vblank wait": "",
 
204
                          data & (1<<2)? ", plane A pending flip wait": "",
 
205
                          data & (1<<1)? ", plane A scan line wait": "");
 
206
        } else {
 
207
                instr_out(ctx, 0, "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s\n",
 
208
                          data & (1<<20)? ", sprite C pending flip wait": "", /* ivb */
 
209
                          cc_wait,
 
210
                          data & (1<<13)? ", pipe B hblank wait": "",
 
211
                          data & (1<<11)? ", pipe B vblank wait": "",
 
212
                          data & (1<<10)? ", sprite B pending flip wait": "",
 
213
                          data & (1<<9)? ", plane B pending flip wait": "",
 
214
                          data & (1<<8)? ", plane B scan line wait": "",
 
215
                          data & (1<<5)? ", pipe A hblank wait": "",
 
216
                          data & (1<<3)? ", pipe A vblank wait": "",
 
217
                          data & (1<<2)? ", sprite A pending flip wait": "",
 
218
                          data & (1<<1)? ", plane A pending flip wait": "",
 
219
                          data & (1<<0)? ", plane A scan line wait": "");
 
220
        }
 
221
 
 
222
        return 1;
 
223
}
 
224
 
 
225
static int
142
226
decode_mi(struct drm_intel_decode *ctx)
143
227
{
144
228
        unsigned int opcode, len = -1;
151
235
                unsigned int min_len;
152
236
                unsigned int max_len;
153
237
                const char *name;
 
238
                int (*func)(struct drm_intel_decode *ctx);
154
239
        } opcodes_mi[] = {
155
240
                { 0x08, 0, 1, 1, "MI_ARB_ON_OFF" },
156
241
                { 0x0a, 0, 1, 1, "MI_BATCH_BUFFER_END" },
164
249
                { 0x00, 0, 1, 1, "MI_NOOP" },
165
250
                { 0x11, 0x3f, 2, 2, "MI_OVERLAY_FLIP" },
166
251
                { 0x07, 0, 1, 1, "MI_REPORT_HEAD" },
167
 
                { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT" },
 
252
                { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT", decode_MI_SET_CONTEXT },
168
253
                { 0x20, 0x3f, 3, 4, "MI_STORE_DATA_IMM" },
169
254
                { 0x21, 0x3f, 3, 4, "MI_STORE_DATA_INDEX" },
170
255
                { 0x24, 0x3f, 3, 3, "MI_STORE_REGISTER_MEM" },
171
256
                { 0x02, 0, 1, 1, "MI_USER_INTERRUPT" },
172
 
                { 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT" },
 
257
                { 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT", decode_MI_WAIT_FOR_EVENT },
173
258
                { 0x16, 0x7f, 3, 3, "MI_SEMAPHORE_MBOX" },
174
259
                { 0x26, 0x1f, 3, 4, "MI_FLUSH_DW" },
175
260
                { 0x0b, 0, 1, 1, "MI_SUSPEND_FLUSH"},
176
 
        };
 
261
        }, *opcode_mi = NULL;
177
262
 
178
263
        /* check instruction length */
179
264
        for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]);
192
277
                                                opcodes_mi[opcode].max_len);
193
278
                                }
194
279
                        }
 
280
                        opcode_mi = &opcodes_mi[opcode];
195
281
                        break;
196
282
                }
197
283
        }
198
284
 
 
285
        if (opcode_mi && opcode_mi->func)
 
286
                return opcode_mi->func(ctx);
 
287
 
199
288
        switch ((data[0] & 0x1f800000) >> 23) {
200
289
        case 0x0a:
201
290
                instr_out(ctx, 0, "MI_BATCH_BUFFER_END\n");
1625
1714
                                        }
1626
1715
                                } else {
1627
1716
                                        instr_out(ctx, i,
1628
 
                                                  "S%d: 0x%08x\n", i, data[i]);
 
1717
                                                  "S%d: 0x%08x\n", word, data[i]);
1629
1718
                                }
1630
1719
                                i++;
1631
1720
                        }
3115
3204
                { 0x7829, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_GS" },
3116
3205
                { 0x782a, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_PS" },
3117
3206
                { 0x782b, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_VS" },
 
3207
                { 0x782c, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_HS" },
 
3208
                { 0x782d, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_DS" },
3118
3209
                { 0x782e, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_GS" },
3119
3210
                { 0x782f, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_PS" },
3120
3211
                { 0x7830, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_VS },
3133
3224
                { 0x790b, 0xffff, 4, 4, "3DSTATE_GS_SVB_INDEX" },
3134
3225
                { 0x790d, 0xffff, 3, 3, "3DSTATE_MULTISAMPLE", 6 },
3135
3226
                { 0x790d, 0xffff, 4, 4, "3DSTATE_MULTISAMPLE", 7 },
3136
 
                { 0x7910, 0xffff, 2, 2, "3DSTATE_CLEAR_PARAMS" },
 
3227
                { 0x7910, 0x00ff, 2, 2, "3DSTATE_CLEAR_PARAMS" },
3137
3228
                { 0x7912, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_VS" },
 
3229
                { 0x7913, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_HS" },
 
3230
                { 0x7914, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_DS" },
 
3231
                { 0x7915, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_GS" },
3138
3232
                { 0x7916, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_PS" },
3139
3233
                { 0x7917, 0x00ff, 2, 2+128*2, "3DSTATE_SO_DECL_LIST" },
3140
3234
                { 0x7918, 0x00ff, 4, 4, "3DSTATE_SO_BUFFER" },
3312
3406
                        instr_out(ctx, i,
3313
3407
                                  "buffer %d: %svalid, type 0x%04x, "
3314
3408
                                  "src offset 0x%04x bytes\n",
3315
 
                                  data[i] >> (IS_GEN6(devid) ? 26 : 27),
3316
 
                                  data[i] & (1 << (IS_GEN6(devid) ? 25 : 26)) ?
 
3409
                                  data[i] >> ((IS_GEN6(devid) || IS_GEN7(devid)) ? 26 : 27),
 
3410
                                  data[i] & (1 << ((IS_GEN6(devid) || IS_GEN7(devid)) ? 25 : 26)) ?
3317
3411
                                  "" : "in", (data[i] >> 16) & 0x1ff,
3318
3412
                                  data[i] & 0x07ff);
3319
3413
                        i++;