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Viewing changes to arch/arm/common/gic.c

  • Committer: Bazaar Package Importer
  • Author(s): John Rigby, John Rigby
  • Date: 2011-03-18 07:36:33 UTC
  • mfrom: (5.1.1 upstream)
  • Revision ID: james.westby@ubuntu.com-20110318073633-tqfe9391ct71zb2p
Tags: 2.6.38-1001.2
https://launchpad.net/bugs/724377
https://launchpad.net/bugs/728603
https://launchpad.net/bugs/720055
https://launchpad.net/bugs/718677
https://launchpad.net/bugs/708883
https://launchpad.net/bugs/723159
https://launchpad.net/bugs/736429
[ John Rigby ]

* Rebase to new upstreams:
  Linux v2.6.38-rc6 -- same
  linaro-linux-2.6.38-upstream-1Mar2011 -- new
  Ubuntu-2.6.38-5.32 -- same
  - LP: #724377
* Enable CONFIG_THUMB2_KERNEL for OMAP[34]
* Bump ABI
* Rebase to new upstreams:
  Linux v2.6.38-rc7
  linaro-linux-2.6.38-upstream-4Mar2011
  ubuntu-natty master-next as of 4Mar2011
* Re-enable display on OMAP4
* Disable CONFIG_OMAP2_DSS_SDI
  - LP: #728603
  - LP: #720055
* Rebase to new upstreams:
  Linux v2.6.38-rc8
  linaro-linux-2.6.38-upstream-9Mar2011
    rebased to 2.6.38-rc8
* Remove generated file kernel-versions and sort kernel-versions.in
* Enable CONFIG_TIMER_STATS
  - LP: #718677
* Rebase to new upstreams:
  Linux v2.6.38 final
  linaro-linux-2.6.38-upstream-16Mar2011
  - LP: #708883
  - LP: #723159
  ubuntu-natty Ubuntu-2.6.38-7.35
* Enable CONFIG_IP_PNP and CONFIG_ROOT_NFS for all flavours
  - LP: #736429
* mach-ux500: fix build error
  workaround a problem in linux-linaro-2.6.38
* OMAP4:Fix -EINVAL for vana, vcxio, vdac
  from omap-linux mailing list pending ack
* turn off ROOT_NFS for mx51
  it makes the kernel too large to boot with current hwpack settings

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Lines of Context:
arch/arm/common/gic.c
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        void __iomem *cpu_base;
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};
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/*
 
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 * Supported arch specific GIC irq extension.
 
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 * Default make them NULL.
 
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 */
 
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struct irq_chip gic_arch_extn = {
 
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        .irq_ack        = NULL,
 
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        .irq_mask       = NULL,
 
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        .irq_unmask     = NULL,
 
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        .irq_retrigger  = NULL,
 
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        .irq_set_type   = NULL,
 
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        .irq_set_wake   = NULL,
 
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};
 
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#ifndef MAX_GIC_NR
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#define MAX_GIC_NR      1
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#endif
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static void gic_ack_irq(struct irq_data *d)
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{
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        spin_lock(&irq_controller_lock);
 
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        if (gic_arch_extn.irq_ack)
 
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                gic_arch_extn.irq_ack(d);
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        writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
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        spin_unlock(&irq_controller_lock);
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}
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        spin_lock(&irq_controller_lock);
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        writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
 
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        if (gic_arch_extn.irq_mask)
 
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                gic_arch_extn.irq_mask(d);
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        spin_unlock(&irq_controller_lock);
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}
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        u32 mask = 1 << (d->irq % 32);
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        spin_lock(&irq_controller_lock);
 
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        if (gic_arch_extn.irq_unmask)
 
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                gic_arch_extn.irq_unmask(d);
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        writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
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        spin_unlock(&irq_controller_lock);
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}
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        spin_lock(&irq_controller_lock);
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        if (gic_arch_extn.irq_set_type)
 
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                gic_arch_extn.irq_set_type(d, type);
 
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        val = readl(base + GIC_DIST_CONFIG + confoff);
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        if (type == IRQ_TYPE_LEVEL_HIGH)
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                val &= ~confmask;
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        return 0;
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}
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static int gic_retrigger(struct irq_data *d)
 
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{
 
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        if (gic_arch_extn.irq_retrigger)
 
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                return gic_arch_extn.irq_retrigger(d);
 
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        return -ENXIO;
 
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}
 
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#ifdef CONFIG_SMP
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static int
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gic_set_cpu(struct irq_data *d, const struct cpumask *mask_val, bool force)
 
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static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 
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                            bool force)
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{
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        void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
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        unsigned int shift = (d->irq % 4) * 8;
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        unsigned int cpu = cpumask_first(mask_val);
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        u32 val;
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        struct irq_desc *desc;
 
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        u32 val, mask, bit;
 
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        if (cpu >= 8)
 
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                return -EINVAL;
 
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        mask = 0xff << shift;
 
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        bit = 1 << (cpu + shift);
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        spin_lock(&irq_controller_lock);
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        desc = irq_to_desc(d->irq);
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        if (desc == NULL) {
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                spin_unlock(&irq_controller_lock);
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                return -EINVAL;
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        }
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        d->node = cpu;
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        val = readl(reg) & ~(0xff << shift);
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        val |= 1 << (cpu + shift);
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        writel(val, reg);
 
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        val = readl(reg) & ~mask;
 
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        writel(val | bit, reg);
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        spin_unlock(&irq_controller_lock);
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        return 0;
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}
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#endif
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#ifdef CONFIG_PM
 
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static int gic_set_wake(struct irq_data *d, unsigned int on)
 
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{
 
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        int ret = -ENXIO;
 
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        if (gic_arch_extn.irq_set_wake)
 
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                ret = gic_arch_extn.irq_set_wake(d, on);
 
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        return ret;
 
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}
 
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#else
 
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#define gic_set_wake    NULL
 
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#endif
 
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static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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        struct gic_chip_data *chip_data = get_irq_data(irq);
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        .irq_mask               = gic_mask_irq,
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        .irq_unmask             = gic_unmask_irq,
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        .irq_set_type           = gic_set_type,
 
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        .irq_retrigger          = gic_retrigger,
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#ifdef CONFIG_SMP
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        .irq_set_affinity       = gic_set_cpu,
 
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        .irq_set_affinity       = gic_set_affinity,
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#endif
 
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        .irq_set_wake           = gic_set_wake,
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};
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void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)