24
23
def M : InstrItinClass;
25
24
def ST : InstrItinClass;
26
25
def S : InstrItinClass;
26
def SYS : InstrItinClass;
27
def MARKER : InstrItinClass;
27
28
def PSEUDO : InstrItinClass;
30
30
def HexagonItineraries :
31
ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [
32
InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
33
InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,
34
InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,
35
InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,
36
InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,
37
InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,
38
InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,
39
InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,
40
InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,
41
InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>
31
ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [
32
InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
33
InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,
34
InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,
35
InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,
36
InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,
37
InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,
38
InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,
39
InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,
40
InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,
41
InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>,
42
InstrItinData<MARKER , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
43
InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>
45
46
//===----------------------------------------------------------------------===//
46
47
// V4 Machine Info +