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/*********************************************************
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* Copyright (C) 1998-2004 VMware, Inc. All rights reserved.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation version 2 and no later version.
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*********************************************************/
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* vm_basic_asm_x86_64.h
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* Basic x86_64 asm macros.
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#ifndef _VM_BASIC_ASM_X86_64_H_
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#define _VM_BASIC_ASM_X86_64_H_
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#define INCLUDE_ALLOW_USERLEVEL
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#define INCLUDE_ALLOW_VMMEXT
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#define INCLUDE_ALLOW_MODULE
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#define INCLUDE_ALLOW_VMMON
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#define INCLUDE_ALLOW_VMK_MODULE
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#define INCLUDE_ALLOW_VMKERNEL
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#define INCLUDE_ALLOW_DISTRIBUTE
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#define INCLUDE_ALLOW_VMCORE
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#define INCLUDE_ALLOW_VMNIXMOD
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#include "includeCheck.h"
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#error "This file is x86-64 only!"
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uint64 _umul128(uint64 multiplier, uint64 multiplicand,
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int64 _mul128(int64 multiplier, int64 multiplicand,
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uint64 __shiftright128(uint64 lowPart, uint64 highPart, uint8 shift);
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#pragma intrinsic(_umul128, _mul128, __shiftright128)
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* save/restore SIMD/MMX fpu state
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* The pointer passed in must be 16-byte aligned.
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* Intel and AMD processors behave differently w.r.t. fxsave/fxrstor. Intel
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* processors unconditionally save the exception pointer state (instruction
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* ptr., data ptr., and error instruction opcode). FXSAVE_ES1 and FXRSTOR_ES1
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* work correctly for Intel processors.
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* AMD processors only save the exception pointer state if ES=1. This leads to a
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* security hole whereby one process/VM can inspect the state of another process
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* VM. The AMD recommended workaround involves clobbering the exception pointer
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* state unconditionally, and this is implemented in FXRSTOR_AMD_ES0. Note that
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* FXSAVE_ES1 will only save the exception pointer state for AMD processors if
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* The workaround (FXRSTOR_AMD_ES0) only costs 1 cycle more than just doing an
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* fxrstor, on both AMD Opteron and Intel Core CPUs.
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FXSAVE_ES1(uint8 *save)
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__asm__ __volatile__ ("fxsaveq %0 \n" : "=m" (*save) : : "memory");
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FXSAVE_COMPAT_ES1(uint8 *save)
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__asm__ __volatile__ ("fxsave %0 \n" : "=m" (*save) : : "memory");
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FXRSTOR_ES1(const uint8 *load)
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__asm__ __volatile__ ("fxrstorq %0 \n" : : "m" (*load) : "memory");
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FXRSTOR_COMPAT_ES1(const uint8 *load)
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__asm__ __volatile__ ("fxrstor %0 \n" : : "m" (*load) : "memory");
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FXRSTOR_AMD_ES0(const uint8 *load)
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("fnstsw %%ax \n" // Grab x87 ES bit
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"bt $7,%%ax \n" // Test ES bit
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"jnc 1f \n" // Jump if ES=0
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"fnclex \n" // ES=1. Clear it so fild doesn't trap
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"ffree %%st(7) \n" // Clear tag bit - avoid poss. stack overflow
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"fildl %0 \n" // Dummy Load from "safe address" changes all
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// x87 exception pointers.
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: "m" (dummy), "m" (*load)
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#endif /* __GNUC__ */
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*-----------------------------------------------------------------------------
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* Unsigned integer by fixed point multiplication:
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* result = multiplicand * multiplier >> shift
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* Unsigned 64-bit integer multiplicand.
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* Unsigned 32-bit fixed point multiplier, represented as
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* multiplier >> shift, where shift < 64.
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* Unsigned 64-bit integer product.
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* Multiply 64x64 bits to yield a full 128-bit product.
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* Shift result in RDX:RAX right by "shift".
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* Return the low-order 64 bits of the above.
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*-----------------------------------------------------------------------------
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#if defined(__GNUC__)
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Mul64x3264(uint64 multiplicand,
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uint64 result, dummy;
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const uint64 multiplier64 = multiplier;
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__asm__("mulq %3 \n\t"
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: "0" (multiplier64),
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#elif defined(_MSC_VER)
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Mul64x3264(uint64 multiplicand, uint32 multiplier, uint32 shift)
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tmplo = _umul128(multiplicand, multiplier, &tmphi);
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return __shiftright128(tmplo, tmphi, (uint8) shift);
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*-----------------------------------------------------------------------------
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* Signed integer by fixed point multiplication:
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* result = multiplicand * multiplier >> shift
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* Signed 64-bit integer multiplicand.
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* Unsigned 32-bit fixed point multiplier, represented as
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* multiplier >> shift, where shift < 64.
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* Signed 64-bit integer product.
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* Multiply 64x64 bits to yield a full 128-bit product.
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* Shift result in RDX:RAX right by "shift".
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* Return the low-order 64 bits of the above.
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* Note: using an unsigned shift instruction is correct because
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* shift < 64 and we return only the low 64 bits of the shifted
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*-----------------------------------------------------------------------------
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#if defined(__GNUC__)
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Muls64x32s64(int64 multiplicand, uint32 multiplier, uint32 shift)
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const int64 multiplier64 = multiplier;
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__asm__("imulq %3 \n\t"
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: "0" (multiplier64),
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#elif defined(_MSC_VER)
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Muls64x32s64(int64 multiplicand, uint32 multiplier, uint32 shift)
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tmplo = _mul128(multiplicand, multiplier, &tmphi);
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return __shiftright128(tmplo, tmphi, (uint8) shift);
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#if defined(__GNUC__)
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uint64set(void *dst, uint64 val, uint64 count)
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__asm__ __volatile__("\t"
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: "=c" (dummy0), "=D" (dummy1)
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: "0" (count), "1" (dst), "a" (val)
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*-----------------------------------------------------------------------------
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* Unsigned integer division:
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* The dividend is 64-bit wide
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* The divisor is 32-bit wide
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* The quotient is 32-bit wide
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* Use this function if you are certain that the quotient will fit in 32 bits,
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* If that is not the case, a #DE exception was generated in 32-bit version,
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* but not in this 64-bit version. So please be careful.
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* Quotient and remainder
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*-----------------------------------------------------------------------------
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#if defined(__GNUC__) || defined(_MSC_VER)
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Div643232(uint64 dividend, // IN
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uint32 divisor, // IN
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uint32 *quotient, // OUT
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uint32 *remainder) // OUT
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*quotient = (uint32)(dividend / divisor);
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*remainder = (uint32)(dividend % divisor);
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*-----------------------------------------------------------------------------
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* Unsigned integer division:
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* The dividend is 64-bit wide
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* The divisor is 32-bit wide
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* The quotient is 64-bit wide
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* Quotient and remainder
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*-----------------------------------------------------------------------------
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#if defined(__GNUC__)
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Div643264(uint64 dividend, // IN
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uint32 divisor, // IN
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uint64 *quotient, // OUT
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uint32 *remainder) // OUT
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*quotient = dividend / divisor;
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*remainder = dividend % divisor;
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#endif // _VM_BASIC_ASM_X86_64_H_
added
removed
modules/linux/vsock/include/vm_basic_asm_x86_64.h
