1
/* Copyright (c) 2009 Atmel Corporation
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id: iotn861a.h,v 1.1.2.2 2009/11/18 22:06:28 arcanum Exp $ */
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/* avr/iotn861a.h - definitions for ATtiny861A */
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/* This file should only be included from <avr/io.h>, never directly. */
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# error "Include <avr/io.h> instead of this file."
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# define _AVR_IOXXX_H_ "iotn861a.h"
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# error "Attempt to include more than one <avr/ioXXX.h> file."
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#ifndef _AVR_ATtiny861A_H_
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#define _AVR_ATtiny861A_H_ 1
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/* Registers and associated bit numbers. */
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#define TCCR1E _SFR_IO8(0x00)
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#define DIDR0 _SFR_IO8(0x01)
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#define DIDR1 _SFR_IO8(0x02)
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#define ADCSRB _SFR_IO8(0x03)
89
#define ADC _SFR_IO16(0x04)
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#define ADCW _SFR_IO16(0x04)
93
#define ADCL _SFR_IO8(0x04)
103
#define ADCH _SFR_IO8(0x05)
113
#define ADCSRA _SFR_IO8(0x06)
123
#define ADMUX _SFR_IO8(0x07)
133
#define ACSRA _SFR_IO8(0x08)
143
#define ACSRB _SFR_IO8(0x09)
150
#define GPIOR0 _SFR_IO8(0x0A)
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#define GPIOR1 _SFR_IO8(0x0B)
170
#define GPIOR2 _SFR_IO8(0x0C)
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#define USICR _SFR_IO8(0x0D)
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#define USISR _SFR_IO8(0x0E)
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#define USIDR _SFR_IO8(0x0F)
210
#define USIBR _SFR_IO8(0x10)
220
#define USIPP _SFR_IO8(0x11)
223
#define OCR0B _SFR_IO8(0x12)
233
#define OCR0A _SFR_IO8(0x13)
243
#define TCNT0H _SFR_IO8(0x14)
253
#define TCCR0A _SFR_IO8(0x15)
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#define PINB _SFR_IO8(0x16)
271
#define DDRB _SFR_IO8(0x17)
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#define PORTB _SFR_IO8(0x18)
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#define PINA _SFR_IO8(0x19)
301
#define DDRA _SFR_IO8(0x1A)
311
#define PORTA _SFR_IO8(0x1B)
321
#define EECR _SFR_IO8(0x1C)
329
#define EEDR _SFR_IO8(0x1D)
339
#define EEAR _SFR_IO16(0x1E)
341
#define EEARL _SFR_IO8(0x1E)
351
#define EEARH _SFR_IO8(0x1F)
354
#define DWDR _SFR_IO8(0x20)
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#define WDTCR _SFR_IO8(0x21)
374
#define PCMSK1 _SFR_IO8(0x22)
384
#define PCMSK0 _SFR_IO8(0x23)
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#define DT1 _SFR_IO8(0x24)
404
#define TC1H _SFR_IO8(0x25)
408
#define TCCR1D _SFR_IO8(0x26)
418
#define TCCR1C _SFR_IO8(0x27)
428
#define CLKPR _SFR_IO8(0x28)
435
#define PLLCSR _SFR_IO8(0x29)
441
#define OCR1D _SFR_IO8(0x2A)
451
#define OCR1C _SFR_IO8(0x2B)
461
#define OCR1B _SFR_IO8(0x2C)
471
#define OCR1A _SFR_IO8(0x2D)
481
#define TCNT1 _SFR_IO8(0x2E)
491
#define TCCR1B _SFR_IO8(0x2F)
500
#define TCCR1A _SFR_IO8(0x30)
510
#define OSCCAL _SFR_IO8(0x31)
520
#define TCNT0L _SFR_IO8(0x32)
530
#define TCCR0B _SFR_IO8(0x33)
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#define MCUSR _SFR_IO8(0x34)
543
#define MCUCR _SFR_IO8(0x35)
553
#define PRR _SFR_IO8(0x36)
559
#define SPMCSR _SFR_IO8(0x37)
566
#define TIFR _SFR_IO8(0x38)
576
#define TIMSK _SFR_IO8(0x39)
586
#define GIFR _SFR_IO8(0x3A)
591
#define GIMSK _SFR_IO8(0x3B)
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/* Interrupt vectors */
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/* Vector 0 is the reset vector */
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#define INT0_vect_num 1
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#define INT0_vect _VECTOR(1) /* External Interrupt 0 */
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#define PCINT_vect_num 2
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#define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */
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#define TIMER1_COMPA_vect_num 3
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#define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */
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#define TIMER1_COMPB_vect_num 4
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#define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */
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#define TIMER1_OVF_vect_num 5
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#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */
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#define TIMER0_OVF_vect_num 6
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#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */
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#define USI_START_vect_num 7
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#define USI_START_vect _VECTOR(7) /* USI Start */
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#define USI_OVF_vect_num 8
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#define USI_OVF_vect _VECTOR(8) /* USI Overflow */
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#define EE_RDY_vect_num 9
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#define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */
618
#define ANA_COMP_vect_num 10
619
#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */
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#define ADC_vect_num 11
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#define ADC_vect _VECTOR(11) /* ADC Conversion Complete */
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#define WDT_vect_num 12
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#define WDT_vect _VECTOR(12) /* Watchdog Time-Out */
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#define INT1_vect_num 13
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#define INT1_vect _VECTOR(13) /* External Interrupt 1 */
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#define TIMER0_COMPA_vect_num 14
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#define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */
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#define TIMER0_COMPB_vect_num 15
629
#define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */
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#define TIMER0_CAPT_vect_num 16
631
#define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */
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#define TIMER1_COMPD_vect_num 17
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#define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */
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#define FAULT_PROTECTION_vect_num 18
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#define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */
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#define _VECTOR_SIZE 2 /* Size of individual vector. */
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#define _VECTORS_SIZE (19 * _VECTOR_SIZE)
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#define SPM_PAGESIZE (64)
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#define RAMSTART (0x60)
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#define RAMSIZE (512)
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#define RAMEND (RAMSTART + RAMSIZE - 1)
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#define XRAMSTART (NA)
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#define XRAMEND (RAMEND)
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#define E2END (0x1FF)
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#define E2PAGESIZE (4)
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#define FLASHEND (0x1FFF)
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#define FUSE_MEMORY_SIZE 3
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#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */
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#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */
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#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */
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#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */
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#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
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#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
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#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */
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#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
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#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
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#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
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#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
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#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
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#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */
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#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */
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#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */
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#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */
676
#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */
677
#define HFUSE_DEFAULT (FUSE_SPIEN)
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/* Extended Fuse Byte */
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#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */
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#define EFUSE_DEFAULT (0xFF)
685
#define __LOCK_BITS_EXIST
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#define SIGNATURE_0 0x1E
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#define SIGNATURE_1 0x93
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#define SIGNATURE_2 0x0D
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/* Device Pin Definitions */
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#define DI_B_DDR DDRMOSI
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#define DI_B_PORT PORTMOSI
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#define DI_B_PIN PINMOSI
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#define DI_B_BIT MOSI
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#define SDA_B_DDR DDRMOSI
701
#define SDA_B_PORT PORTMOSI
702
#define SDA_B_PIN PINMOSI
703
#define SDA_B_BIT MOSI
705
#define _OC1A_DDR DDRMOSI
706
#define _OC1A_PORT PORTMOSI
707
#define _OC1A_PIN PINMOSI
708
#define _OC1A_BIT MOSI
710
#define PCINT8_DDR DDRMOSI
711
#define PCINT8_PORT PORTMOSI
712
#define PCINT8_PIN PINMOSI
713
#define PCINT8_BIT MOSI
715
#define PB0_DDR DDRMOSI
716
#define PB0_PORT PORTMOSI
717
#define PB0_PIN PINMOSI
720
#define DO_B_DDR DDRMISO
721
#define DO_B_PORT PORTMISO
722
#define DO_B_PIN PINMISO
723
#define DO_B_BIT MISO
725
#define OC1A_DDR DDRMISO
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#define OC1A_PORT PORTMISO
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#define OC1A_PIN PINMISO
728
#define OC1A_BIT MISO
730
#define PCINT9_DDR DDRMISO
731
#define PCINT9_PORT PORTMISO
732
#define PCINT9_PIN PINMISO
733
#define PCINT9_BIT MISO
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#define PB1_DDR DDRMISO
736
#define PB1_PORT PORTMISO
737
#define PB1_PIN PINMISO
740
#define USCK_B_DDR DDRSCK
741
#define USCK_B_PORT PORTSCK
742
#define USCK_B_PIN PINSCK
743
#define USCK_B_BIT SCK
745
#define SCL_B_DDR DDRSCK
746
#define SCL_B_PORT PORTSCK
747
#define SCL_B_PIN PINSCK
748
#define SCL_B_BIT SCK
750
#define OC1B_DDR DDRSCK
751
#define OC1B_PORT PORTSCK
752
#define OC1B_PIN PINSCK
755
#define PCINT10_DDR DDRSCK
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#define PCINT10_PORT PORTSCK
757
#define PCINT10_PIN PINSCK
758
#define PCINT10_BIT SCK
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#define PB2_DDR DDRSCK
761
#define PB2_PORT PORTSCK
762
#define PB2_PIN PINSCK
765
#define PCINT11_DDR DDROC1B
766
#define PCINT11_PORT PORTOC1B
767
#define PCINT11_PIN PINOC1B
768
#define PCINT11_BIT OC1B
770
#define PB3_DDR DDROC1B
771
#define PB3_PORT PORTOC1B
772
#define PB3_PIN PINOC1B
775
#define PCINT12_DDR DDRADC
776
#define PCINT12_PORT PORTADC
777
#define PCINT12_PIN PINADC
778
#define PCINT12_BIT ADC7
780
#define _OC1D_DDR DDRADC
781
#define _OC1D_PORT PORTADC
782
#define _OC1D_PIN PINADC
783
#define _OC1D_BIT ADC7
785
#define CLKI_DDR DDRADC
786
#define CLKI_PORT PORTADC
787
#define CLKI_PIN PINADC
788
#define CLKI_BIT ADC7
790
#define PB4_DDR DDRADC
791
#define PB4_PORT PORTADC
792
#define PB4_PIN PINADC
795
#define PCINT13_DDR DDRADC
796
#define PCINT13_PORT PORTADC
797
#define PCINT13_PIN PINADC
798
#define PCINT13_BIT ADC8
800
#define OC1D_DDR DDRADC
801
#define OC1D_PORT PORTADC
802
#define OC1D_PIN PINADC
803
#define OC1D_BIT ADC8
805
#define CKLO_DDR DDRADC
806
#define CKLO_PORT PORTADC
807
#define CKLO_PIN PINADC
808
#define CKLO_BIT ADC8
810
#define PB5_DDR DDRADC
811
#define PB5_PORT PORTADC
812
#define PB5_PIN PINADC
815
#define INT0_DDR DDRADC
816
#define INT0_PORT PORTADC
817
#define INT0_PIN PINADC
818
#define INT0_BIT ADC9
820
#define T0_DDR DDRADC
821
#define T0_PORT PORTADC
822
#define T0_PIN PINADC
825
#define PCINT14_DDR DDRADC
826
#define PCINT14_PORT PORTADC
827
#define PCINT14_PIN PINADC
828
#define PCINT14_BIT ADC9
830
#define PB6_DDR DDRADC
831
#define PB6_PORT PORTADC
832
#define PB6_PIN PINADC
835
#define PCINT15_DDR DDRADC1
836
#define PCINT15_PORT PORTADC1
837
#define PCINT15_PIN PINADC1
838
#define PCINT15_BIT ADC10
840
#define PB7_DDR DDRADC1
841
#define PB7_PORT PORTADC1
842
#define PB7_PIN PINADC1
843
#define PB7_BIT ADC10
845
#define AIN1_DDR DDRADC
846
#define AIN1_PORT PORTADC
847
#define AIN1_PIN PINADC
848
#define AIN1_BIT ADC6
850
#define PCINT7_DDR DDRADC
851
#define PCINT7_PORT PORTADC
852
#define PCINT7_PIN PINADC
853
#define PCINT7_BIT ADC6
855
#define PA7_DDR DDRADC
856
#define PA7_PORT PORTADC
857
#define PA7_PIN PINADC
860
#define AIN0_DDR DDRADC
861
#define AIN0_PORT PORTADC
862
#define AIN0_PIN PINADC
863
#define AIN0_BIT ADC5
865
#define PCINT6_DDR DDRADC
866
#define PCINT6_PORT PORTADC
867
#define PCINT6_PIN PINADC
868
#define PCINT6_BIT ADC5
870
#define PA6_DDR DDRADC
871
#define PA6_PORT PORTADC
872
#define PA6_PIN PINADC
875
#define AIN2_DDR DDRADC
876
#define AIN2_PORT PORTADC
877
#define AIN2_PIN PINADC
878
#define AIN2_BIT ADC4
880
#define PCINT5_DDR DDRADC
881
#define PCINT5_PORT PORTADC
882
#define PCINT5_PIN PINADC
883
#define PCINT5_BIT ADC4
885
#define PA5_DDR DDRADC
886
#define PA5_PORT PORTADC
887
#define PA5_PIN PINADC
890
#define ICP0_DDR DDRADC
891
#define ICP0_PORT PORTADC
892
#define ICP0_PIN PINADC
893
#define ICP0_BIT ADC3
895
#define PCINT4_DDR DDRADC
896
#define PCINT4_PORT PORTADC
897
#define PCINT4_PIN PINADC
898
#define PCINT4_BIT ADC3
900
#define PA4_DDR DDRADC
901
#define PA4_PORT PORTADC
902
#define PA4_PIN PINADC
905
#define PCINT3_DDR DDRAREF
906
#define PCINT3_PORT PORTAREF
907
#define PCINT3_PIN PINAREF
908
#define PCINT3_BIT AREF
910
#define PA3_DDR DDRAREF
911
#define PA3_PORT PORTAREF
912
#define PA3_PIN PINAREF
915
#define INT1_DDR DDRADC
916
#define INT1_PORT PORTADC
917
#define INT1_PIN PINADC
918
#define INT1_BIT ADC2
920
#define USCK_A_DDR DDRADC
921
#define USCK_A_PORT PORTADC
922
#define USCK_A_PIN PINADC
923
#define USCK_A_BIT ADC2
925
#define SCL_A_DDR DDRADC
926
#define SCL_A_PORT PORTADC
927
#define SCL_A_PIN PINADC
928
#define SCL_A_BIT ADC2
930
#define PCINT2_DDR DDRADC
931
#define PCINT2_PORT PORTADC
932
#define PCINT2_PIN PINADC
933
#define PCINT2_BIT ADC2
935
#define PA2_DDR DDRADC
936
#define PA2_PORT PORTADC
937
#define PA2_PIN PINADC
940
#define DO_A_DDR DDRADC
941
#define DO_A_PORT PORTADC
942
#define DO_A_PIN PINADC
943
#define DO_A_BIT ADC1
945
#define PCINT1_DDR DDRADC
946
#define PCINT1_PORT PORTADC
947
#define PCINT1_PIN PINADC
948
#define PCINT1_BIT ADC1
950
#define PA1_DDR DDRADC
951
#define PA1_PORT PORTADC
952
#define PA1_PIN PINADC
955
#define DI_A_DDR DDRADC
956
#define DI_A_PORT PORTADC
957
#define DI_A_PIN PINADC
958
#define DI_A_BIT ADC0
960
#define SDA_A_DDR DDRADC
961
#define SDA_A_PORT PORTADC
962
#define SDA_A_PIN PINADC
963
#define SDA_A_BIT ADC0
965
#define PCINT0_DDR DDRADC
966
#define PCINT0_PORT PORTADC
967
#define PCINT0_PIN PINADC
968
#define PCINT0_BIT ADC0
970
#define PA0_DDR DDRADC
971
#define PA0_PORT PORTADC
972
#define PA0_PIN PINADC
975
#endif /* _AVR_ATtiny861A_H_ */
added
removed
include/avr/iotn861a.h
