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Viewing changes to drivers/char/agp/intel-gtt.c

  • Committer: Package Import Robot
  • Author(s): Tim Gardner, Tim Gardner, Andy Whitcroft, James M Leddy, Paolo Pisati, Stefan Bader, Upstream Kernel Changes, Wen-chien Jesse Sung, David Henningsson, Leann Ogasawara, Rob Herring, git at e4ward
  • Date: 2012-10-09 15:40:14 UTC
  • Revision ID: package-import@ubuntu.com-20121009154014-iktauc26lb0l5alw
Tags: 3.5.0-213.20
[ Tim Gardner ]

* rebased on Ubuntu-3.5.0-17.28

[ Andy Whitcroft ]

* [packaging] we already have a valid src_pkg_name
* [packaging] allow us to select which builds have uefi signed versions

[ James M Leddy ]

* SAUCE: input: fix weird issue of synaptics psmouse sync lost after
  resume
  - LP: #717970

[ Paolo Pisati ]

* SAUCE: omap3 clocks .dev_id = NULL
  - LP: #1061599
* [Config] omap: disable USB_[EHCI|OHCI]_HCD_PLATFORM
  - LP: #1061599
* [Config] omap: enforce USB_[EHCI|OHCI]_HCD_PLATFORM=n
  - LP: #1061599

[ Stefan Bader ]

* SAUCE: net/ipv4: Always flush route cache on unregister batch call
  - LP: #1021471

[ Upstream Kernel Changes ]

* Bluetooth: Add USB_VENDOR_AND_INTERFACE_INFO() for Broadcom/Foxconn
  - LP: #1030233

[ Wen-chien Jesse Sung ]

* SAUCE: Bluetooth: Remove rules for matching Broadcom vendor specific
  IDs
  - LP: #1030233

[ Andy Whitcroft ]

* [packaging] add custom upload for the kernel binary package

[ David Henningsson ]

* SAUCE: ALSA: hda - fix indices on boost volume on Conexant
  - LP: #1059523

[ Leann Ogasawara ]

* [Config] Build in CONFIG_X86_PCC_CPUFREQ=y
  - LP: #1061126

[ Rob Herring ]

* Revert "SAUCE: ahci_platform: add custom hard reset for Calxeda ahci
  ctrlr"
  - LP: #1059432
* Revert "SAUCE: net: calxedaxgmac: add write barriers around setting
  owner bit"
  - LP: #1059432
* Revert "SAUCE: ARM: highbank: use writel_relaxed variant for pwr
  requests"
  - LP: #1059432
* Revert "SAUCE: force DMA buffers to non-bufferable on highbank"
  - LP: #1059432
* Revert "SAUCE: input: add a key driver for highbank"
  - LP: #1059432
* [Config] Align highbank config with amd64-generic and add new configs
  - LP: #1059432
* SAUCE: net: calxedaxgmac: enable operate on 2nd frame mode
  - LP: #1059432
* SAUCE: net: calxedaxgmac: remove explicit rx dma buffer polling
  - LP: #1059432
* SAUCE: net: calxedaxgmac: use relaxed i/o accessors in rx and tx paths
  - LP: #1059432
* SAUCE: net: calxedaxgmac: drop some unnecessary register writes
  - LP: #1059432
* SAUCE: net: calxedaxgmac: rework transmit ring handling
  - LP: #1059432
* SAUCE: ARM: highbank: retry wfi on reset request
  - LP: #1059432

[ Tim Gardner ]

* [Config] TIDSPBRIDGE=m
  - LP: #1058022
* rebase to v3.5.5

[ Upstream Kernel Changes ]

* common: DMA-mapping: add DMA_ATTR_NO_KERNEL_MAPPING attribute
  - LP: #1059432
* common: DMA-mapping: add DMA_ATTR_SKIP_CPU_SYNC attribute
  - LP: #1059432
* ARM: dma-mapping: add support for DMA_ATTR_SKIP_CPU_SYNC attribute
  - LP: #1059432
* ARM: add coherent dma ops
  - LP: #1059432
* ARM: add coherent iommu dma ops
  - LP: #1059432
* ARM: highbank: add coherent DMA setup
  - LP: #1059432
* sata: add platform driver for Calxeda AHCI controller
  - LP: #1059432
* xhci: Rate-limit XHCI_TRUST_TX_LENGTH quirk warning.
  - LP: #1039478
* agp/intel-gtt: remove dead code
  - LP: #1011440
* drm/i915: stop using dev->agp->base
  - LP: #1011440
* agp/intel-gtt: don't require the agp bridge on setup
  - LP: #1011440
* drm/i915 + agp/intel-gtt: prep work for direct setup
  - LP: #1011440
* agp/intel-gtt: move gart base addres setup
  - LP: #1011440
* drm/i915: don't use dev->agp
  - LP: #1011440
* drm/i915: disable drm agp support for !gen3 with kms enabled
  - LP: #1011440
* agp/intel-agp: remove snb+ host bridge pciids
  - LP: #1011440
* rebase to v3.5.5
  - LP: #1000424

[ git@status.e4ward.com ]

* SAUCE: input: Cypress PS/2 Trackpad fix multi-source, double-click
  - LP: #1055788

[ Tim Gardner ]

* [Config] revert '[Config] enable CONFIG_X86_X32=y'
  - LP: #1041883

[ Upstream Kernel Changes ]

* vmwgfx: corruption in vmw_event_fence_action_create()
* drm/nvd0/disp: hopefully fix selection of 6/8bpc mode on DP outputs
  - LP: #1058088
* drm/nv50-/gpio: initialise to vbios defaults during init
  - LP: #1058088
* igb: A fix to VF TX rate limit
  - LP: #1058188
* igb: Add switch case for supported hardware to igb_ptp_remove.
  - LP: #1058188
* igb: Support the get_ts_info ethtool method.
  - LP: #1058188
* igb: Streamline RSS queue and queue pairing assignment logic.
  - LP: #1058188
* igb: Update firmware info output
  - LP: #1058188
* igb: Version bump
  - LP: #1058188
* igb: reset PHY in the link_up process to recover PHY setting after
  power down.
  - LP: #1058188
* igb: Fix for failure to init on some 82576 devices.
  - LP: #1058188
* igb: correct hardware type (i210/i211) check in igb_loopback_test()
  - LP: #1058188
* igb: don't break user visible strings over multiple lines in
  igb_ethtool.c
  - LP: #1058188
* igb: add delay to allow igb loopback test to succeed on 8086:10c9
  - LP: #1058188
* igb: fix panic while dumping packets on Tx hang with IOMMU
  - LP: #1058188
* igb: Fix register defines for all non-82575 hardware
  - LP: #1058188
* e1000e: use more informative logging macros when netdev not yet
  registered
  - LP: #1058219
* e1000e: Cleanup code logic in e1000_check_for_serdes_link_82571()
  - LP: #1058219
* e1000e: Program the correct register for ITR when using MSI-X.
  - LP: #1058219
* e1000e: advertise transmit time stamping
  - LP: #1058219
* e1000e: 82571 Tx Data Corruption during Tx hang recovery
  - LP: #1058219
* e1000e: fix panic while dumping packets on Tx hang with IOMMU
  - LP: #1058219
* e1000: Combining Bitwise OR in one expression.
  - LP: #1058221
* e1000: advertise transmit time stamping
  - LP: #1058221
* e1000: Small packets may get corrupted during padding by HW
  - LP: #1058221
* sched: Fix migration thread runtime bogosity
  - LP: #1057593
* ACER: Add support for accelerometer sensor
  - LP: #1055433
* ACER: Fix Smatch double-free issue
  - LP: #1055433

[ Wen-chien Jesse Sung ]

* SAUCE: HID: ntrig: change default value of logical/physical
  width/height to 1
  - LP: #1044248

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added added

removed removed

Lines of Context:
66
66
        struct pci_dev *bridge_dev;
67
67
        u8 __iomem *registers;
68
68
        phys_addr_t gtt_bus_addr;
69
 
        phys_addr_t gma_bus_addr;
70
69
        u32 PGETBL_save;
71
70
        u32 __iomem *gtt;               /* I915G */
72
71
        bool clear_fake_agp; /* on first access via agp, fill with scratch */
76
75
        struct resource ifp_resource;
77
76
        int resource_valid;
78
77
        struct page *scratch_page;
 
78
        int refcount;
79
79
} intel_private;
80
80
 
81
81
#define INTEL_GTT_GEN   intel_private.driver->gen
648
648
 
649
649
static int intel_gtt_init(void)
650
650
{
 
651
        u32 gma_addr;
651
652
        u32 gtt_map_size;
652
653
        int ret;
653
654
 
694
695
                return ret;
695
696
        }
696
697
 
 
698
        if (INTEL_GTT_GEN <= 2)
 
699
                pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
 
700
                                      &gma_addr);
 
701
        else
 
702
                pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
 
703
                                      &gma_addr);
 
704
 
 
705
        intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
 
706
 
697
707
        return 0;
698
708
}
699
709
 
769
779
 
770
780
static bool intel_enable_gtt(void)
771
781
{
772
 
        u32 gma_addr;
773
782
        u8 __iomem *reg;
774
783
 
775
 
        if (INTEL_GTT_GEN <= 2)
776
 
                pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
777
 
                                      &gma_addr);
778
 
        else
779
 
                pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
780
 
                                      &gma_addr);
781
 
 
782
 
        intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
783
 
 
784
784
        if (INTEL_GTT_GEN >= 6)
785
785
            return true;
786
786
 
860
860
            return -EIO;
861
861
 
862
862
        intel_private.clear_fake_agp = true;
863
 
        agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
 
863
        agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr;
864
864
 
865
865
        return 0;
866
866
}
1581
1581
        return 1;
1582
1582
}
1583
1583
 
1584
 
int intel_gmch_probe(struct pci_dev *pdev,
1585
 
                                      struct agp_bridge_data *bridge)
 
1584
int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
 
1585
                     struct agp_bridge_data *bridge)
1586
1586
{
1587
1587
        int i, mask;
1588
 
        intel_private.driver = NULL;
 
1588
 
 
1589
        /*
 
1590
         * Can be called from the fake agp driver but also directly from
 
1591
         * drm/i915.ko. Hence we need to check whether everything is set up
 
1592
         * already.
 
1593
         */
 
1594
        if (intel_private.driver) {
 
1595
                intel_private.refcount++;
 
1596
                return 1;
 
1597
        }
1589
1598
 
1590
1599
        for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1591
 
                if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
 
1600
                if (gpu_pdev) {
 
1601
                        if (gpu_pdev->device ==
 
1602
                            intel_gtt_chipsets[i].gmch_chip_id) {
 
1603
                                intel_private.pcidev = pci_dev_get(gpu_pdev);
 
1604
                                intel_private.driver =
 
1605
                                        intel_gtt_chipsets[i].gtt_driver;
 
1606
 
 
1607
                                break;
 
1608
                        }
 
1609
                } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1592
1610
                        intel_private.driver =
1593
1611
                                intel_gtt_chipsets[i].gtt_driver;
1594
1612
                        break;
1598
1616
        if (!intel_private.driver)
1599
1617
                return 0;
1600
1618
 
1601
 
        bridge->driver = &intel_fake_agp_driver;
1602
 
        bridge->dev_private_data = &intel_private;
1603
 
        bridge->dev = pdev;
1604
 
 
1605
 
        intel_private.bridge_dev = pci_dev_get(pdev);
1606
 
 
1607
 
        dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
 
1619
        intel_private.refcount++;
 
1620
 
 
1621
        if (bridge) {
 
1622
                bridge->driver = &intel_fake_agp_driver;
 
1623
                bridge->dev_private_data = &intel_private;
 
1624
                bridge->dev = bridge_pdev;
 
1625
        }
 
1626
 
 
1627
        intel_private.bridge_dev = pci_dev_get(bridge_pdev);
 
1628
 
 
1629
        dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1608
1630
 
1609
1631
        mask = intel_private.driver->dma_mask_size;
1610
1632
        if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1614
1636
                pci_set_consistent_dma_mask(intel_private.pcidev,
1615
1637
                                            DMA_BIT_MASK(mask));
1616
1638
 
1617
 
        /*if (bridge->driver == &intel_810_driver)
1618
 
                return 1;*/
 
1639
        if (intel_gtt_init() != 0) {
 
1640
                intel_gmch_remove();
1619
1641
 
1620
 
        if (intel_gtt_init() != 0)
1621
1642
                return 0;
 
1643
        }
1622
1644
 
1623
1645
        return 1;
1624
1646
}
1637
1659
}
1638
1660
EXPORT_SYMBOL(intel_gtt_chipset_flush);
1639
1661
 
1640
 
void intel_gmch_remove(struct pci_dev *pdev)
 
1662
void intel_gmch_remove(void)
1641
1663
{
 
1664
        if (--intel_private.refcount)
 
1665
                return;
 
1666
 
1642
1667
        if (intel_private.pcidev)
1643
1668
                pci_dev_put(intel_private.pcidev);
1644
1669
        if (intel_private.bridge_dev)
1645
1670
                pci_dev_put(intel_private.bridge_dev);
 
1671
        intel_private.driver = NULL;
1646
1672
}
1647
1673
EXPORT_SYMBOL(intel_gmch_remove);
1648
1674