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Viewing changes to drivers/gpu/drm/radeon/si.c

  • Committer: Package Import Robot
  • Author(s): Paolo Pisati, Paolo Pisati, Ubuntu: 3.5.0-25.38
  • Date: 2013-02-20 22:03:31 UTC
  • mfrom: (74.1.1 quantal-proposed)
  • Revision ID: package-import@ubuntu.com-20130220220331-0ea4l33x3cr61nch
Tags: 3.5.0-220.28
https://launchpad.net/bugs/1130311
https://launchpad.net/bugs/1129472
https://launchpad.net/bugs/1119885
https://launchpad.net/bugs/1129192
https://launchpad.net/bugs/1119885
https://launchpad.net/bugs/1129192
https://launchpad.net/bugs/1119885
https://launchpad.net/bugs/1129192
* Release Tracking Bug
  - LP: #1130311

[ Paolo Pisati ]

* rebased on Ubuntu-3.5.0-25.38

[ Ubuntu: 3.5.0-25.38 ]

* Release Tracking Bug
  - LP: #1129472
* ptrace: introduce signal_wake_up_state() and ptrace_signal_wake_up()
  - LP: #1119885, #1129192
  - CVE-2013-0871
* ptrace: ensure arch_ptrace/ptrace_request can never race with SIGKILL
  - LP: #1119885, #1129192
  - CVE-2013-0871
* wake_up_process() should be never used to wakeup a TASK_STOPPED/TRACED
  task
  - LP: #1119885, #1129192
  - CVE-2013-0871

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Lines of Context:
drivers/gpu/drm/radeon/si.c
2391
2391
        /* enable context1-15 */
2392
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        WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2393
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               (u32)(rdev->dummy_page.addr >> 12));
2394
 
        WREG32(VM_CONTEXT1_CNTL2, 0);
 
2394
        WREG32(VM_CONTEXT1_CNTL2, 4);
2395
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        WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2396
 
                                RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 
2396
                                RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
 
2397
                                RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
 
2398
                                DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
 
2399
                                DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
 
2400
                                PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
 
2401
                                PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
 
2402
                                VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
 
2403
                                VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
 
2404
                                READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
 
2405
                                READ_PROTECTION_FAULT_ENABLE_DEFAULT |
 
2406
                                WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
 
2407
                                WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
2397
2408
 
2398
2409
        si_pcie_gart_tlb_flush(rdev);
2399
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        DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
3604
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                                break;
3605
3616
                        }
3606
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                        break;
 
3618
                case 146:
 
3619
                case 147:
 
3620
                        dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
 
3621
                        dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
 
3622
                                RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
 
3623
                        dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
 
3624
                                RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
 
3625
                        /* reset addr and status */
 
3626
                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
 
3627
                        break;
3607
3628
                case 176: /* RINGID0 CP_INT */
3608
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                        radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
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                        break;