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Viewing changes to drivers/net/ethernet/broadcom/tg3.c

  • Committer: Package Import Robot
  • Author(s): Paolo Pisati, Paolo Pisati, Ubuntu: 3.5.0-26.42
  • Date: 2013-03-14 15:21:40 UTC
  • mfrom: (76.1.1 quantal-proposed)
  • Revision ID: package-import@ubuntu.com-20130314152140-tl4mkjmxa038tm3h
Tags: 3.5.0-221.31
https://launchpad.net/bugs/1153648
https://launchpad.net/bugs/1152715
https://launchpad.net/bugs/1122094
https://launchpad.net/bugs/1147678
* Release Tracking Bug
  - LP: #1153648

[ Paolo Pisati ]

* rebased on Ubuntu-3.5.0-26.42

[ Ubuntu: 3.5.0-26.42 ]

* Release Tracking Bug
  - LP: #1152715
* ubuntu: overlayfs -- fix missmerge of vfs_open changes
  - LP: #1122094, #1147678

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Lines of Context:
drivers/net/ethernet/broadcom/tg3.c
1136
1136
        return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1137
1137
}
1138
1138
 
1139
 
#define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1140
 
        tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1141
 
                             MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1142
 
                             MII_TG3_AUXCTL_ACTL_TX_6DB)
1143
 
 
1144
 
#define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1145
 
        tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1146
 
                             MII_TG3_AUXCTL_ACTL_TX_6DB);
 
1139
static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
 
1140
{
 
1141
        u32 val;
 
1142
        int err;
 
1143
 
 
1144
        err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
 
1145
 
 
1146
        if (err)
 
1147
                return err;
 
1148
        if (enable)
 
1149
 
 
1150
                val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
 
1151
        else
 
1152
                val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
 
1153
 
 
1154
        err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
 
1155
                                   val | MII_TG3_AUXCTL_ACTL_TX_6DB);
 
1156
 
 
1157
        return err;
 
1158
}
1147
1159
 
1148
1160
static int tg3_bmcr_reset(struct tg3 *tp)
1149
1161
{
2076
2088
 
2077
2089
        otp = tp->phy_otp;
2078
2090
 
2079
 
        if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
 
2091
        if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2080
2092
                return;
2081
2093
 
2082
2094
        phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2101
2113
              ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2102
2114
        tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2103
2115
 
2104
 
        TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 
2116
        tg3_phy_toggle_auxctl_smdsp(tp, false);
2105
2117
}
2106
2118
 
2107
2119
static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2137
2149
 
2138
2150
        if (!tp->setlpicnt) {
2139
2151
                if (current_link_up == 1 &&
2140
 
                   !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
 
2152
                   !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2141
2153
                        tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2142
 
                        TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 
2154
                        tg3_phy_toggle_auxctl_smdsp(tp, false);
2143
2155
                }
2144
2156
 
2145
2157
                val = tr32(TG3_CPMU_EEE_MODE);
2155
2167
            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2156
2168
             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2157
2169
             tg3_flag(tp, 57765_CLASS)) &&
2158
 
            !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
 
2170
            !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2159
2171
                val = MII_TG3_DSP_TAP26_ALNOKO |
2160
2172
                      MII_TG3_DSP_TAP26_RMRXSTO;
2161
2173
                tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2162
 
                TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 
2174
                tg3_phy_toggle_auxctl_smdsp(tp, false);
2163
2175
        }
2164
2176
 
2165
2177
        val = tr32(TG3_CPMU_EEE_MODE);
2303
2315
                tg3_writephy(tp, MII_CTRL1000,
2304
2316
                             CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2305
2317
 
2306
 
                err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
 
2318
                err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2307
2319
                if (err)
2308
2320
                        return err;
2309
2321
 
2324
2336
        tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2325
2337
        tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2326
2338
 
2327
 
        TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 
2339
        tg3_phy_toggle_auxctl_smdsp(tp, false);
2328
2340
 
2329
2341
        tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2330
2342
 
2413
2425
 
2414
2426
out:
2415
2427
        if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2416
 
            !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
 
2428
            !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2417
2429
                tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2418
2430
                tg3_phydsp_write(tp, 0x000a, 0x0323);
2419
 
                TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 
2431
                tg3_phy_toggle_auxctl_smdsp(tp, false);
2420
2432
        }
2421
2433
 
2422
2434
        if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2425
2437
        }
2426
2438
 
2427
2439
        if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2428
 
                if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
 
2440
                if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2429
2441
                        tg3_phydsp_write(tp, 0x000a, 0x310b);
2430
2442
                        tg3_phydsp_write(tp, 0x201f, 0x9506);
2431
2443
                        tg3_phydsp_write(tp, 0x401f, 0x14e2);
2432
 
                        TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 
2444
                        tg3_phy_toggle_auxctl_smdsp(tp, false);
2433
2445
                }
2434
2446
        } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2435
 
                if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
 
2447
                if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2436
2448
                        tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2437
2449
                        if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2438
2450
                                tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2441
2453
                        } else
2442
2454
                                tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2443
2455
 
2444
 
                        TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 
2456
                        tg3_phy_toggle_auxctl_smdsp(tp, false);
2445
2457
                }
2446
2458
        }
2447
2459
 
3858
3870
        tw32(TG3_CPMU_EEE_MODE,
3859
3871
             tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3860
3872
 
3861
 
        err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
 
3873
        err = tg3_phy_toggle_auxctl_smdsp(tp, true);
3862
3874
        if (!err) {
3863
3875
                u32 err2;
3864
3876
 
3891
3903
                                                 MII_TG3_DSP_CH34TP2_HIBW01);
3892
3904
                }
3893
3905
 
3894
 
                err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 
3906
                err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
3895
3907
                if (!err)
3896
3908
                        err = err2;
3897
3909
        }
6594
6606
        int i;
6595
6607
        struct tg3 *tp = netdev_priv(dev);
6596
6608
 
 
6609
        if (tg3_irq_sync(tp))
 
6610
                return;
 
6611
 
6597
6612
        for (i = 0; i < tp->irq_cnt; i++)
6598
6613
                tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
6599
6614
}
15556
15571
        tp->pm_cap = pm_cap;
15557
15572
        tp->rx_mode = TG3_DEF_RX_MODE;
15558
15573
        tp->tx_mode = TG3_DEF_TX_MODE;
 
15574
        tp->irq_sync = 1;
15559
15575
 
15560
15576
        if (tg3_debug > 0)
15561
15577
                tp->msg_enable = tg3_debug;