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- Committer: Bazaar Package Importer
- Author(s): Hakan Ardo
- Date: 2011-07-14 11:15:32 UTC
- mfrom: (1.1.10 upstream) (4.1.6 sid)
- Revision ID: james.westby@ubuntu.com-20110714111532-e83i3vqdowgxw8lv
Tags: 1:1.7.1-2
include/util/delay.h.in: Add math.h to list of includes (closes:
#633822)
#633822)
- files added:
- avr/lib/avr25/attiny84a
- avr/lib/avr5/atmega16hvbrevb
- avr/lib/avr5/atmega3250a
- avr/lib/avr5/atmega325a
- avr/lib/avr5/atmega3290a
- avr/lib/avr5/atmega329a
- avr/lib/avr5/atmega32hvbrevb
- avr/lib/avr5/m3000
- avr/lib/avrtiny10
- avr/lib/avrtiny10/attiny10
- avr/lib/avrtiny10/attiny20
- avr/lib/avrtiny10/attiny4
- avr/lib/avrtiny10/attiny40
- avr/lib/avrtiny10/attiny5
- avr/lib/avrtiny10/attiny9
- avr/lib/avrxmega2/atxmega32a4
- avr/lib/avrxmega5/atxmega64a1u
- avr/lib/avrxmega7/atxmega128a1u
- files removed:
- AvrCommon.am
- avr/lib/avrxmega3
- avr/lib/avrxmega3/atxmega32a4
- files modified:
- ChangeLog
added
removed
include/avr/iox64a1u.h
1
/* Copyright (c) 2010 Atmel Corporation
2
All rights reserved.
3
4
Redistribution and use in source and binary forms, with or without
5
modification, are permitted provided that the following conditions are met:
6
7
* Redistributions of source code must retain the above copyright
8
notice, this list of conditions and the following disclaimer.
9
10
* Redistributions in binary form must reproduce the above copyright
11
notice, this list of conditions and the following disclaimer in
12
the documentation and/or other materials provided with the
13
distribution.
14
15
* Neither the name of the copyright holders nor the names of
16
contributors may be used to endorse or promote products derived
17
from this software without specific prior written permission.
18
19
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
POSSIBILITY OF SUCH DAMAGE. */
30
31
/* $Id$ */
32
33
/* avr/iox64a1u.h - definitions for ATxmega64A1U */
34
35
/* This file should only be included from <avr/io.h>, never directly. */
36
37
#ifndef _AVR_IO_H_
38
# error "Include <avr/io.h> instead of this file."
39
#endif
40
41
#ifndef _AVR_IOXXX_H_
42
# define _AVR_IOXXX_H_ "iox64a1u.h"
43
#else
44
# error "Attempt to include more than one <avr/ioXXX.h> file."
45
#endif
46
47
48
#ifndef _AVR_ATxmega64A1U_H_
49
#define _AVR_ATxmega64A1U_H_ 1
50
51
52
/* Ungrouped common registers */
53
#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
54
#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
55
#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
56
#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
57
#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
58
#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
59
#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
60
#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
61
#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
62
#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
63
#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
64
#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
65
#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
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#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
67
#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
68
#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
69
70
#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
71
#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
72
#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
73
#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
74
#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
75
#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
76
#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
77
#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
78
#define SREG _SFR_MEM8(0x003F) /* Status Register */
79
80
81
/* C Language Only */
82
#if !defined (__ASSEMBLER__)
83
84
#include <stdint.h>
85
86
typedef volatile uint8_t register8_t;
87
typedef volatile uint16_t register16_t;
88
typedef volatile uint32_t register32_t;
89
90
91
#ifdef _WORDREGISTER
92
#undef _WORDREGISTER
93
#endif
94
#define _WORDREGISTER(regname) \
95
__extension__ union \
96
{ \
97
register16_t regname; \
98
struct \
99
{ \
100
register8_t regname ## L; \
101
register8_t regname ## H; \
102
}; \
103
}
104
105
#ifdef _DWORDREGISTER
106
#undef _DWORDREGISTER
107
#endif
108
#define _DWORDREGISTER(regname) \
109
__extension__ union \
110
{ \
111
register32_t regname; \
112
struct \
113
{ \
114
register8_t regname ## 0; \
115
register8_t regname ## 1; \
116
register8_t regname ## 2; \
117
register8_t regname ## 3; \
118
}; \
119
}
120
121
122
/*
123
==========================================================================
124
IO Module Structures
125
==========================================================================
126
*/
127
128
129
/*
130
--------------------------------------------------------------------------
131
VPORT - Virtual Ports
132
--------------------------------------------------------------------------
133
*/
134
135
/* Virtual Port */
136
typedef struct VPORT_struct
137
{
138
register8_t DIR; /* I/O Port Data Direction */
139
register8_t OUT; /* I/O Port Output */
140
register8_t IN; /* I/O Port Input */
141
register8_t INTFLAGS; /* Interrupt Flag Register */
142
} VPORT_t;
143
144
145
/*
146
--------------------------------------------------------------------------
147
XOCD - On-Chip Debug System
148
--------------------------------------------------------------------------
149
*/
150
151
/* On-Chip Debug System */
152
typedef struct OCD_struct
153
{
154
register8_t OCDR0; /* OCD Register 0 */
155
register8_t OCDR1; /* OCD Register 1 */
156
} OCD_t;
157
158
159
/* CCP signatures */
160
typedef enum CCP_enum
161
{
162
CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
163
CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
164
} CCP_t;
165
166
167
/*
168
--------------------------------------------------------------------------
169
CLK - Clock System
170
--------------------------------------------------------------------------
171
*/
172
173
/* Clock System */
174
typedef struct CLK_struct
175
{
176
register8_t CTRL; /* Control Register */
177
register8_t PSCTRL; /* Prescaler Control Register */
178
register8_t LOCK; /* Lock register */
179
register8_t RTCCTRL; /* RTC Control Register */
180
register8_t USBCTRL; /* USB Control Register */
181
} CLK_t;
182
183
/*
184
--------------------------------------------------------------------------
185
CLK - Clock System
186
--------------------------------------------------------------------------
187
*/
188
189
/* Power Reduction */
190
typedef struct PR_struct
191
{
192
register8_t PRGEN; /* General Power Reduction */
193
register8_t PRPA; /* Power Reduction Port A */
194
register8_t PRPB; /* Power Reduction Port B */
195
register8_t PRPC; /* Power Reduction Port C */
196
register8_t PRPD; /* Power Reduction Port D */
197
register8_t PRPE; /* Power Reduction Port E */
198
register8_t PRPF; /* Power Reduction Port F */
199
} PR_t;
200
201
/* System Clock Selection */
202
typedef enum CLK_SCLKSEL_enum
203
{
204
CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
205
CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
206
CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
207
CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
208
CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
209
} CLK_SCLKSEL_t;
210
211
/* Prescaler A Division Factor */
212
typedef enum CLK_PSADIV_enum
213
{
214
CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
215
CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
216
CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
217
CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
218
CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
219
CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
220
CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
221
CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
222
CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
223
CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
224
} CLK_PSADIV_t;
225
226
/* Prescaler B and C Division Factor */
227
typedef enum CLK_PSBCDIV_enum
228
{
229
CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
230
CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
231
CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
232
CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
233
} CLK_PSBCDIV_t;
234
235
/* RTC Clock Source */
236
typedef enum CLK_RTCSRC_enum
237
{
238
CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
239
CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
240
CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
241
CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
242
CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
243
CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
244
} CLK_RTCSRC_t;
245
246
/* USB Prescaler Division Factor */
247
typedef enum CLK_USBPSDIV_enum
248
{
249
CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
250
CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
251
CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
252
CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
253
CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
254
CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
255
} CLK_USBPSDIV_t;
256
257
/* USB Clock Source */
258
typedef enum CLK_USBSRC_enum
259
{
260
CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
261
} CLK_USBSRC_t;
262
263
264
/*
265
--------------------------------------------------------------------------
266
SLEEP - Sleep Controller
267
--------------------------------------------------------------------------
268
*/
269
270
/* Sleep Controller */
271
typedef struct SLEEP_struct
272
{
273
register8_t CTRL; /* Control Register */
274
} SLEEP_t;
275
276
/* Sleep Mode */
277
typedef enum SLEEP_SMODE_enum
278
{
279
SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
280
SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
281
SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
282
SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
283
SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
284
} SLEEP_SMODE_t;
285
286
287
/*
288
--------------------------------------------------------------------------
289
OSC - Oscillator
290
--------------------------------------------------------------------------
291
*/
292
293
/* Oscillator */
294
typedef struct OSC_struct
295
{
296
register8_t CTRL; /* Control Register */
297
register8_t STATUS; /* Status Register */
298
register8_t XOSCCTRL; /* External Oscillator Control Register */
299
register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
300
register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
301
register8_t PLLCTRL; /* PLL Control REgister */
302
register8_t DFLLCTRL; /* DFLL Control Register */
303
} OSC_t;
304
305
/* Oscillator Frequency Range */
306
typedef enum OSC_FRQRANGE_enum
307
{
308
OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
309
OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
310
OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
311
OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
312
} OSC_FRQRANGE_t;
313
314
/* External Oscillator Selection and Startup Time */
315
typedef enum OSC_XOSCSEL_enum
316
{
317
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
318
OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
319
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
320
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
321
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
322
} OSC_XOSCSEL_t;
323
324
/* PLL Clock Source */
325
typedef enum OSC_PLLSRC_enum
326
{
327
OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
328
OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
329
OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
330
} OSC_PLLSRC_t;
331
332
/* 32 MHz Calibration Reference */
333
typedef enum OSC_RC32MCREF_enum
334
{
335
OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
336
OSC_RC32MCREF_XOSC32_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
337
} OSC_RC32MCREF_t;
338
339
340
/*
341
--------------------------------------------------------------------------
342
DFLL - DFLL
343
--------------------------------------------------------------------------
344
*/
345
346
/* DFLL */
347
typedef struct DFLL_struct
348
{
349
register8_t CTRL; /* Control Register */
350
register8_t reserved_0x01;
351
register8_t CALA; /* Calibration Register A */
352
register8_t CALB; /* Calibration Register B */
353
register8_t COMP0; /* Oscillator Compare Register 0 */
354
register8_t COMP1; /* Oscillator Compare Register 1 */
355
register8_t COMP2; /* Oscillator Compare Register 2 */
356
register8_t reserved_0x07;
357
} DFLL_t;
358
359
360
/*
361
--------------------------------------------------------------------------
362
RST - Reset
363
--------------------------------------------------------------------------
364
*/
365
366
/* Reset */
367
typedef struct RST_struct
368
{
369
register8_t STATUS; /* Status Register */
370
register8_t CTRL; /* Control Register */
371
} RST_t;
372
373
374
/*
375
--------------------------------------------------------------------------
376
WDT - Watch-Dog Timer
377
--------------------------------------------------------------------------
378
*/
379
380
/* Watch-Dog Timer */
381
typedef struct WDT_struct
382
{
383
register8_t CTRL; /* Control */
384
register8_t WINCTRL; /* Windowed Mode Control */
385
register8_t STATUS; /* Status */
386
} WDT_t;
387
388
/* Period setting */
389
typedef enum WDT_PER_enum
390
{
391
WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
392
WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
393
WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
394
WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
395
WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
396
WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
397
WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
398
WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
399
WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
400
WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
401
WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
402
} WDT_PER_t;
403
404
/* Closed window period */
405
typedef enum WDT_WPER_enum
406
{
407
WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
408
WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
409
WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
410
WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
411
WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
412
WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
413
WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
414
WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
415
WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
416
WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
417
WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
418
} WDT_WPER_t;
419
420
421
/*
422
--------------------------------------------------------------------------
423
MCU - MCU Control
424
--------------------------------------------------------------------------
425
*/
426
427
/* MCU Control */
428
typedef struct MCU_struct
429
{
430
register8_t DEVID0; /* Device ID byte 0 */
431
register8_t DEVID1; /* Device ID byte 1 */
432
register8_t DEVID2; /* Device ID byte 2 */
433
register8_t REVID; /* Revision ID */
434
register8_t JTAGUID; /* JTAG User ID */
435
register8_t reserved_0x05;
436
register8_t MCUCR; /* MCU Control */
437
register8_t ANAINIT; /* Analog Startup Delay */
438
register8_t EVSYSLOCK; /* Event System Lock */
439
register8_t AWEXLOCK; /* AWEX Lock */
440
register8_t reserved_0x0A;
441
register8_t reserved_0x0B;
442
} MCU_t;
443
444
445
/*
446
--------------------------------------------------------------------------
447
PMIC - Programmable Multi-level Interrupt Controller
448
--------------------------------------------------------------------------
449
*/
450
451
/* Programmable Multi-level Interrupt Controller */
452
typedef struct PMIC_struct
453
{
454
register8_t STATUS; /* Status Register */
455
register8_t INTPRI; /* Interrupt Priority */
456
register8_t CTRL; /* Control Register */
457
} PMIC_t;
458
459
460
/*
461
--------------------------------------------------------------------------
462
PORTCFG - Port Configuration
463
--------------------------------------------------------------------------
464
*/
465
466
/* I/O port Configuration */
467
typedef struct PORTCFG_struct
468
{
469
register8_t MPCMASK; /* Multi-pin Configuration Mask */
470
register8_t reserved_0x01;
471
register8_t VPCTRLA; /* Virtual Port Control Register A */
472
register8_t VPCTRLB; /* Virtual Port Control Register B */
473
register8_t CLKEVOUT; /* Clock and Event Out Register */
474
} PORTCFG_t;
475
476
/* Virtual Port Mapping */
477
typedef enum PORTCFG_VP02MAP_enum
478
{
479
PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
480
PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
481
PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
482
PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
483
PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
484
PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
485
PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
486
PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
487
PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
488
PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
489
PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
490
PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
491
PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
492
PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
493
PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
494
PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
495
} PORTCFG_VP02MAP_t;
496
497
/* Virtual Port Mapping */
498
typedef enum PORTCFG_VP13MAP_enum
499
{
500
PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
501
PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
502
PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
503
PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
504
PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
505
PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
506
PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
507
PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
508
PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
509
PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
510
PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
511
PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
512
PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
513
PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
514
PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
515
PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
516
} PORTCFG_VP13MAP_t;
517
518
/* System Clock Output Port */
519
typedef enum PORTCFG_CLKOUT_enum
520
{
521
PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
522
PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
523
PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
524
PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
525
} PORTCFG_CLKOUT_t;
526
527
/* Peripheral Clock Output Select */
528
typedef enum PORTCFG_CLKOUTSEL_enum
529
{
530
PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
531
PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
532
PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
533
} PORTCFG_CLKOUTSEL_t;
534
535
/* Event Output Port */
536
typedef enum PORTCFG_EVOUT_enum
537
{
538
PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
539
PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
540
PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
541
PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
542
} PORTCFG_EVOUT_t;
543
544
545
/*
546
--------------------------------------------------------------------------
547
AES - AES Module
548
--------------------------------------------------------------------------
549
*/
550
551
/* AES Module */
552
typedef struct AES_struct
553
{
554
register8_t CTRL; /* AES Control Register */
555
register8_t STATUS; /* AES Status Register */
556
register8_t STATE; /* AES State Register */
557
register8_t KEY; /* AES Key Register */
558
register8_t INTCTRL; /* AES Interrupt Control Register */
559
} AES_t;
560
561
/* Interrupt level */
562
typedef enum AES_INTLVL_enum
563
{
564
AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
565
AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
566
AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
567
AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
568
} AES_INTLVL_t;
569
570
571
/*
572
--------------------------------------------------------------------------
573
CRC - Cyclic Redundancy Checker
574
--------------------------------------------------------------------------
575
*/
576
577
/* Cyclic Redundancy Checker */
578
typedef struct CRC_struct
579
{
580
register8_t CTRL; /* CRC Control Register */
581
register8_t STATUS; /* CRC Status Register */
582
register8_t DATAIN; /* CRC Data Input */
583
register8_t CHECKSUM0; /* CRC Checksum byte 0 */
584
register8_t CHECKSUM1; /* CRC Checksum byte 1 */
585
register8_t CHECKSUM2; /* CRC Checksum byte 2 */
586
register8_t CHECKSUM3; /* CRC Checksum byte 3 */
587
} CRC_t;
588
589
/* CRC Reset */
590
typedef enum CRC_RESET_enum
591
{
592
CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
593
CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
594
CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
595
} CRC_RESET_t;
596
597
/* CRC Input Source */
598
typedef enum CRC_SOURCE_enum
599
{
600
CRC_SOURCE_DISABLE_gc = (0x00<<0), /* CRC Disabled */
601
CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
602
CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
603
CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
604
CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
605
CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
606
CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
607
} CRC_SOURCE_t;
608
609
610
/*
611
--------------------------------------------------------------------------
612
DMA - DMA Controller
613
--------------------------------------------------------------------------
614
*/
615
616
/* DMA Channel */
617
typedef struct DMA_CH_struct
618
{
619
register8_t CTRLA; /* Channel Control */
620
register8_t CTRLB; /* Channel Control */
621
register8_t ADDRCTRL; /* Address Control */
622
register8_t TRIGSRC; /* Channel Trigger Source */
623
_WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
624
register8_t REPCNT; /* Channel Repeat Count */
625
register8_t reserved_0x07;
626
register8_t SRCADDR0; /* Channel Source Address 0 */
627
register8_t SRCADDR1; /* Channel Source Address 1 */
628
register8_t SRCADDR2; /* Channel Source Address 2 */
629
register8_t reserved_0x0B;
630
register8_t DESTADDR0; /* Channel Destination Address 0 */
631
register8_t DESTADDR1; /* Channel Destination Address 1 */
632
register8_t DESTADDR2; /* Channel Destination Address 2 */
633
register8_t reserved_0x0F;
634
} DMA_CH_t;
635
636
/*
637
--------------------------------------------------------------------------
638
DMA - DMA Controller
639
--------------------------------------------------------------------------
640
*/
641
642
/* DMA Controller */
643
typedef struct DMA_struct
644
{
645
register8_t CTRL; /* Control */
646
register8_t reserved_0x01;
647
register8_t reserved_0x02;
648
register8_t INTFLAGS; /* Transfer Interrupt Status */
649
register8_t STATUS; /* Status */
650
register8_t reserved_0x05;
651
_WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
652
register8_t reserved_0x08;
653
register8_t reserved_0x09;
654
register8_t reserved_0x0A;
655
register8_t reserved_0x0B;
656
register8_t reserved_0x0C;
657
register8_t reserved_0x0D;
658
register8_t reserved_0x0E;
659
register8_t reserved_0x0F;
660
DMA_CH_t CH0; /* DMA Channel 0 */
661
DMA_CH_t CH1; /* DMA Channel 1 */
662
DMA_CH_t CH2; /* DMA Channel 2 */
663
DMA_CH_t CH3; /* DMA Channel 3 */
664
} DMA_t;
665
666
/* Burst mode */
667
typedef enum DMA_CH_BURSTLEN_enum
668
{
669
DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
670
DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
671
DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
672
DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
673
} DMA_CH_BURSTLEN_t;
674
675
/* Source address reload mode */
676
typedef enum DMA_CH_SRCRELOAD_enum
677
{
678
DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
679
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
680
DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
681
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
682
} DMA_CH_SRCRELOAD_t;
683
684
/* Source addressing mode */
685
typedef enum DMA_CH_SRCDIR_enum
686
{
687
DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
688
DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
689
DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
690
} DMA_CH_SRCDIR_t;
691
692
/* Destination adress reload mode */
693
typedef enum DMA_CH_DESTRELOAD_enum
694
{
695
DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
696
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
697
DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
698
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
699
} DMA_CH_DESTRELOAD_t;
700
701
/* Destination adressing mode */
702
typedef enum DMA_CH_DESTDIR_enum
703
{
704
DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
705
DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
706
DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
707
} DMA_CH_DESTDIR_t;
708
709
/* Transfer trigger source */
710
typedef enum DMA_CH_TRIGSRC_enum
711
{
712
DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
713
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
714
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
715
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
716
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
717
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
718
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
719
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
720
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
721
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
722
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
723
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
724
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
725
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
726
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
727
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
728
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
729
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
730
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
731
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
732
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
733
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
734
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
735
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
736
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
737
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
738
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
739
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
740
DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
741
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
742
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
743
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
744
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
745
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
746
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
747
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
748
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
749
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
750
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
751
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
752
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
753
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
754
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
755
DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
756
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
757
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
758
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
759
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
760
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
761
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
762
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
763
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
764
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
765
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
766
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
767
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
768
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
769
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
770
DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
771
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
772
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
773
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
774
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
775
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
776
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
777
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
778
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
779
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
780
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
781
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
782
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
783
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
784
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
785
DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
786
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
787
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
788
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
789
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
790
} DMA_CH_TRIGSRC_t;
791
792
/* Double buffering mode */
793
typedef enum DMA_DBUFMODE_enum
794
{
795
DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
796
DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
797
DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
798
DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
799
} DMA_DBUFMODE_t;
800
801
/* Priority mode */
802
typedef enum DMA_PRIMODE_enum
803
{
804
DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
805
DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
806
DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
807
DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
808
} DMA_PRIMODE_t;
809
810
/* Interrupt level */
811
typedef enum DMA_CH_ERRINTLVL_enum
812
{
813
DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
814
DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
815
DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
816
DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
817
} DMA_CH_ERRINTLVL_t;
818
819
/* Interrupt level */
820
typedef enum DMA_CH_TRNINTLVL_enum
821
{
822
DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
823
DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
824
DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
825
DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
826
} DMA_CH_TRNINTLVL_t;
827
828
829
/*
830
--------------------------------------------------------------------------
831
EVSYS - Event System
832
--------------------------------------------------------------------------
833
*/
834
835
/* Event System */
836
typedef struct EVSYS_struct
837
{
838
register8_t CH0MUX; /* Event Channel 0 Multiplexer */
839
register8_t CH1MUX; /* Event Channel 1 Multiplexer */
840
register8_t CH2MUX; /* Event Channel 2 Multiplexer */
841
register8_t CH3MUX; /* Event Channel 3 Multiplexer */
842
register8_t CH4MUX; /* Event Channel 4 Multiplexer */
843
register8_t CH5MUX; /* Event Channel 5 Multiplexer */
844
register8_t CH6MUX; /* Event Channel 6 Multiplexer */
845
register8_t CH7MUX; /* Event Channel 7 Multiplexer */
846
register8_t CH0CTRL; /* Channel 0 Control Register */
847
register8_t CH1CTRL; /* Channel 1 Control Register */
848
register8_t CH2CTRL; /* Channel 2 Control Register */
849
register8_t CH3CTRL; /* Channel 3 Control Register */
850
register8_t CH4CTRL; /* Channel 4 Control Register */
851
register8_t CH5CTRL; /* Channel 5 Control Register */
852
register8_t CH6CTRL; /* Channel 6 Control Register */
853
register8_t CH7CTRL; /* Channel 7 Control Register */
854
register8_t STROBE; /* Event Strobe */
855
register8_t DATA; /* Event Data */
856
} EVSYS_t;
857
858
/* Quadrature Decoder Index Recognition Mode */
859
typedef enum EVSYS_QDIRM_enum
860
{
861
EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
862
EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
863
EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
864
EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
865
} EVSYS_QDIRM_t;
866
867
/* Digital filter coefficient */
868
typedef enum EVSYS_DIGFILT_enum
869
{
870
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
871
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
872
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
873
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
874
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
875
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
876
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
877
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
878
} EVSYS_DIGFILT_t;
879
880
/* Event Channel multiplexer input selection */
881
typedef enum EVSYS_CHMUX_enum
882
{
883
EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
884
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
885
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
886
EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
887
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
888
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
889
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
890
EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
891
EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
892
EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
893
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
894
EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
895
EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
896
EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
897
EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
898
EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
899
EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
900
EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
901
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
902
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
903
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
904
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
905
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
906
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
907
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
908
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
909
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
910
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
911
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
912
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
913
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
914
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
915
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
916
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
917
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
918
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
919
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
920
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
921
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
922
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
923
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
924
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
925
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
926
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
927
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
928
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
929
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
930
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
931
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
932
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
933
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
934
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
935
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
936
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
937
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
938
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
939
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
940
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
941
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
942
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
943
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
944
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
945
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
946
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
947
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
948
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
949
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
950
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
951
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
952
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
953
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
954
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
955
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
956
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
957
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
958
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
959
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
960
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
961
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
962
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
963
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
964
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
965
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
966
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
967
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
968
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
969
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
970
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
971
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
972
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
973
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
974
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
975
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
976
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
977
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
978
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
979
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
980
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
981
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
982
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
983
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
984
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
985
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
986
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
987
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
988
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
989
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
990
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
991
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
992
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
993
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
994
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
995
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
996
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
997
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
998
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
999
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
1000
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
1001
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
1002
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
1003
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
1004
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
1005
} EVSYS_CHMUX_t;
1006
1007
1008
/*
1009
--------------------------------------------------------------------------
1010
NVM - Non Volatile Memory Controller
1011
--------------------------------------------------------------------------
1012
*/
1013
1014
/* Non-volatile Memory Controller */
1015
typedef struct NVM_struct
1016
{
1017
register8_t ADDR0; /* Address Register 0 */
1018
register8_t ADDR1; /* Address Register 1 */
1019
register8_t ADDR2; /* Address Register 2 */
1020
register8_t reserved_0x03;
1021
register8_t DATA0; /* Data Register 0 */
1022
register8_t DATA1; /* Data Register 1 */
1023
register8_t DATA2; /* Data Register 2 */
1024
register8_t reserved_0x07;
1025
register8_t reserved_0x08;
1026
register8_t reserved_0x09;
1027
register8_t CMD; /* Command */
1028
register8_t CTRLA; /* Control Register A */
1029
register8_t CTRLB; /* Control Register B */
1030
register8_t INTCTRL; /* Interrupt Control */
1031
register8_t reserved_0x0E;
1032
register8_t STATUS; /* Status */
1033
register8_t LOCKBITS; /* Lock Bits */
1034
} NVM_t;
1035
1036
/* NVM Command */
1037
typedef enum NVM_CMD_enum
1038
{
1039
NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
1040
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
1041
NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0), /* Read user signature row */
1042
NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
1043
NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
1044
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
1045
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
1046
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
1047
NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
1048
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
1049
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
1050
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
1051
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
1052
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
1053
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
1054
NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
1055
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
1056
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
1057
NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
1058
NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
1059
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
1060
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
1061
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
1062
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
1063
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
1064
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
1065
NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
1066
NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
1067
NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
1068
NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
1069
NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
1070
NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
1071
NVM_CMD_FLASH_RANGE_CRC_gc = (0x78<<0), /* Generate Flash Range CRC */
1072
} NVM_CMD_t;
1073
1074
/* SPM ready interrupt level */
1075
typedef enum NVM_SPMLVL_enum
1076
{
1077
NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
1078
NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
1079
NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
1080
NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
1081
} NVM_SPMLVL_t;
1082
1083
/* EEPROM ready interrupt level */
1084
typedef enum NVM_EELVL_enum
1085
{
1086
NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
1087
NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
1088
NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
1089
NVM_EELVL_HI_gc = (0x03<<0), /* High level */
1090
} NVM_EELVL_t;
1091
1092
/* Boot lock bits - boot setcion */
1093
typedef enum NVM_BLBB_enum
1094
{
1095
NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
1096
NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
1097
NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
1098
NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
1099
} NVM_BLBB_t;
1100
1101
/* Boot lock bits - application section */
1102
typedef enum NVM_BLBA_enum
1103
{
1104
NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
1105
NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
1106
NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
1107
NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
1108
} NVM_BLBA_t;
1109
1110
/* Boot lock bits - application table section */
1111
typedef enum NVM_BLBAT_enum
1112
{
1113
NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
1114
NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
1115
NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
1116
NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
1117
} NVM_BLBAT_t;
1118
1119
/* Lock bits */
1120
typedef enum NVM_LB_enum
1121
{
1122
NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
1123
NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
1124
NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
1125
} NVM_LB_t;
1126
1127
1128
/*
1129
--------------------------------------------------------------------------
1130
ADC - Analog/Digital Converter
1131
--------------------------------------------------------------------------
1132
*/
1133
1134
/* ADC Channel */
1135
typedef struct ADC_CH_struct
1136
{
1137
register8_t CTRL; /* Control Register */
1138
register8_t MUXCTRL; /* MUX Control */
1139
register8_t INTCTRL; /* Channel Interrupt Control */
1140
register8_t INTFLAGS; /* Interrupt Flags */
1141
_WORDREGISTER(RES); /* Channel Result */
1142
register8_t reserved_0x7;
1143
} ADC_CH_t;
1144
1145
/*
1146
--------------------------------------------------------------------------
1147
ADC - Analog/Digital Converter
1148
--------------------------------------------------------------------------
1149
*/
1150
1151
/* Analog-to-Digital Converter */
1152
typedef struct ADC_struct
1153
{
1154
register8_t CTRLA; /* Control Register A */
1155
register8_t CTRLB; /* Control Register B */
1156
register8_t REFCTRL; /* Reference Control */
1157
register8_t EVCTRL; /* Event Control */
1158
register8_t PRESCALER; /* Clock Prescaler */
1159
register8_t reserved_0x05;
1160
register8_t INTFLAGS; /* Interrupt Flags */
1161
register8_t TEMP; /* Temporary register */
1162
register8_t reserved_0x08;
1163
register8_t reserved_0x09;
1164
register8_t reserved_0x0A;
1165
register8_t reserved_0x0B;
1166
_WORDREGISTER(CAL); /* Calibration Value */
1167
register8_t reserved_0x0E;
1168
register8_t reserved_0x0F;
1169
_WORDREGISTER(CH0RES); /* Channel 0 Result */
1170
_WORDREGISTER(CH1RES); /* Channel 1 Result */
1171
_WORDREGISTER(CH2RES); /* Channel 2 Result */
1172
_WORDREGISTER(CH3RES); /* Channel 3 Result */
1173
_WORDREGISTER(CMP); /* Compare Value */
1174
register8_t reserved_0x1A;
1175
register8_t reserved_0x1B;
1176
register8_t reserved_0x1C;
1177
register8_t reserved_0x1D;
1178
register8_t reserved_0x1E;
1179
register8_t reserved_0x1F;
1180
ADC_CH_t CH0; /* ADC Channel 0 */
1181
ADC_CH_t CH1; /* ADC Channel 1 */
1182
ADC_CH_t CH2; /* ADC Channel 2 */
1183
ADC_CH_t CH3; /* ADC Channel 3 */
1184
} ADC_t;
1185
1186
/* Positive input multiplexer selection */
1187
typedef enum ADC_CH_MUXPOS_enum
1188
{
1189
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
1190
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
1191
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
1192
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
1193
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
1194
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
1195
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
1196
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
1197
ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
1198
ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
1199
ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
1200
ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
1201
ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
1202
ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
1203
ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
1204
ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
1205
} ADC_CH_MUXPOS_t;
1206
1207
/* Internal input multiplexer selections */
1208
typedef enum ADC_CH_MUXINT_enum
1209
{
1210
ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
1211
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
1212
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
1213
ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
1214
} ADC_CH_MUXINT_t;
1215
1216
/* Negative input multiplexer selection */
1217
typedef enum ADC_CH_MUXNEG_enum
1218
{
1219
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
1220
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
1221
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
1222
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
1223
ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
1224
ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
1225
ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
1226
ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
1227
} ADC_CH_MUXNEG_t;
1228
1229
/* Input mode */
1230
typedef enum ADC_CH_INPUTMODE_enum
1231
{
1232
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
1233
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
1234
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
1235
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
1236
} ADC_CH_INPUTMODE_t;
1237
1238
/* Gain factor */
1239
typedef enum ADC_CH_GAIN_enum
1240
{
1241
ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
1242
ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
1243
ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
1244
ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
1245
ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
1246
ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
1247
ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
1248
ADC_CH_GAIN_128X_gc = (0x07<<2), /* 128x gain */
1249
} ADC_CH_GAIN_t;
1250
1251
/* Conversion result resolution */
1252
typedef enum ADC_RESOLUTION_enum
1253
{
1254
ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
1255
ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
1256
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
1257
} ADC_RESOLUTION_t;
1258
1259
/* Current Limitation Mode */
1260
typedef enum ADC_CURRENT_enum
1261
{
1262
ADC_CURRENT_NO_gc = (0x00<<5), /* No Current Reduction */
1263
ADC_CURRENT_SMALL_gc = (0x01<<5), /* 10% current reduction */
1264
ADC_CURRENT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
1265
ADC_CURRENT_LARGE_gc = (0x03<<5), /* 30% current reduction */
1266
} ADC_CURRENT_t;
1267
1268
/* Voltage reference selection */
1269
typedef enum ADC_REFSEL_enum
1270
{
1271
ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
1272
ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
1273
ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
1274
ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
1275
ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
1276
} ADC_REFSEL_t;
1277
1278
/* Channel sweep selection */
1279
typedef enum ADC_SWEEP_enum
1280
{
1281
ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
1282
ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
1283
ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
1284
ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
1285
} ADC_SWEEP_t;
1286
1287
/* Event channel input selection */
1288
typedef enum ADC_EVSEL_enum
1289
{
1290
ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
1291
ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
1292
ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
1293
ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
1294
ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
1295
ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
1296
ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
1297
ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
1298
} ADC_EVSEL_t;
1299
1300
/* Event action selection */
1301
typedef enum ADC_EVACT_enum
1302
{
1303
ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
1304
ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
1305
ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
1306
ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
1307
ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
1308
ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
1309
ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
1310
} ADC_EVACT_t;
1311
1312
/* Interupt mode */
1313
typedef enum ADC_CH_INTMODE_enum
1314
{
1315
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
1316
ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
1317
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
1318
} ADC_CH_INTMODE_t;
1319
1320
/* Interrupt level */
1321
typedef enum ADC_CH_INTLVL_enum
1322
{
1323
ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
1324
ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
1325
ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
1326
ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
1327
} ADC_CH_INTLVL_t;
1328
1329
/* DMA request selection */
1330
typedef enum ADC_DMASEL_enum
1331
{
1332
ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
1333
ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
1334
ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
1335
ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
1336
} ADC_DMASEL_t;
1337
1338
/* Clock prescaler */
1339
typedef enum ADC_PRESCALER_enum
1340
{
1341
ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
1342
ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
1343
ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
1344
ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
1345
ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
1346
ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
1347
ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
1348
ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
1349
} ADC_PRESCALER_t;
1350
1351
1352
/*
1353
--------------------------------------------------------------------------
1354
DAC - Digital/Analog Converter
1355
--------------------------------------------------------------------------
1356
*/
1357
1358
/* Digital-to-Analog Converter */
1359
typedef struct DAC_struct
1360
{
1361
register8_t CTRLA; /* Control Register A */
1362
register8_t CTRLB; /* Control Register B */
1363
register8_t CTRLC; /* Control Register C */
1364
register8_t EVCTRL; /* Event Input Control */
1365
register8_t TIMCTRL; /* Timing Control */
1366
register8_t STATUS; /* Status */
1367
register8_t reserved_0x06;
1368
register8_t reserved_0x07;
1369
register8_t CH0GAINCAL; /* Gain Calibration */
1370
register8_t CH0OFFSETCAL; /* Offset Calibration */
1371
register8_t CH1GAINCAL; /* Gain Calibration */
1372
register8_t CH1OFFSETCAL; /* Offset Calibration */
1373
register8_t reserved_0x0C;
1374
register8_t reserved_0x0D;
1375
register8_t reserved_0x0E;
1376
register8_t reserved_0x0F;
1377
register8_t reserved_0x10;
1378
register8_t reserved_0x11;
1379
register8_t reserved_0x12;
1380
register8_t reserved_0x13;
1381
register8_t reserved_0x14;
1382
register8_t reserved_0x15;
1383
register8_t reserved_0x16;
1384
register8_t reserved_0x17;
1385
_WORDREGISTER(CH0DATA); /* Channel 0 Data */
1386
_WORDREGISTER(CH1DATA); /* Channel 1 Data */
1387
} DAC_t;
1388
1389
/* Output channel selection */
1390
typedef enum DAC_CHSEL_enum
1391
{
1392
DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
1393
DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
1394
DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
1395
} DAC_CHSEL_t;
1396
1397
/* Reference voltage selection */
1398
typedef enum DAC_REFSEL_enum
1399
{
1400
DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
1401
DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
1402
DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
1403
DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
1404
} DAC_REFSEL_t;
1405
1406
/* Event channel selection */
1407
typedef enum DAC_EVSEL_enum
1408
{
1409
DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
1410
DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
1411
DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
1412
DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
1413
DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
1414
DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
1415
DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
1416
DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
1417
} DAC_EVSEL_t;
1418
1419
/* Conversion interval */
1420
typedef enum DAC_CONINTVAL_enum
1421
{
1422
DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
1423
DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
1424
DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
1425
DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
1426
DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
1427
DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
1428
DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
1429
DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
1430
} DAC_CONINTVAL_t;
1431
1432
/* Refresh rate */
1433
typedef enum DAC_REFRESH_enum
1434
{
1435
DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
1436
DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
1437
DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
1438
DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
1439
DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
1440
DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
1441
DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
1442
DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
1443
DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */
1444
DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
1445
DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
1446
DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
1447
DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
1448
DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
1449
} DAC_REFRESH_t;
1450
1451
1452
/*
1453
--------------------------------------------------------------------------
1454
AC - Analog Comparator
1455
--------------------------------------------------------------------------
1456
*/
1457
1458
/* Analog Comparator */
1459
typedef struct AC_struct
1460
{
1461
register8_t AC0CTRL; /* Analog Comparator 0 Control */
1462
register8_t AC1CTRL; /* Analog Comparator 1 Control */
1463
register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
1464
register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
1465
register8_t CTRLA; /* Control Register A */
1466
register8_t CTRLB; /* Control Register B */
1467
register8_t WINCTRL; /* Window Mode Control */
1468
register8_t STATUS; /* Status */
1469
} AC_t;
1470
1471
/* Interrupt mode */
1472
typedef enum AC_INTMODE_enum
1473
{
1474
AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
1475
AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
1476
AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
1477
} AC_INTMODE_t;
1478
1479
/* Interrupt level */
1480
typedef enum AC_INTLVL_enum
1481
{
1482
AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
1483
AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
1484
AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
1485
AC_INTLVL_HI_gc = (0x03<<4), /* High level */
1486
} AC_INTLVL_t;
1487
1488
/* Hysteresis mode selection */
1489
typedef enum AC_HYSMODE_enum
1490
{
1491
AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
1492
AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
1493
AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
1494
} AC_HYSMODE_t;
1495
1496
/* Positive input multiplexer selection */
1497
typedef enum AC_MUXPOS_enum
1498
{
1499
AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
1500
AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
1501
AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
1502
AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
1503
AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
1504
AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
1505
AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
1506
AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
1507
} AC_MUXPOS_t;
1508
1509
/* Negative input multiplexer selection */
1510
typedef enum AC_MUXNEG_enum
1511
{
1512
AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
1513
AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
1514
AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
1515
AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
1516
AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
1517
AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
1518
AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
1519
AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
1520
} AC_MUXNEG_t;
1521
1522
/* Windows interrupt mode */
1523
typedef enum AC_WINTMODE_enum
1524
{
1525
AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
1526
AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
1527
AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
1528
AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
1529
} AC_WINTMODE_t;
1530
1531
/* Window interrupt level */
1532
typedef enum AC_WINTLVL_enum
1533
{
1534
AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
1535
AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
1536
AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
1537
AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
1538
} AC_WINTLVL_t;
1539
1540
/* Window mode state */
1541
typedef enum AC_WSTATE_enum
1542
{
1543
AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
1544
AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
1545
AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
1546
} AC_WSTATE_t;
1547
1548
1549
/*
1550
--------------------------------------------------------------------------
1551
RTC - Real-Time Clounter
1552
--------------------------------------------------------------------------
1553
*/
1554
1555
/* Real-Time Counter */
1556
typedef struct RTC_struct
1557
{
1558
register8_t CTRL; /* Control Register */
1559
register8_t STATUS; /* Status Register */
1560
register8_t INTCTRL; /* Interrupt Control Register */
1561
register8_t INTFLAGS; /* Interrupt Flags */
1562
register8_t TEMP; /* Temporary register */
1563
register8_t reserved_0x05;
1564
register8_t reserved_0x06;
1565
register8_t reserved_0x07;
1566
_WORDREGISTER(CNT); /* Count Register */
1567
_WORDREGISTER(PER); /* Period Register */
1568
_WORDREGISTER(COMP); /* Compare Register */
1569
} RTC_t;
1570
1571
/* Prescaler Factor */
1572
typedef enum RTC_PRESCALER_enum
1573
{
1574
RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
1575
RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
1576
RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
1577
RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
1578
RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
1579
RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
1580
RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
1581
RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
1582
} RTC_PRESCALER_t;
1583
1584
/* Compare Interrupt level */
1585
typedef enum RTC_COMPINTLVL_enum
1586
{
1587
RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1588
RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
1589
RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1590
RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
1591
} RTC_COMPINTLVL_t;
1592
1593
/* Overflow Interrupt level */
1594
typedef enum RTC_OVFINTLVL_enum
1595
{
1596
RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1597
RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
1598
RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1599
RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
1600
} RTC_OVFINTLVL_t;
1601
1602
1603
/*
1604
--------------------------------------------------------------------------
1605
EBI - External Bus Interface
1606
--------------------------------------------------------------------------
1607
*/
1608
1609
/* EBI Chip Select Module */
1610
typedef struct EBI_CS_struct
1611
{
1612
register8_t CTRLA; /* Chip Select Control Register A */
1613
register8_t CTRLB; /* Chip Select Control Register B */
1614
_WORDREGISTER(BASEADDR); /* Chip Select Base Address */
1615
} EBI_CS_t;
1616
1617
/*
1618
--------------------------------------------------------------------------
1619
EBI - External Bus Interface
1620
--------------------------------------------------------------------------
1621
*/
1622
1623
/* External Bus Interface */
1624
typedef struct EBI_struct
1625
{
1626
register8_t CTRL; /* Control */
1627
register8_t SDRAMCTRLA; /* SDRAM Control Register A */
1628
register8_t reserved_0x02;
1629
register8_t reserved_0x03;
1630
_WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
1631
_WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
1632
register8_t SDRAMCTRLB; /* SDRAM Control Register B */
1633
register8_t SDRAMCTRLC; /* SDRAM Control Register C */
1634
register8_t reserved_0x0A;
1635
register8_t reserved_0x0B;
1636
register8_t reserved_0x0C;
1637
register8_t reserved_0x0D;
1638
register8_t reserved_0x0E;
1639
register8_t reserved_0x0F;
1640
EBI_CS_t CS0; /* Chip Select 0 */
1641
EBI_CS_t CS1; /* Chip Select 1 */
1642
EBI_CS_t CS2; /* Chip Select 2 */
1643
EBI_CS_t CS3; /* Chip Select 3 */
1644
} EBI_t;
1645
1646
/* Chip Select adress space */
1647
typedef enum EBI_CS_ASIZE_enum
1648
{
1649
EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */
1650
EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */
1651
EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */
1652
EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */
1653
EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */
1654
EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */
1655
EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */
1656
EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */
1657
EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */
1658
EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */
1659
EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */
1660
EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */
1661
EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */
1662
EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */
1663
EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */
1664
EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */
1665
EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */
1666
} EBI_CS_ASIZE_t;
1667
1668
/* */
1669
typedef enum EBI_CS_SRWS_enum
1670
{
1671
EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
1672
EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
1673
EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
1674
EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
1675
EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
1676
EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
1677
EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
1678
EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
1679
} EBI_CS_SRWS_t;
1680
1681
/* Chip Select address mode */
1682
typedef enum EBI_CS_MODE_enum
1683
{
1684
EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
1685
EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
1686
EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
1687
EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
1688
} EBI_CS_MODE_t;
1689
1690
/* Chip Select SDRAM mode */
1691
typedef enum EBI_CS_SDMODE_enum
1692
{
1693
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
1694
EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
1695
} EBI_CS_SDMODE_t;
1696
1697
/* */
1698
typedef enum EBI_SDDATAW_enum
1699
{
1700
EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
1701
EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
1702
} EBI_SDDATAW_t;
1703
1704
/* */
1705
typedef enum EBI_LPCMODE_enum
1706
{
1707
EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
1708
EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
1709
} EBI_LPCMODE_t;
1710
1711
/* */
1712
typedef enum EBI_SRMODE_enum
1713
{
1714
EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
1715
EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
1716
EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
1717
EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
1718
} EBI_SRMODE_t;
1719
1720
/* */
1721
typedef enum EBI_IFMODE_enum
1722
{
1723
EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
1724
EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
1725
EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
1726
EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
1727
} EBI_IFMODE_t;
1728
1729
/* */
1730
typedef enum EBI_SDCOL_enum
1731
{
1732
EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
1733
EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
1734
EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
1735
EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
1736
} EBI_SDCOL_t;
1737
1738
/* */
1739
typedef enum EBI_MRDLY_enum
1740
{
1741
EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1742
EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1743
EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1744
EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1745
} EBI_MRDLY_t;
1746
1747
/* */
1748
typedef enum EBI_ROWCYCDLY_enum
1749
{
1750
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1751
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1752
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1753
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1754
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1755
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1756
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1757
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1758
} EBI_ROWCYCDLY_t;
1759
1760
/* */
1761
typedef enum EBI_RPDLY_enum
1762
{
1763
EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1764
EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1765
EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1766
EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1767
EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1768
EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1769
EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1770
EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1771
} EBI_RPDLY_t;
1772
1773
/* */
1774
typedef enum EBI_WRDLY_enum
1775
{
1776
EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1777
EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1778
EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1779
EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1780
} EBI_WRDLY_t;
1781
1782
/* */
1783
typedef enum EBI_ESRDLY_enum
1784
{
1785
EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1786
EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1787
EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1788
EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1789
EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1790
EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1791
EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1792
EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1793
} EBI_ESRDLY_t;
1794
1795
/* */
1796
typedef enum EBI_ROWCOLDLY_enum
1797
{
1798
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1799
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1800
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1801
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1802
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1803
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1804
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1805
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1806
} EBI_ROWCOLDLY_t;
1807
1808
1809
/*
1810
--------------------------------------------------------------------------
1811
TWI - Two-Wire Interface
1812
--------------------------------------------------------------------------
1813
*/
1814
1815
/* */
1816
typedef struct TWI_MASTER_struct
1817
{
1818
register8_t CTRLA; /* Control Register A */
1819
register8_t CTRLB; /* Control Register B */
1820
register8_t CTRLC; /* Control Register C */
1821
register8_t STATUS; /* Status Register */
1822
register8_t BAUD; /* Baurd Rate Control Register */
1823
register8_t ADDR; /* Address Register */
1824
register8_t DATA; /* Data Register */
1825
} TWI_MASTER_t;
1826
1827
/*
1828
--------------------------------------------------------------------------
1829
TWI - Two-Wire Interface
1830
--------------------------------------------------------------------------
1831
*/
1832
1833
/* */
1834
typedef struct TWI_SLAVE_struct
1835
{
1836
register8_t CTRLA; /* Control Register A */
1837
register8_t CTRLB; /* Control Register B */
1838
register8_t STATUS; /* Status Register */
1839
register8_t ADDR; /* Address Register */
1840
register8_t DATA; /* Data Register */
1841
register8_t ADDRMASK; /* Address Mask Register */
1842
} TWI_SLAVE_t;
1843
1844
/*
1845
--------------------------------------------------------------------------
1846
TWI - Two-Wire Interface
1847
--------------------------------------------------------------------------
1848
*/
1849
1850
/* Two-Wire Interface */
1851
typedef struct TWI_struct
1852
{
1853
register8_t CTRL; /* TWI Common Control Register */
1854
TWI_MASTER_t MASTER; /* TWI master module */
1855
TWI_SLAVE_t SLAVE; /* TWI slave module */
1856
} TWI_t;
1857
1858
/* Master Interrupt Level */
1859
typedef enum TWI_MASTER_INTLVL_enum
1860
{
1861
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1862
TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1863
TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1864
TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
1865
} TWI_MASTER_INTLVL_t;
1866
1867
/* Inactive Timeout */
1868
typedef enum TWI_MASTER_TIMEOUT_enum
1869
{
1870
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
1871
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
1872
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
1873
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
1874
} TWI_MASTER_TIMEOUT_t;
1875
1876
/* Master Command */
1877
typedef enum TWI_MASTER_CMD_enum
1878
{
1879
TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
1880
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
1881
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
1882
TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
1883
} TWI_MASTER_CMD_t;
1884
1885
/* Master Bus State */
1886
typedef enum TWI_MASTER_BUSSTATE_enum
1887
{
1888
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
1889
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
1890
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
1891
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
1892
} TWI_MASTER_BUSSTATE_t;
1893
1894
/* Slave Interrupt Level */
1895
typedef enum TWI_SLAVE_INTLVL_enum
1896
{
1897
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1898
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1899
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1900
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
1901
} TWI_SLAVE_INTLVL_t;
1902
1903
/* Slave Command */
1904
typedef enum TWI_SLAVE_CMD_enum
1905
{
1906
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
1907
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
1908
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
1909
} TWI_SLAVE_CMD_t;
1910
1911
1912
/*
1913
--------------------------------------------------------------------------
1914
USB - USB Module
1915
--------------------------------------------------------------------------
1916
*/
1917
1918
/* USB Endpoint */
1919
typedef struct USB_EP_struct
1920
{
1921
register8_t STATUS; /* Endpoint Status */
1922
register8_t CTRL; /* Endpoint Control */
1923
register8_t CNTL; /* USB Endpoint Counter Low Byte */
1924
register8_t CNTH; /* USB Endpoint Counter High Byte */
1925
register8_t DATAPTRL; /* Data Pointer Low Byte */
1926
register8_t DATAPTRH; /* Data Pointer High Byte */
1927
register8_t AUXDATAL; /* Auxiliary Data Low Byte */
1928
register8_t AUXDATAH; /* Auxiliary Data High Byte */
1929
} USB_EP_t;
1930
1931
/*
1932
--------------------------------------------------------------------------
1933
USB - USB Module
1934
--------------------------------------------------------------------------
1935
*/
1936
1937
/* USB Endpoint table */
1938
typedef struct USB_EP_TABLE_struct
1939
{
1940
USB_EP_t EP0OUT; /* USB Endpoint 0 Output */
1941
USB_EP_t EP0IN; /* USB Endpoint 0 Input */
1942
USB_EP_t EP1OUT; /* USB Endpoint 1 Output */
1943
USB_EP_t EP1IN; /* USB Endpoint 1 Input */
1944
USB_EP_t EP2OUT; /* USB Endpoint 2 Output */
1945
USB_EP_t EP2IN; /* USB Endpoint 2 Input */
1946
USB_EP_t EP3OUT; /* USB Endpoint 3 Output */
1947
USB_EP_t EP3IN; /* USB Endpoint 3 Input */
1948
USB_EP_t EP4OUT; /* USB Endpoint 4 Output */
1949
USB_EP_t EP4IN; /* USB Endpoint 4 Input */
1950
USB_EP_t EP5OUT; /* USB Endpoint 5 Output */
1951
USB_EP_t EP5IN; /* USB Endpoint 5 Input */
1952
USB_EP_t EP6OUT; /* USB Endpoint 6 Output */
1953
USB_EP_t EP6IN; /* USB Endpoint 6 Input */
1954
USB_EP_t EP7OUT; /* USB Endpoint 7 Output */
1955
USB_EP_t EP7IN; /* USB Endpoint 7 Input */
1956
USB_EP_t EP8OUT; /* USB Endpoint 8 Output */
1957
USB_EP_t EP8IN; /* USB Endpoint 8 Input */
1958
USB_EP_t EP9OUT; /* USB Endpoint 9 Output */
1959
USB_EP_t EP9IN; /* USB Endpoint 9 Input */
1960
USB_EP_t EP10OUT; /* USB Endpoint 10 Output */
1961
USB_EP_t EP10IN; /* USB Endpoint 10 Input */
1962
USB_EP_t EP11OUT; /* USB Endpoint 11 Output */
1963
USB_EP_t EP11IN; /* USB Endpoint 11 Input */
1964
USB_EP_t EP12OUT; /* USB Endpoint 12 Output */
1965
USB_EP_t EP12IN; /* USB Endpoint 12 Input */
1966
USB_EP_t EP13OUT; /* USB Endpoint 13 Output */
1967
USB_EP_t EP13IN; /* USB Endpoint 13 Input */
1968
USB_EP_t EP14OUT; /* USB Endpoint 14 Output */
1969
USB_EP_t EP14IN; /* USB Endpoint 14 Input */
1970
USB_EP_t EP15OUT; /* USB Endpoint 15 Output */
1971
USB_EP_t EP15IN; /* USB Endpoint 15 Input */
1972
register8_t FRAMENUML; /* Frame Number Low Byte */
1973
register8_t FRAMENUMH; /* Frame Number High Byte */
1974
} USB_EP_TABLE_t;
1975
1976
/*
1977
--------------------------------------------------------------------------
1978
USB - USB Module
1979
--------------------------------------------------------------------------
1980
*/
1981
1982
/* USB Module */
1983
typedef struct USB_struct
1984
{
1985
register8_t CTRLA; /* Control Register A */
1986
register8_t CTRLB; /* Control Register B */
1987
register8_t STATUS; /* Status Register */
1988
register8_t ADDR; /* Address Register */
1989
register8_t FIFOWP; /* FIFO Write Pointer Register */
1990
register8_t FIFORP; /* FIFO Read Pointer Register */
1991
_WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
1992
register8_t INTCTRLA; /* Interrupt Control Register A */
1993
register8_t INTCTRLB; /* Interrupt Control Register B */
1994
register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
1995
register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
1996
register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
1997
register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
1998
register8_t reserved_0x0E;
1999
register8_t reserved_0x0F;
2000
register8_t reserved_0x10;
2001
register8_t reserved_0x11;
2002
register8_t reserved_0x12;
2003
register8_t reserved_0x13;
2004
register8_t reserved_0x14;
2005
register8_t reserved_0x15;
2006
register8_t reserved_0x16;
2007
register8_t reserved_0x17;
2008
register8_t reserved_0x18;
2009
register8_t reserved_0x19;
2010
register8_t reserved_0x1A;
2011
register8_t reserved_0x1B;
2012
register8_t reserved_0x1C;
2013
register8_t reserved_0x1D;
2014
register8_t reserved_0x1E;
2015
register8_t reserved_0x1F;
2016
register8_t reserved_0x20;
2017
register8_t reserved_0x21;
2018
register8_t reserved_0x22;
2019
register8_t reserved_0x23;
2020
register8_t reserved_0x24;
2021
register8_t reserved_0x25;
2022
register8_t reserved_0x26;
2023
register8_t reserved_0x27;
2024
register8_t reserved_0x28;
2025
register8_t reserved_0x29;
2026
register8_t reserved_0x2A;
2027
register8_t reserved_0x2B;
2028
register8_t reserved_0x2C;
2029
register8_t reserved_0x2D;
2030
register8_t reserved_0x2E;
2031
register8_t reserved_0x2F;
2032
register8_t reserved_0x30;
2033
register8_t reserved_0x31;
2034
register8_t reserved_0x32;
2035
register8_t reserved_0x33;
2036
register8_t reserved_0x34;
2037
register8_t reserved_0x35;
2038
register8_t reserved_0x36;
2039
register8_t reserved_0x37;
2040
register8_t reserved_0x38;
2041
register8_t reserved_0x39;
2042
register8_t CAL0; /* Calibration Byte 0 */
2043
register8_t CAL1; /* Calibration Byte 1 */
2044
} USB_t;
2045
2046
/* USB Endpoint Type */
2047
typedef enum USB_EP_TYPE_enum
2048
{
2049
USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
2050
USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
2051
USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
2052
USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
2053
} USB_EP_TYPE_t;
2054
2055
/* USB Endpoint Buffer Size */
2056
typedef enum USB_EP_SIZE_enum
2057
{
2058
USB_EP_SIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
2059
USB_EP_SIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
2060
USB_EP_SIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
2061
USB_EP_SIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
2062
USB_EP_SIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
2063
USB_EP_SIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
2064
USB_EP_SIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
2065
USB_EP_SIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
2066
} USB_EP_SIZE_t;
2067
2068
/* Interrupt level */
2069
typedef enum USB_INTLVL_enum
2070
{
2071
USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
2072
USB_INTLVL_LO_gc = (0x01<<0), /* Low Level */
2073
USB_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
2074
USB_INTLVL_HI_gc = (0x03<<0), /* High Level */
2075
} USB_INTLVL_t;
2076
2077
2078
/*
2079
--------------------------------------------------------------------------
2080
PORT - I/O Port Configuration
2081
--------------------------------------------------------------------------
2082
*/
2083
2084
/* I/O Ports */
2085
typedef struct PORT_struct
2086
{
2087
register8_t DIR; /* I/O Port Data Direction */
2088
register8_t DIRSET; /* I/O Port Data Direction Set */
2089
register8_t DIRCLR; /* I/O Port Data Direction Clear */
2090
register8_t DIRTGL; /* I/O Port Data Direction Toggle */
2091
register8_t OUT; /* I/O Port Output */
2092
register8_t OUTSET; /* I/O Port Output Set */
2093
register8_t OUTCLR; /* I/O Port Output Clear */
2094
register8_t OUTTGL; /* I/O Port Output Toggle */
2095
register8_t IN; /* I/O port Input */
2096
register8_t INTCTRL; /* Interrupt Control Register */
2097
register8_t INT0MASK; /* Port Interrupt 0 Mask */
2098
register8_t INT1MASK; /* Port Interrupt 1 Mask */
2099
register8_t INTFLAGS; /* Interrupt Flag Register */
2100
register8_t reserved_0x0D;
2101
register8_t reserved_0x0F;
2102
register8_t PIN0CTRL; /* Pin 0 Control Register */
2103
register8_t PIN1CTRL; /* Pin 1 Control Register */
2104
register8_t PIN2CTRL; /* Pin 2 Control Register */
2105
register8_t PIN3CTRL; /* Pin 3 Control Register */
2106
register8_t PIN4CTRL; /* Pin 4 Control Register */
2107
register8_t PIN5CTRL; /* Pin 5 Control Register */
2108
register8_t PIN6CTRL; /* Pin 6 Control Register */
2109
register8_t PIN7CTRL; /* Pin 7 Control Register */
2110
} PORT_t;
2111
2112
/* Port Interrupt 0 Level */
2113
typedef enum PORT_INT0LVL_enum
2114
{
2115
PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2116
PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
2117
PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
2118
PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
2119
} PORT_INT0LVL_t;
2120
2121
/* Port Interrupt 1 Level */
2122
typedef enum PORT_INT1LVL_enum
2123
{
2124
PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2125
PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
2126
PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
2127
PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
2128
} PORT_INT1LVL_t;
2129
2130
/* Output/Pull Configuration */
2131
typedef enum PORT_OPC_enum
2132
{
2133
PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
2134
PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
2135
PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
2136
PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
2137
PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
2138
PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
2139
PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
2140
PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
2141
} PORT_OPC_t;
2142
2143
/* Input/Sense Configuration */
2144
typedef enum PORT_ISC_enum
2145
{
2146
PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
2147
PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
2148
PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
2149
PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
2150
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
2151
} PORT_ISC_t;
2152
2153
2154
/*
2155
--------------------------------------------------------------------------
2156
TC - 16-bit Timer/Counter With PWM
2157
--------------------------------------------------------------------------
2158
*/
2159
2160
/* 16-bit Timer/Counter 0 */
2161
typedef struct TC0_struct
2162
{
2163
register8_t CTRLA; /* Control Register A */
2164
register8_t CTRLB; /* Control Register B */
2165
register8_t CTRLC; /* Control register C */
2166
register8_t CTRLD; /* Control Register D */
2167
register8_t CTRLE; /* Control Register E */
2168
register8_t reserved_0x05;
2169
register8_t INTCTRLA; /* Interrupt Control Register A */
2170
register8_t INTCTRLB; /* Interrupt Control Register B */
2171
register8_t CTRLFCLR; /* Control Register F Clear */
2172
register8_t CTRLFSET; /* Control Register F Set */
2173
register8_t CTRLGCLR; /* Control Register G Clear */
2174
register8_t CTRLGSET; /* Control Register G Set */
2175
register8_t INTFLAGS; /* Interrupt Flag Register */
2176
register8_t reserved_0x0D;
2177
register8_t reserved_0x0E;
2178
register8_t TEMP; /* Temporary Register For 16-bit Access */
2179
register8_t reserved_0x10;
2180
register8_t reserved_0x11;
2181
register8_t reserved_0x12;
2182
register8_t reserved_0x13;
2183
register8_t reserved_0x14;
2184
register8_t reserved_0x15;
2185
register8_t reserved_0x16;
2186
register8_t reserved_0x17;
2187
register8_t reserved_0x18;
2188
register8_t reserved_0x19;
2189
register8_t reserved_0x1A;
2190
register8_t reserved_0x1B;
2191
register8_t reserved_0x1C;
2192
register8_t reserved_0x1D;
2193
register8_t reserved_0x1E;
2194
register8_t reserved_0x1F;
2195
_WORDREGISTER(CNT); /* Count */
2196
register8_t reserved_0x22;
2197
register8_t reserved_0x23;
2198
register8_t reserved_0x24;
2199
register8_t reserved_0x25;
2200
_WORDREGISTER(PER); /* Period */
2201
_WORDREGISTER(CCA); /* Compare or Capture A */
2202
_WORDREGISTER(CCB); /* Compare or Capture B */
2203
_WORDREGISTER(CCC); /* Compare or Capture C */
2204
_WORDREGISTER(CCD); /* Compare or Capture D */
2205
register8_t reserved_0x30;
2206
register8_t reserved_0x31;
2207
register8_t reserved_0x32;
2208
register8_t reserved_0x33;
2209
register8_t reserved_0x34;
2210
register8_t reserved_0x35;
2211
_WORDREGISTER(PERBUF); /* Period Buffer */
2212
_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
2213
_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
2214
_WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
2215
_WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
2216
} TC0_t;
2217
2218
/*
2219
--------------------------------------------------------------------------
2220
TC - 16-bit Timer/Counter With PWM
2221
--------------------------------------------------------------------------
2222
*/
2223
2224
/* 16-bit Timer/Counter 1 */
2225
typedef struct TC1_struct
2226
{
2227
register8_t CTRLA; /* Control Register A */
2228
register8_t CTRLB; /* Control Register B */
2229
register8_t CTRLC; /* Control register C */
2230
register8_t CTRLD; /* Control Register D */
2231
register8_t CTRLE; /* Control Register E */
2232
register8_t reserved_0x05;
2233
register8_t INTCTRLA; /* Interrupt Control Register A */
2234
register8_t INTCTRLB; /* Interrupt Control Register B */
2235
register8_t CTRLFCLR; /* Control Register F Clear */
2236
register8_t CTRLFSET; /* Control Register F Set */
2237
register8_t CTRLGCLR; /* Control Register G Clear */
2238
register8_t CTRLGSET; /* Control Register G Set */
2239
register8_t INTFLAGS; /* Interrupt Flag Register */
2240
register8_t reserved_0x0D;
2241
register8_t reserved_0x0E;
2242
register8_t TEMP; /* Temporary Register For 16-bit Access */
2243
register8_t reserved_0x10;
2244
register8_t reserved_0x11;
2245
register8_t reserved_0x12;
2246
register8_t reserved_0x13;
2247
register8_t reserved_0x14;
2248
register8_t reserved_0x15;
2249
register8_t reserved_0x16;
2250
register8_t reserved_0x17;
2251
register8_t reserved_0x18;
2252
register8_t reserved_0x19;
2253
register8_t reserved_0x1A;
2254
register8_t reserved_0x1B;
2255
register8_t reserved_0x1C;
2256
register8_t reserved_0x1D;
2257
register8_t reserved_0x1E;
2258
register8_t reserved_0x1F;
2259
_WORDREGISTER(CNT); /* Count */
2260
register8_t reserved_0x22;
2261
register8_t reserved_0x23;
2262
register8_t reserved_0x24;
2263
register8_t reserved_0x25;
2264
_WORDREGISTER(PER); /* Period */
2265
_WORDREGISTER(CCA); /* Compare or Capture A */
2266
_WORDREGISTER(CCB); /* Compare or Capture B */
2267
register8_t reserved_0x2C;
2268
register8_t reserved_0x2D;
2269
register8_t reserved_0x2E;
2270
register8_t reserved_0x2F;
2271
register8_t reserved_0x30;
2272
register8_t reserved_0x31;
2273
register8_t reserved_0x32;
2274
register8_t reserved_0x33;
2275
register8_t reserved_0x34;
2276
register8_t reserved_0x35;
2277
_WORDREGISTER(PERBUF); /* Period Buffer */
2278
_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
2279
_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
2280
} TC1_t;
2281
2282
/* Clock Selection */
2283
typedef enum TC_CLKSEL_enum
2284
{
2285
TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
2286
TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
2287
TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
2288
TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
2289
TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
2290
TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
2291
TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
2292
TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
2293
TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
2294
TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
2295
TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
2296
TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
2297
TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
2298
TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
2299
TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
2300
TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
2301
} TC_CLKSEL_t;
2302
2303
/* Waveform Generation Mode */
2304
typedef enum TC_WGMODE_enum
2305
{
2306
TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
2307
TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
2308
TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
2309
TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
2310
TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
2311
TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
2312
} TC_WGMODE_t;
2313
2314
/* Event Action */
2315
typedef enum TC_EVACT_enum
2316
{
2317
TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
2318
TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
2319
TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
2320
TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
2321
TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
2322
TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
2323
TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
2324
} TC_EVACT_t;
2325
2326
/* Event Selection */
2327
typedef enum TC_EVSEL_enum
2328
{
2329
TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
2330
TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
2331
TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
2332
TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
2333
TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
2334
TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
2335
TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
2336
TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
2337
TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
2338
} TC_EVSEL_t;
2339
2340
/* Error Interrupt Level */
2341
typedef enum TC_ERRINTLVL_enum
2342
{
2343
TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2344
TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
2345
TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2346
TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
2347
} TC_ERRINTLVL_t;
2348
2349
/* Overflow Interrupt Level */
2350
typedef enum TC_OVFINTLVL_enum
2351
{
2352
TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2353
TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
2354
TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2355
TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
2356
} TC_OVFINTLVL_t;
2357
2358
/* Compare or Capture D Interrupt Level */
2359
typedef enum TC_CCDINTLVL_enum
2360
{
2361
TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
2362
TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
2363
TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
2364
TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
2365
} TC_CCDINTLVL_t;
2366
2367
/* Compare or Capture C Interrupt Level */
2368
typedef enum TC_CCCINTLVL_enum
2369
{
2370
TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
2371
TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
2372
TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
2373
TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
2374
} TC_CCCINTLVL_t;
2375
2376
/* Compare or Capture B Interrupt Level */
2377
typedef enum TC_CCBINTLVL_enum
2378
{
2379
TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2380
TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
2381
TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2382
TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
2383
} TC_CCBINTLVL_t;
2384
2385
/* Compare or Capture A Interrupt Level */
2386
typedef enum TC_CCAINTLVL_enum
2387
{
2388
TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2389
TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
2390
TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2391
TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
2392
} TC_CCAINTLVL_t;
2393
2394
/* Timer/Counter Command */
2395
typedef enum TC_CMD_enum
2396
{
2397
TC_CMD_NONE_gc = (0x00<<2), /* No Command */
2398
TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
2399
TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
2400
TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
2401
} TC_CMD_t;
2402
2403
2404
/*
2405
--------------------------------------------------------------------------
2406
AWEX - Timer/Counter Advanced Waveform Extension
2407
--------------------------------------------------------------------------
2408
*/
2409
2410
/* Advanced Waveform Extension */
2411
typedef struct AWEX_struct
2412
{
2413
register8_t CTRL; /* Control Register */
2414
register8_t reserved_0x01;
2415
register8_t FDEMASK; /* Fault Detection Event Mask */
2416
register8_t FDCTRL; /* Fault Detection Control Register */
2417
register8_t STATUS; /* Status Register */
2418
register8_t reserved_0x05;
2419
register8_t DTBOTH; /* Dead Time Both Sides */
2420
register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
2421
register8_t DTLS; /* Dead Time Low Side */
2422
register8_t DTHS; /* Dead Time High Side */
2423
register8_t DTLSBUF; /* Dead Time Low Side Buffer */
2424
register8_t DTHSBUF; /* Dead Time High Side Buffer */
2425
register8_t OUTOVEN; /* Output Override Enable */
2426
} AWEX_t;
2427
2428
/* Fault Detect Action */
2429
typedef enum AWEX_FDACT_enum
2430
{
2431
AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
2432
AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
2433
AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
2434
} AWEX_FDACT_t;
2435
2436
2437
/*
2438
--------------------------------------------------------------------------
2439
HIRES - Timer/Counter High-Resolution Extension
2440
--------------------------------------------------------------------------
2441
*/
2442
2443
/* High-Resolution Extension */
2444
typedef struct HIRES_struct
2445
{
2446
register8_t CTRLA; /* Control Register */
2447
} HIRES_t;
2448
2449
/* High Resolution Enable */
2450
typedef enum HIRES_HREN_enum
2451
{
2452
HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
2453
HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
2454
HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
2455
HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
2456
} HIRES_HREN_t;
2457
2458
2459
/*
2460
--------------------------------------------------------------------------
2461
USART - Universal Asynchronous Receiver-Transmitter
2462
--------------------------------------------------------------------------
2463
*/
2464
2465
/* Universal Synchronous/Asynchronous Receiver/Transmitter */
2466
typedef struct USART_struct
2467
{
2468
register8_t DATA; /* Data Register */
2469
register8_t STATUS; /* Status Register */
2470
register8_t reserved_0x02;
2471
register8_t CTRLA; /* Control Register A */
2472
register8_t CTRLB; /* Control Register B */
2473
register8_t CTRLC; /* Control Register C */
2474
register8_t BAUDCTRLA; /* Baud Rate Control Register A */
2475
register8_t BAUDCTRLB; /* Baud Rate Control Register B */
2476
} USART_t;
2477
2478
/* Receive Complete Interrupt level */
2479
typedef enum USART_RXCINTLVL_enum
2480
{
2481
USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
2482
USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
2483
USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
2484
USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
2485
} USART_RXCINTLVL_t;
2486
2487
/* Transmit Complete Interrupt level */
2488
typedef enum USART_TXCINTLVL_enum
2489
{
2490
USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2491
USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
2492
USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2493
USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
2494
} USART_TXCINTLVL_t;
2495
2496
/* Data Register Empty Interrupt level */
2497
typedef enum USART_DREINTLVL_enum
2498
{
2499
USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2500
USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
2501
USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2502
USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
2503
} USART_DREINTLVL_t;
2504
2505
/* Character Size */
2506
typedef enum USART_CHSIZE_enum
2507
{
2508
USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
2509
USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
2510
USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
2511
USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
2512
USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
2513
} USART_CHSIZE_t;
2514
2515
/* Communication Mode */
2516
typedef enum USART_CMODE_enum
2517
{
2518
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
2519
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
2520
USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
2521
USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
2522
} USART_CMODE_t;
2523
2524
/* Parity Mode */
2525
typedef enum USART_PMODE_enum
2526
{
2527
USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
2528
USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
2529
USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
2530
} USART_PMODE_t;
2531
2532
2533
/*
2534
--------------------------------------------------------------------------
2535
SPI - Serial Peripheral Interface
2536
--------------------------------------------------------------------------
2537
*/
2538
2539
/* Serial Peripheral Interface */
2540
typedef struct SPI_struct
2541
{
2542
register8_t CTRL; /* Control Register */
2543
register8_t INTCTRL; /* Interrupt Control Register */
2544
register8_t STATUS; /* Status Register */
2545
register8_t DATA; /* Data Register */
2546
} SPI_t;
2547
2548
/* SPI Mode */
2549
typedef enum SPI_MODE_enum
2550
{
2551
SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
2552
SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
2553
SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
2554
SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
2555
} SPI_MODE_t;
2556
2557
/* Prescaler setting */
2558
typedef enum SPI_PRESCALER_enum
2559
{
2560
SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
2561
SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
2562
SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
2563
SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
2564
} SPI_PRESCALER_t;
2565
2566
/* Interrupt level */
2567
typedef enum SPI_INTLVL_enum
2568
{
2569
SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2570
SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
2571
SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
2572
SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
2573
} SPI_INTLVL_t;
2574
2575
2576
/*
2577
--------------------------------------------------------------------------
2578
IRCOM - IR Communication Module
2579
--------------------------------------------------------------------------
2580
*/
2581
2582
/* IR Communication Module */
2583
typedef struct IRCOM_struct
2584
{
2585
register8_t CTRL; /* Control Register */
2586
register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
2587
register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
2588
} IRCOM_t;
2589
2590
/* Event channel selection */
2591
typedef enum IRDA_EVSEL_enum
2592
{
2593
IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
2594
IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
2595
IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
2596
IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
2597
IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
2598
IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
2599
IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
2600
IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
2601
IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
2602
} IRDA_EVSEL_t;
2603
2604
2605
/*
2606
--------------------------------------------------------------------------
2607
PRESC - Prescaler
2608
--------------------------------------------------------------------------
2609
*/
2610
2611
/* Prescaler */
2612
typedef struct PRESC_struct
2613
{
2614
register8_t PRESCALER; /* Control Register */
2615
} PRESC_t;
2616
2617
2618
2619
/*
2620
==========================================================================
2621
IO Module Instances. Mapped to memory.
2622
==========================================================================
2623
*/
2624
2625
#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
2626
#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
2627
#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
2628
#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
2629
#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
2630
#define CLK (*(CLK_t *) 0x0040) /* Clock System */
2631
#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
2632
#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
2633
#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
2634
#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
2635
#define PR (*(PR_t *) 0x0070) /* Power Reduction */
2636
#define RST (*(RST_t *) 0x0078) /* Reset Controller */
2637
#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
2638
#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
2639
#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
2640
#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
2641
#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */
2642
#define CRC (*(CRC_t *) 0x00D0) /* CRC Module */
2643
#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
2644
#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
2645
#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
2646
#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
2647
#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */
2648
#define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */
2649
#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */
2650
#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
2651
#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */
2652
#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
2653
#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */
2654
#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
2655
#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */
2656
#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */
2657
#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */
2658
#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus Module */
2659
#define PORTA (*(PORT_t *) 0x0600) /* Port A */
2660
#define PORTB (*(PORT_t *) 0x0620) /* Port B */
2661
#define PORTC (*(PORT_t *) 0x0640) /* Port C */
2662
#define PORTD (*(PORT_t *) 0x0660) /* Port D */
2663
#define PORTE (*(PORT_t *) 0x0680) /* Port E */
2664
#define PORTF (*(PORT_t *) 0x06A0) /* Port F */
2665
#define PORTH (*(PORT_t *) 0x06E0) /* Port H */
2666
#define PORTJ (*(PORT_t *) 0x0700) /* Port J */
2667
#define PORTK (*(PORT_t *) 0x0720) /* Port K */
2668
#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */
2669
#define PORTR (*(PORT_t *) 0x07E0) /* Port R */
2670
#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
2671
#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
2672
#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
2673
#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
2674
#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
2675
#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */
2676
#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
2677
#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
2678
#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
2679
#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */
2680
#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */
2681
#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
2682
#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */
2683
#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
2684
#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
2685
#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */
2686
#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */
2687
#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */
2688
#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
2689
#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */
2690
#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */
2691
#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */
2692
#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */
2693
#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */
2694
#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */
2695
#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */
2696
#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */
2697
2698
2699
#endif /* !defined (__ASSEMBLER__) */
2700
2701
2702
/* ========== Flattened fully qualified IO register names ========== */
2703
2704
/* GPIO - General Purpose IO Registers */
2705
#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
2706
#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
2707
#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
2708
#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
2709
#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
2710
#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
2711
#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
2712
#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
2713
#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
2714
#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
2715
#define GPIO_GPIORA _SFR_MEM8(0x000A)
2716
#define GPIO_GPIORB _SFR_MEM8(0x000B)
2717
#define GPIO_GPIORC _SFR_MEM8(0x000C)
2718
#define GPIO_GPIORD _SFR_MEM8(0x000D)
2719
#define GPIO_GPIORE _SFR_MEM8(0x000E)
2720
#define GPIO_GPIORF _SFR_MEM8(0x000F)
2721
2722
/* VPORT0 - Virtual Port 0 */
2723
#define VPORT0_DIR _SFR_MEM8(0x0010)
2724
#define VPORT0_OUT _SFR_MEM8(0x0011)
2725
#define VPORT0_IN _SFR_MEM8(0x0012)
2726
#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
2727
2728
/* VPORT1 - Virtual Port 1 */
2729
#define VPORT1_DIR _SFR_MEM8(0x0014)
2730
#define VPORT1_OUT _SFR_MEM8(0x0015)
2731
#define VPORT1_IN _SFR_MEM8(0x0016)
2732
#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
2733
2734
/* VPORT2 - Virtual Port 2 */
2735
#define VPORT2_DIR _SFR_MEM8(0x0018)
2736
#define VPORT2_OUT _SFR_MEM8(0x0019)
2737
#define VPORT2_IN _SFR_MEM8(0x001A)
2738
#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
2739
2740
/* VPORT3 - Virtual Port 3 */
2741
#define VPORT3_DIR _SFR_MEM8(0x001C)
2742
#define VPORT3_OUT _SFR_MEM8(0x001D)
2743
#define VPORT3_IN _SFR_MEM8(0x001E)
2744
#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
2745
2746
/* OCD - On-Chip Debug System */
2747
#define OCD_OCDR0 _SFR_MEM8(0x002E)
2748
#define OCD_OCDR1 _SFR_MEM8(0x002F)
2749
2750
/* CPU - CPU Registers */
2751
#define CPU_CCP _SFR_MEM8(0x0034)
2752
#define CPU_RAMPD _SFR_MEM8(0x0038)
2753
#define CPU_RAMPX _SFR_MEM8(0x0039)
2754
#define CPU_RAMPY _SFR_MEM8(0x003A)
2755
#define CPU_RAMPZ _SFR_MEM8(0x003B)
2756
#define CPU_EIND _SFR_MEM8(0x003C)
2757
#define CPU_SPL _SFR_MEM8(0x003D)
2758
#define CPU_SPH _SFR_MEM8(0x003E)
2759
#define CPU_SREG _SFR_MEM8(0x003F)
2760
2761
/* CLK - Clock System */
2762
#define CLK_CTRL _SFR_MEM8(0x0040)
2763
#define CLK_PSCTRL _SFR_MEM8(0x0041)
2764
#define CLK_LOCK _SFR_MEM8(0x0042)
2765
#define CLK_RTCCTRL _SFR_MEM8(0x0043)
2766
#define CLK_USBCTRL _SFR_MEM8(0x0044)
2767
2768
/* SLEEP - Sleep Controller */
2769
#define SLEEP_CTRL _SFR_MEM8(0x0048)
2770
2771
/* OSC - Oscillator Control */
2772
#define OSC_CTRL _SFR_MEM8(0x0050)
2773
#define OSC_STATUS _SFR_MEM8(0x0051)
2774
#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
2775
#define OSC_XOSCFAIL _SFR_MEM8(0x005F)
2776
#define OSC_RC32KCAL _SFR_MEM8(0x0054)
2777
#define OSC_PLLCTRL _SFR_MEM8(0x0055)
2778
#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
2779
2780
/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
2781
#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
2782
#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
2783
#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
2784
#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
2785
#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
2786
#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
2787
2788
/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
2789
#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
2790
#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
2791
#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
2792
#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
2793
#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
2794
#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
2795
2796
/* PR - Power Reduction */
2797
#define PR_PRGEN _SFR_MEM8(0x0070)
2798
#define PR_PRPA _SFR_MEM8(0x0071)
2799
#define PR_PRPB _SFR_MEM8(0x0072)
2800
#define PR_PRPC _SFR_MEM8(0x0073)
2801
#define PR_PRPD _SFR_MEM8(0x0074)
2802
#define PR_PRPE _SFR_MEM8(0x0075)
2803
#define PR_PRPF _SFR_MEM8(0x0076)
2804
2805
/* RST - Reset Controller */
2806
#define RST_STATUS _SFR_MEM8(0x0078)
2807
#define RST_CTRL _SFR_MEM8(0x0079)
2808
2809
/* WDT - Watch-Dog Timer */
2810
#define WDT_CTRL _SFR_MEM8(0x0080)
2811
#define WDT_WINCTRL _SFR_MEM8(0x0081)
2812
#define WDT_STATUS _SFR_MEM8(0x0082)
2813
2814
/* MCU - MCU Control */
2815
#define MCU_DEVID0 _SFR_MEM8(0x0090)
2816
#define MCU_DEVID1 _SFR_MEM8(0x0091)
2817
#define MCU_DEVID2 _SFR_MEM8(0x0092)
2818
#define MCU_REVID _SFR_MEM8(0x0093)
2819
#define MCU_JTAGUID _SFR_MEM8(0x0094)
2820
#define MCU_MCUCR _SFR_MEM8(0x0096)
2821
#define MCU_ANAINIT _SFR_MEM8(0x0097)
2822
#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
2823
#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
2824
2825
/* PMIC - Programmable Interrupt Controller */
2826
#define PMIC_STATUS _SFR_MEM8(0x00A0)
2827
#define PMIC_INTPRI _SFR_MEM8(0x00A1)
2828
#define PMIC_CTRL _SFR_MEM8(0x00A2)
2829
2830
/* PORTCFG - Port Configuration */
2831
#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
2832
#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
2833
#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
2834
#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
2835
2836
/* AES - AES Crypto Module */
2837
#define AES_CTRL _SFR_MEM8(0x00C0)
2838
#define AES_STATUS _SFR_MEM8(0x00C1)
2839
#define AES_STATE _SFR_MEM8(0x00C2)
2840
#define AES_KEY _SFR_MEM8(0x00C3)
2841
#define AES_INTCTRL _SFR_MEM8(0x00C4)
2842
2843
/* CRC - CRC Module */
2844
#define CRC_CTRL _SFR_MEM8(0x00D0)
2845
#define CRC_STATUS _SFR_MEM8(0x00D1)
2846
#define CRC_DATAIN _SFR_MEM8(0x00D3)
2847
#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
2848
#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
2849
#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
2850
#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
2851
2852
/* DMA - DMA Controller */
2853
#define DMA_CTRL _SFR_MEM8(0x0100)
2854
#define DMA_INTFLAGS _SFR_MEM8(0x0103)
2855
#define DMA_STATUS _SFR_MEM8(0x0104)
2856
#define DMA_TEMP _SFR_MEM16(0x0106)
2857
#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
2858
#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
2859
#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
2860
#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
2861
#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
2862
#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
2863
#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
2864
#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
2865
#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
2866
#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
2867
#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
2868
#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
2869
#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
2870
#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
2871
#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
2872
#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
2873
#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
2874
#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
2875
#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
2876
#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
2877
#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
2878
#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
2879
#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
2880
#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
2881
#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
2882
#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
2883
#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
2884
#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
2885
#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
2886
#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
2887
#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
2888
#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
2889
#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
2890
#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
2891
#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
2892
#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
2893
#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
2894
#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
2895
#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
2896
#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
2897
#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
2898
#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
2899
#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
2900
#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
2901
#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
2902
#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
2903
#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
2904
#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
2905
2906
/* EVSYS - Event System */
2907
#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
2908
#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
2909
#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
2910
#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
2911
#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
2912
#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
2913
#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
2914
#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
2915
#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
2916
#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
2917
#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
2918
#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
2919
#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
2920
#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
2921
#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
2922
#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
2923
#define EVSYS_STROBE _SFR_MEM8(0x0190)
2924
#define EVSYS_DATA _SFR_MEM8(0x0191)
2925
2926
/* NVM - Non Volatile Memory Controller */
2927
#define NVM_ADDR0 _SFR_MEM8(0x01C0)
2928
#define NVM_ADDR1 _SFR_MEM8(0x01C1)
2929
#define NVM_ADDR2 _SFR_MEM8(0x01C2)
2930
#define NVM_DATA0 _SFR_MEM8(0x01C4)
2931
#define NVM_DATA1 _SFR_MEM8(0x01C5)
2932
#define NVM_DATA2 _SFR_MEM8(0x01C6)
2933
#define NVM_CMD _SFR_MEM8(0x01CA)
2934
#define NVM_CTRLA _SFR_MEM8(0x01CB)
2935
#define NVM_CTRLB _SFR_MEM8(0x01CC)
2936
#define NVM_INTCTRL _SFR_MEM8(0x01CD)
2937
#define NVM_STATUS _SFR_MEM8(0x01CF)
2938
#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
2939
2940
/* ADCA - Analog to Digital Converter A */
2941
#define ADCA_CTRLA _SFR_MEM8(0x0200)
2942
#define ADCA_CTRLB _SFR_MEM8(0x0201)
2943
#define ADCA_REFCTRL _SFR_MEM8(0x0202)
2944
#define ADCA_EVCTRL _SFR_MEM8(0x0203)
2945
#define ADCA_PRESCALER _SFR_MEM8(0x0204)
2946
#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
2947
#define ADCA_TEMP _SFR_MEM8(0x0207)
2948
#define ADCA_CAL _SFR_MEM16(0x020C)
2949
#define ADCA_CH0RES _SFR_MEM16(0x0210)
2950
#define ADCA_CH1RES _SFR_MEM16(0x0212)
2951
#define ADCA_CH2RES _SFR_MEM16(0x0214)
2952
#define ADCA_CH3RES _SFR_MEM16(0x0216)
2953
#define ADCA_CMP _SFR_MEM16(0x0218)
2954
#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
2955
#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
2956
#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
2957
#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
2958
#define ADCA_CH0_RES _SFR_MEM16(0x0224)
2959
#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
2960
#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
2961
#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
2962
#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
2963
#define ADCA_CH1_RES _SFR_MEM16(0x022C)
2964
#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
2965
#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
2966
#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
2967
#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
2968
#define ADCA_CH2_RES _SFR_MEM16(0x0234)
2969
#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
2970
#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
2971
#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
2972
#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
2973
#define ADCA_CH3_RES _SFR_MEM16(0x023C)
2974
2975
/* ADCB - Analog to Digital Converter B */
2976
#define ADCB_CTRLA _SFR_MEM8(0x0240)
2977
#define ADCB_CTRLB _SFR_MEM8(0x0241)
2978
#define ADCB_REFCTRL _SFR_MEM8(0x0242)
2979
#define ADCB_EVCTRL _SFR_MEM8(0x0243)
2980
#define ADCB_PRESCALER _SFR_MEM8(0x0244)
2981
#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
2982
#define ADCB_TEMP _SFR_MEM8(0x0247)
2983
#define ADCB_CAL _SFR_MEM16(0x024C)
2984
#define ADCB_CH0RES _SFR_MEM16(0x0250)
2985
#define ADCB_CH1RES _SFR_MEM16(0x0252)
2986
#define ADCB_CH2RES _SFR_MEM16(0x0254)
2987
#define ADCB_CH3RES _SFR_MEM16(0x0256)
2988
#define ADCB_CMP _SFR_MEM16(0x0258)
2989
#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
2990
#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
2991
#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
2992
#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
2993
#define ADCB_CH0_RES _SFR_MEM16(0x0264)
2994
#define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
2995
#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
2996
#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
2997
#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
2998
#define ADCB_CH1_RES _SFR_MEM16(0x026C)
2999
#define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
3000
#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
3001
#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
3002
#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
3003
#define ADCB_CH2_RES _SFR_MEM16(0x0274)
3004
#define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
3005
#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
3006
#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
3007
#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
3008
#define ADCB_CH3_RES _SFR_MEM16(0x027C)
3009
3010
/* DACA - Digital to Analog Converter A */
3011
#define DACA_CTRLA _SFR_MEM8(0x0300)
3012
#define DACA_CTRLB _SFR_MEM8(0x0301)
3013
#define DACA_CTRLC _SFR_MEM8(0x0302)
3014
#define DACA_EVCTRL _SFR_MEM8(0x0303)
3015
#define DACA_TIMCTRL _SFR_MEM8(0x0304)
3016
#define DACA_STATUS _SFR_MEM8(0x0305)
3017
#define DACA_CH0GAINCAL _SFR_MEM8(0x0308)
3018
#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309)
3019
#define DACA_CH1GAINCAL _SFR_MEM8(0x030A)
3020
#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B)
3021
#define DACA_CH0DATA _SFR_MEM16(0x0318)
3022
#define DACA_CH1DATA _SFR_MEM16(0x031A)
3023
3024
/* DACB - Digital to Analog Converter B */
3025
#define DACB_CTRLA _SFR_MEM8(0x0320)
3026
#define DACB_CTRLB _SFR_MEM8(0x0321)
3027
#define DACB_CTRLC _SFR_MEM8(0x0322)
3028
#define DACB_EVCTRL _SFR_MEM8(0x0323)
3029
#define DACB_TIMCTRL _SFR_MEM8(0x0324)
3030
#define DACB_STATUS _SFR_MEM8(0x0325)
3031
#define DACB_CH0GAINCAL _SFR_MEM8(0x0328)
3032
#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329)
3033
#define DACB_CH1GAINCAL _SFR_MEM8(0x032A)
3034
#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B)
3035
#define DACB_CH0DATA _SFR_MEM16(0x0338)
3036
#define DACB_CH1DATA _SFR_MEM16(0x033A)
3037
3038
/* ACA - Analog Comparator A */
3039
#define ACA_AC0CTRL _SFR_MEM8(0x0380)
3040
#define ACA_AC1CTRL _SFR_MEM8(0x0381)
3041
#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
3042
#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
3043
#define ACA_CTRLA _SFR_MEM8(0x0384)
3044
#define ACA_CTRLB _SFR_MEM8(0x0385)
3045
#define ACA_WINCTRL _SFR_MEM8(0x0386)
3046
#define ACA_STATUS _SFR_MEM8(0x0387)
3047
3048
/* ACB - Analog Comparator B */
3049
#define ACB_AC0CTRL _SFR_MEM8(0x0390)
3050
#define ACB_AC1CTRL _SFR_MEM8(0x0391)
3051
#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
3052
#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
3053
#define ACB_CTRLA _SFR_MEM8(0x0394)
3054
#define ACB_CTRLB _SFR_MEM8(0x0395)
3055
#define ACB_WINCTRL _SFR_MEM8(0x0396)
3056
#define ACB_STATUS _SFR_MEM8(0x0397)
3057
3058
/* RTC - Real-Time Counter */
3059
#define RTC_CTRL _SFR_MEM8(0x0400)
3060
#define RTC_STATUS _SFR_MEM8(0x0401)
3061
#define RTC_INTCTRL _SFR_MEM8(0x0402)
3062
#define RTC_INTFLAGS _SFR_MEM8(0x0403)
3063
#define RTC_TEMP _SFR_MEM8(0x0404)
3064
#define RTC_CNT _SFR_MEM16(0x0408)
3065
#define RTC_PER _SFR_MEM16(0x040A)
3066
#define RTC_COMP _SFR_MEM16(0x040C)
3067
3068
/* EBI - External Bus Interface */
3069
#define EBI_CTRL _SFR_MEM8(0x0440)
3070
#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441)
3071
#define EBI_REFRESH _SFR_MEM16(0x0444)
3072
#define EBI_INITDLY _SFR_MEM16(0x0446)
3073
#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448)
3074
#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449)
3075
#define EBI_CS0_CTRLA _SFR_MEM8(0x0450)
3076
#define EBI_CS0_CTRLB _SFR_MEM8(0x0451)
3077
#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452)
3078
#define EBI_CS1_CTRLA _SFR_MEM8(0x0454)
3079
#define EBI_CS1_CTRLB _SFR_MEM8(0x0455)
3080
#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456)
3081
#define EBI_CS2_CTRLA _SFR_MEM8(0x0458)
3082
#define EBI_CS2_CTRLB _SFR_MEM8(0x0459)
3083
#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A)
3084
#define EBI_CS3_CTRLA _SFR_MEM8(0x045C)
3085
#define EBI_CS3_CTRLB _SFR_MEM8(0x045D)
3086
#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E)
3087
3088
/* TWIC - Two-Wire Interface C */
3089
#define TWIC_CTRL _SFR_MEM8(0x0480)
3090
#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
3091
#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
3092
#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
3093
#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
3094
#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
3095
#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
3096
#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
3097
#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
3098
#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
3099
#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
3100
#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
3101
#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
3102
#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
3103
3104
/* TWID - Two-Wire Interface D */
3105
#define TWID_CTRL _SFR_MEM8(0x0490)
3106
#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491)
3107
#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492)
3108
#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493)
3109
#define TWID_MASTER_STATUS _SFR_MEM8(0x0494)
3110
#define TWID_MASTER_BAUD _SFR_MEM8(0x0495)
3111
#define TWID_MASTER_ADDR _SFR_MEM8(0x0496)
3112
#define TWID_MASTER_DATA _SFR_MEM8(0x0497)
3113
#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498)
3114
#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499)
3115
#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A)
3116
#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B)
3117
#define TWID_SLAVE_DATA _SFR_MEM8(0x049C)
3118
#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D)
3119
3120
/* TWIE - Two-Wire Interface E */
3121
#define TWIE_CTRL _SFR_MEM8(0x04A0)
3122
#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
3123
#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
3124
#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
3125
#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
3126
#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
3127
#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
3128
#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
3129
#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
3130
#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
3131
#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
3132
#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
3133
#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
3134
#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
3135
3136
/* TWIF - Two-Wire Interface F */
3137
#define TWIF_CTRL _SFR_MEM8(0x04B0)
3138
#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1)
3139
#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2)
3140
#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3)
3141
#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4)
3142
#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5)
3143
#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6)
3144
#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7)
3145
#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8)
3146
#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9)
3147
#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA)
3148
#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB)
3149
#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC)
3150
#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD)
3151
3152
/* USB - Universal Serial Bus Module */
3153
#define USB_CTRLA _SFR_MEM8(0x04C0)
3154
#define USB_CTRLB _SFR_MEM8(0x04C1)
3155
#define USB_STATUS _SFR_MEM8(0x04C2)
3156
#define USB_ADDR _SFR_MEM8(0x04C3)
3157
#define USB_FIFOWP _SFR_MEM8(0x04C4)
3158
#define USB_FIFORP _SFR_MEM8(0x04C5)
3159
#define USB_EPPTR _SFR_MEM16(0x04C6)
3160
#define USB_INTCTRLA _SFR_MEM8(0x04C8)
3161
#define USB_INTCTRLB _SFR_MEM8(0x04C9)
3162
#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
3163
#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
3164
#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
3165
#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
3166
#define USB_CAL0 _SFR_MEM8(0x04FA)
3167
#define USB_CAL1 _SFR_MEM8(0x04FB)
3168
3169
/* PORTA - Port A */
3170
#define PORTA_DIR _SFR_MEM8(0x0600)
3171
#define PORTA_DIRSET _SFR_MEM8(0x0601)
3172
#define PORTA_DIRCLR _SFR_MEM8(0x0602)
3173
#define PORTA_DIRTGL _SFR_MEM8(0x0603)
3174
#define PORTA_OUT _SFR_MEM8(0x0604)
3175
#define PORTA_OUTSET _SFR_MEM8(0x0605)
3176
#define PORTA_OUTCLR _SFR_MEM8(0x0606)
3177
#define PORTA_OUTTGL _SFR_MEM8(0x0607)
3178
#define PORTA_IN _SFR_MEM8(0x0608)
3179
#define PORTA_INTCTRL _SFR_MEM8(0x0609)
3180
#define PORTA_INT0MASK _SFR_MEM8(0x060A)
3181
#define PORTA_INT1MASK _SFR_MEM8(0x060B)
3182
#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
3183
#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
3184
#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
3185
#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
3186
#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
3187
#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
3188
#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
3189
#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
3190
#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
3191
3192
/* PORTB - Port B */
3193
#define PORTB_DIR _SFR_MEM8(0x0620)
3194
#define PORTB_DIRSET _SFR_MEM8(0x0621)
3195
#define PORTB_DIRCLR _SFR_MEM8(0x0622)
3196
#define PORTB_DIRTGL _SFR_MEM8(0x0623)
3197
#define PORTB_OUT _SFR_MEM8(0x0624)
3198
#define PORTB_OUTSET _SFR_MEM8(0x0625)
3199
#define PORTB_OUTCLR _SFR_MEM8(0x0626)
3200
#define PORTB_OUTTGL _SFR_MEM8(0x0627)
3201
#define PORTB_IN _SFR_MEM8(0x0628)
3202
#define PORTB_INTCTRL _SFR_MEM8(0x0629)
3203
#define PORTB_INT0MASK _SFR_MEM8(0x062A)
3204
#define PORTB_INT1MASK _SFR_MEM8(0x062B)
3205
#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
3206
#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
3207
#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
3208
#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
3209
#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
3210
#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
3211
#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
3212
#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
3213
#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
3214
3215
/* PORTC - Port C */
3216
#define PORTC_DIR _SFR_MEM8(0x0640)
3217
#define PORTC_DIRSET _SFR_MEM8(0x0641)
3218
#define PORTC_DIRCLR _SFR_MEM8(0x0642)
3219
#define PORTC_DIRTGL _SFR_MEM8(0x0643)
3220
#define PORTC_OUT _SFR_MEM8(0x0644)
3221
#define PORTC_OUTSET _SFR_MEM8(0x0645)
3222
#define PORTC_OUTCLR _SFR_MEM8(0x0646)
3223
#define PORTC_OUTTGL _SFR_MEM8(0x0647)
3224
#define PORTC_IN _SFR_MEM8(0x0648)
3225
#define PORTC_INTCTRL _SFR_MEM8(0x0649)
3226
#define PORTC_INT0MASK _SFR_MEM8(0x064A)
3227
#define PORTC_INT1MASK _SFR_MEM8(0x064B)
3228
#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
3229
#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
3230
#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
3231
#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
3232
#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
3233
#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
3234
#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
3235
#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
3236
#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
3237
3238
/* PORTD - Port D */
3239
#define PORTD_DIR _SFR_MEM8(0x0660)
3240
#define PORTD_DIRSET _SFR_MEM8(0x0661)
3241
#define PORTD_DIRCLR _SFR_MEM8(0x0662)
3242
#define PORTD_DIRTGL _SFR_MEM8(0x0663)
3243
#define PORTD_OUT _SFR_MEM8(0x0664)
3244
#define PORTD_OUTSET _SFR_MEM8(0x0665)
3245
#define PORTD_OUTCLR _SFR_MEM8(0x0666)
3246
#define PORTD_OUTTGL _SFR_MEM8(0x0667)
3247
#define PORTD_IN _SFR_MEM8(0x0668)
3248
#define PORTD_INTCTRL _SFR_MEM8(0x0669)
3249
#define PORTD_INT0MASK _SFR_MEM8(0x066A)
3250
#define PORTD_INT1MASK _SFR_MEM8(0x066B)
3251
#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
3252
#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
3253
#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
3254
#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
3255
#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
3256
#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
3257
#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
3258
#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
3259
#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
3260
3261
/* PORTE - Port E */
3262
#define PORTE_DIR _SFR_MEM8(0x0680)
3263
#define PORTE_DIRSET _SFR_MEM8(0x0681)
3264
#define PORTE_DIRCLR _SFR_MEM8(0x0682)
3265
#define PORTE_DIRTGL _SFR_MEM8(0x0683)
3266
#define PORTE_OUT _SFR_MEM8(0x0684)
3267
#define PORTE_OUTSET _SFR_MEM8(0x0685)
3268
#define PORTE_OUTCLR _SFR_MEM8(0x0686)
3269
#define PORTE_OUTTGL _SFR_MEM8(0x0687)
3270
#define PORTE_IN _SFR_MEM8(0x0688)
3271
#define PORTE_INTCTRL _SFR_MEM8(0x0689)
3272
#define PORTE_INT0MASK _SFR_MEM8(0x068A)
3273
#define PORTE_INT1MASK _SFR_MEM8(0x068B)
3274
#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
3275
#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
3276
#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
3277
#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
3278
#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
3279
#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
3280
#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
3281
#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
3282
#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
3283
3284
/* PORTF - Port F */
3285
#define PORTF_DIR _SFR_MEM8(0x06A0)
3286
#define PORTF_DIRSET _SFR_MEM8(0x06A1)
3287
#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
3288
#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
3289
#define PORTF_OUT _SFR_MEM8(0x06A4)
3290
#define PORTF_OUTSET _SFR_MEM8(0x06A5)
3291
#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
3292
#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
3293
#define PORTF_IN _SFR_MEM8(0x06A8)
3294
#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
3295
#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
3296
#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
3297
#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
3298
#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
3299
#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
3300
#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
3301
#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
3302
#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
3303
#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
3304
#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
3305
#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
3306
3307
/* PORTH - Port H */
3308
#define PORTH_DIR _SFR_MEM8(0x06E0)
3309
#define PORTH_DIRSET _SFR_MEM8(0x06E1)
3310
#define PORTH_DIRCLR _SFR_MEM8(0x06E2)
3311
#define PORTH_DIRTGL _SFR_MEM8(0x06E3)
3312
#define PORTH_OUT _SFR_MEM8(0x06E4)
3313
#define PORTH_OUTSET _SFR_MEM8(0x06E5)
3314
#define PORTH_OUTCLR _SFR_MEM8(0x06E6)
3315
#define PORTH_OUTTGL _SFR_MEM8(0x06E7)
3316
#define PORTH_IN _SFR_MEM8(0x06E8)
3317
#define PORTH_INTCTRL _SFR_MEM8(0x06E9)
3318
#define PORTH_INT0MASK _SFR_MEM8(0x06EA)
3319
#define PORTH_INT1MASK _SFR_MEM8(0x06EB)
3320
#define PORTH_INTFLAGS _SFR_MEM8(0x06EC)
3321
#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0)
3322
#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1)
3323
#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2)
3324
#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3)
3325
#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4)
3326
#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5)
3327
#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6)
3328
#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7)
3329
3330
/* PORTJ - Port J */
3331
#define PORTJ_DIR _SFR_MEM8(0x0700)
3332
#define PORTJ_DIRSET _SFR_MEM8(0x0701)
3333
#define PORTJ_DIRCLR _SFR_MEM8(0x0702)
3334
#define PORTJ_DIRTGL _SFR_MEM8(0x0703)
3335
#define PORTJ_OUT _SFR_MEM8(0x0704)
3336
#define PORTJ_OUTSET _SFR_MEM8(0x0705)
3337
#define PORTJ_OUTCLR _SFR_MEM8(0x0706)
3338
#define PORTJ_OUTTGL _SFR_MEM8(0x0707)
3339
#define PORTJ_IN _SFR_MEM8(0x0708)
3340
#define PORTJ_INTCTRL _SFR_MEM8(0x0709)
3341
#define PORTJ_INT0MASK _SFR_MEM8(0x070A)
3342
#define PORTJ_INT1MASK _SFR_MEM8(0x070B)
3343
#define PORTJ_INTFLAGS _SFR_MEM8(0x070C)
3344
#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710)
3345
#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711)
3346
#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712)
3347
#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713)
3348
#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714)
3349
#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715)
3350
#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716)
3351
#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717)
3352
3353
/* PORTK - Port K */
3354
#define PORTK_DIR _SFR_MEM8(0x0720)
3355
#define PORTK_DIRSET _SFR_MEM8(0x0721)
3356
#define PORTK_DIRCLR _SFR_MEM8(0x0722)
3357
#define PORTK_DIRTGL _SFR_MEM8(0x0723)
3358
#define PORTK_OUT _SFR_MEM8(0x0724)
3359
#define PORTK_OUTSET _SFR_MEM8(0x0725)
3360
#define PORTK_OUTCLR _SFR_MEM8(0x0726)
3361
#define PORTK_OUTTGL _SFR_MEM8(0x0727)
3362
#define PORTK_IN _SFR_MEM8(0x0728)
3363
#define PORTK_INTCTRL _SFR_MEM8(0x0729)
3364
#define PORTK_INT0MASK _SFR_MEM8(0x072A)
3365
#define PORTK_INT1MASK _SFR_MEM8(0x072B)
3366
#define PORTK_INTFLAGS _SFR_MEM8(0x072C)
3367
#define PORTK_PIN0CTRL _SFR_MEM8(0x0730)
3368
#define PORTK_PIN1CTRL _SFR_MEM8(0x0731)
3369
#define PORTK_PIN2CTRL _SFR_MEM8(0x0732)
3370
#define PORTK_PIN3CTRL _SFR_MEM8(0x0733)
3371
#define PORTK_PIN4CTRL _SFR_MEM8(0x0734)
3372
#define PORTK_PIN5CTRL _SFR_MEM8(0x0735)
3373
#define PORTK_PIN6CTRL _SFR_MEM8(0x0736)
3374
#define PORTK_PIN7CTRL _SFR_MEM8(0x0737)
3375
3376
/* PORTQ - Port Q */
3377
#define PORTQ_DIR _SFR_MEM8(0x07C0)
3378
#define PORTQ_DIRSET _SFR_MEM8(0x07C1)
3379
#define PORTQ_DIRCLR _SFR_MEM8(0x07C2)
3380
#define PORTQ_DIRTGL _SFR_MEM8(0x07C3)
3381
#define PORTQ_OUT _SFR_MEM8(0x07C4)
3382
#define PORTQ_OUTSET _SFR_MEM8(0x07C5)
3383
#define PORTQ_OUTCLR _SFR_MEM8(0x07C6)
3384
#define PORTQ_OUTTGL _SFR_MEM8(0x07C7)
3385
#define PORTQ_IN _SFR_MEM8(0x07C8)
3386
#define PORTQ_INTCTRL _SFR_MEM8(0x07C9)
3387
#define PORTQ_INT0MASK _SFR_MEM8(0x07CA)
3388
#define PORTQ_INT1MASK _SFR_MEM8(0x07CB)
3389
#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC)
3390
#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0)
3391
#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1)
3392
#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2)
3393
#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3)
3394
#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4)
3395
#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5)
3396
#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6)
3397
#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7)
3398
3399
/* PORTR - Port R */
3400
#define PORTR_DIR _SFR_MEM8(0x07E0)
3401
#define PORTR_DIRSET _SFR_MEM8(0x07E1)
3402
#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
3403
#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
3404
#define PORTR_OUT _SFR_MEM8(0x07E4)
3405
#define PORTR_OUTSET _SFR_MEM8(0x07E5)
3406
#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
3407
#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
3408
#define PORTR_IN _SFR_MEM8(0x07E8)
3409
#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
3410
#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
3411
#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
3412
#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
3413
#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
3414
#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
3415
#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
3416
#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
3417
#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
3418
#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
3419
#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
3420
#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
3421
3422
/* TCC0 - Timer/Counter C0 */
3423
#define TCC0_CTRLA _SFR_MEM8(0x0800)
3424
#define TCC0_CTRLB _SFR_MEM8(0x0801)
3425
#define TCC0_CTRLC _SFR_MEM8(0x0802)
3426
#define TCC0_CTRLD _SFR_MEM8(0x0803)
3427
#define TCC0_CTRLE _SFR_MEM8(0x0804)
3428
#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
3429
#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
3430
#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
3431
#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
3432
#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
3433
#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
3434
#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
3435
#define TCC0_TEMP _SFR_MEM8(0x080F)
3436
#define TCC0_CNT _SFR_MEM16(0x0820)
3437
#define TCC0_PER _SFR_MEM16(0x0826)
3438
#define TCC0_CCA _SFR_MEM16(0x0828)
3439
#define TCC0_CCB _SFR_MEM16(0x082A)
3440
#define TCC0_CCC _SFR_MEM16(0x082C)
3441
#define TCC0_CCD _SFR_MEM16(0x082E)
3442
#define TCC0_PERBUF _SFR_MEM16(0x0836)
3443
#define TCC0_CCABUF _SFR_MEM16(0x0838)
3444
#define TCC0_CCBBUF _SFR_MEM16(0x083A)
3445
#define TCC0_CCCBUF _SFR_MEM16(0x083C)
3446
#define TCC0_CCDBUF _SFR_MEM16(0x083E)
3447
3448
/* TCC1 - Timer/Counter C1 */
3449
#define TCC1_CTRLA _SFR_MEM8(0x0840)
3450
#define TCC1_CTRLB _SFR_MEM8(0x0841)
3451
#define TCC1_CTRLC _SFR_MEM8(0x0842)
3452
#define TCC1_CTRLD _SFR_MEM8(0x0843)
3453
#define TCC1_CTRLE _SFR_MEM8(0x0844)
3454
#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
3455
#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
3456
#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
3457
#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
3458
#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
3459
#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
3460
#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
3461
#define TCC1_TEMP _SFR_MEM8(0x084F)
3462
#define TCC1_CNT _SFR_MEM16(0x0860)
3463
#define TCC1_PER _SFR_MEM16(0x0866)
3464
#define TCC1_CCA _SFR_MEM16(0x0868)
3465
#define TCC1_CCB _SFR_MEM16(0x086A)
3466
#define TCC1_PERBUF _SFR_MEM16(0x0876)
3467
#define TCC1_CCABUF _SFR_MEM16(0x0878)
3468
#define TCC1_CCBBUF _SFR_MEM16(0x087A)
3469
3470
/* AWEXC - Advanced Waveform Extension C */
3471
#define AWEXC_CTRL _SFR_MEM8(0x0880)
3472
#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
3473
#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
3474
#define AWEXC_STATUS _SFR_MEM8(0x0884)
3475
#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
3476
#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
3477
#define AWEXC_DTLS _SFR_MEM8(0x0888)
3478
#define AWEXC_DTHS _SFR_MEM8(0x0889)
3479
#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
3480
#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
3481
#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
3482
3483
/* HIRESC - High-Resolution Extension C */
3484
#define HIRESC_CTRLA _SFR_MEM8(0x0890)
3485
3486
/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
3487
#define USARTC0_DATA _SFR_MEM8(0x08A0)
3488
#define USARTC0_STATUS _SFR_MEM8(0x08A1)
3489
#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
3490
#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
3491
#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
3492
#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
3493
#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
3494
3495
/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
3496
#define USARTC1_DATA _SFR_MEM8(0x08B0)
3497
#define USARTC1_STATUS _SFR_MEM8(0x08B1)
3498
#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
3499
#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
3500
#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
3501
#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
3502
#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
3503
3504
/* SPIC - Serial Peripheral Interface C */
3505
#define SPIC_CTRL _SFR_MEM8(0x08C0)
3506
#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
3507
#define SPIC_STATUS _SFR_MEM8(0x08C2)
3508
#define SPIC_DATA _SFR_MEM8(0x08C3)
3509
3510
/* IRCOM - IR Communication Module */
3511
#define IRCOM_CTRL _SFR_MEM8(0x08F8)
3512
#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
3513
#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
3514
3515
/* TCD0 - Timer/Counter D0 */
3516
#define TCD0_CTRLA _SFR_MEM8(0x0900)
3517
#define TCD0_CTRLB _SFR_MEM8(0x0901)
3518
#define TCD0_CTRLC _SFR_MEM8(0x0902)
3519
#define TCD0_CTRLD _SFR_MEM8(0x0903)
3520
#define TCD0_CTRLE _SFR_MEM8(0x0904)
3521
#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
3522
#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
3523
#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
3524
#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
3525
#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
3526
#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
3527
#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
3528
#define TCD0_TEMP _SFR_MEM8(0x090F)
3529
#define TCD0_CNT _SFR_MEM16(0x0920)
3530
#define TCD0_PER _SFR_MEM16(0x0926)
3531
#define TCD0_CCA _SFR_MEM16(0x0928)
3532
#define TCD0_CCB _SFR_MEM16(0x092A)
3533
#define TCD0_CCC _SFR_MEM16(0x092C)
3534
#define TCD0_CCD _SFR_MEM16(0x092E)
3535
#define TCD0_PERBUF _SFR_MEM16(0x0936)
3536
#define TCD0_CCABUF _SFR_MEM16(0x0938)
3537
#define TCD0_CCBBUF _SFR_MEM16(0x093A)
3538
#define TCD0_CCCBUF _SFR_MEM16(0x093C)
3539
#define TCD0_CCDBUF _SFR_MEM16(0x093E)
3540
3541
/* TCD1 - Timer/Counter D1 */
3542
#define TCD1_CTRLA _SFR_MEM8(0x0940)
3543
#define TCD1_CTRLB _SFR_MEM8(0x0941)
3544
#define TCD1_CTRLC _SFR_MEM8(0x0942)
3545
#define TCD1_CTRLD _SFR_MEM8(0x0943)
3546
#define TCD1_CTRLE _SFR_MEM8(0x0944)
3547
#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
3548
#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
3549
#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
3550
#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
3551
#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
3552
#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
3553
#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
3554
#define TCD1_TEMP _SFR_MEM8(0x094F)
3555
#define TCD1_CNT _SFR_MEM16(0x0960)
3556
#define TCD1_PER _SFR_MEM16(0x0966)
3557
#define TCD1_CCA _SFR_MEM16(0x0968)
3558
#define TCD1_CCB _SFR_MEM16(0x096A)
3559
#define TCD1_PERBUF _SFR_MEM16(0x0976)
3560
#define TCD1_CCABUF _SFR_MEM16(0x0978)
3561
#define TCD1_CCBBUF _SFR_MEM16(0x097A)
3562
3563
/* HIRESD - High-Resolution Extension D */
3564
#define HIRESD_CTRLA _SFR_MEM8(0x0990)
3565
3566
/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
3567
#define USARTD0_DATA _SFR_MEM8(0x09A0)
3568
#define USARTD0_STATUS _SFR_MEM8(0x09A1)
3569
#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
3570
#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
3571
#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
3572
#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
3573
#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
3574
3575
/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
3576
#define USARTD1_DATA _SFR_MEM8(0x09B0)
3577
#define USARTD1_STATUS _SFR_MEM8(0x09B1)
3578
#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
3579
#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
3580
#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
3581
#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
3582
#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
3583
3584
/* SPID - Serial Peripheral Interface D */
3585
#define SPID_CTRL _SFR_MEM8(0x09C0)
3586
#define SPID_INTCTRL _SFR_MEM8(0x09C1)
3587
#define SPID_STATUS _SFR_MEM8(0x09C2)
3588
#define SPID_DATA _SFR_MEM8(0x09C3)
3589
3590
/* TCE0 - Timer/Counter E0 */
3591
#define TCE0_CTRLA _SFR_MEM8(0x0A00)
3592
#define TCE0_CTRLB _SFR_MEM8(0x0A01)
3593
#define TCE0_CTRLC _SFR_MEM8(0x0A02)
3594
#define TCE0_CTRLD _SFR_MEM8(0x0A03)
3595
#define TCE0_CTRLE _SFR_MEM8(0x0A04)
3596
#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
3597
#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
3598
#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
3599
#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
3600
#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
3601
#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
3602
#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
3603
#define TCE0_TEMP _SFR_MEM8(0x0A0F)
3604
#define TCE0_CNT _SFR_MEM16(0x0A20)
3605
#define TCE0_PER _SFR_MEM16(0x0A26)
3606
#define TCE0_CCA _SFR_MEM16(0x0A28)
3607
#define TCE0_CCB _SFR_MEM16(0x0A2A)
3608
#define TCE0_CCC _SFR_MEM16(0x0A2C)
3609
#define TCE0_CCD _SFR_MEM16(0x0A2E)
3610
#define TCE0_PERBUF _SFR_MEM16(0x0A36)
3611
#define TCE0_CCABUF _SFR_MEM16(0x0A38)
3612
#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
3613
#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
3614
#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
3615
3616
/* TCE1 - Timer/Counter E1 */
3617
#define TCE1_CTRLA _SFR_MEM8(0x0A40)
3618
#define TCE1_CTRLB _SFR_MEM8(0x0A41)
3619
#define TCE1_CTRLC _SFR_MEM8(0x0A42)
3620
#define TCE1_CTRLD _SFR_MEM8(0x0A43)
3621
#define TCE1_CTRLE _SFR_MEM8(0x0A44)
3622
#define TCE1_INTCTRLA _SFR_MEM8(0x0A46)
3623
#define TCE1_INTCTRLB _SFR_MEM8(0x0A47)
3624
#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48)
3625
#define TCE1_CTRLFSET _SFR_MEM8(0x0A49)
3626
#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A)
3627
#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B)
3628
#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C)
3629
#define TCE1_TEMP _SFR_MEM8(0x0A4F)
3630
#define TCE1_CNT _SFR_MEM16(0x0A60)
3631
#define TCE1_PER _SFR_MEM16(0x0A66)
3632
#define TCE1_CCA _SFR_MEM16(0x0A68)
3633
#define TCE1_CCB _SFR_MEM16(0x0A6A)
3634
#define TCE1_PERBUF _SFR_MEM16(0x0A76)
3635
#define TCE1_CCABUF _SFR_MEM16(0x0A78)
3636
#define TCE1_CCBBUF _SFR_MEM16(0x0A7A)
3637
3638
/* AWEXE - Advanced Waveform Extension E */
3639
#define AWEXE_CTRL _SFR_MEM8(0x0A80)
3640
#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
3641
#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
3642
#define AWEXE_STATUS _SFR_MEM8(0x0A84)
3643
#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
3644
#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
3645
#define AWEXE_DTLS _SFR_MEM8(0x0A88)
3646
#define AWEXE_DTHS _SFR_MEM8(0x0A89)
3647
#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
3648
#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
3649
#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
3650
3651
/* HIRESE - High-Resolution Extension E */
3652
#define HIRESE_CTRLA _SFR_MEM8(0x0A90)
3653
3654
/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
3655
#define USARTE0_DATA _SFR_MEM8(0x0AA0)
3656
#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
3657
#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
3658
#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
3659
#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
3660
#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
3661
#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
3662
3663
/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
3664
#define USARTE1_DATA _SFR_MEM8(0x0AB0)
3665
#define USARTE1_STATUS _SFR_MEM8(0x0AB1)
3666
#define USARTE1_CTRLA _SFR_MEM8(0x0AB3)
3667
#define USARTE1_CTRLB _SFR_MEM8(0x0AB4)
3668
#define USARTE1_CTRLC _SFR_MEM8(0x0AB5)
3669
#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6)
3670
#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7)
3671
3672
/* SPIE - Serial Peripheral Interface E */
3673
#define SPIE_CTRL _SFR_MEM8(0x0AC0)
3674
#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
3675
#define SPIE_STATUS _SFR_MEM8(0x0AC2)
3676
#define SPIE_DATA _SFR_MEM8(0x0AC3)
3677
3678
/* TCF0 - Timer/Counter F0 */
3679
#define TCF0_CTRLA _SFR_MEM8(0x0B00)
3680
#define TCF0_CTRLB _SFR_MEM8(0x0B01)
3681
#define TCF0_CTRLC _SFR_MEM8(0x0B02)
3682
#define TCF0_CTRLD _SFR_MEM8(0x0B03)
3683
#define TCF0_CTRLE _SFR_MEM8(0x0B04)
3684
#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
3685
#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
3686
#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
3687
#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
3688
#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
3689
#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
3690
#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
3691
#define TCF0_TEMP _SFR_MEM8(0x0B0F)
3692
#define TCF0_CNT _SFR_MEM16(0x0B20)
3693
#define TCF0_PER _SFR_MEM16(0x0B26)
3694
#define TCF0_CCA _SFR_MEM16(0x0B28)
3695
#define TCF0_CCB _SFR_MEM16(0x0B2A)
3696
#define TCF0_CCC _SFR_MEM16(0x0B2C)
3697
#define TCF0_CCD _SFR_MEM16(0x0B2E)
3698
#define TCF0_PERBUF _SFR_MEM16(0x0B36)
3699
#define TCF0_CCABUF _SFR_MEM16(0x0B38)
3700
#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
3701
#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
3702
#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
3703
3704
/* TCF1 - Timer/Counter F1 */
3705
#define TCF1_CTRLA _SFR_MEM8(0x0B40)
3706
#define TCF1_CTRLB _SFR_MEM8(0x0B41)
3707
#define TCF1_CTRLC _SFR_MEM8(0x0B42)
3708
#define TCF1_CTRLD _SFR_MEM8(0x0B43)
3709
#define TCF1_CTRLE _SFR_MEM8(0x0B44)
3710
#define TCF1_INTCTRLA _SFR_MEM8(0x0B46)
3711
#define TCF1_INTCTRLB _SFR_MEM8(0x0B47)
3712
#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48)
3713
#define TCF1_CTRLFSET _SFR_MEM8(0x0B49)
3714
#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A)
3715
#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B)
3716
#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C)
3717
#define TCF1_TEMP _SFR_MEM8(0x0B4F)
3718
#define TCF1_CNT _SFR_MEM16(0x0B60)
3719
#define TCF1_PER _SFR_MEM16(0x0B66)
3720
#define TCF1_CCA _SFR_MEM16(0x0B68)
3721
#define TCF1_CCB _SFR_MEM16(0x0B6A)
3722
#define TCF1_PERBUF _SFR_MEM16(0x0B76)
3723
#define TCF1_CCABUF _SFR_MEM16(0x0B78)
3724
#define TCF1_CCBBUF _SFR_MEM16(0x0B7A)
3725
3726
/* HIRESF - High-Resolution Extension F */
3727
#define HIRESF_CTRLA _SFR_MEM8(0x0B90)
3728
3729
/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
3730
#define USARTF0_DATA _SFR_MEM8(0x0BA0)
3731
#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
3732
#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
3733
#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
3734
#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
3735
#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
3736
#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
3737
3738
/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
3739
#define USARTF1_DATA _SFR_MEM8(0x0BB0)
3740
#define USARTF1_STATUS _SFR_MEM8(0x0BB1)
3741
#define USARTF1_CTRLA _SFR_MEM8(0x0BB3)
3742
#define USARTF1_CTRLB _SFR_MEM8(0x0BB4)
3743
#define USARTF1_CTRLC _SFR_MEM8(0x0BB5)
3744
#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6)
3745
#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7)
3746
3747
/* SPIF - Serial Peripheral Interface F */
3748
#define SPIF_CTRL _SFR_MEM8(0x0BC0)
3749
#define SPIF_INTCTRL _SFR_MEM8(0x0BC1)
3750
#define SPIF_STATUS _SFR_MEM8(0x0BC2)
3751
#define SPIF_DATA _SFR_MEM8(0x0BC3)
3752
3753
3754
3755
/*================== Bitfield Definitions ================== */
3756
3757
/* VPORT - Virtual Ports */
3758
/* VPORT.INTFLAGS bit masks and bit positions */
3759
#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
3760
#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
3761
3762
#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
3763
#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
3764
3765
3766
/* XOCD - On-Chip Debug System */
3767
/* OCD.OCDR1 bit masks and bit positions */
3768
#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
3769
#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
3770
3771
3772
/* CPU - CPU */
3773
/* CPU.CCP bit masks and bit positions */
3774
#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
3775
#define CPU_CCP_gp 0 /* CCP signature group position. */
3776
#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
3777
#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
3778
#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
3779
#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
3780
#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
3781
#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
3782
#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
3783
#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
3784
#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
3785
#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
3786
#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
3787
#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
3788
#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
3789
#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
3790
#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
3791
#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
3792
3793
3794
/* CPU.SREG bit masks and bit positions */
3795
#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
3796
#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
3797
3798
#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
3799
#define CPU_T_bp 6 /* Transfer Bit bit position. */
3800
3801
#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
3802
#define CPU_H_bp 5 /* Half Carry Flag bit position. */
3803
3804
#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
3805
#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
3806
3807
#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
3808
#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
3809
3810
#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
3811
#define CPU_N_bp 2 /* Negative Flag bit position. */
3812
3813
#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
3814
#define CPU_Z_bp 1 /* Zero Flag bit position. */
3815
3816
#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
3817
#define CPU_C_bp 0 /* Carry Flag bit position. */
3818
3819
3820
/* CLK - Clock System */
3821
/* CLK.CTRL bit masks and bit positions */
3822
#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
3823
#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
3824
#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
3825
#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
3826
#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
3827
#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
3828
#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
3829
#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
3830
3831
3832
/* CLK.PSCTRL bit masks and bit positions */
3833
#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
3834
#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
3835
#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
3836
#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
3837
#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
3838
#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
3839
#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
3840
#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
3841
#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
3842
#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
3843
#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
3844
#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
3845
3846
#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
3847
#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
3848
#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
3849
#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
3850
#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
3851
#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
3852
3853
3854
/* CLK.LOCK bit masks and bit positions */
3855
#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
3856
#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
3857
3858
3859
/* CLK.RTCCTRL bit masks and bit positions */
3860
#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
3861
#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
3862
#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
3863
#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
3864
#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
3865
#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
3866
#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
3867
#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
3868
3869
#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
3870
#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
3871
3872
3873
/* CLK.USBCTRL bit masks and bit positions */
3874
#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
3875
#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
3876
#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
3877
#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
3878
#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
3879
#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
3880
#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
3881
#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
3882
3883
#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
3884
#define CLK_USBSRC_gp 1 /* Clock Source group position. */
3885
#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
3886
#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
3887
#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
3888
#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
3889
3890
#define CLK_USBEN_bm 0x01 /* Clock Source Enable bit mask. */
3891
#define CLK_USBEN_bp 0 /* Clock Source Enable bit position. */
3892
3893
3894
/* PR.PRGEN bit masks and bit positions */
3895
#define PR_USB_bm 0x40 /* USB bit mask. */
3896
#define PR_USB_bp 6 /* USB bit position. */
3897
3898
#define PR_AES_bm 0x10 /* AES bit mask. */
3899
#define PR_AES_bp 4 /* AES bit position. */
3900
3901
#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
3902
#define PR_EBI_bp 3 /* External Bus Interface bit position. */
3903
3904
#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
3905
#define PR_RTC_bp 2 /* Real-time Counter bit position. */
3906
3907
#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
3908
#define PR_EVSYS_bp 1 /* Event System bit position. */
3909
3910
#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
3911
#define PR_DMA_bp 0 /* DMA-Controller bit position. */
3912
3913
3914
/* PR.PRPA bit masks and bit positions */
3915
#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
3916
#define PR_DAC_bp 2 /* Port A DAC bit position. */
3917
3918
#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
3919
#define PR_ADC_bp 1 /* Port A ADC bit position. */
3920
3921
#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
3922
#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
3923
3924
3925
/* PR.PRPB bit masks and bit positions */
3926
/* PR_DAC_bm Predefined. */
3927
/* PR_DAC_bp Predefined. */
3928
3929
/* PR_ADC_bm Predefined. */
3930
/* PR_ADC_bp Predefined. */
3931
3932
/* PR_AC_bm Predefined. */
3933
/* PR_AC_bp Predefined. */
3934
3935
3936
/* PR.PRPC bit masks and bit positions */
3937
#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
3938
#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
3939
3940
#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
3941
#define PR_USART1_bp 5 /* Port C USART1 bit position. */
3942
3943
#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
3944
#define PR_USART0_bp 4 /* Port C USART0 bit position. */
3945
3946
#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
3947
#define PR_SPI_bp 3 /* Port C SPI bit position. */
3948
3949
#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
3950
#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
3951
3952
#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
3953
#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
3954
3955
#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
3956
#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
3957
3958
3959
/* PR.PRPD bit masks and bit positions */
3960
/* PR_TWI_bm Predefined. */
3961
/* PR_TWI_bp Predefined. */
3962
3963
/* PR_USART1_bm Predefined. */
3964
/* PR_USART1_bp Predefined. */
3965
3966
/* PR_USART0_bm Predefined. */
3967
/* PR_USART0_bp Predefined. */
3968
3969
/* PR_SPI_bm Predefined. */
3970
/* PR_SPI_bp Predefined. */
3971
3972
/* PR_HIRES_bm Predefined. */
3973
/* PR_HIRES_bp Predefined. */
3974
3975
/* PR_TC1_bm Predefined. */
3976
/* PR_TC1_bp Predefined. */
3977
3978
/* PR_TC0_bm Predefined. */
3979
/* PR_TC0_bp Predefined. */
3980
3981
3982
/* PR.PRPE bit masks and bit positions */
3983
/* PR_TWI_bm Predefined. */
3984
/* PR_TWI_bp Predefined. */
3985
3986
/* PR_USART1_bm Predefined. */
3987
/* PR_USART1_bp Predefined. */
3988
3989
/* PR_USART0_bm Predefined. */
3990
/* PR_USART0_bp Predefined. */
3991
3992
/* PR_SPI_bm Predefined. */
3993
/* PR_SPI_bp Predefined. */
3994
3995
/* PR_HIRES_bm Predefined. */
3996
/* PR_HIRES_bp Predefined. */
3997
3998
/* PR_TC1_bm Predefined. */
3999
/* PR_TC1_bp Predefined. */
4000
4001
/* PR_TC0_bm Predefined. */
4002
/* PR_TC0_bp Predefined. */
4003
4004
4005
/* PR.PRPF bit masks and bit positions */
4006
/* PR_TWI_bm Predefined. */
4007
/* PR_TWI_bp Predefined. */
4008
4009
/* PR_USART1_bm Predefined. */
4010
/* PR_USART1_bp Predefined. */
4011
4012
/* PR_USART0_bm Predefined. */
4013
/* PR_USART0_bp Predefined. */
4014
4015
/* PR_SPI_bm Predefined. */
4016
/* PR_SPI_bp Predefined. */
4017
4018
/* PR_HIRES_bm Predefined. */
4019
/* PR_HIRES_bp Predefined. */
4020
4021
/* PR_TC1_bm Predefined. */
4022
/* PR_TC1_bp Predefined. */
4023
4024
/* PR_TC0_bm Predefined. */
4025
/* PR_TC0_bp Predefined. */
4026
4027
4028
/* SLEEP - Sleep Controller */
4029
/* SLEEP.CTRL bit masks and bit positions */
4030
#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
4031
#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
4032
#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
4033
#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
4034
#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
4035
#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
4036
#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
4037
#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
4038
4039
#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
4040
#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
4041
4042
4043
/* OSC - Oscillator */
4044
/* OSC.CTRL bit masks and bit positions */
4045
#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
4046
#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
4047
4048
#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
4049
#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
4050
4051
#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
4052
#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
4053
4054
#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
4055
#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
4056
4057
#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
4058
#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
4059
4060
4061
/* OSC.STATUS bit masks and bit positions */
4062
#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
4063
#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
4064
4065
#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
4066
#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
4067
4068
#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
4069
#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
4070
4071
#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
4072
#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
4073
4074
#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
4075
#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
4076
4077
4078
/* OSC.XOSCCTRL bit masks and bit positions */
4079
#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
4080
#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
4081
#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
4082
#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
4083
#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
4084
#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
4085
4086
#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
4087
#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
4088
4089
#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
4090
#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
4091
#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
4092
#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
4093
#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
4094
#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
4095
#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
4096
#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
4097
#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
4098
#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
4099
4100
4101
/* OSC.XOSCFAIL bit masks and bit positions */
4102
#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
4103
#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
4104
4105
#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
4106
#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
4107
4108
#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
4109
#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
4110
4111
#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
4112
#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
4113
4114
4115
/* OSC.PLLCTRL bit masks and bit positions */
4116
#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
4117
#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
4118
#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
4119
#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
4120
#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
4121
#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
4122
4123
#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
4124
#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
4125
#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
4126
#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
4127
#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
4128
#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
4129
#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
4130
#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
4131
#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
4132
#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
4133
#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
4134
#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
4135
4136
4137
/* OSC.DFLLCTRL bit masks and bit positions */
4138
#define OSC_RC32MCREF_gm 0x06 /* 32 MHz Calibration Reference group mask. */
4139
#define OSC_RC32MCREF_gp 1 /* 32 MHz Calibration Reference group position. */
4140
#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz Calibration Reference bit 0 mask. */
4141
#define OSC_RC32MCREF0_bp 1 /* 32 MHz Calibration Reference bit 0 position. */
4142
#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz Calibration Reference bit 1 mask. */
4143
#define OSC_RC32MCREF1_bp 2 /* 32 MHz Calibration Reference bit 1 position. */
4144
4145
#define OSC_RC2MCREF_bm 0x01 /* 2 MHz Calibration Reference bit mask. */
4146
#define OSC_RC2MCREF_bp 0 /* 2 MHz Calibration Reference bit position. */
4147
4148
4149
/* DFLL - DFLL */
4150
/* DFLL.CTRL bit masks and bit positions */
4151
#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
4152
#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
4153
4154
4155
/* DFLL.CALA bit masks and bit positions */
4156
#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
4157
#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
4158
#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
4159
#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
4160
#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
4161
#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
4162
#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
4163
#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
4164
#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
4165
#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
4166
#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
4167
#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
4168
#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
4169
#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
4170
#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
4171
#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
4172
4173
4174
/* DFLL.CALB bit masks and bit positions */
4175
#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
4176
#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
4177
#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
4178
#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
4179
#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
4180
#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
4181
#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
4182
#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
4183
#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
4184
#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
4185
#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
4186
#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
4187
#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
4188
#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
4189
4190
4191
/* RST - Reset */
4192
/* RST.STATUS bit masks and bit positions */
4193
#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
4194
#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
4195
4196
#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
4197
#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
4198
4199
#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
4200
#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
4201
4202
#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
4203
#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
4204
4205
#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
4206
#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
4207
4208
#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
4209
#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
4210
4211
#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
4212
#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
4213
4214
4215
/* RST.CTRL bit masks and bit positions */
4216
#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
4217
#define RST_SWRST_bp 0 /* Software Reset bit position. */
4218
4219
4220
/* WDT - Watch-Dog Timer */
4221
/* WDT.CTRL bit masks and bit positions */
4222
#define WDT_PER_gm 0x3C /* Period group mask. */
4223
#define WDT_PER_gp 2 /* Period group position. */
4224
#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
4225
#define WDT_PER0_bp 2 /* Period bit 0 position. */
4226
#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
4227
#define WDT_PER1_bp 3 /* Period bit 1 position. */
4228
#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
4229
#define WDT_PER2_bp 4 /* Period bit 2 position. */
4230
#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
4231
#define WDT_PER3_bp 5 /* Period bit 3 position. */
4232
4233
#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
4234
#define WDT_ENABLE_bp 1 /* Enable bit position. */
4235
4236
#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
4237
#define WDT_CEN_bp 0 /* Change Enable bit position. */
4238
4239
4240
/* WDT.WINCTRL bit masks and bit positions */
4241
#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
4242
#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
4243
#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
4244
#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
4245
#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
4246
#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
4247
#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
4248
#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
4249
#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
4250
#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
4251
4252
#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
4253
#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
4254
4255
#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
4256
#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
4257
4258
4259
/* WDT.STATUS bit masks and bit positions */
4260
#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
4261
#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
4262
4263
4264
/* MCU - MCU Control */
4265
/* MCU.MCUCR bit masks and bit positions */
4266
#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
4267
#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
4268
4269
4270
/* MCU.ANAINIT bit masks and bit positions */
4271
#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port A group mask. */
4272
#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port A group position. */
4273
#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port A bit 0 mask. */
4274
#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port A bit 0 position. */
4275
#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port A bit 1 mask. */
4276
#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port A bit 1 position. */
4277
4278
#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port B group mask. */
4279
#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port B group position. */
4280
#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port B bit 0 mask. */
4281
#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port B bit 0 position. */
4282
#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port B bit 1 mask. */
4283
#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port B bit 1 position. */
4284
4285
4286
/* MCU.EVSYSLOCK bit masks and bit positions */
4287
#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
4288
#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
4289
4290
#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
4291
#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
4292
4293
4294
/* MCU.AWEXLOCK bit masks and bit positions */
4295
#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
4296
#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
4297
4298
#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
4299
#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
4300
4301
4302
/* PMIC - Programmable Multi-level Interrupt Controller */
4303
/* PMIC.STATUS bit masks and bit positions */
4304
#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
4305
#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
4306
4307
#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
4308
#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
4309
4310
#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
4311
#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
4312
4313
#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
4314
#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
4315
4316
4317
/* PMIC.CTRL bit masks and bit positions */
4318
#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
4319
#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
4320
4321
#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
4322
#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
4323
4324
#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
4325
#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
4326
4327
#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
4328
#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
4329
4330
#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
4331
#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
4332
4333
4334
/* PORTCFG - Port Configuration */
4335
/* PORTCFG.VPCTRLA bit masks and bit positions */
4336
#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
4337
#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
4338
#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
4339
#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
4340
#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
4341
#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
4342
#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
4343
#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
4344
#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
4345
#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
4346
4347
#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
4348
#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
4349
#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
4350
#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
4351
#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
4352
#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
4353
#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
4354
#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
4355
#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
4356
#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
4357
4358
4359
/* PORTCFG.VPCTRLB bit masks and bit positions */
4360
#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
4361
#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
4362
#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
4363
#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
4364
#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
4365
#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
4366
#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
4367
#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
4368
#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
4369
#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
4370
4371
#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
4372
#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
4373
#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
4374
#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
4375
#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
4376
#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
4377
#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
4378
#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
4379
#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
4380
#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
4381
4382
4383
/* PORTCFG.CLKEVOUT bit masks and bit positions */
4384
#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
4385
#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
4386
#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
4387
#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
4388
#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
4389
#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
4390
4391
#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
4392
#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
4393
#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
4394
#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
4395
#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
4396
#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
4397
4398
#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
4399
#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
4400
#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
4401
#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
4402
#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
4403
#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
4404
4405
#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
4406
#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
4407
4408
#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
4409
#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
4410
4411
4412
/* AES - AES Module */
4413
/* AES.CTRL bit masks and bit positions */
4414
#define AES_START_bm 0x80 /* Start/Run bit mask. */
4415
#define AES_START_bp 7 /* Start/Run bit position. */
4416
4417
#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
4418
#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
4419
4420
#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
4421
#define AES_RESET_bp 5 /* AES Software Reset bit position. */
4422
4423
#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
4424
#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
4425
4426
#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
4427
#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
4428
4429
4430
/* AES.STATUS bit masks and bit positions */
4431
#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
4432
#define AES_ERROR_bp 7 /* AES Error bit position. */
4433
4434
#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
4435
#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
4436
4437
4438
/* AES.INTCTRL bit masks and bit positions */
4439
#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
4440
#define AES_INTLVL_gp 0 /* Interrupt level group position. */
4441
#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
4442
#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
4443
#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
4444
#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
4445
4446
4447
/* CRC - Cyclic Redundancy Checker */
4448
/* CRC.CTRL bit masks and bit positions */
4449
#define CRC_RESET_gm 0xC0 /* CRC Reset group mask. */
4450
#define CRC_RESET_gp 6 /* CRC Reset group position. */
4451
#define CRC_RESET0_bm (1<<6) /* CRC Reset bit 0 mask. */
4452
#define CRC_RESET0_bp 6 /* CRC Reset bit 0 position. */
4453
#define CRC_RESET1_bm (1<<7) /* CRC Reset bit 1 mask. */
4454
#define CRC_RESET1_bp 7 /* CRC Reset bit 1 position. */
4455
4456
#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
4457
#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
4458
4459
#define CRC_SOURCE_gm 0x0F /* CRC Input Source group mask. */
4460
#define CRC_SOURCE_gp 0 /* CRC Input Source group position. */
4461
#define CRC_SOURCE0_bm (1<<0) /* CRC Input Source bit 0 mask. */
4462
#define CRC_SOURCE0_bp 0 /* CRC Input Source bit 0 position. */
4463
#define CRC_SOURCE1_bm (1<<1) /* CRC Input Source bit 1 mask. */
4464
#define CRC_SOURCE1_bp 1 /* CRC Input Source bit 1 position. */
4465
#define CRC_SOURCE2_bm (1<<2) /* CRC Input Source bit 2 mask. */
4466
#define CRC_SOURCE2_bp 2 /* CRC Input Source bit 2 position. */
4467
#define CRC_SOURCE3_bm (1<<3) /* CRC Input Source bit 3 mask. */
4468
#define CRC_SOURCE3_bp 3 /* CRC Input Source bit 3 position. */
4469
4470
4471
/* CRC.STATUS bit masks and bit positions */
4472
#define CRC_ZERO_bm 0x02 /* Zero CRC detection bit mask. */
4473
#define CRC_ZERO_bp 1 /* Zero CRC detection bit position. */
4474
4475
#define CRC_BUSY_bm 0x01 /* Enable bit mask. */
4476
#define CRC_BUSY_bp 0 /* Enable bit position. */
4477
4478
4479
/* DMA - DMA Controller */
4480
/* DMA_CH.CTRLA bit masks and bit positions */
4481
#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
4482
#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
4483
4484
#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
4485
#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
4486
4487
#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
4488
#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
4489
4490
#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
4491
#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
4492
4493
#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
4494
#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
4495
4496
#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
4497
#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
4498
#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
4499
#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
4500
#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
4501
#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
4502
4503
4504
/* DMA_CH.CTRLB bit masks and bit positions */
4505
#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
4506
#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
4507
4508
#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
4509
#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
4510
4511
#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
4512
#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
4513
4514
#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
4515
#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
4516
4517
#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
4518
#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
4519
#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
4520
#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
4521
#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
4522
#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
4523
4524
#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
4525
#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
4526
#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
4527
#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
4528
#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
4529
#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
4530
4531
4532
/* DMA_CH.ADDRCTRL bit masks and bit positions */
4533
#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
4534
#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
4535
#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
4536
#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
4537
#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
4538
#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
4539
4540
#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
4541
#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
4542
#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
4543
#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
4544
#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
4545
#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
4546
4547
#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
4548
#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
4549
#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
4550
#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
4551
#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
4552
#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
4553
4554
#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
4555
#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
4556
#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
4557
#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
4558
#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
4559
#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
4560
4561
4562
/* DMA_CH.TRIGSRC bit masks and bit positions */
4563
#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
4564
#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
4565
#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
4566
#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
4567
#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
4568
#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
4569
#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
4570
#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
4571
#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
4572
#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
4573
#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
4574
#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
4575
#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
4576
#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
4577
#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
4578
#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
4579
#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
4580
#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
4581
4582
4583
/* DMA.CTRL bit masks and bit positions */
4584
#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
4585
#define DMA_ENABLE_bp 7 /* Enable bit position. */
4586
4587
#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
4588
#define DMA_RESET_bp 6 /* Software Reset bit position. */
4589
4590
#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
4591
#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
4592
#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
4593
#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
4594
#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
4595
#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
4596
4597
#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
4598
#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
4599
#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
4600
#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
4601
#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
4602
#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
4603
4604
4605
/* DMA.INTFLAGS bit masks and bit positions */
4606
#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
4607
#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
4608
4609
#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
4610
#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
4611
4612
#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
4613
#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
4614
4615
#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
4616
#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
4617
4618
#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
4619
#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
4620
4621
#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
4622
#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
4623
4624
#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
4625
#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
4626
4627
#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
4628
#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
4629
4630
4631
/* DMA.STATUS bit masks and bit positions */
4632
#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
4633
#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
4634
4635
#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
4636
#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
4637
4638
#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
4639
#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
4640
4641
#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
4642
#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
4643
4644
#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
4645
#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
4646
4647
#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
4648
#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
4649
4650
#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
4651
#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
4652
4653
#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
4654
#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
4655
4656
4657
/* EVSYS - Event System */
4658
/* EVSYS.CH0MUX bit masks and bit positions */
4659
#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
4660
#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
4661
#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
4662
#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
4663
#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
4664
#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
4665
#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
4666
#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
4667
#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
4668
#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
4669
#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
4670
#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
4671
#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
4672
#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
4673
#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
4674
#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
4675
#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
4676
#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
4677
4678
4679
/* EVSYS.CH1MUX bit masks and bit positions */
4680
/* EVSYS_CHMUX_gm Predefined. */
4681
/* EVSYS_CHMUX_gp Predefined. */
4682
/* EVSYS_CHMUX0_bm Predefined. */
4683
/* EVSYS_CHMUX0_bp Predefined. */
4684
/* EVSYS_CHMUX1_bm Predefined. */
4685
/* EVSYS_CHMUX1_bp Predefined. */
4686
/* EVSYS_CHMUX2_bm Predefined. */
4687
/* EVSYS_CHMUX2_bp Predefined. */
4688
/* EVSYS_CHMUX3_bm Predefined. */
4689
/* EVSYS_CHMUX3_bp Predefined. */
4690
/* EVSYS_CHMUX4_bm Predefined. */
4691
/* EVSYS_CHMUX4_bp Predefined. */
4692
/* EVSYS_CHMUX5_bm Predefined. */
4693
/* EVSYS_CHMUX5_bp Predefined. */
4694
/* EVSYS_CHMUX6_bm Predefined. */
4695
/* EVSYS_CHMUX6_bp Predefined. */
4696
/* EVSYS_CHMUX7_bm Predefined. */
4697
/* EVSYS_CHMUX7_bp Predefined. */
4698
4699
4700
/* EVSYS.CH2MUX bit masks and bit positions */
4701
/* EVSYS_CHMUX_gm Predefined. */
4702
/* EVSYS_CHMUX_gp Predefined. */
4703
/* EVSYS_CHMUX0_bm Predefined. */
4704
/* EVSYS_CHMUX0_bp Predefined. */
4705
/* EVSYS_CHMUX1_bm Predefined. */
4706
/* EVSYS_CHMUX1_bp Predefined. */
4707
/* EVSYS_CHMUX2_bm Predefined. */
4708
/* EVSYS_CHMUX2_bp Predefined. */
4709
/* EVSYS_CHMUX3_bm Predefined. */
4710
/* EVSYS_CHMUX3_bp Predefined. */
4711
/* EVSYS_CHMUX4_bm Predefined. */
4712
/* EVSYS_CHMUX4_bp Predefined. */
4713
/* EVSYS_CHMUX5_bm Predefined. */
4714
/* EVSYS_CHMUX5_bp Predefined. */
4715
/* EVSYS_CHMUX6_bm Predefined. */
4716
/* EVSYS_CHMUX6_bp Predefined. */
4717
/* EVSYS_CHMUX7_bm Predefined. */
4718
/* EVSYS_CHMUX7_bp Predefined. */
4719
4720
4721
/* EVSYS.CH3MUX bit masks and bit positions */
4722
/* EVSYS_CHMUX_gm Predefined. */
4723
/* EVSYS_CHMUX_gp Predefined. */
4724
/* EVSYS_CHMUX0_bm Predefined. */
4725
/* EVSYS_CHMUX0_bp Predefined. */
4726
/* EVSYS_CHMUX1_bm Predefined. */
4727
/* EVSYS_CHMUX1_bp Predefined. */
4728
/* EVSYS_CHMUX2_bm Predefined. */
4729
/* EVSYS_CHMUX2_bp Predefined. */
4730
/* EVSYS_CHMUX3_bm Predefined. */
4731
/* EVSYS_CHMUX3_bp Predefined. */
4732
/* EVSYS_CHMUX4_bm Predefined. */
4733
/* EVSYS_CHMUX4_bp Predefined. */
4734
/* EVSYS_CHMUX5_bm Predefined. */
4735
/* EVSYS_CHMUX5_bp Predefined. */
4736
/* EVSYS_CHMUX6_bm Predefined. */
4737
/* EVSYS_CHMUX6_bp Predefined. */
4738
/* EVSYS_CHMUX7_bm Predefined. */
4739
/* EVSYS_CHMUX7_bp Predefined. */
4740
4741
4742
/* EVSYS.CH4MUX bit masks and bit positions */
4743
/* EVSYS_CHMUX_gm Predefined. */
4744
/* EVSYS_CHMUX_gp Predefined. */
4745
/* EVSYS_CHMUX0_bm Predefined. */
4746
/* EVSYS_CHMUX0_bp Predefined. */
4747
/* EVSYS_CHMUX1_bm Predefined. */
4748
/* EVSYS_CHMUX1_bp Predefined. */
4749
/* EVSYS_CHMUX2_bm Predefined. */
4750
/* EVSYS_CHMUX2_bp Predefined. */
4751
/* EVSYS_CHMUX3_bm Predefined. */
4752
/* EVSYS_CHMUX3_bp Predefined. */
4753
/* EVSYS_CHMUX4_bm Predefined. */
4754
/* EVSYS_CHMUX4_bp Predefined. */
4755
/* EVSYS_CHMUX5_bm Predefined. */
4756
/* EVSYS_CHMUX5_bp Predefined. */
4757
/* EVSYS_CHMUX6_bm Predefined. */
4758
/* EVSYS_CHMUX6_bp Predefined. */
4759
/* EVSYS_CHMUX7_bm Predefined. */
4760
/* EVSYS_CHMUX7_bp Predefined. */
4761
4762
4763
/* EVSYS.CH5MUX bit masks and bit positions */
4764
/* EVSYS_CHMUX_gm Predefined. */
4765
/* EVSYS_CHMUX_gp Predefined. */
4766
/* EVSYS_CHMUX0_bm Predefined. */
4767
/* EVSYS_CHMUX0_bp Predefined. */
4768
/* EVSYS_CHMUX1_bm Predefined. */
4769
/* EVSYS_CHMUX1_bp Predefined. */
4770
/* EVSYS_CHMUX2_bm Predefined. */
4771
/* EVSYS_CHMUX2_bp Predefined. */
4772
/* EVSYS_CHMUX3_bm Predefined. */
4773
/* EVSYS_CHMUX3_bp Predefined. */
4774
/* EVSYS_CHMUX4_bm Predefined. */
4775
/* EVSYS_CHMUX4_bp Predefined. */
4776
/* EVSYS_CHMUX5_bm Predefined. */
4777
/* EVSYS_CHMUX5_bp Predefined. */
4778
/* EVSYS_CHMUX6_bm Predefined. */
4779
/* EVSYS_CHMUX6_bp Predefined. */
4780
/* EVSYS_CHMUX7_bm Predefined. */
4781
/* EVSYS_CHMUX7_bp Predefined. */
4782
4783
4784
/* EVSYS.CH6MUX bit masks and bit positions */
4785
/* EVSYS_CHMUX_gm Predefined. */
4786
/* EVSYS_CHMUX_gp Predefined. */
4787
/* EVSYS_CHMUX0_bm Predefined. */
4788
/* EVSYS_CHMUX0_bp Predefined. */
4789
/* EVSYS_CHMUX1_bm Predefined. */
4790
/* EVSYS_CHMUX1_bp Predefined. */
4791
/* EVSYS_CHMUX2_bm Predefined. */
4792
/* EVSYS_CHMUX2_bp Predefined. */
4793
/* EVSYS_CHMUX3_bm Predefined. */
4794
/* EVSYS_CHMUX3_bp Predefined. */
4795
/* EVSYS_CHMUX4_bm Predefined. */
4796
/* EVSYS_CHMUX4_bp Predefined. */
4797
/* EVSYS_CHMUX5_bm Predefined. */
4798
/* EVSYS_CHMUX5_bp Predefined. */
4799
/* EVSYS_CHMUX6_bm Predefined. */
4800
/* EVSYS_CHMUX6_bp Predefined. */
4801
/* EVSYS_CHMUX7_bm Predefined. */
4802
/* EVSYS_CHMUX7_bp Predefined. */
4803
4804
4805
/* EVSYS.CH7MUX bit masks and bit positions */
4806
/* EVSYS_CHMUX_gm Predefined. */
4807
/* EVSYS_CHMUX_gp Predefined. */
4808
/* EVSYS_CHMUX0_bm Predefined. */
4809
/* EVSYS_CHMUX0_bp Predefined. */
4810
/* EVSYS_CHMUX1_bm Predefined. */
4811
/* EVSYS_CHMUX1_bp Predefined. */
4812
/* EVSYS_CHMUX2_bm Predefined. */
4813
/* EVSYS_CHMUX2_bp Predefined. */
4814
/* EVSYS_CHMUX3_bm Predefined. */
4815
/* EVSYS_CHMUX3_bp Predefined. */
4816
/* EVSYS_CHMUX4_bm Predefined. */
4817
/* EVSYS_CHMUX4_bp Predefined. */
4818
/* EVSYS_CHMUX5_bm Predefined. */
4819
/* EVSYS_CHMUX5_bp Predefined. */
4820
/* EVSYS_CHMUX6_bm Predefined. */
4821
/* EVSYS_CHMUX6_bp Predefined. */
4822
/* EVSYS_CHMUX7_bm Predefined. */
4823
/* EVSYS_CHMUX7_bp Predefined. */
4824
4825
4826
/* EVSYS.CH0CTRL bit masks and bit positions */
4827
#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
4828
#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
4829
#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
4830
#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
4831
#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
4832
#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
4833
4834
#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
4835
#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
4836
4837
#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
4838
#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
4839
4840
#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
4841
#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
4842
#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
4843
#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
4844
#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
4845
#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
4846
#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
4847
#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
4848
4849
4850
/* EVSYS.CH1CTRL bit masks and bit positions */
4851
/* EVSYS_DIGFILT_gm Predefined. */
4852
/* EVSYS_DIGFILT_gp Predefined. */
4853
/* EVSYS_DIGFILT0_bm Predefined. */
4854
/* EVSYS_DIGFILT0_bp Predefined. */
4855
/* EVSYS_DIGFILT1_bm Predefined. */
4856
/* EVSYS_DIGFILT1_bp Predefined. */
4857
/* EVSYS_DIGFILT2_bm Predefined. */
4858
/* EVSYS_DIGFILT2_bp Predefined. */
4859
4860
4861
/* EVSYS.CH2CTRL bit masks and bit positions */
4862
/* EVSYS_QDIRM_gm Predefined. */
4863
/* EVSYS_QDIRM_gp Predefined. */
4864
/* EVSYS_QDIRM0_bm Predefined. */
4865
/* EVSYS_QDIRM0_bp Predefined. */
4866
/* EVSYS_QDIRM1_bm Predefined. */
4867
/* EVSYS_QDIRM1_bp Predefined. */
4868
4869
/* EVSYS_QDIEN_bm Predefined. */
4870
/* EVSYS_QDIEN_bp Predefined. */
4871
4872
/* EVSYS_QDEN_bm Predefined. */
4873
/* EVSYS_QDEN_bp Predefined. */
4874
4875
/* EVSYS_DIGFILT_gm Predefined. */
4876
/* EVSYS_DIGFILT_gp Predefined. */
4877
/* EVSYS_DIGFILT0_bm Predefined. */
4878
/* EVSYS_DIGFILT0_bp Predefined. */
4879
/* EVSYS_DIGFILT1_bm Predefined. */
4880
/* EVSYS_DIGFILT1_bp Predefined. */
4881
/* EVSYS_DIGFILT2_bm Predefined. */
4882
/* EVSYS_DIGFILT2_bp Predefined. */
4883
4884
4885
/* EVSYS.CH3CTRL bit masks and bit positions */
4886
/* EVSYS_DIGFILT_gm Predefined. */
4887
/* EVSYS_DIGFILT_gp Predefined. */
4888
/* EVSYS_DIGFILT0_bm Predefined. */
4889
/* EVSYS_DIGFILT0_bp Predefined. */
4890
/* EVSYS_DIGFILT1_bm Predefined. */
4891
/* EVSYS_DIGFILT1_bp Predefined. */
4892
/* EVSYS_DIGFILT2_bm Predefined. */
4893
/* EVSYS_DIGFILT2_bp Predefined. */
4894
4895
4896
/* EVSYS.CH4CTRL bit masks and bit positions */
4897
/* EVSYS_QDIRM_gm Predefined. */
4898
/* EVSYS_QDIRM_gp Predefined. */
4899
/* EVSYS_QDIRM0_bm Predefined. */
4900
/* EVSYS_QDIRM0_bp Predefined. */
4901
/* EVSYS_QDIRM1_bm Predefined. */
4902
/* EVSYS_QDIRM1_bp Predefined. */
4903
4904
/* EVSYS_QDIEN_bm Predefined. */
4905
/* EVSYS_QDIEN_bp Predefined. */
4906
4907
/* EVSYS_QDEN_bm Predefined. */
4908
/* EVSYS_QDEN_bp Predefined. */
4909
4910
/* EVSYS_DIGFILT_gm Predefined. */
4911
/* EVSYS_DIGFILT_gp Predefined. */
4912
/* EVSYS_DIGFILT0_bm Predefined. */
4913
/* EVSYS_DIGFILT0_bp Predefined. */
4914
/* EVSYS_DIGFILT1_bm Predefined. */
4915
/* EVSYS_DIGFILT1_bp Predefined. */
4916
/* EVSYS_DIGFILT2_bm Predefined. */
4917
/* EVSYS_DIGFILT2_bp Predefined. */
4918
4919
4920
/* EVSYS.CH5CTRL bit masks and bit positions */
4921
/* EVSYS_DIGFILT_gm Predefined. */
4922
/* EVSYS_DIGFILT_gp Predefined. */
4923
/* EVSYS_DIGFILT0_bm Predefined. */
4924
/* EVSYS_DIGFILT0_bp Predefined. */
4925
/* EVSYS_DIGFILT1_bm Predefined. */
4926
/* EVSYS_DIGFILT1_bp Predefined. */
4927
/* EVSYS_DIGFILT2_bm Predefined. */
4928
/* EVSYS_DIGFILT2_bp Predefined. */
4929
4930
4931
/* EVSYS.CH6CTRL bit masks and bit positions */
4932
/* EVSYS_DIGFILT_gm Predefined. */
4933
/* EVSYS_DIGFILT_gp Predefined. */
4934
/* EVSYS_DIGFILT0_bm Predefined. */
4935
/* EVSYS_DIGFILT0_bp Predefined. */
4936
/* EVSYS_DIGFILT1_bm Predefined. */
4937
/* EVSYS_DIGFILT1_bp Predefined. */
4938
/* EVSYS_DIGFILT2_bm Predefined. */
4939
/* EVSYS_DIGFILT2_bp Predefined. */
4940
4941
4942
/* EVSYS.CH7CTRL bit masks and bit positions */
4943
/* EVSYS_DIGFILT_gm Predefined. */
4944
/* EVSYS_DIGFILT_gp Predefined. */
4945
/* EVSYS_DIGFILT0_bm Predefined. */
4946
/* EVSYS_DIGFILT0_bp Predefined. */
4947
/* EVSYS_DIGFILT1_bm Predefined. */
4948
/* EVSYS_DIGFILT1_bp Predefined. */
4949
/* EVSYS_DIGFILT2_bm Predefined. */
4950
/* EVSYS_DIGFILT2_bp Predefined. */
4951
4952
4953
/* NVM - Non Volatile Memory Controller */
4954
/* NVM.CMD bit masks and bit positions */
4955
#define NVM_CMD_gm 0x7F /* Command group mask. */
4956
#define NVM_CMD_gp 0 /* Command group position. */
4957
#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
4958
#define NVM_CMD0_bp 0 /* Command bit 0 position. */
4959
#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
4960
#define NVM_CMD1_bp 1 /* Command bit 1 position. */
4961
#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
4962
#define NVM_CMD2_bp 2 /* Command bit 2 position. */
4963
#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
4964
#define NVM_CMD3_bp 3 /* Command bit 3 position. */
4965
#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
4966
#define NVM_CMD4_bp 4 /* Command bit 4 position. */
4967
#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
4968
#define NVM_CMD5_bp 5 /* Command bit 5 position. */
4969
#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
4970
#define NVM_CMD6_bp 6 /* Command bit 6 position. */
4971
4972
4973
/* NVM.CTRLA bit masks and bit positions */
4974
#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
4975
#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
4976
4977
4978
/* NVM.CTRLB bit masks and bit positions */
4979
#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
4980
#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
4981
4982
#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
4983
#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
4984
4985
#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
4986
#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
4987
4988
#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
4989
#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
4990
4991
4992
/* NVM.INTCTRL bit masks and bit positions */
4993
#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
4994
#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
4995
#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
4996
#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
4997
#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
4998
#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
4999
5000
#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
5001
#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
5002
#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
5003
#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
5004
#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
5005
#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
5006
5007
5008
/* NVM.STATUS bit masks and bit positions */
5009
#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
5010
#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
5011
5012
#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
5013
#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
5014
5015
#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
5016
#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
5017
5018
#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
5019
#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
5020
5021
5022
/* NVM.LOCKBITS bit masks and bit positions */
5023
#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
5024
#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
5025
#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
5026
#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
5027
#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
5028
#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
5029
5030
#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
5031
#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
5032
#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
5033
#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
5034
#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
5035
#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
5036
5037
#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
5038
#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
5039
#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
5040
#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
5041
#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
5042
#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
5043
5044
#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
5045
#define NVM_LB_gp 0 /* Lock Bits group position. */
5046
#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
5047
#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
5048
#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
5049
#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
5050
5051
5052
/* ADC - Analog/Digital Converter */
5053
/* ADC_CH.CTRL bit masks and bit positions */
5054
#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
5055
#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
5056
5057
#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
5058
#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
5059
#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
5060
#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
5061
#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
5062
#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
5063
#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
5064
#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
5065
5066
#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
5067
#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
5068
#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
5069
#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
5070
#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
5071
#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
5072
5073
5074
/* ADC_CH.MUXCTRL bit masks and bit positions */
5075
#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
5076
#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
5077
#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
5078
#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
5079
#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
5080
#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
5081
#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
5082
#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
5083
#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
5084
#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
5085
5086
#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
5087
#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
5088
#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
5089
#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
5090
#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
5091
#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
5092
#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
5093
#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
5094
#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
5095
#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
5096
5097
#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
5098
#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
5099
#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
5100
#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
5101
#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
5102
#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
5103
5104
5105
/* ADC_CH.INTCTRL bit masks and bit positions */
5106
#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
5107
#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
5108
#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
5109
#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
5110
#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
5111
#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
5112
5113
#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
5114
#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
5115
#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
5116
#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
5117
#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
5118
#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
5119
5120
5121
/* ADC_CH.INTFLAGS bit masks and bit positions */
5122
#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
5123
#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
5124
5125
5126
/* ADC.CTRLA bit masks and bit positions */
5127
#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
5128
#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
5129
#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
5130
#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
5131
#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
5132
#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
5133
5134
#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
5135
#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
5136
5137
#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
5138
#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
5139
5140
#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
5141
#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
5142
5143
#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
5144
#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
5145
5146
#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
5147
#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
5148
5149
#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
5150
#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
5151
5152
5153
/* ADC.CTRLB bit masks and bit positions */
5154
#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
5155
#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
5156
5157
#define ADC_CURRENT_gm 0x60 /* Current Limitation group mask. */
5158
#define ADC_CURRENT_gp 5 /* Current Limitation group position. */
5159
#define ADC_CURRENT0_bm (1<<5) /* Current Limitation bit 0 mask. */
5160
#define ADC_CURRENT0_bp 5 /* Current Limitation bit 0 position. */
5161
#define ADC_CURRENT1_bm (1<<6) /* Current Limitation bit 1 mask. */
5162
#define ADC_CURRENT1_bp 6 /* Current Limitation bit 1 position. */
5163
5164
#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
5165
#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
5166
5167
#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
5168
#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
5169
5170
#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
5171
#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
5172
#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
5173
#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
5174
#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
5175
#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
5176
5177
5178
/* ADC.REFCTRL bit masks and bit positions */
5179
#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
5180
#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
5181
#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
5182
#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
5183
#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
5184
#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
5185
#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
5186
#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
5187
5188
#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
5189
#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
5190
5191
#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
5192
#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
5193
5194
5195
/* ADC.EVCTRL bit masks and bit positions */
5196
#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
5197
#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
5198
#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
5199
#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
5200
#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
5201
#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
5202
5203
#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
5204
#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
5205
#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
5206
#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
5207
#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
5208
#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
5209
#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
5210
#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
5211
5212
#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
5213
#define ADC_EVACT_gp 0 /* Event Action Select group position. */
5214
#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
5215
#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
5216
#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
5217
#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
5218
#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
5219
#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
5220
5221
5222
/* ADC.PRESCALER bit masks and bit positions */
5223
#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
5224
#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
5225
#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
5226
#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
5227
#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
5228
#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
5229
#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
5230
#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
5231
5232
5233
/* ADC.INTFLAGS bit masks and bit positions */
5234
#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
5235
#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
5236
5237
#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
5238
#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
5239
5240
#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
5241
#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
5242
5243
#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
5244
#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
5245
5246
5247
/* DAC - Digital/Analog Converter */
5248
/* DAC.CTRLA bit masks and bit positions */
5249
#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
5250
#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
5251
5252
#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
5253
#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
5254
5255
#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
5256
#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
5257
5258
#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
5259
#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
5260
5261
#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
5262
#define DAC_ENABLE_bp 0 /* Enable bit position. */
5263
5264
5265
/* DAC.CTRLB bit masks and bit positions */
5266
#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
5267
#define DAC_CHSEL_gp 5 /* Channel Select group position. */
5268
#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
5269
#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
5270
#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
5271
#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
5272
5273
#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
5274
#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
5275
5276
#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
5277
#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
5278
5279
5280
/* DAC.CTRLC bit masks and bit positions */
5281
#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
5282
#define DAC_REFSEL_gp 3 /* Reference Select group position. */
5283
#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
5284
#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
5285
#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
5286
#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
5287
5288
#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
5289
#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
5290
5291
5292
/* DAC.EVCTRL bit masks and bit positions */
5293
#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
5294
#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
5295
5296
#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
5297
#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
5298
#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
5299
#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
5300
#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
5301
#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
5302
#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
5303
#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
5304
5305
5306
/* DAC.TIMCTRL bit masks and bit positions */
5307
#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
5308
#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
5309
#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
5310
#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
5311
#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
5312
#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
5313
#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
5314
#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
5315
5316
#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
5317
#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
5318
#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
5319
#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
5320
#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
5321
#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
5322
#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
5323
#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
5324
#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
5325
#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
5326
5327
5328
/* DAC.STATUS bit masks and bit positions */
5329
#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
5330
#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
5331
5332
#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
5333
#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
5334
5335
5336
/* DAC.CH0GAINCAL bit masks and bit positions */
5337
#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
5338
#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
5339
#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
5340
#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
5341
#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
5342
#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
5343
#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
5344
#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
5345
#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
5346
#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
5347
#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
5348
#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
5349
#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
5350
#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
5351
#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
5352
#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
5353
5354
5355
/* DAC.CH0OFFSETCAL bit masks and bit positions */
5356
#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
5357
#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
5358
#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
5359
#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
5360
#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
5361
#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
5362
#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
5363
#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
5364
#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
5365
#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
5366
#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
5367
#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
5368
#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
5369
#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
5370
#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
5371
#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
5372
5373
5374
/* DAC.CH1GAINCAL bit masks and bit positions */
5375
#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
5376
#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
5377
#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
5378
#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
5379
#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
5380
#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
5381
#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
5382
#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
5383
#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
5384
#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
5385
#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
5386
#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
5387
#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
5388
#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
5389
#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
5390
#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
5391
5392
5393
/* DAC.CH1OFFSETCAL bit masks and bit positions */
5394
#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
5395
#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
5396
#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
5397
#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
5398
#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
5399
#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
5400
#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
5401
#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
5402
#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
5403
#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
5404
#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
5405
#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
5406
#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
5407
#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
5408
#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
5409
#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
5410
5411
5412
/* AC - Analog Comparator */
5413
/* AC.AC0CTRL bit masks and bit positions */
5414
#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
5415
#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
5416
#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
5417
#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
5418
#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
5419
#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
5420
5421
#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
5422
#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
5423
#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
5424
#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
5425
#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
5426
#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
5427
5428
#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
5429
#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
5430
5431
#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
5432
#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
5433
#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
5434
#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
5435
#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
5436
#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
5437
5438
#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
5439
#define AC_ENABLE_bp 0 /* Enable bit position. */
5440
5441
5442
/* AC.AC1CTRL bit masks and bit positions */
5443
/* AC_INTMODE_gm Predefined. */
5444
/* AC_INTMODE_gp Predefined. */
5445
/* AC_INTMODE0_bm Predefined. */
5446
/* AC_INTMODE0_bp Predefined. */
5447
/* AC_INTMODE1_bm Predefined. */
5448
/* AC_INTMODE1_bp Predefined. */
5449
5450
/* AC_INTLVL_gm Predefined. */
5451
/* AC_INTLVL_gp Predefined. */
5452
/* AC_INTLVL0_bm Predefined. */
5453
/* AC_INTLVL0_bp Predefined. */
5454
/* AC_INTLVL1_bm Predefined. */
5455
/* AC_INTLVL1_bp Predefined. */
5456
5457
/* AC_HSMODE_bm Predefined. */
5458
/* AC_HSMODE_bp Predefined. */
5459
5460
/* AC_HYSMODE_gm Predefined. */
5461
/* AC_HYSMODE_gp Predefined. */
5462
/* AC_HYSMODE0_bm Predefined. */
5463
/* AC_HYSMODE0_bp Predefined. */
5464
/* AC_HYSMODE1_bm Predefined. */
5465
/* AC_HYSMODE1_bp Predefined. */
5466
5467
/* AC_ENABLE_bm Predefined. */
5468
/* AC_ENABLE_bp Predefined. */
5469
5470
5471
/* AC.AC0MUXCTRL bit masks and bit positions */
5472
#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
5473
#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
5474
#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
5475
#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
5476
#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
5477
#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
5478
#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
5479
#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
5480
5481
#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
5482
#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
5483
#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
5484
#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
5485
#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
5486
#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
5487
#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
5488
#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
5489
5490
5491
/* AC.AC1MUXCTRL bit masks and bit positions */
5492
/* AC_MUXPOS_gm Predefined. */
5493
/* AC_MUXPOS_gp Predefined. */
5494
/* AC_MUXPOS0_bm Predefined. */
5495
/* AC_MUXPOS0_bp Predefined. */
5496
/* AC_MUXPOS1_bm Predefined. */
5497
/* AC_MUXPOS1_bp Predefined. */
5498
/* AC_MUXPOS2_bm Predefined. */
5499
/* AC_MUXPOS2_bp Predefined. */
5500
5501
/* AC_MUXNEG_gm Predefined. */
5502
/* AC_MUXNEG_gp Predefined. */
5503
/* AC_MUXNEG0_bm Predefined. */
5504
/* AC_MUXNEG0_bp Predefined. */
5505
/* AC_MUXNEG1_bm Predefined. */
5506
/* AC_MUXNEG1_bp Predefined. */
5507
/* AC_MUXNEG2_bm Predefined. */
5508
/* AC_MUXNEG2_bp Predefined. */
5509
5510
5511
/* AC.CTRLA bit masks and bit positions */
5512
#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
5513
#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
5514
5515
5516
/* AC.CTRLB bit masks and bit positions */
5517
#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
5518
#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
5519
#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
5520
#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
5521
#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
5522
#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
5523
#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
5524
#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
5525
#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
5526
#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
5527
#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
5528
#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
5529
#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
5530
#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
5531
5532
5533
/* AC.WINCTRL bit masks and bit positions */
5534
#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
5535
#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
5536
5537
#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
5538
#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
5539
#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
5540
#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
5541
#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
5542
#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
5543
5544
#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
5545
#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
5546
#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
5547
#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
5548
#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
5549
#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
5550
5551
5552
/* AC.STATUS bit masks and bit positions */
5553
#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
5554
#define AC_WSTATE_gp 6 /* Window Mode State group position. */
5555
#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
5556
#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
5557
#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
5558
#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
5559
5560
#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
5561
#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
5562
5563
#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
5564
#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
5565
5566
#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
5567
#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
5568
5569
#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
5570
#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
5571
5572
#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
5573
#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
5574
5575
5576
/* RTC - Real-Time Clounter */
5577
/* RTC.CTRL bit masks and bit positions */
5578
#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
5579
#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
5580
#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
5581
#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
5582
#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
5583
#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
5584
#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
5585
#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
5586
5587
5588
/* RTC.STATUS bit masks and bit positions */
5589
#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
5590
#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
5591
5592
5593
/* RTC.INTCTRL bit masks and bit positions */
5594
#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
5595
#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
5596
#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
5597
#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
5598
#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
5599
#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
5600
5601
#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
5602
#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
5603
#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
5604
#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
5605
#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
5606
#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
5607
5608
5609
/* RTC.INTFLAGS bit masks and bit positions */
5610
#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
5611
#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
5612
5613
#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
5614
#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
5615
5616
5617
/* EBI - External Bus Interface */
5618
/* EBI_CS.CTRLA bit masks and bit positions */
5619
#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */
5620
#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */
5621
#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */
5622
#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */
5623
#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */
5624
#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */
5625
#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */
5626
#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */
5627
#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */
5628
#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */
5629
#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */
5630
#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */
5631
5632
#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
5633
#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
5634
#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */
5635
#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
5636
#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
5637
#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
5638
5639
5640
/* EBI_CS.CTRLB bit masks and bit positions */
5641
#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
5642
#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
5643
#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */
5644
#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
5645
#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */
5646
#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
5647
#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */
5648
#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */
5649
5650
#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
5651
#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */
5652
5653
#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
5654
#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */
5655
5656
#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
5657
#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
5658
#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */
5659
#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
5660
#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
5661
#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
5662
5663
5664
/* EBI.CTRL bit masks and bit positions */
5665
#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
5666
#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
5667
#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */
5668
#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
5669
#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */
5670
#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */
5671
5672
#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
5673
#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
5674
#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */
5675
#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
5676
#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */
5677
#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */
5678
5679
#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
5680
#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
5681
#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */
5682
#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
5683
#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */
5684
#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */
5685
5686
#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
5687
#define EBI_IFMODE_gp 0 /* Interface Mode group position. */
5688
#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */
5689
#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
5690
#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
5691
#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
5692
5693
5694
/* EBI.SDRAMCTRLA bit masks and bit positions */
5695
#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
5696
#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
5697
5698
#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
5699
#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */
5700
5701
#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
5702
#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
5703
#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */
5704
#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
5705
#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
5706
#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
5707
5708
5709
/* EBI.SDRAMCTRLB bit masks and bit positions */
5710
#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
5711
#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
5712
#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */
5713
#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
5714
#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */
5715
#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */
5716
5717
#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
5718
#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
5719
#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */
5720
#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
5721
#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */
5722
#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
5723
#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */
5724
#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */
5725
5726
#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
5727
#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
5728
#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
5729
#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
5730
#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
5731
#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
5732
#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
5733
#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
5734
5735
5736
/* EBI.SDRAMCTRLC bit masks and bit positions */
5737
#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
5738
#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
5739
#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */
5740
#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
5741
#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */
5742
#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */
5743
5744
#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
5745
#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
5746
#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
5747
#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
5748
#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
5749
#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
5750
#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
5751
#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
5752
5753
#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
5754
#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
5755
#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */
5756
#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
5757
#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */
5758
#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
5759
#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
5760
#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
5761
5762
5763
/* TWI - Two-Wire Interface */
5764
/* TWI_MASTER.CTRLA bit masks and bit positions */
5765
#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
5766
#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
5767
#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
5768
#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
5769
#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
5770
#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
5771
5772
#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
5773
#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
5774
5775
#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
5776
#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
5777
5778
#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
5779
#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
5780
5781
5782
/* TWI_MASTER.CTRLB bit masks and bit positions */
5783
#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
5784
#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
5785
#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
5786
#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
5787
#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
5788
#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
5789
5790
#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
5791
#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
5792
5793
#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
5794
#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
5795
5796
5797
/* TWI_MASTER.CTRLC bit masks and bit positions */
5798
#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
5799
#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
5800
5801
#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
5802
#define TWI_MASTER_CMD_gp 0 /* Command group position. */
5803
#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
5804
#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
5805
#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
5806
#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
5807
5808
5809
/* TWI_MASTER.STATUS bit masks and bit positions */
5810
#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
5811
#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
5812
5813
#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
5814
#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
5815
5816
#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
5817
#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
5818
5819
#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
5820
#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
5821
5822
#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
5823
#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
5824
5825
#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
5826
#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
5827
5828
#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
5829
#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
5830
#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
5831
#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
5832
#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
5833
#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
5834
5835
5836
/* TWI_SLAVE.CTRLA bit masks and bit positions */
5837
#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
5838
#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
5839
#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
5840
#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
5841
#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
5842
#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
5843
5844
#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
5845
#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
5846
5847
#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
5848
#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
5849
5850
#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
5851
#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
5852
5853
#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
5854
#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
5855
5856
#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
5857
#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
5858
5859
#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
5860
#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
5861
5862
5863
/* TWI_SLAVE.CTRLB bit masks and bit positions */
5864
#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
5865
#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
5866
5867
#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
5868
#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
5869
#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
5870
#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
5871
#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
5872
#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
5873
5874
5875
/* TWI_SLAVE.STATUS bit masks and bit positions */
5876
#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
5877
#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
5878
5879
#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
5880
#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
5881
5882
#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
5883
#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
5884
5885
#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
5886
#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
5887
5888
#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
5889
#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
5890
5891
#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
5892
#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
5893
5894
#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
5895
#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
5896
5897
#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
5898
#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
5899
5900
5901
/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
5902
#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
5903
#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
5904
#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
5905
#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
5906
#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
5907
#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
5908
#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
5909
#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
5910
#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
5911
#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
5912
#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
5913
#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
5914
#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
5915
#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
5916
#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
5917
#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
5918
5919
#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
5920
#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
5921
5922
5923
/* TWI.CTRL bit masks and bit positions */
5924
#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
5925
#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
5926
5927
#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
5928
#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
5929
5930
5931
/* USB - USB Module */
5932
/* USB_EP.STATUS bit masks and bit positions */
5933
#define USB_EP_STALL_bm 0x80 /* Endpoint Stall Flag bit mask. */
5934
#define USB_EP_STALL_bp 7 /* Endpoint Stall Flag bit position. */
5935
5936
#define USB_EP_CRC_bm 0x80 /* CRC Error Flag for Isochronous Out Endpoints bit mask. */
5937
#define USB_EP_CRC_bp 7 /* CRC Error Flag for Isochronous Out Endpoints bit position. */
5938
5939
#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint Flag for Input Endpoints bit mask. */
5940
#define USB_EP_UNF_bp 6 /* Underflow Enpoint Flag for Input Endpoints bit position. */
5941
5942
#define USB_EP_OVF_bm 0x40 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit mask. */
5943
#define USB_EP_OVF_bp 6 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit position. */
5944
5945
#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete Flag bit mask. */
5946
#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete Flag bit position. */
5947
5948
#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
5949
#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
5950
5951
#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
5952
#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
5953
5954
#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
5955
#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
5956
5957
#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
5958
#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
5959
5960
#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
5961
#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
5962
5963
5964
/* USB_EP.CTRL bit masks and bit positions */
5965
#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
5966
#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
5967
#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
5968
#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
5969
#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
5970
#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
5971
5972
#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
5973
#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
5974
5975
#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
5976
#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
5977
5978
#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
5979
#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
5980
5981
/* USB_EP_STALL_bm Predefined. */
5982
/* USB_EP_STALL_bp Predefined. */
5983
5984
#define USB_EP_SIZE_gm 0x07 /* Data Buffer Size group mask. */
5985
#define USB_EP_SIZE_gp 0 /* Data Buffer Size group position. */
5986
#define USB_EP_SIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
5987
#define USB_EP_SIZE0_bp 0 /* Data Buffer Size bit 0 position. */
5988
#define USB_EP_SIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
5989
#define USB_EP_SIZE1_bp 1 /* Data Buffer Size bit 1 position. */
5990
#define USB_EP_SIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
5991
#define USB_EP_SIZE2_bp 2 /* Data Buffer Size bit 2 position. */
5992
5993
5994
/* USB_EP.CNTH bit masks and bit positions */
5995
#define USB_EP_ZLP_bm 0x80 /* Zero Length Packet bit mask. */
5996
#define USB_EP_ZLP_bp 7 /* Zero Length Packet bit position. */
5997
5998
#define USB_EP_CNT_gm 0x03 /* Endpoint Byte Counter group mask. */
5999
#define USB_EP_CNT_gp 0 /* Endpoint Byte Counter group position. */
6000
#define USB_EP_CNT0_bm (1<<0) /* Endpoint Byte Counter bit 0 mask. */
6001
#define USB_EP_CNT0_bp 0 /* Endpoint Byte Counter bit 0 position. */
6002
#define USB_EP_CNT1_bm (1<<1) /* Endpoint Byte Counter bit 1 mask. */
6003
#define USB_EP_CNT1_bp 1 /* Endpoint Byte Counter bit 1 position. */
6004
6005
6006
/* USB.CTRLA bit masks and bit positions */
6007
#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
6008
#define USB_ENABLE_bp 7 /* USB Enable bit position. */
6009
6010
#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
6011
#define USB_SPEED_bp 6 /* Speed Select bit position. */
6012
6013
#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
6014
#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
6015
6016
#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
6017
#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
6018
6019
#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
6020
#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
6021
#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
6022
#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
6023
#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
6024
#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
6025
#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
6026
#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
6027
#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
6028
#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
6029
6030
6031
/* USB.CTRLB bit masks and bit positions */
6032
#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
6033
#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
6034
6035
#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
6036
#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
6037
6038
#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
6039
#define USB_GNACK_bp 1 /* Global NACK bit position. */
6040
6041
#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
6042
#define USB_ATTACH_bp 0 /* Attach bit position. */
6043
6044
6045
/* USB.STATUS bit masks and bit positions */
6046
#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
6047
#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
6048
6049
#define USB_RESUME_bm 0x04 /* Resume bit mask. */
6050
#define USB_RESUME_bp 2 /* Resume bit position. */
6051
6052
#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
6053
#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
6054
6055
#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
6056
#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
6057
6058
6059
/* USB.ADDR bit masks and bit positions */
6060
#define USB_ADDR_gm 0x7F /* Device Address group mask. */
6061
#define USB_ADDR_gp 0 /* Device Address group position. */
6062
#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
6063
#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
6064
#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
6065
#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
6066
#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
6067
#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
6068
#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
6069
#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
6070
#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
6071
#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
6072
#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
6073
#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
6074
#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
6075
#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
6076
6077
6078
/* USB.FIFOWP bit masks and bit positions */
6079
#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
6080
#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
6081
#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
6082
#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
6083
#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
6084
#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
6085
#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
6086
#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
6087
#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
6088
#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
6089
#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
6090
#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
6091
6092
6093
/* USB.FIFORP bit masks and bit positions */
6094
#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
6095
#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
6096
#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
6097
#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
6098
#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
6099
#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
6100
#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
6101
#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
6102
#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
6103
#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
6104
#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
6105
#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
6106
6107
6108
/* USB.INTCTRLA bit masks and bit positions */
6109
#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
6110
#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
6111
6112
#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
6113
#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
6114
6115
#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
6116
#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
6117
6118
#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
6119
#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
6120
6121
#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
6122
#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
6123
#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
6124
#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
6125
#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
6126
#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
6127
6128
6129
/* USB.INTCTRLB bit masks and bit positions */
6130
#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
6131
#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
6132
6133
#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
6134
#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
6135
6136
6137
/* USB.INTFLAGSACLR bit masks and bit positions */
6138
#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
6139
#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
6140
6141
#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
6142
#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
6143
6144
#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
6145
#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
6146
6147
#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
6148
#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
6149
6150
#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
6151
#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
6152
6153
#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
6154
#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
6155
6156
#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
6157
#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
6158
6159
#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
6160
#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
6161
6162
6163
/* USB.INTFLAGSASET bit masks and bit positions */
6164
/* USB_SOFIF_bm Predefined. */
6165
/* USB_SOFIF_bp Predefined. */
6166
6167
/* USB_SUSPENDIF_bm Predefined. */
6168
/* USB_SUSPENDIF_bp Predefined. */
6169
6170
/* USB_RESUMEIF_bm Predefined. */
6171
/* USB_RESUMEIF_bp Predefined. */
6172
6173
/* USB_RSTIF_bm Predefined. */
6174
/* USB_RSTIF_bp Predefined. */
6175
6176
/* USB_CRCIF_bm Predefined. */
6177
/* USB_CRCIF_bp Predefined. */
6178
6179
/* USB_UNFIF_bm Predefined. */
6180
/* USB_UNFIF_bp Predefined. */
6181
6182
/* USB_OVFIF_bm Predefined. */
6183
/* USB_OVFIF_bp Predefined. */
6184
6185
/* USB_STALLIF_bm Predefined. */
6186
/* USB_STALLIF_bp Predefined. */
6187
6188
6189
/* USB.INTFLAGSBCLR bit masks and bit positions */
6190
#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
6191
#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
6192
6193
#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
6194
#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
6195
6196
6197
/* USB.INTFLAGSBSET bit masks and bit positions */
6198
/* USB_TRNIF_bm Predefined. */
6199
/* USB_TRNIF_bp Predefined. */
6200
6201
/* USB_SETUPIF_bm Predefined. */
6202
/* USB_SETUPIF_bp Predefined. */
6203
6204
6205
/* PORT - I/O Port Configuration */
6206
/* PORT.INTCTRL bit masks and bit positions */
6207
#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
6208
#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
6209
#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
6210
#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
6211
#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
6212
#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
6213
6214
#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
6215
#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
6216
#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
6217
#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
6218
#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
6219
#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
6220
6221
6222
/* PORT.INTFLAGS bit masks and bit positions */
6223
#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
6224
#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
6225
6226
#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
6227
#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
6228
6229
6230
/* PORT.PIN0CTRL bit masks and bit positions */
6231
#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
6232
#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
6233
6234
#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
6235
#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
6236
6237
#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
6238
#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
6239
#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
6240
#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
6241
#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
6242
#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
6243
#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
6244
#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
6245
6246
#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
6247
#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
6248
#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
6249
#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
6250
#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
6251
#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
6252
#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
6253
#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
6254
6255
6256
/* PORT.PIN1CTRL bit masks and bit positions */
6257
/* PORT_SRLEN_bm Predefined. */
6258
/* PORT_SRLEN_bp Predefined. */
6259
6260
/* PORT_INVEN_bm Predefined. */
6261
/* PORT_INVEN_bp Predefined. */
6262
6263
/* PORT_OPC_gm Predefined. */
6264
/* PORT_OPC_gp Predefined. */
6265
/* PORT_OPC0_bm Predefined. */
6266
/* PORT_OPC0_bp Predefined. */
6267
/* PORT_OPC1_bm Predefined. */
6268
/* PORT_OPC1_bp Predefined. */
6269
/* PORT_OPC2_bm Predefined. */
6270
/* PORT_OPC2_bp Predefined. */
6271
6272
/* PORT_ISC_gm Predefined. */
6273
/* PORT_ISC_gp Predefined. */
6274
/* PORT_ISC0_bm Predefined. */
6275
/* PORT_ISC0_bp Predefined. */
6276
/* PORT_ISC1_bm Predefined. */
6277
/* PORT_ISC1_bp Predefined. */
6278
/* PORT_ISC2_bm Predefined. */
6279
/* PORT_ISC2_bp Predefined. */
6280
6281
6282
/* PORT.PIN2CTRL bit masks and bit positions */
6283
/* PORT_SRLEN_bm Predefined. */
6284
/* PORT_SRLEN_bp Predefined. */
6285
6286
/* PORT_INVEN_bm Predefined. */
6287
/* PORT_INVEN_bp Predefined. */
6288
6289
/* PORT_OPC_gm Predefined. */
6290
/* PORT_OPC_gp Predefined. */
6291
/* PORT_OPC0_bm Predefined. */
6292
/* PORT_OPC0_bp Predefined. */
6293
/* PORT_OPC1_bm Predefined. */
6294
/* PORT_OPC1_bp Predefined. */
6295
/* PORT_OPC2_bm Predefined. */
6296
/* PORT_OPC2_bp Predefined. */
6297
6298
/* PORT_ISC_gm Predefined. */
6299
/* PORT_ISC_gp Predefined. */
6300
/* PORT_ISC0_bm Predefined. */
6301
/* PORT_ISC0_bp Predefined. */
6302
/* PORT_ISC1_bm Predefined. */
6303
/* PORT_ISC1_bp Predefined. */
6304
/* PORT_ISC2_bm Predefined. */
6305
/* PORT_ISC2_bp Predefined. */
6306
6307
6308
/* PORT.PIN3CTRL bit masks and bit positions */
6309
/* PORT_SRLEN_bm Predefined. */
6310
/* PORT_SRLEN_bp Predefined. */
6311
6312
/* PORT_INVEN_bm Predefined. */
6313
/* PORT_INVEN_bp Predefined. */
6314
6315
/* PORT_OPC_gm Predefined. */
6316
/* PORT_OPC_gp Predefined. */
6317
/* PORT_OPC0_bm Predefined. */
6318
/* PORT_OPC0_bp Predefined. */
6319
/* PORT_OPC1_bm Predefined. */
6320
/* PORT_OPC1_bp Predefined. */
6321
/* PORT_OPC2_bm Predefined. */
6322
/* PORT_OPC2_bp Predefined. */
6323
6324
/* PORT_ISC_gm Predefined. */
6325
/* PORT_ISC_gp Predefined. */
6326
/* PORT_ISC0_bm Predefined. */
6327
/* PORT_ISC0_bp Predefined. */
6328
/* PORT_ISC1_bm Predefined. */
6329
/* PORT_ISC1_bp Predefined. */
6330
/* PORT_ISC2_bm Predefined. */
6331
/* PORT_ISC2_bp Predefined. */
6332
6333
6334
/* PORT.PIN4CTRL bit masks and bit positions */
6335
/* PORT_SRLEN_bm Predefined. */
6336
/* PORT_SRLEN_bp Predefined. */
6337
6338
/* PORT_INVEN_bm Predefined. */
6339
/* PORT_INVEN_bp Predefined. */
6340
6341
/* PORT_OPC_gm Predefined. */
6342
/* PORT_OPC_gp Predefined. */
6343
/* PORT_OPC0_bm Predefined. */
6344
/* PORT_OPC0_bp Predefined. */
6345
/* PORT_OPC1_bm Predefined. */
6346
/* PORT_OPC1_bp Predefined. */
6347
/* PORT_OPC2_bm Predefined. */
6348
/* PORT_OPC2_bp Predefined. */
6349
6350
/* PORT_ISC_gm Predefined. */
6351
/* PORT_ISC_gp Predefined. */
6352
/* PORT_ISC0_bm Predefined. */
6353
/* PORT_ISC0_bp Predefined. */
6354
/* PORT_ISC1_bm Predefined. */
6355
/* PORT_ISC1_bp Predefined. */
6356
/* PORT_ISC2_bm Predefined. */
6357
/* PORT_ISC2_bp Predefined. */
6358
6359
6360
/* PORT.PIN5CTRL bit masks and bit positions */
6361
/* PORT_SRLEN_bm Predefined. */
6362
/* PORT_SRLEN_bp Predefined. */
6363
6364
/* PORT_INVEN_bm Predefined. */
6365
/* PORT_INVEN_bp Predefined. */
6366
6367
/* PORT_OPC_gm Predefined. */
6368
/* PORT_OPC_gp Predefined. */
6369
/* PORT_OPC0_bm Predefined. */
6370
/* PORT_OPC0_bp Predefined. */
6371
/* PORT_OPC1_bm Predefined. */
6372
/* PORT_OPC1_bp Predefined. */
6373
/* PORT_OPC2_bm Predefined. */
6374
/* PORT_OPC2_bp Predefined. */
6375
6376
/* PORT_ISC_gm Predefined. */
6377
/* PORT_ISC_gp Predefined. */
6378
/* PORT_ISC0_bm Predefined. */
6379
/* PORT_ISC0_bp Predefined. */
6380
/* PORT_ISC1_bm Predefined. */
6381
/* PORT_ISC1_bp Predefined. */
6382
/* PORT_ISC2_bm Predefined. */
6383
/* PORT_ISC2_bp Predefined. */
6384
6385
6386
/* PORT.PIN6CTRL bit masks and bit positions */
6387
/* PORT_SRLEN_bm Predefined. */
6388
/* PORT_SRLEN_bp Predefined. */
6389
6390
/* PORT_INVEN_bm Predefined. */
6391
/* PORT_INVEN_bp Predefined. */
6392
6393
/* PORT_OPC_gm Predefined. */
6394
/* PORT_OPC_gp Predefined. */
6395
/* PORT_OPC0_bm Predefined. */
6396
/* PORT_OPC0_bp Predefined. */
6397
/* PORT_OPC1_bm Predefined. */
6398
/* PORT_OPC1_bp Predefined. */
6399
/* PORT_OPC2_bm Predefined. */
6400
/* PORT_OPC2_bp Predefined. */
6401
6402
/* PORT_ISC_gm Predefined. */
6403
/* PORT_ISC_gp Predefined. */
6404
/* PORT_ISC0_bm Predefined. */
6405
/* PORT_ISC0_bp Predefined. */
6406
/* PORT_ISC1_bm Predefined. */
6407
/* PORT_ISC1_bp Predefined. */
6408
/* PORT_ISC2_bm Predefined. */
6409
/* PORT_ISC2_bp Predefined. */
6410
6411
6412
/* PORT.PIN7CTRL bit masks and bit positions */
6413
/* PORT_SRLEN_bm Predefined. */
6414
/* PORT_SRLEN_bp Predefined. */
6415
6416
/* PORT_INVEN_bm Predefined. */
6417
/* PORT_INVEN_bp Predefined. */
6418
6419
/* PORT_OPC_gm Predefined. */
6420
/* PORT_OPC_gp Predefined. */
6421
/* PORT_OPC0_bm Predefined. */
6422
/* PORT_OPC0_bp Predefined. */
6423
/* PORT_OPC1_bm Predefined. */
6424
/* PORT_OPC1_bp Predefined. */
6425
/* PORT_OPC2_bm Predefined. */
6426
/* PORT_OPC2_bp Predefined. */
6427
6428
/* PORT_ISC_gm Predefined. */
6429
/* PORT_ISC_gp Predefined. */
6430
/* PORT_ISC0_bm Predefined. */
6431
/* PORT_ISC0_bp Predefined. */
6432
/* PORT_ISC1_bm Predefined. */
6433
/* PORT_ISC1_bp Predefined. */
6434
/* PORT_ISC2_bm Predefined. */
6435
/* PORT_ISC2_bp Predefined. */
6436
6437
6438
/* TC - 16-bit Timer/Counter With PWM */
6439
/* TC0.CTRLA bit masks and bit positions */
6440
#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
6441
#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
6442
#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
6443
#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
6444
#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
6445
#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
6446
#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
6447
#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
6448
#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
6449
#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
6450
6451
6452
/* TC0.CTRLB bit masks and bit positions */
6453
#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
6454
#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
6455
6456
#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
6457
#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
6458
6459
#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
6460
#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
6461
6462
#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
6463
#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
6464
6465
#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
6466
#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
6467
#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
6468
#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
6469
#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
6470
#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
6471
#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
6472
#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
6473
6474
6475
/* TC0.CTRLC bit masks and bit positions */
6476
#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
6477
#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
6478
6479
#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
6480
#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
6481
6482
#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
6483
#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
6484
6485
#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
6486
#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
6487
6488
6489
/* TC0.CTRLD bit masks and bit positions */
6490
#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
6491
#define TC0_EVACT_gp 5 /* Event Action group position. */
6492
#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
6493
#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
6494
#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
6495
#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
6496
#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
6497
#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
6498
6499
#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
6500
#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
6501
6502
#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
6503
#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
6504
#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
6505
#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
6506
#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
6507
#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
6508
#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
6509
#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
6510
#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
6511
#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
6512
6513
6514
/* TC0.CTRLE bit masks and bit positions */
6515
#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
6516
#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
6517
6518
6519
/* TC0.INTCTRLA bit masks and bit positions */
6520
#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
6521
#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
6522
#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
6523
#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
6524
#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
6525
#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
6526
6527
#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
6528
#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
6529
#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
6530
#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
6531
#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
6532
#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
6533
6534
6535
/* TC0.INTCTRLB bit masks and bit positions */
6536
#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
6537
#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
6538
#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
6539
#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
6540
#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
6541
#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
6542
6543
#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
6544
#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
6545
#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
6546
#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
6547
#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
6548
#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
6549
6550
#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
6551
#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
6552
#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
6553
#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
6554
#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
6555
#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
6556
6557
#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
6558
#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
6559
#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
6560
#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
6561
#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
6562
#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
6563
6564
6565
/* TC0.CTRLFCLR bit masks and bit positions */
6566
#define TC0_CMD_gm 0x0C /* Command group mask. */
6567
#define TC0_CMD_gp 2 /* Command group position. */
6568
#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
6569
#define TC0_CMD0_bp 2 /* Command bit 0 position. */
6570
#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
6571
#define TC0_CMD1_bp 3 /* Command bit 1 position. */
6572
6573
#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
6574
#define TC0_LUPD_bp 1 /* Lock Update bit position. */
6575
6576
#define TC0_DIR_bm 0x01 /* Direction bit mask. */
6577
#define TC0_DIR_bp 0 /* Direction bit position. */
6578
6579
6580
/* TC0.CTRLFSET bit masks and bit positions */
6581
/* TC0_CMD_gm Predefined. */
6582
/* TC0_CMD_gp Predefined. */
6583
/* TC0_CMD0_bm Predefined. */
6584
/* TC0_CMD0_bp Predefined. */
6585
/* TC0_CMD1_bm Predefined. */
6586
/* TC0_CMD1_bp Predefined. */
6587
6588
/* TC0_LUPD_bm Predefined. */
6589
/* TC0_LUPD_bp Predefined. */
6590
6591
/* TC0_DIR_bm Predefined. */
6592
/* TC0_DIR_bp Predefined. */
6593
6594
6595
/* TC0.CTRLGCLR bit masks and bit positions */
6596
#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
6597
#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
6598
6599
#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
6600
#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
6601
6602
#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
6603
#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
6604
6605
#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
6606
#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
6607
6608
#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
6609
#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
6610
6611
6612
/* TC0.CTRLGSET bit masks and bit positions */
6613
/* TC0_CCDBV_bm Predefined. */
6614
/* TC0_CCDBV_bp Predefined. */
6615
6616
/* TC0_CCCBV_bm Predefined. */
6617
/* TC0_CCCBV_bp Predefined. */
6618
6619
/* TC0_CCBBV_bm Predefined. */
6620
/* TC0_CCBBV_bp Predefined. */
6621
6622
/* TC0_CCABV_bm Predefined. */
6623
/* TC0_CCABV_bp Predefined. */
6624
6625
/* TC0_PERBV_bm Predefined. */
6626
/* TC0_PERBV_bp Predefined. */
6627
6628
6629
/* TC0.INTFLAGS bit masks and bit positions */
6630
#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
6631
#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
6632
6633
#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
6634
#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
6635
6636
#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
6637
#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
6638
6639
#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
6640
#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
6641
6642
#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
6643
#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
6644
6645
#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
6646
#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
6647
6648
6649
/* TC1.CTRLA bit masks and bit positions */
6650
#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
6651
#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
6652
#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
6653
#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
6654
#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
6655
#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
6656
#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
6657
#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
6658
#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
6659
#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
6660
6661
6662
/* TC1.CTRLB bit masks and bit positions */
6663
#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
6664
#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
6665
6666
#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
6667
#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
6668
6669
#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
6670
#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
6671
#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
6672
#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
6673
#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
6674
#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
6675
#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
6676
#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
6677
6678
6679
/* TC1.CTRLC bit masks and bit positions */
6680
#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
6681
#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
6682
6683
#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
6684
#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
6685
6686
6687
/* TC1.CTRLD bit masks and bit positions */
6688
#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
6689
#define TC1_EVACT_gp 5 /* Event Action group position. */
6690
#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
6691
#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
6692
#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
6693
#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
6694
#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
6695
#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
6696
6697
#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
6698
#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
6699
6700
#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
6701
#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
6702
#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
6703
#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
6704
#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
6705
#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
6706
#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
6707
#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
6708
#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
6709
#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
6710
6711
6712
/* TC1.CTRLE bit masks and bit positions */
6713
#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
6714
#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
6715
6716
6717
/* TC1.INTCTRLA bit masks and bit positions */
6718
#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
6719
#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
6720
#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
6721
#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
6722
#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
6723
#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
6724
6725
#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
6726
#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
6727
#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
6728
#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
6729
#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
6730
#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
6731
6732
6733
/* TC1.INTCTRLB bit masks and bit positions */
6734
#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
6735
#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
6736
#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
6737
#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
6738
#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
6739
#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
6740
6741
#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
6742
#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
6743
#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
6744
#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
6745
#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
6746
#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
6747
6748
6749
/* TC1.CTRLFCLR bit masks and bit positions */
6750
#define TC1_CMD_gm 0x0C /* Command group mask. */
6751
#define TC1_CMD_gp 2 /* Command group position. */
6752
#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
6753
#define TC1_CMD0_bp 2 /* Command bit 0 position. */
6754
#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
6755
#define TC1_CMD1_bp 3 /* Command bit 1 position. */
6756
6757
#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
6758
#define TC1_LUPD_bp 1 /* Lock Update bit position. */
6759
6760
#define TC1_DIR_bm 0x01 /* Direction bit mask. */
6761
#define TC1_DIR_bp 0 /* Direction bit position. */
6762
6763
6764
/* TC1.CTRLFSET bit masks and bit positions */
6765
/* TC1_CMD_gm Predefined. */
6766
/* TC1_CMD_gp Predefined. */
6767
/* TC1_CMD0_bm Predefined. */
6768
/* TC1_CMD0_bp Predefined. */
6769
/* TC1_CMD1_bm Predefined. */
6770
/* TC1_CMD1_bp Predefined. */
6771
6772
/* TC1_LUPD_bm Predefined. */
6773
/* TC1_LUPD_bp Predefined. */
6774
6775
/* TC1_DIR_bm Predefined. */
6776
/* TC1_DIR_bp Predefined. */
6777
6778
6779
/* TC1.CTRLGCLR bit masks and bit positions */
6780
#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
6781
#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
6782
6783
#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
6784
#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
6785
6786
#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
6787
#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
6788
6789
6790
/* TC1.CTRLGSET bit masks and bit positions */
6791
/* TC1_CCBBV_bm Predefined. */
6792
/* TC1_CCBBV_bp Predefined. */
6793
6794
/* TC1_CCABV_bm Predefined. */
6795
/* TC1_CCABV_bp Predefined. */
6796
6797
/* TC1_PERBV_bm Predefined. */
6798
/* TC1_PERBV_bp Predefined. */
6799
6800
6801
/* TC1.INTFLAGS bit masks and bit positions */
6802
#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
6803
#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
6804
6805
#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
6806
#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
6807
6808
#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
6809
#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
6810
6811
#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
6812
#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
6813
6814
6815
/* AWEX - Timer/Counter Advanced Waveform Extension */
6816
/* AWEX.CTRL bit masks and bit positions */
6817
#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
6818
#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
6819
6820
#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
6821
#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
6822
6823
#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
6824
#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
6825
6826
#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
6827
#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
6828
6829
#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
6830
#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
6831
6832
#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
6833
#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
6834
6835
6836
/* AWEX.FDCTRL bit masks and bit positions */
6837
#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
6838
#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
6839
6840
#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
6841
#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
6842
6843
#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
6844
#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
6845
#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
6846
#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
6847
#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
6848
#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
6849
6850
6851
/* AWEX.STATUS bit masks and bit positions */
6852
#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
6853
#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
6854
6855
#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
6856
#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
6857
6858
#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
6859
#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
6860
6861
6862
/* HIRES - Timer/Counter High-Resolution Extension */
6863
/* HIRES.CTRLA bit masks and bit positions */
6864
#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
6865
#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
6866
#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
6867
#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
6868
#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
6869
#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
6870
6871
6872
/* USART - Universal Asynchronous Receiver-Transmitter */
6873
/* USART.STATUS bit masks and bit positions */
6874
#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
6875
#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
6876
6877
#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
6878
#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
6879
6880
#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
6881
#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
6882
6883
#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
6884
#define USART_FERR_bp 4 /* Frame Error bit position. */
6885
6886
#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
6887
#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
6888
6889
#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
6890
#define USART_PERR_bp 2 /* Parity Error bit position. */
6891
6892
#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
6893
#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
6894
6895
6896
/* USART.CTRLA bit masks and bit positions */
6897
#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
6898
#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
6899
#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
6900
#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
6901
#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
6902
#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
6903
6904
#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
6905
#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
6906
#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
6907
#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
6908
#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
6909
#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
6910
6911
#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
6912
#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
6913
#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
6914
#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
6915
#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
6916
#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
6917
6918
6919
/* USART.CTRLB bit masks and bit positions */
6920
#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
6921
#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
6922
6923
#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
6924
#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
6925
6926
#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
6927
#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
6928
6929
#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
6930
#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
6931
6932
#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
6933
#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
6934
6935
6936
/* USART.CTRLC bit masks and bit positions */
6937
#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
6938
#define USART_CMODE_gp 6 /* Communication Mode group position. */
6939
#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
6940
#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
6941
#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
6942
#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
6943
6944
#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
6945
#define USART_PMODE_gp 4 /* Parity Mode group position. */
6946
#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
6947
#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
6948
#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
6949
#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
6950
6951
#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
6952
#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
6953
6954
#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
6955
#define USART_CHSIZE_gp 0 /* Character Size group position. */
6956
#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
6957
#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
6958
#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
6959
#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
6960
#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
6961
#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
6962
6963
6964
/* USART.BAUDCTRLA bit masks and bit positions */
6965
#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
6966
#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
6967
#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
6968
#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
6969
#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
6970
#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
6971
#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
6972
#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
6973
#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
6974
#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
6975
#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
6976
#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
6977
#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
6978
#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
6979
#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
6980
#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
6981
#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
6982
#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
6983
6984
6985
/* USART.BAUDCTRLB bit masks and bit positions */
6986
#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
6987
#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
6988
#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
6989
#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
6990
#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
6991
#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
6992
#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
6993
#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
6994
#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
6995
#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
6996
6997
/* USART_BSEL_gm Predefined. */
6998
/* USART_BSEL_gp Predefined. */
6999
/* USART_BSEL0_bm Predefined. */
7000
/* USART_BSEL0_bp Predefined. */
7001
/* USART_BSEL1_bm Predefined. */
7002
/* USART_BSEL1_bp Predefined. */
7003
/* USART_BSEL2_bm Predefined. */
7004
/* USART_BSEL2_bp Predefined. */
7005
/* USART_BSEL3_bm Predefined. */
7006
/* USART_BSEL3_bp Predefined. */
7007
7008
7009
/* SPI - Serial Peripheral Interface */
7010
/* SPI.CTRL bit masks and bit positions */
7011
#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
7012
#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
7013
7014
#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
7015
#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
7016
7017
#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
7018
#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
7019
7020
#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
7021
#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
7022
7023
#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
7024
#define SPI_MODE_gp 2 /* SPI Mode group position. */
7025
#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
7026
#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
7027
#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
7028
#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
7029
7030
#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
7031
#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
7032
#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
7033
#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
7034
#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
7035
#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
7036
7037
7038
/* SPI.INTCTRL bit masks and bit positions */
7039
#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
7040
#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
7041
#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
7042
#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
7043
#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
7044
#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
7045
7046
7047
/* SPI.STATUS bit masks and bit positions */
7048
#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
7049
#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
7050
7051
#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
7052
#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
7053
7054
7055
/* IRCOM - IR Communication Module */
7056
/* IRCOM.CTRL bit masks and bit positions */
7057
#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
7058
#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
7059
#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
7060
#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
7061
#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
7062
#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
7063
#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
7064
#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
7065
#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
7066
#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
7067
7068
7069
/* PRESC - Prescaler */
7070
/* PRESC.PRESCALER bit masks and bit positions */
7071
#define PRESC_RESET_bm 0x01 /* Reset bit mask. */
7072
#define PRESC_RESET_bp 0 /* Reset bit position. */
7073
7074
7075
7076
// Generic Port Pins
7077
7078
#define PIN0_bm 0x01
7079
#define PIN0_bp 0
7080
#define PIN1_bm 0x02
7081
#define PIN1_bp 1
7082
#define PIN2_bm 0x04
7083
#define PIN2_bp 2
7084
#define PIN3_bm 0x08
7085
#define PIN3_bp 3
7086
#define PIN4_bm 0x10
7087
#define PIN4_bp 4
7088
#define PIN5_bm 0x20
7089
#define PIN5_bp 5
7090
#define PIN6_bm 0x40
7091
#define PIN6_bp 6
7092
#define PIN7_bm 0x80
7093
#define PIN7_bp 7
7094
7095
7096
/* ========== Interrupt Vector Definitions ========== */
7097
/* Vector 0 is the reset vector */
7098
7099
/* OSC interrupt vectors */
7100
#define OSC_OSCF_vect_num 1
7101
#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
7102
7103
/* PORTC interrupt vectors */
7104
#define PORTC_INT0_vect_num 2
7105
#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
7106
#define PORTC_INT1_vect_num 3
7107
#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
7108
7109
/* PORTR interrupt vectors */
7110
#define PORTR_INT0_vect_num 4
7111
#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
7112
#define PORTR_INT1_vect_num 5
7113
#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
7114
7115
/* DMA interrupt vectors */
7116
#define DMA_CH0_vect_num 6
7117
#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
7118
#define DMA_CH1_vect_num 7
7119
#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
7120
#define DMA_CH2_vect_num 8
7121
#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
7122
#define DMA_CH3_vect_num 9
7123
#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
7124
7125
/* RTC interrupt vectors */
7126
#define RTC_OVF_vect_num 10
7127
#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
7128
#define RTC_COMP_vect_num 11
7129
#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
7130
7131
/* TWIC interrupt vectors */
7132
#define TWIC_TWIS_vect_num 12
7133
#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
7134
#define TWIC_TWIM_vect_num 13
7135
#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
7136
7137
/* TCC0 interrupt vectors */
7138
#define TCC0_OVF_vect_num 14
7139
#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
7140
#define TCC0_ERR_vect_num 15
7141
#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
7142
#define TCC0_CCA_vect_num 16
7143
#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
7144
#define TCC0_CCB_vect_num 17
7145
#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
7146
#define TCC0_CCC_vect_num 18
7147
#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
7148
#define TCC0_CCD_vect_num 19
7149
#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
7150
7151
/* TCC1 interrupt vectors */
7152
#define TCC1_OVF_vect_num 20
7153
#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
7154
#define TCC1_ERR_vect_num 21
7155
#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
7156
#define TCC1_CCA_vect_num 22
7157
#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
7158
#define TCC1_CCB_vect_num 23
7159
#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
7160
7161
/* SPIC interrupt vectors */
7162
#define SPIC_INT_vect_num 24
7163
#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
7164
7165
/* USARTC0 interrupt vectors */
7166
#define USARTC0_RXC_vect_num 25
7167
#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
7168
#define USARTC0_DRE_vect_num 26
7169
#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
7170
#define USARTC0_TXC_vect_num 27
7171
#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
7172
7173
/* USARTC1 interrupt vectors */
7174
#define USARTC1_RXC_vect_num 28
7175
#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
7176
#define USARTC1_DRE_vect_num 29
7177
#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
7178
#define USARTC1_TXC_vect_num 30
7179
#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
7180
7181
/* AES interrupt vectors */
7182
#define AES_INT_vect_num 31
7183
#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
7184
7185
/* NVM interrupt vectors */
7186
#define NVM_SPM_vect_num 32
7187
#define NVM_SPM_vect _VECTOR(32) /* SPM Interrupt */
7188
#define NVM_EE_vect_num 33
7189
#define NVM_EE_vect _VECTOR(33) /* EE Interrupt */
7190
7191
/* PORTB interrupt vectors */
7192
#define PORTB_INT0_vect_num 34
7193
#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
7194
#define PORTB_INT1_vect_num 35
7195
#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
7196
7197
/* ACB interrupt vectors */
7198
#define ACB_AC0_vect_num 36
7199
#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */
7200
#define ACB_AC1_vect_num 37
7201
#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */
7202
#define ACB_ACW_vect_num 38
7203
#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */
7204
7205
/* ADCB interrupt vectors */
7206
#define ADCB_CH0_vect_num 39
7207
#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */
7208
#define ADCB_CH1_vect_num 40
7209
#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */
7210
#define ADCB_CH2_vect_num 41
7211
#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */
7212
#define ADCB_CH3_vect_num 42
7213
#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */
7214
7215
/* PORTE interrupt vectors */
7216
#define PORTE_INT0_vect_num 43
7217
#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
7218
#define PORTE_INT1_vect_num 44
7219
#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
7220
7221
/* TWIE interrupt vectors */
7222
#define TWIE_TWIS_vect_num 45
7223
#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
7224
#define TWIE_TWIM_vect_num 46
7225
#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
7226
7227
/* TCE0 interrupt vectors */
7228
#define TCE0_OVF_vect_num 47
7229
#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
7230
#define TCE0_ERR_vect_num 48
7231
#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
7232
#define TCE0_CCA_vect_num 49
7233
#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
7234
#define TCE0_CCB_vect_num 50
7235
#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
7236
#define TCE0_CCC_vect_num 51
7237
#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
7238
#define TCE0_CCD_vect_num 52
7239
#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
7240
7241
/* TCE1 interrupt vectors */
7242
#define TCE1_OVF_vect_num 53
7243
#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
7244
#define TCE1_ERR_vect_num 54
7245
#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */
7246
#define TCE1_CCA_vect_num 55
7247
#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */
7248
#define TCE1_CCB_vect_num 56
7249
#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */
7250
7251
/* SPIE interrupt vectors */
7252
#define SPIE_INT_vect_num 57
7253
#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */
7254
7255
/* USARTE0 interrupt vectors */
7256
#define USARTE0_RXC_vect_num 58
7257
#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
7258
#define USARTE0_DRE_vect_num 59
7259
#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
7260
#define USARTE0_TXC_vect_num 60
7261
#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
7262
7263
/* USARTE1 interrupt vectors */
7264
#define USARTE1_RXC_vect_num 61
7265
#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */
7266
#define USARTE1_DRE_vect_num 62
7267
#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */
7268
#define USARTE1_TXC_vect_num 63
7269
#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */
7270
7271
/* PORTD interrupt vectors */
7272
#define PORTD_INT0_vect_num 64
7273
#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
7274
#define PORTD_INT1_vect_num 65
7275
#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
7276
7277
/* PORTA interrupt vectors */
7278
#define PORTA_INT0_vect_num 66
7279
#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
7280
#define PORTA_INT1_vect_num 67
7281
#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
7282
7283
/* ACA interrupt vectors */
7284
#define ACA_AC0_vect_num 68
7285
#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
7286
#define ACA_AC1_vect_num 69
7287
#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
7288
#define ACA_ACW_vect_num 70
7289
#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
7290
7291
/* ADCA interrupt vectors */
7292
#define ADCA_CH0_vect_num 71
7293
#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
7294
#define ADCA_CH1_vect_num 72
7295
#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
7296
#define ADCA_CH2_vect_num 73
7297
#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
7298
#define ADCA_CH3_vect_num 74
7299
#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
7300
7301
/* TWID interrupt vectors */
7302
#define TWID_TWIS_vect_num 75
7303
#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */
7304
#define TWID_TWIM_vect_num 76
7305
#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */
7306
7307
/* TCD0 interrupt vectors */
7308
#define TCD0_OVF_vect_num 77
7309
#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
7310
#define TCD0_ERR_vect_num 78
7311
#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
7312
#define TCD0_CCA_vect_num 79
7313
#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
7314
#define TCD0_CCB_vect_num 80
7315
#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
7316
#define TCD0_CCC_vect_num 81
7317
#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
7318
#define TCD0_CCD_vect_num 82
7319
#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
7320
7321
/* TCD1 interrupt vectors */
7322
#define TCD1_OVF_vect_num 83
7323
#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
7324
#define TCD1_ERR_vect_num 84
7325
#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
7326
#define TCD1_CCA_vect_num 85
7327
#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
7328
#define TCD1_CCB_vect_num 86
7329
#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
7330
7331
/* SPID interrupt vectors */
7332
#define SPID_INT_vect_num 87
7333
#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
7334
7335
/* USARTD0 interrupt vectors */
7336
#define USARTD0_RXC_vect_num 88
7337
#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
7338
#define USARTD0_DRE_vect_num 89
7339
#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
7340
#define USARTD0_TXC_vect_num 90
7341
#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
7342
7343
/* USARTD1 interrupt vectors */
7344
#define USARTD1_RXC_vect_num 91
7345
#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
7346
#define USARTD1_DRE_vect_num 92
7347
#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
7348
#define USARTD1_TXC_vect_num 93
7349
#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
7350
7351
/* PORTQ interrupt vectors */
7352
#define PORTQ_INT0_vect_num 94
7353
#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */
7354
#define PORTQ_INT1_vect_num 95
7355
#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */
7356
7357
/* PORTH interrupt vectors */
7358
#define PORTH_INT0_vect_num 96
7359
#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */
7360
#define PORTH_INT1_vect_num 97
7361
#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */
7362
7363
/* PORTJ interrupt vectors */
7364
#define PORTJ_INT0_vect_num 98
7365
#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */
7366
#define PORTJ_INT1_vect_num 99
7367
#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */
7368
7369
/* PORTK interrupt vectors */
7370
#define PORTK_INT0_vect_num 100
7371
#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */
7372
#define PORTK_INT1_vect_num 101
7373
#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */
7374
7375
/* PORTF interrupt vectors */
7376
#define PORTF_INT0_vect_num 104
7377
#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
7378
#define PORTF_INT1_vect_num 105
7379
#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
7380
7381
/* TWIF interrupt vectors */
7382
#define TWIF_TWIS_vect_num 106
7383
#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */
7384
#define TWIF_TWIM_vect_num 107
7385
#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */
7386
7387
/* TCF0 interrupt vectors */
7388
#define TCF0_OVF_vect_num 108
7389
#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
7390
#define TCF0_ERR_vect_num 109
7391
#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
7392
#define TCF0_CCA_vect_num 110
7393
#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
7394
#define TCF0_CCB_vect_num 111
7395
#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
7396
#define TCF0_CCC_vect_num 112
7397
#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
7398
#define TCF0_CCD_vect_num 113
7399
#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
7400
7401
/* TCF1 interrupt vectors */
7402
#define TCF1_OVF_vect_num 114
7403
#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */
7404
#define TCF1_ERR_vect_num 115
7405
#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */
7406
#define TCF1_CCA_vect_num 116
7407
#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */
7408
#define TCF1_CCB_vect_num 117
7409
#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */
7410
7411
/* SPIF interrupt vectors */
7412
#define SPIF_INT_vect_num 118
7413
#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */
7414
7415
/* USARTF0 interrupt vectors */
7416
#define USARTF0_RXC_vect_num 119
7417
#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */
7418
#define USARTF0_DRE_vect_num 120
7419
#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */
7420
#define USARTF0_TXC_vect_num 121
7421
#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */
7422
7423
/* USARTF1 interrupt vectors */
7424
#define USARTF1_RXC_vect_num 122
7425
#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */
7426
#define USARTF1_DRE_vect_num 123
7427
#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */
7428
#define USARTF1_TXC_vect_num 124
7429
#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */
7430
7431
/* USB interrupt vectors */
7432
#define USB_BUSEVENT_vect_num 125
7433
#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts and crc, underflow, overflow and stall error interrupts */
7434
#define USB_TRNCOMPL_vect_num 127
7435
#define USB_TRNCOMPL_vect _VECTOR(127) /* Transaction complete interrupt */
7436
7437
7438
#define _VECTOR_SIZE 4 /* Size of individual vector. */
7439
#define _VECTORS_SIZE (128 * _VECTOR_SIZE)
7440
7441
7442
/* ========== Constants ========== */
7443
7444
#define PROGMEM_START (0x00000)
7445
#define PROGMEM_SIZE (69632)
7446
#define PROGMEM_PAGE_SIZE (512)
7447
#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
7448
7449
#define APP_SECTION_START (0x00000)
7450
#define APP_SECTION_SIZE (65536)
7451
#define APP_SECTION_PAGE_SIZE (512)
7452
#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
7453
7454
#define APPTABLE_SECTION_START (0x1E000)
7455
#define APPTABLE_SECTION_SIZE (4096)
7456
#define APPTABLE_SECTION_PAGE_SIZE (512)
7457
#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
7458
7459
#define BOOT_SECTION_START (0x20000)
7460
#define BOOT_SECTION_SIZE (4096)
7461
#define BOOT_SECTION_PAGE_SIZE (512)
7462
#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
7463
7464
#define EEPROM_START (0x0000)
7465
#define EEPROM_SIZE (2048)
7466
#define EEPROM_PAGE_SIZE (32)
7467
#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
7468
7469
#define DATAMEM_START (0x0000)
7470
#define DATAMEM_SIZE (16777216)
7471
#define DATAMEM_PAGE_SIZE (0)
7472
#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
7473
7474
#define IO_START (0x0000)
7475
#define IO_SIZE (4096)
7476
#define IO_PAGE_SIZE (0)
7477
#define IO_END (IO_START + IO_SIZE - 1)
7478
7479
#define MAPPED_EEPROM_START (0x1000)
7480
#define MAPPED_EEPROM_SIZE (2048)
7481
#define MAPPED_EEPROM_PAGE_SIZE (0)
7482
#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
7483
7484
#define INTERNAL_SRAM_START (0x2000)
7485
#define INTERNAL_SRAM_SIZE (4096)
7486
#define INTERNAL_SRAM_PAGE_SIZE (0)
7487
#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
7488
7489
#define EXTERNAL_SRAM_START (0x4000)
7490
#define EXTERNAL_SRAM_SIZE (16760832)
7491
#define EXTERNAL_SRAM_PAGE_SIZE (0)
7492
#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1)
7493
7494
#define FUSE_START (0x0000)
7495
#define FUSE_SIZE (6)
7496
#define FUSE_PAGE_SIZE (0)
7497
#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
7498
7499
#define LOCKBIT_START (0x0000)
7500
#define LOCKBIT_SIZE (1)
7501
#define LOCKBIT_PAGE_SIZE (0)
7502
#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
7503
7504
#define SIGNATURES_START (0x0000)
7505
#define SIGNATURES_SIZE (3)
7506
#define SIGNATURES_PAGE_SIZE (0)
7507
#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
7508
7509
#define USER_SIGNATURES_START (0x0000)
7510
#define USER_SIGNATURES_SIZE (512)
7511
#define USER_SIGNATURES_PAGE_SIZE (0)
7512
#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
7513
7514
#define PROD_SIGNATURES_START (0x0000)
7515
#define PROD_SIGNATURES_SIZE (52)
7516
#define PROD_SIGNATURES_PAGE_SIZE (0)
7517
#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
7518
7519
#define FLASHEND PROGMEM_END
7520
#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
7521
#define RAMSTART INTERNAL_SRAM_START
7522
#define RAMSIZE INTERNAL_SRAM_SIZE
7523
#define RAMEND INTERNAL_SRAM_END
7524
#define XRAMSTART EXTERNAL_SRAM_START
7525
#define XRAMSIZE EXTERNAL_SRAM_SIZE
7526
#define XRAMEND EXTERNAL_SRAM_END
7527
#define E2END EEPROM_END
7528
#define E2PAGESIZE EEPROM_PAGE_SIZE
7529
7530
7531
/* ========== Fuses ========== */
7532
#define FUSE_MEMORY_SIZE 0
7533
7534
7535
/* ========== Lock Bits ========== */
7536
#define __LOCK_BITS_EXIST
7537
#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
7538
#define __BOOT_LOCK_APPLICATION_BITS_EXIST
7539
#define __BOOT_LOCK_BOOT_BITS_EXIST
7540
7541
7542
/* ========== Signature ========== */
7543
#define SIGNATURE_0 0x1E
7544
#define SIGNATURE_1 0x96
7545
#define SIGNATURE_2 0x4E
7546
7547
7548
#endif /* _AVR_ATxmega64A1U_H_ */
7549
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Version: 2.0.1