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//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file contains the X86 implementation of the TargetRegisterInfo class.
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// This file is responsible for the frame pointer elimination optimization
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//===----------------------------------------------------------------------===//
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#include "X86RegisterInfo.h"
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#include "X86InstrBuilder.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/CommandLine.h"
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ForceStackAlign("force-align-stack",
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cl::desc("Force align the stack to the minimum alignment"
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" needed for the function."),
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cl::init(false), cl::Hidden);
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X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
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const TargetInstrInfo &tii)
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: X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
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X86::ADJCALLSTACKDOWN64 :
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X86::ADJCALLSTACKDOWN32,
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tm.getSubtarget<X86Subtarget>().is64Bit() ?
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X86::ADJCALLSTACKUP64 :
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X86::ADJCALLSTACKUP32),
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// Cache some information.
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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Is64Bit = Subtarget->is64Bit();
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IsWin64 = Subtarget->isTargetWin64();
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StackAlign = TM.getFrameInfo()->getStackAlignment();
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/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
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/// specific numbering, used in debug info and exception tables.
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int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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unsigned Flavour = DWARFFlavour::X86_64;
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if (!Subtarget->is64Bit()) {
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if (Subtarget->isTargetDarwin()) {
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Flavour = DWARFFlavour::X86_32_DarwinEH;
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Flavour = DWARFFlavour::X86_32_Generic;
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} else if (Subtarget->isTargetCygMing()) {
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// Unsupported by now, just quick fallback
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Flavour = DWARFFlavour::X86_32_Generic;
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Flavour = DWARFFlavour::X86_32_Generic;
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return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
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/// getX86RegNum - This function maps LLVM register identifiers to their X86
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/// specific numbering, which is used in various places encoding instructions.
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unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
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case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
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case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
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case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
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case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
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case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
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case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
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case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
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case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
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case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
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case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
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case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
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case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
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case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
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case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
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case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
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case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
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case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
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case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
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return RegNo-X86::ST0;
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case X86::XMM0: case X86::XMM8:
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case X86::YMM0: case X86::YMM8: case X86::MM0:
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case X86::XMM1: case X86::XMM9:
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case X86::YMM1: case X86::YMM9: case X86::MM1:
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case X86::XMM2: case X86::XMM10:
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case X86::YMM2: case X86::YMM10: case X86::MM2:
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case X86::XMM3: case X86::XMM11:
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case X86::YMM3: case X86::YMM11: case X86::MM3:
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case X86::XMM4: case X86::XMM12:
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case X86::YMM4: case X86::YMM12: case X86::MM4:
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case X86::XMM5: case X86::XMM13:
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case X86::YMM5: case X86::YMM13: case X86::MM5:
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case X86::XMM6: case X86::XMM14:
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case X86::YMM6: case X86::YMM14: case X86::MM6:
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case X86::XMM7: case X86::XMM15:
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case X86::YMM7: case X86::YMM15: case X86::MM7:
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// Pseudo index registers are equivalent to a "none"
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// scaled index (See Intel Manual 2A, table 2-3)
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assert(isVirtualRegister(RegNo) && "Unknown physical register!");
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llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
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const TargetRegisterClass *
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X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned SubIdx) const {
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if (B == &X86::GR8RegClass) {
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if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
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} else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass ||
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A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
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A == &X86::GR32_NOREXRegClass ||
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A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_ABCDRegClass;
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else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
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A == &X86::GR16_NOREXRegClass)
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return &X86::GR16_ABCDRegClass;
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} else if (B == &X86::GR8_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
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A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_NOREXRegClass;
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else if (A == &X86::GR32_ABCDRegClass)
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return &X86::GR32_ABCDRegClass;
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else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
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return &X86::GR16_NOREXRegClass;
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else if (A == &X86::GR16_ABCDRegClass)
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return &X86::GR16_ABCDRegClass;
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case X86::sub_8bit_hi:
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if (B == &X86::GR8_ABCD_HRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass ||
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A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
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A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_ABCDRegClass;
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else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
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A == &X86::GR16_NOREXRegClass)
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return &X86::GR16_ABCDRegClass;
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if (B == &X86::GR16RegClass) {
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if (A->getSize() == 4 || A->getSize() == 8)
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} else if (B == &X86::GR16_ABCDRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass ||
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A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
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A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_ABCDRegClass;
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} else if (B == &X86::GR16_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
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A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_NOREXRegClass;
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else if (A == &X86::GR32_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
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if (A->getSize() == 8)
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} else if (B == &X86::GR32_ABCDRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass ||
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A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_ABCDRegClass;
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} else if (B == &X86::GR32_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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if (B == &X86::FR32RegClass)
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if (B == &X86::FR64RegClass)
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if (B == &X86::VR128RegClass)
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const TargetRegisterClass *
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X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
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default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
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case 0: // Normal GPRs.
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if (TM.getSubtarget<X86Subtarget>().is64Bit())
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return &X86::GR64RegClass;
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return &X86::GR32RegClass;
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case 1: // Normal GRPs except the stack pointer (for encoding reasons).
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if (TM.getSubtarget<X86Subtarget>().is64Bit())
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return &X86::GR64_NOSPRegClass;
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return &X86::GR32_NOSPRegClass;
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const TargetRegisterClass *
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X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
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if (RC == &X86::CCRRegClass) {
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return &X86::GR64RegClass;
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return &X86::GR32RegClass;
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X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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bool callsEHReturn = false;
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bool ghcCall = false;
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callsEHReturn = MF->getMMI().callsEHReturn();
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const Function *F = MF->getFunction();
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ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
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static const unsigned GhcCalleeSavedRegs[] = {
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static const unsigned CalleeSavedRegs32Bit[] = {
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X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
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static const unsigned CalleeSavedRegs32EHRet[] = {
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X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
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static const unsigned CalleeSavedRegs64Bit[] = {
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X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
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static const unsigned CalleeSavedRegs64EHRet[] = {
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X86::RAX, X86::RDX, X86::RBX, X86::R12,
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X86::R13, X86::R14, X86::R15, X86::RBP, 0
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static const unsigned CalleeSavedRegsWin64[] = {
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X86::RBX, X86::RBP, X86::RDI, X86::RSI,
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X86::R12, X86::R13, X86::R14, X86::R15,
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X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
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X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
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X86::XMM14, X86::XMM15, 0
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return GhcCalleeSavedRegs;
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} else if (Is64Bit) {
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return CalleeSavedRegsWin64;
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return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
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return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
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BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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// Set the stack-pointer register and its aliases as reserved.
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Reserved.set(X86::RSP);
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Reserved.set(X86::ESP);
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Reserved.set(X86::SP);
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Reserved.set(X86::SPL);
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// Set the instruction pointer register and its aliases as reserved.
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Reserved.set(X86::RIP);
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Reserved.set(X86::EIP);
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Reserved.set(X86::IP);
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// Set the frame-pointer register and its aliases as reserved if needed.
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Reserved.set(X86::RBP);
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Reserved.set(X86::EBP);
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Reserved.set(X86::BP);
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Reserved.set(X86::BPL);
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// Mark the x87 stack registers as reserved, since they don't behave normally
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// with respect to liveness. We don't fully model the effects of x87 stack
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// pushes and pops after stackification.
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Reserved.set(X86::ST0);
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Reserved.set(X86::ST1);
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Reserved.set(X86::ST2);
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Reserved.set(X86::ST3);
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Reserved.set(X86::ST4);
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Reserved.set(X86::ST5);
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Reserved.set(X86::ST6);
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Reserved.set(X86::ST7);
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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/// hasFP - Return true if the specified function should have a dedicated frame
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/// pointer register. This is true if the function has variable sized allocas
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/// or if frame pointer elimination is disabled.
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bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const MachineModuleInfo &MMI = MF.getMMI();
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return (DisableFramePointerElim(MF) ||
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needsStackRealignment(MF) ||
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MFI->hasVarSizedObjects() ||
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MFI->isFrameAddressTaken() ||
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MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
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MMI.callsUnwindInit());
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bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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return (RealignStack &&
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!MFI->hasVarSizedObjects());
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bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const Function *F = MF.getFunction();
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bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
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F->hasFnAttr(Attribute::StackAlignment));
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// FIXME: Currently we don't support stack realignment for functions with
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// variable-sized allocas.
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// FIXME: It's more complicated than this...
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if (0 && requiresRealignment && MFI->hasVarSizedObjects())
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"Stack realignment in presense of dynamic allocas is not supported");
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// If we've requested that we force align the stack do so now.
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return canRealignStack(MF);
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return requiresRealignment && canRealignStack(MF);
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bool X86RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
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return !MF.getFrameInfo()->hasVarSizedObjects();
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bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
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unsigned Reg, int &FrameIdx) const {
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if (Reg == FramePtr && hasFP(MF)) {
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FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
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X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
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const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
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uint64_t StackSize = MFI->getStackSize();
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if (needsStackRealignment(MF)) {
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// Skip the saved EBP.
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unsigned Align = MFI->getObjectAlignment(FI);
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assert((-(Offset + StackSize)) % Align == 0);
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return Offset + StackSize;
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// FIXME: Support tail calls
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return Offset + StackSize;
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// Skip the saved EBP.
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// Skip the RETADDR move area
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const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
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int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
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if (TailCallReturnAddrDelta < 0)
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Offset -= TailCallReturnAddrDelta;
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static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
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return X86::SUB64ri8;
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return X86::SUB64ri32;
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return X86::SUB32ri8;
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static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
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return X86::ADD64ri8;
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return X86::ADD64ri32;
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return X86::ADD32ri8;
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void X86RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (!hasReservedCallFrame(MF)) {
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// If the stack pointer can be changed after prologue, turn the
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// adjcallstackup instruction into a 'sub ESP, <amt>' and the
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// adjcallstackdown instruction into 'add ESP, <amt>'
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// TODO: consider using push / pop instead of sub + store / add
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MachineInstr *Old = I;
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uint64_t Amount = Old->getOperand(0).getImm();
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
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MachineInstr *New = 0;
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if (Old->getOpcode() == getCallFrameSetupOpcode()) {
579
New = BuildMI(MF, Old->getDebugLoc(),
580
TII.get(getSUBriOpcode(Is64Bit, Amount)),
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assert(Old->getOpcode() == getCallFrameDestroyOpcode());
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// Factor out the amount the callee already popped.
588
uint64_t CalleeAmt = Old->getOperand(1).getImm();
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unsigned Opc = getADDriOpcode(Is64Bit, Amount);
593
New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
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// The EFLAGS implicit def is dead.
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New->getOperand(3).setIsDead();
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// Replace the pseudo instruction with a new instruction.
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} else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
608
// If we are performing frame pointer elimination and if the callee pops
609
// something off the stack pointer, add it back. We do this until we have
610
// more advanced stack pointer tracking ability.
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if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
612
unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
613
MachineInstr *Old = I;
615
BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
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// The EFLAGS implicit def is dead.
621
New->getOperand(3).setIsDead();
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X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const{
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
636
MachineFunction &MF = *MI.getParent()->getParent();
638
while (!MI.getOperand(i).isFI()) {
640
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
643
int FrameIndex = MI.getOperand(i).getIndex();
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unsigned Opc = MI.getOpcode();
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bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
648
if (needsStackRealignment(MF))
649
BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
653
BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
655
// This must be part of a four operand memory reference. Replace the
656
// FrameIndex with base register with EBP. Add an offset to the offset.
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MI.getOperand(i).ChangeToRegister(BasePtr, false);
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// Now add the frame object offset to the offset from EBP.
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// Tail call jmp happens after FP is popped.
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const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
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const MachineFrameInfo *MFI = MF.getFrameInfo();
665
FIOffset = MFI->getObjectOffset(FrameIndex) - TFI.getOffsetOfLocalArea();
667
FIOffset = getFrameIndexOffset(MF, FrameIndex);
669
if (MI.getOperand(i+3).isImm()) {
670
// Offset is a 32-bit integer.
671
int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
672
MI.getOperand(i + 3).ChangeToImmediate(Offset);
674
// Offset is symbolic. This is extremely rare.
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uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
676
MI.getOperand(i+3).setOffset(Offset);
681
X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
682
RegScavenger *RS) const {
683
MachineFrameInfo *MFI = MF.getFrameInfo();
685
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
686
int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
688
if (TailCallReturnAddrDelta < 0) {
689
// create RETURNADDR area
698
MFI->CreateFixedObject(-TailCallReturnAddrDelta,
699
(-1U*SlotSize)+TailCallReturnAddrDelta, true);
703
assert((TailCallReturnAddrDelta <= 0) &&
704
"The Delta should always be zero or negative");
705
const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
707
// Create a frame entry for the EBP register that must be saved.
708
int FrameIdx = MFI->CreateFixedObject(SlotSize,
710
TFI.getOffsetOfLocalArea() +
711
TailCallReturnAddrDelta,
713
assert(FrameIdx == MFI->getObjectIndexBegin() &&
714
"Slot for EBP register must be last in order to be found!");
719
/// emitSPUpdate - Emit a series of instructions to increment / decrement the
720
/// stack pointer by a constant value.
722
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
723
unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
724
const TargetInstrInfo &TII) {
725
bool isSub = NumBytes < 0;
726
uint64_t Offset = isSub ? -NumBytes : NumBytes;
727
unsigned Opc = isSub ?
728
getSUBriOpcode(Is64Bit, Offset) :
729
getADDriOpcode(Is64Bit, Offset);
730
uint64_t Chunk = (1LL << 31) - 1;
731
DebugLoc DL = MBB.findDebugLoc(MBBI);
734
uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
736
BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
739
MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
744
/// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
746
void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
747
unsigned StackPtr, uint64_t *NumBytes = NULL) {
748
if (MBBI == MBB.begin()) return;
750
MachineBasicBlock::iterator PI = prior(MBBI);
751
unsigned Opc = PI->getOpcode();
752
if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
753
Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
754
PI->getOperand(0).getReg() == StackPtr) {
756
*NumBytes += PI->getOperand(2).getImm();
758
} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
759
Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
760
PI->getOperand(0).getReg() == StackPtr) {
762
*NumBytes -= PI->getOperand(2).getImm();
767
/// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
769
void mergeSPUpdatesDown(MachineBasicBlock &MBB,
770
MachineBasicBlock::iterator &MBBI,
771
unsigned StackPtr, uint64_t *NumBytes = NULL) {
772
// FIXME: THIS ISN'T RUN!!!
775
if (MBBI == MBB.end()) return;
777
MachineBasicBlock::iterator NI = llvm::next(MBBI);
778
if (NI == MBB.end()) return;
780
unsigned Opc = NI->getOpcode();
781
if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
782
Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
783
NI->getOperand(0).getReg() == StackPtr) {
785
*NumBytes -= NI->getOperand(2).getImm();
788
} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
789
Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
790
NI->getOperand(0).getReg() == StackPtr) {
792
*NumBytes += NI->getOperand(2).getImm();
798
/// mergeSPUpdates - Checks the instruction before/after the passed
799
/// instruction. If it is an ADD/SUB instruction it is deleted argument and the
800
/// stack adjustment is returned as a positive value for ADD and a negative for
802
static int mergeSPUpdates(MachineBasicBlock &MBB,
803
MachineBasicBlock::iterator &MBBI,
805
bool doMergeWithPrevious) {
806
if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
807
(!doMergeWithPrevious && MBBI == MBB.end()))
810
MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
811
MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
812
unsigned Opc = PI->getOpcode();
815
if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
816
Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
817
PI->getOperand(0).getReg() == StackPtr){
818
Offset += PI->getOperand(2).getImm();
820
if (!doMergeWithPrevious) MBBI = NI;
821
} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
822
Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
823
PI->getOperand(0).getReg() == StackPtr) {
824
Offset -= PI->getOperand(2).getImm();
826
if (!doMergeWithPrevious) MBBI = NI;
832
void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
834
unsigned FramePtr) const {
835
MachineFrameInfo *MFI = MF.getFrameInfo();
836
MachineModuleInfo &MMI = MF.getMMI();
838
// Add callee saved registers to move list.
839
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
840
if (CSI.empty()) return;
842
std::vector<MachineMove> &Moves = MMI.getFrameMoves();
843
const TargetData *TD = MF.getTarget().getTargetData();
844
bool HasFP = hasFP(MF);
846
// Calculate amount of bytes used for return address storing.
848
(MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
849
TargetFrameInfo::StackGrowsUp ?
850
TD->getPointerSize() : -TD->getPointerSize());
852
// FIXME: This is dirty hack. The code itself is pretty mess right now.
853
// It should be rewritten from scratch and generalized sometimes.
855
// Determine maximum offset (minumum due to stack growth).
856
int64_t MaxOffset = 0;
857
for (std::vector<CalleeSavedInfo>::const_iterator
858
I = CSI.begin(), E = CSI.end(); I != E; ++I)
859
MaxOffset = std::min(MaxOffset,
860
MFI->getObjectOffset(I->getFrameIdx()));
862
// Calculate offsets.
863
int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
864
for (std::vector<CalleeSavedInfo>::const_iterator
865
I = CSI.begin(), E = CSI.end(); I != E; ++I) {
866
int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
867
unsigned Reg = I->getReg();
868
Offset = MaxOffset - Offset + saveAreaOffset;
870
// Don't output a new machine move if we're re-saving the frame
871
// pointer. This happens when the PrologEpilogInserter has inserted an extra
872
// "PUSH" of the frame pointer -- the "emitPrologue" method automatically
873
// generates one when frame pointers are used. If we generate a "machine
874
// move" for this extra "PUSH", the linker will lose track of the fact that
875
// the frame pointer should have the value of the first "PUSH" when it's
878
// FIXME: This looks inelegant. It's possibly correct, but it's covering up
879
// another bug. I.e., one where we generate a prolog like this:
887
// The immediate re-push of EBP is unnecessary. At the least, it's an
888
// optimization bug. EBP can be used as a scratch register in certain
889
// cases, but probably not when we have a frame pointer.
890
if (HasFP && FramePtr == Reg)
893
MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
894
MachineLocation CSSrc(Reg);
895
Moves.push_back(MachineMove(Label, CSDst, CSSrc));
899
/// emitPrologue - Push callee-saved registers onto the stack, which
900
/// automatically adjust the stack pointer. Adjust the stack pointer to allocate
901
/// space for local variables. Also emit labels used by the exception handler to
902
/// generate the exception handling frames.
903
void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
904
MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
905
MachineBasicBlock::iterator MBBI = MBB.begin();
906
MachineFrameInfo *MFI = MF.getFrameInfo();
907
const Function *Fn = MF.getFunction();
908
const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
909
MachineModuleInfo &MMI = MF.getMMI();
910
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
911
bool needsFrameMoves = MMI.hasDebugInfo() ||
912
!Fn->doesNotThrow() || UnwindTablesMandatory;
913
uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
914
uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
915
bool HasFP = hasFP(MF);
918
// If we're forcing a stack realignment we can't rely on just the frame
919
// info, we need to know the ABI stack alignment as well in case we
920
// have a call out. Otherwise just make sure we have some alignment - we'll
921
// go with the minimum SlotSize.
922
if (ForceStackAlign) {
924
MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
925
else if (MaxAlign < SlotSize)
929
// Add RETADDR move area to callee saved frame size.
930
int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
931
if (TailCallReturnAddrDelta < 0)
932
X86FI->setCalleeSavedFrameSize(
933
X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
935
// If this is x86-64 and the Red Zone is not disabled, if we are a leaf
936
// function, and use up to 128 bytes of stack space, don't have a frame
937
// pointer, calls, or dynamic alloca then we do not need to adjust the
938
// stack pointer (we fit in the Red Zone).
939
if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
940
!needsStackRealignment(MF) &&
941
!MFI->hasVarSizedObjects() && // No dynamic alloca.
942
!MFI->adjustsStack() && // No calls.
943
!Subtarget->isTargetWin64()) { // Win64 has no Red Zone
944
uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
945
if (HasFP) MinSize += SlotSize;
946
StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
947
MFI->setStackSize(StackSize);
948
} else if (Subtarget->isTargetWin64()) {
949
// We need to always allocate 32 bytes as register spill area.
950
// FIXME: We might reuse these 32 bytes for leaf functions.
952
MFI->setStackSize(StackSize);
955
// Insert stack pointer adjustment for later moving of return addr. Only
956
// applies to tail call optimized functions where the callee argument stack
957
// size is bigger than the callers.
958
if (TailCallReturnAddrDelta < 0) {
960
BuildMI(MBB, MBBI, DL,
961
TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
964
.addImm(-TailCallReturnAddrDelta);
965
MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
968
// Mapping for machine moves:
970
// DST: VirtualFP AND
971
// SRC: VirtualFP => DW_CFA_def_cfa_offset
972
// ELSE => DW_CFA_def_cfa
974
// SRC: VirtualFP AND
975
// DST: Register => DW_CFA_def_cfa_register
978
// OFFSET < 0 => DW_CFA_offset_extended_sf
979
// REG < 64 => DW_CFA_offset + Reg
980
// ELSE => DW_CFA_offset_extended
982
std::vector<MachineMove> &Moves = MMI.getFrameMoves();
983
const TargetData *TD = MF.getTarget().getTargetData();
984
uint64_t NumBytes = 0;
985
int stackGrowth = -TD->getPointerSize();
988
// Calculate required stack adjustment.
989
uint64_t FrameSize = StackSize - SlotSize;
990
if (needsStackRealignment(MF))
991
FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
993
NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
995
// Get the offset of the stack slot for the EBP register, which is
996
// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
997
// Update the frame offset adjustment.
998
MFI->setOffsetAdjustment(-NumBytes);
1000
// Save EBP/RBP into the appropriate stack slot.
1001
BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1002
.addReg(FramePtr, RegState::Kill);
1004
if (needsFrameMoves) {
1005
// Mark the place where EBP/RBP was saved.
1006
MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
1007
BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel);
1009
// Define the current CFA rule to use the provided offset.
1011
MachineLocation SPDst(MachineLocation::VirtualFP);
1012
MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
1013
Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
1015
// FIXME: Verify & implement for FP
1016
MachineLocation SPDst(StackPtr);
1017
MachineLocation SPSrc(StackPtr, stackGrowth);
1018
Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
1021
// Change the rule for the FramePtr to be an "offset" rule.
1022
MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
1023
MachineLocation FPSrc(FramePtr);
1024
Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1027
// Update EBP with the new base value...
1028
BuildMI(MBB, MBBI, DL,
1029
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
1032
if (needsFrameMoves) {
1033
// Mark effective beginning of when frame pointer becomes valid.
1034
MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
1035
BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel);
1037
// Define the current CFA to use the EBP/RBP register.
1038
MachineLocation FPDst(FramePtr);
1039
MachineLocation FPSrc(MachineLocation::VirtualFP);
1040
Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1043
// Mark the FramePtr as live-in in every block except the entry.
1044
for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
1046
I->addLiveIn(FramePtr);
1049
if (needsStackRealignment(MF)) {
1051
BuildMI(MBB, MBBI, DL,
1052
TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1053
StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1055
// The EFLAGS implicit def is dead.
1056
MI->getOperand(3).setIsDead();
1059
NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1062
// Skip the callee-saved push instructions.
1063
bool PushedRegs = false;
1064
int StackOffset = 2 * stackGrowth;
1066
while (MBBI != MBB.end() &&
1067
(MBBI->getOpcode() == X86::PUSH32r ||
1068
MBBI->getOpcode() == X86::PUSH64r)) {
1072
if (!HasFP && needsFrameMoves) {
1073
// Mark callee-saved push instruction.
1074
MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1075
BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
1077
// Define the current CFA rule to use the provided offset.
1078
unsigned Ptr = StackSize ?
1079
MachineLocation::VirtualFP : StackPtr;
1080
MachineLocation SPDst(Ptr);
1081
MachineLocation SPSrc(Ptr, StackOffset);
1082
Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1083
StackOffset += stackGrowth;
1087
DL = MBB.findDebugLoc(MBBI);
1089
// Adjust stack pointer: ESP -= numbytes.
1091
// Windows and cygwin/mingw require a prologue helper routine when allocating
1092
// more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
1093
// uses __alloca. __alloca and the 32-bit version of __chkstk will probe
1094
// the stack and adjust the stack pointer in one go. The 64-bit version
1095
// of __chkstk is only responsible for probing the stack. The 64-bit
1096
// prologue is responsible for adjusting the stack pointer. Touching the
1097
// stack at 4K increments is necessary to ensure that the guard pages used
1098
// by the OS virtual memory manager are allocated in correct sequence.
1099
if (NumBytes >= 4096 &&
1100
(Subtarget->isTargetCygMing() || Subtarget->isTargetWin32())) {
1101
// Check, whether EAX is livein for this function.
1102
bool isEAXAlive = false;
1103
for (MachineRegisterInfo::livein_iterator
1104
II = MF.getRegInfo().livein_begin(),
1105
EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1106
unsigned Reg = II->first;
1107
isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1108
Reg == X86::AH || Reg == X86::AL);
1112
const char *StackProbeSymbol =
1113
Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
1115
BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1117
BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1118
.addExternalSymbol(StackProbeSymbol)
1119
.addReg(StackPtr, RegState::Define | RegState::Implicit)
1120
.addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
1123
BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1124
.addReg(X86::EAX, RegState::Kill);
1126
// Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1127
// allocated bytes for EAX.
1128
BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1129
.addImm(NumBytes - 4);
1130
BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1131
.addExternalSymbol(StackProbeSymbol)
1132
.addReg(StackPtr, RegState::Define | RegState::Implicit)
1133
.addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
1136
MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1138
StackPtr, false, NumBytes - 4);
1139
MBB.insert(MBBI, MI);
1141
} else if (NumBytes) {
1142
// If there is an SUB32ri of ESP immediately before this instruction, merge
1143
// the two. This can be the case when tail call elimination is enabled and
1144
// the callee has more arguments then the caller.
1145
NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1147
// If there is an ADD32ri or SUB32ri of ESP immediately after this
1148
// instruction, merge the two instructions.
1149
mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1152
emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1155
if ((NumBytes || PushedRegs) && needsFrameMoves) {
1156
// Mark end of stack pointer adjustment.
1157
MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1158
BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
1160
if (!HasFP && NumBytes) {
1161
// Define the current CFA rule to use the provided offset.
1163
MachineLocation SPDst(MachineLocation::VirtualFP);
1164
MachineLocation SPSrc(MachineLocation::VirtualFP,
1165
-StackSize + stackGrowth);
1166
Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1168
// FIXME: Verify & implement for FP
1169
MachineLocation SPDst(StackPtr);
1170
MachineLocation SPSrc(StackPtr, stackGrowth);
1171
Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1175
// Emit DWARF info specifying the offsets of the callee-saved registers.
1177
emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
1181
void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1182
MachineBasicBlock &MBB) const {
1183
const MachineFrameInfo *MFI = MF.getFrameInfo();
1184
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1185
MachineBasicBlock::iterator MBBI = prior(MBB.end());
1186
unsigned RetOpcode = MBBI->getOpcode();
1187
DebugLoc DL = MBBI->getDebugLoc();
1189
switch (RetOpcode) {
1191
llvm_unreachable("Can only insert epilog into returning blocks");
1194
case X86::TCRETURNdi:
1195
case X86::TCRETURNri:
1196
case X86::TCRETURNmi:
1197
case X86::TCRETURNdi64:
1198
case X86::TCRETURNri64:
1199
case X86::TCRETURNmi64:
1200
case X86::EH_RETURN:
1201
case X86::EH_RETURN64:
1202
break; // These are ok
1205
// Get the number of bytes to allocate from the FrameInfo.
1206
uint64_t StackSize = MFI->getStackSize();
1207
uint64_t MaxAlign = MFI->getMaxAlignment();
1208
unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1209
uint64_t NumBytes = 0;
1211
// If we're forcing a stack realignment we can't rely on just the frame
1212
// info, we need to know the ABI stack alignment as well in case we
1213
// have a call out. Otherwise just make sure we have some alignment - we'll
1214
// go with the minimum.
1215
if (ForceStackAlign) {
1216
if (MFI->hasCalls())
1217
MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
1219
MaxAlign = MaxAlign ? MaxAlign : 4;
1223
// Calculate required stack adjustment.
1224
uint64_t FrameSize = StackSize - SlotSize;
1225
if (needsStackRealignment(MF))
1226
FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1228
NumBytes = FrameSize - CSSize;
1231
BuildMI(MBB, MBBI, DL,
1232
TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1234
NumBytes = StackSize - CSSize;
1237
// Skip the callee-saved pop instructions.
1238
MachineBasicBlock::iterator LastCSPop = MBBI;
1239
while (MBBI != MBB.begin()) {
1240
MachineBasicBlock::iterator PI = prior(MBBI);
1241
unsigned Opc = PI->getOpcode();
1243
if (Opc != X86::POP32r && Opc != X86::POP64r &&
1244
!PI->getDesc().isTerminator())
1250
DL = MBBI->getDebugLoc();
1252
// If there is an ADD32ri or SUB32ri of ESP immediately before this
1253
// instruction, merge the two instructions.
1254
if (NumBytes || MFI->hasVarSizedObjects())
1255
mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1257
// If dynamic alloca is used, then reset esp to point to the last callee-saved
1258
// slot before popping them off! Same applies for the case, when stack was
1260
if (needsStackRealignment(MF)) {
1261
// We cannot use LEA here, because stack pointer was realigned. We need to
1262
// deallocate local frame back.
1264
emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1265
MBBI = prior(LastCSPop);
1268
BuildMI(MBB, MBBI, DL,
1269
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1270
StackPtr).addReg(FramePtr);
1271
} else if (MFI->hasVarSizedObjects()) {
1273
unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1275
addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1276
FramePtr, false, -CSSize);
1277
MBB.insert(MBBI, MI);
1279
BuildMI(MBB, MBBI, DL,
1280
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1283
} else if (NumBytes) {
1284
// Adjust stack pointer back: ESP += numbytes.
1285
emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1288
// We're returning from function via eh_return.
1289
if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1290
MBBI = prior(MBB.end());
1291
MachineOperand &DestAddr = MBBI->getOperand(0);
1292
assert(DestAddr.isReg() && "Offset should be in register!");
1293
BuildMI(MBB, MBBI, DL,
1294
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1295
StackPtr).addReg(DestAddr.getReg());
1296
} else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1297
RetOpcode == X86::TCRETURNmi ||
1298
RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1299
RetOpcode == X86::TCRETURNmi64) {
1300
bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1301
// Tail call return: adjust the stack pointer and jump to callee.
1302
MBBI = prior(MBB.end());
1303
MachineOperand &JumpTarget = MBBI->getOperand(0);
1304
MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1305
assert(StackAdjust.isImm() && "Expecting immediate value.");
1307
// Adjust stack pointer.
1308
int StackAdj = StackAdjust.getImm();
1309
int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1311
assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1313
// Incoporate the retaddr area.
1314
Offset = StackAdj-MaxTCDelta;
1315
assert(Offset >= 0 && "Offset should never be negative");
1318
// Check for possible merge with preceeding ADD instruction.
1319
Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1320
emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1323
// Jump to label or value in register.
1324
if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1325
BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1326
? X86::TAILJMPd : X86::TAILJMPd64)).
1327
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1328
JumpTarget.getTargetFlags());
1329
} else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1330
MachineInstrBuilder MIB =
1331
BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1332
? X86::TAILJMPm : X86::TAILJMPm64));
1333
for (unsigned i = 0; i != 5; ++i)
1334
MIB.addOperand(MBBI->getOperand(i));
1335
} else if (RetOpcode == X86::TCRETURNri64) {
1336
BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1337
addReg(JumpTarget.getReg(), RegState::Kill);
1339
BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1340
addReg(JumpTarget.getReg(), RegState::Kill);
1343
MachineInstr *NewMI = prior(MBBI);
1344
for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1345
NewMI->addOperand(MBBI->getOperand(i));
1347
// Delete the pseudo instruction TCRETURN.
1349
} else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1350
(X86FI->getTCReturnAddrDelta() < 0)) {
1351
// Add the return addr area delta back since we are not tail calling.
1352
int delta = -1*X86FI->getTCReturnAddrDelta();
1353
MBBI = prior(MBB.end());
1355
// Check for possible merge with preceeding ADD instruction.
1356
delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1357
emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1361
unsigned X86RegisterInfo::getRARegister() const {
1362
return Is64Bit ? X86::RIP // Should have dwarf #16.
1363
: X86::EIP; // Should have dwarf #8.
1366
unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1367
return hasFP(MF) ? FramePtr : StackPtr;
1371
X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1372
// Calculate amount of bytes used for return address storing
1373
int stackGrowth = (Is64Bit ? -8 : -4);
1375
// Initial state of the frame pointer is esp+stackGrowth.
1376
MachineLocation Dst(MachineLocation::VirtualFP);
1377
MachineLocation Src(StackPtr, stackGrowth);
1378
Moves.push_back(MachineMove(0, Dst, Src));
1380
// Add return address to move list
1381
MachineLocation CSDst(StackPtr, stackGrowth);
1382
MachineLocation CSSrc(getRARegister());
1383
Moves.push_back(MachineMove(0, CSDst, CSSrc));
1386
unsigned X86RegisterInfo::getEHExceptionRegister() const {
1387
llvm_unreachable("What is the exception register");
1391
unsigned X86RegisterInfo::getEHHandlerRegister() const {
1392
llvm_unreachable("What is the exception handler register");
1397
unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1398
switch (VT.getSimpleVT().SimpleTy) {
1399
default: return Reg;
1404
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1406
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1408
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1410
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1416
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1418
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1420
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1422
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1424
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1426
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1428
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1430
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1432
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1434
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1436
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1438
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1440
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1442
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1444
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1446
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1452
default: return Reg;
1453
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1455
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1457
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1459
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1461
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1463
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1465
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1467
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1469
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1471
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1473
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1475
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1477
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1479
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1481
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1483
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1488
default: return Reg;
1489
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1491
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1493
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1495
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1497
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1499
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1501
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1503
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1505
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1507
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1509
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1511
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1513
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1515
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1517
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1519
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1524
default: return Reg;
1525
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1527
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1529
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1531
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1533
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1535
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1537
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1539
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1541
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1543
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1545
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1547
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1549
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1551
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1553
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1555
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1564
#include "X86GenRegisterInfo.inc"
1567
struct MSAH : public MachineFunctionPass {
1569
MSAH() : MachineFunctionPass(ID) {}
1571
virtual bool runOnMachineFunction(MachineFunction &MF) {
1572
const X86TargetMachine *TM =
1573
static_cast<const X86TargetMachine *>(&MF.getTarget());
1574
const X86RegisterInfo *X86RI = TM->getRegisterInfo();
1575
MachineRegisterInfo &RI = MF.getRegInfo();
1576
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1577
unsigned StackAlignment = X86RI->getStackAlignment();
1579
// Be over-conservative: scan over all vreg defs and find whether vector
1580
// registers are used. If yes, there is a possibility that vector register
1581
// will be spilled and thus require dynamic stack realignment.
1582
for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1583
RegNum < RI.getLastVirtReg(); ++RegNum)
1584
if (RI.getRegClass(RegNum)->getAlignment() > StackAlignment) {
1585
FuncInfo->setReserveFP(true);
1593
virtual const char *getPassName() const {
1594
return "X86 Maximal Stack Alignment Check";
1597
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1598
AU.setPreservesCFG();
1599
MachineFunctionPass::getAnalysisUsage(AU);
1607
llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }
added
removed
libclamav/c++/llvm/lib/Target/X86/X86RegisterInfo.cpp
