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  • Committer: Package Import Robot
  • Author(s): Sebastian Dröge
  • Date: 2013-07-30 09:00:15 UTC
  • mfrom: (1.1.16) (7.1.7 experimental)
  • Revision ID: package-import@ubuntu.com-20130730090015-sc1ou2yssu7q5w4e
Tags: 1.1.3-1
* New upstream development snapshot:
  + debian/control:
    - Build depend on GStreamer and gst-plugins-base >= 1.1.3.

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gst-libs/ext/libav/libavcodec/arm/h264cmc_neon.S
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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 */
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#include "asm.S"
 
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#include "libavutil/arm/asm.S"
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/* chroma_mc8(uint8_t *dst, uint8_t *src, int stride, int h, int x, int y) */
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.macro  h264_chroma_mc8 type, codec=h264
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function ff_\type\()_\codec\()_chroma_mc8_neon, export=1
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        push            {r4-r7, lr}
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        ldrd            r4,  [sp, #20]
 
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        ldrd            r4,  r5,  [sp, #20]
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  .ifc \type,avg
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        mov             lr,  r0
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  .endif
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        beq             2f
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        add             r5,  r1,  r2
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        vdup.8          d0,  r4
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        lsl             r4,  r2,  #1
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        vdup.8          d1,  r12
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        vld1.8          {d4, d5}, [r1], r4
 
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        vld1.8          {d4, d5}, [r1], r2
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        vdup.8          d2,  r6
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        vld1.8          {d6, d7}, [r5], r4
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        vdup.8          d3,  r7
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        vext.8          d5,  d4,  d5,  #1
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        vext.8          d7,  d6,  d7,  #1
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1:      pld             [r5]
 
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1:      vld1.8          {d6, d7}, [r1], r2
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        vmull.u8        q8,  d4,  d0
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        vmlal.u8        q8,  d5,  d1
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        vld1.8          {d4, d5}, [r1], r4
 
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        vext.8          d7,  d6,  d7,  #1
 
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        vld1.8          {d4, d5}, [r1], r2
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        vmlal.u8        q8,  d6,  d2
 
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        pld             [r1]
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        vext.8          d5,  d4,  d5,  #1
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        vmlal.u8        q8,  d7,  d3
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        vmull.u8        q9,  d6,  d0
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        vmlal.u8        q9,  d7,  d1
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        vmlal.u8        q9,  d4,  d2
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        vmlal.u8        q9,  d5,  d3
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        vld1.8          {d6, d7}, [r5], r4
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        pld             [r1]
 
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        pld             [r1, r2]
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  .ifc \codec,h264
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        vrshrn.u16      d16, q8,  #6
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        vrshrn.u16      d17, q9,  #6
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        vld1.8          {d21}, [lr,:64], r2
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        vrhadd.u8       q8,  q8,  q10
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  .endif
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        vext.8          d7,  d6,  d7,  #1
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        vst1.8          {d16}, [r0,:64], r2
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        vst1.8          {d17}, [r0,:64], r2
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        bgt             1b
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        beq             4f
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        add             r5,  r1,  r2
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        lsl             r4,  r2,  #1
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        vld1.8          {d4}, [r1], r4
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        vld1.8          {d6}, [r5], r4
 
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        vld1.8          {d4}, [r1], r2
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3:      pld             [r5]
 
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3:      vld1.8          {d6}, [r1], r2
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        vmull.u8        q8,  d4,  d0
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        vmlal.u8        q8,  d6,  d1
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        vld1.8          {d4}, [r1], r4
 
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        vld1.8          {d4}, [r1], r2
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        vmull.u8        q9,  d6,  d0
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        vmlal.u8        q9,  d4,  d1
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        vld1.8          {d6}, [r5], r4
 
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        pld             [r1]
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  .ifc \codec,h264
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        vrshrn.u16      d16, q8,  #6
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        vrshrn.u16      d17, q9,  #6
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        vshrn.u16       d16, q8,  #6
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        vshrn.u16       d17, q9,  #6
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  .endif
 
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        pld             [r1, r2]
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  .ifc \type,avg
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        vld1.8          {d20}, [lr,:64], r2
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        vld1.8          {d21}, [lr,:64], r2
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        vrhadd.u8       q8,  q8,  q10
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  .endif
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        subs            r3,  r3,  #2
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        pld             [r1]
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        vst1.8          {d16}, [r0,:64], r2
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        vst1.8          {d17}, [r0,:64], r2
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        bgt             3b
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        vld1.8          {d6, d7}, [r1], r2
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        vext.8          d5,  d4,  d5,  #1
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        vext.8          d7,  d6,  d7,  #1
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5:      pld             [r1]
 
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        pld             [r1]
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        subs            r3,  r3,  #2
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        vmull.u8        q8,  d4,  d0
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        vmlal.u8        q8,  d5,  d1
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        vld1.8          {d4, d5}, [r1], r2
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        vmull.u8        q9,  d6,  d0
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        vmlal.u8        q9,  d7,  d1
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        pld             [r1]
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        vext.8          d5,  d4,  d5,  #1
 
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        pld             [r1, r2]
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  .ifc \codec,h264
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        vrshrn.u16      d16, q8,  #6
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        vrshrn.u16      d17, q9,  #6
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        vld1.8          {d21}, [lr,:64], r2
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        vrhadd.u8       q8,  q8,  q10
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  .endif
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        vld1.8          {d6, d7}, [r1], r2
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        vext.8          d7,  d6,  d7,  #1
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        vst1.8          {d16}, [r0,:64], r2
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        vst1.8          {d17}, [r0,:64], r2
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        bgt             5b
 
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        bgt             4b
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        pop             {r4-r7, pc}
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endfunc
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.macro  h264_chroma_mc4 type, codec=h264
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function ff_\type\()_\codec\()_chroma_mc4_neon, export=1
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        push            {r4-r7, lr}
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        ldrd            r4,  [sp, #20]
 
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        ldrd            r4,  r5,  [sp, #20]
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  .ifc \type,avg
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        mov             lr,  r0
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  .endif
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        beq             2f
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        add             r5,  r1,  r2
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        vdup.8          d0,  r4
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        lsl             r4,  r2,  #1
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        vdup.8          d1,  r12
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        vld1.8          {d4},     [r1], r4
 
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        vld1.8          {d4},     [r1], r2
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        vdup.8          d2,  r6
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        vld1.8          {d6},     [r5], r4
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        vdup.8          d3,  r7
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        vext.8          d5,  d4,  d5,  #1
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        vext.8          d7,  d6,  d7,  #1
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        vtrn.32         d4,  d5
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        vtrn.32         d6,  d7
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        vtrn.32         d0,  d1
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        vtrn.32         d2,  d3
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1:      pld             [r5]
 
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1:      vld1.8          {d6},     [r1], r2
 
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        vext.8          d7,  d6,  d7,  #1
 
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        vtrn.32         d6,  d7
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        vmull.u8        q8,  d4,  d0
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        vmlal.u8        q8,  d6,  d2
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        vld1.8          {d4},     [r1], r4
 
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        vld1.8          {d4},     [r1], r2
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        vext.8          d5,  d4,  d5,  #1
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        vtrn.32         d4,  d5
 
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        pld             [r1]
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        vmull.u8        q9,  d6,  d0
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        vmlal.u8        q9,  d4,  d2
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        vld1.8          {d6},     [r5], r4
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        vadd.i16        d16, d16, d17
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        vadd.i16        d17, d18, d19
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  .ifc \codec,h264
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        vshrn.u16       d16, q8,  #6
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  .endif
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        subs            r3,  r3,  #2
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        pld             [r1]
 
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        pld             [r1, r2]
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  .ifc \type,avg
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        vld1.32         {d20[0]}, [lr,:32], r2
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        vld1.32         {d20[1]}, [lr,:32], r2
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        vrhadd.u8       d16, d16, d20
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  .endif
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        vext.8          d7,  d6,  d7,  #1
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        vtrn.32         d6,  d7
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        vst1.32         {d16[0]}, [r0,:32], r2
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        vst1.32         {d16[1]}, [r0,:32], r2
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        bgt             1b
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        beq             4f
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        vext.32         d1,  d0,  d1,  #1
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        add             r5,  r1,  r2
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        lsl             r4,  r2,  #1
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        vld1.32         {d4[0]},  [r1], r4
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        vld1.32         {d4[1]},  [r5], r4
 
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        vld1.32         {d4[0]},  [r1], r2
275
252
 
276
 
3:      pld             [r5]
 
253
3:      vld1.32         {d4[1]},  [r1], r2
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        vmull.u8        q8,  d4,  d0
278
 
        vld1.32         {d4[0]},  [r1], r4
 
255
        vld1.32         {d4[0]},  [r1], r2
279
256
        vmull.u8        q9,  d4,  d1
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        vld1.32         {d4[1]},  [r5], r4
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        vadd.i16        d16, d16, d17
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258
        vadd.i16        d17, d18, d19
 
259
        pld             [r1]
283
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  .ifc \codec,h264
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        vrshrn.u16      d16, q8,  #6
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  .else
292
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        vrhadd.u8       d16, d16, d20
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270
  .endif
294
271
        subs            r3,  r3,  #2
295
 
        pld             [r1]
 
272
        pld             [r1, r2]
296
273
        vst1.32         {d16[0]}, [r0,:32], r2
297
274
        vst1.32         {d16[1]}, [r0,:32], r2
298
275
        bgt             3b
305
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        vext.8          d7,  d6,  d7,  #1
306
283
        vtrn.32         d4,  d5
307
284
        vtrn.32         d6,  d7
308
 
 
309
 
5:      vmull.u8        q8,  d4,  d0
 
285
        vmull.u8        q8,  d4,  d0
310
286
        vmull.u8        q9,  d6,  d0
311
287
        subs            r3,  r3,  #2
312
 
        vld1.8          {d4},     [r1], r2
313
 
        vext.8          d5,  d4,  d5,  #1
314
 
        vtrn.32         d4,  d5
315
288
        vadd.i16        d16, d16, d17
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        vadd.i16        d17, d18, d19
317
290
        pld             [r1]
326
299
        vld1.32         {d20[1]}, [lr,:32], r2
327
300
        vrhadd.u8       d16, d16, d20
328
301
  .endif
329
 
        vld1.8          {d6},     [r1], r2
330
 
        vext.8          d7,  d6,  d7,  #1
331
 
        vtrn.32         d6,  d7
332
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        pld             [r1]
333
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        vst1.32         {d16[0]}, [r0,:32], r2
334
304
        vst1.32         {d16[1]}, [r0,:32], r2
335
 
        bgt             5b
 
305
        bgt             4b
336
306
 
337
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        pop             {r4-r7, pc}
338
308
endfunc