1
Amiga 4-joystick parport extension
2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
6
(3) - Down1 (7) - Down2
7
(4) - Left1 (8) - Left2
8
(5) - Right1 (9) - Right2
9
(13) - Fire1 (11) - Fire2
10
(18) - Gnd1 (18) - Gnd2
12
Amiga digital joystick pinout
13
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
36
Amiga analog joystick pinout
37
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
60
-------------------------------------------------------------------------------
62
NAME rev ADDR type chip Description
63
JOY0DAT 00A R Denise Joystick-mouse 0 data (left vert, horiz)
64
JOY1DAT 00C R Denise Joystick-mouse 1 data (right vert,horiz)
66
These addresses each read a 16 bit register. These in turn
67
are loaded from the MDAT serial stream and are clocked in on
68
the rising edge of SCLK. MLD output is used to parallel load
69
the external parallel-to-serial converter.This in turn is
70
loaded with the 4 quadrature inputs from each of two game
71
controller ports (8 total) plus 8 miscellaneous control bits
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which are new for LISA and can be read in upper 8 bits of
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Register bits are as follows:
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Mouse counter usage (pins 1,3 =Yclock, pins 2,4 =Xclock)
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BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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JOY0DAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
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JOY1DAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
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0=LEFT CONTROLLER PAIR, 1=RIGHT CONTROLLER PAIR.
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(4 counters total).The bit usage for both left and right
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addresses is shown below. Each 6 bit counter (Y7-Y2,X7-X2) is
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clocked by 2 of the signals input from the mouse serial
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stream. Starting with first bit recived:
87
+-------------------+-----------------------------------------+
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| Serial | Bit Name | Description |
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+--------+----------+-----------------------------------------+
90
| 0 | M0H | JOY0DAT Horizontal Clock |
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| 1 | M0HQ | JOY0DAT Horizontal Clock (quadrature) |
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| 2 | M0V | JOY0DAT Vertical Clock |
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| 3 | M0VQ | JOY0DAT Vertical Clock (quadrature) |
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| 4 | M1V | JOY1DAT Horizontall Clock |
95
| 5 | M1VQ | JOY1DAT Horizontall Clock (quadrature) |
96
| 6 | M1V | JOY1DAT Vertical Clock |
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| 7 | M1VQ | JOY1DAT Vertical Clock (quadrature) |
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+--------+----------+-----------------------------------------+
100
Bits 1 and 0 of each counter (Y1-Y0,X1-X0) may be
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read to determine the state of the related input signal pair.
102
This allows these pins to double as joystick switch inputs.
103
Joystick switch closures can be deciphered as follows:
105
+------------+------+---------------------------------+
106
| Directions | Pin# | Counter bits |
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+------------+------+---------------------------------+
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| Forward | 1 | Y1 xor Y0 (BIT#09 xor BIT#08) |
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| Back | 2 | X1 xor X0 (BIT#01 xor BIT#00) |
112
+------------+------+---------------------------------+
114
-------------------------------------------------------------------------------
116
NAME rev ADDR type chip Description
117
JOYTEST 036 W Denise Write to all 4 joystick-mouse counters at once.
119
Mouse counter write test data:
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BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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JOYxDAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx
122
JOYxDAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx
124
-------------------------------------------------------------------------------
126
NAME rev ADDR type chip Description
127
POT0DAT h 012 R Paula Pot counter data left pair (vert, horiz)
128
POT1DAT h 014 R Paula Pot counter data right pair (vert,horiz)
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These addresses each read a pair of 8 bit pot counters.
131
(4 counters total). The bit assignment for both
132
addresses is shown below. The counters are stopped by signals
133
from 2 controller connectors (left-right) with 2 pins each.
135
BIT# 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
136
RIGHT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
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LEFT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
139
+--------------------------+-------+
140
| CONNECTORS | PAULA |
141
+-------+------+-----+-----+-------+
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| Loc. | Dir. | Sym | pin | pin |
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+-------+------+-----+-----+-------+
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| RIGHT | Y | RX | 9 | 33 |
145
| RIGHT | X | RX | 5 | 32 |
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| LEFT | Y | LY | 9 | 36 |
147
| LEFT | X | LX | 5 | 35 |
148
+-------+------+-----+-----+-------+
150
With normal (NTSC or PAL) horiz. line rate, the pots will
151
give a full scale (FF) reading with about 500kohms in one
152
frame time. With proportionally faster horiz line times,
153
the counters will count proportionally faster.
154
This should be noted when doing variable beam displays.
156
-------------------------------------------------------------------------------
158
NAME rev ADDR type chip Description
159
POTGO 034 W Paula Pot port (4 bit) bi-direction and data, and pot counter start.
161
-------------------------------------------------------------------------------
163
NAME rev ADDR type chip Description
164
POTINP 016 R Paula Pot pin data read
166
This register controls a 4 bit bi-direction I/O port
167
that shares the same 4 pins as the 4 pot counters above.
169
+-------+----------+---------------------------------------------+
170
| BIT# | FUNCTION | DESCRIPTION |
171
+-------+----------+---------------------------------------------+
172
| 15 | OUTRY | Output enable for Paula pin 33 |
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| 14 | DATRY | I/O data Paula pin 33 |
174
| 13 | OUTRX | Output enable for Paula pin 32 |
175
| 12 | DATRX | I/O data Paula pin 32 |
176
| 11 | OUTLY | Out put enable for Paula pin 36 |
177
| 10 | DATLY | I/O data Paula pin 36 |
178
| 09 | OUTLX | Output enable for Paula pin 35 |
179
| 08 | DATLX | I/O data Paula pin 35 |
180
| 07-01 | X | Not used |
181
| 00 | START | Start pots (dump capacitors,start counters) |
182
+-------+----------+---------------------------------------------+
184
-------------------------------------------------------------------------------
added
removed
linux/Documentation/input/amijoy.txt
