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/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*-
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* vim: set ts=8 sw=4 et tw=79:
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* ***** BEGIN LICENSE BLOCK *****
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* Copyright (C) 2008 Apple Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ***** END LICENSE BLOCK ***** */
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#ifndef MacroAssemblerX86Common_h
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#define MacroAssemblerX86Common_h
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#include "assembler/wtf/Platform.h"
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#include "X86Assembler.h"
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#include "AbstractMacroAssembler.h"
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class MacroAssemblerX86Common : public AbstractMacroAssembler<X86Assembler> {
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static const int DoubleConditionBitInvert = 0x10;
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static const int DoubleConditionBitSpecial = 0x20;
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static const int DoubleConditionBits = DoubleConditionBitInvert | DoubleConditionBitSpecial;
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static const X86Registers::RegisterID scratchRegister = X86Registers::r11;
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Equal = X86Assembler::ConditionE,
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NotEqual = X86Assembler::ConditionNE,
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Above = X86Assembler::ConditionA,
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AboveOrEqual = X86Assembler::ConditionAE,
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Below = X86Assembler::ConditionB,
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BelowOrEqual = X86Assembler::ConditionBE,
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GreaterThan = X86Assembler::ConditionG,
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GreaterThanOrEqual = X86Assembler::ConditionGE,
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LessThan = X86Assembler::ConditionL,
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LessThanOrEqual = X86Assembler::ConditionLE,
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Overflow = X86Assembler::ConditionO,
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Signed = X86Assembler::ConditionS,
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Zero = X86Assembler::ConditionE,
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NonZero = X86Assembler::ConditionNE
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enum DoubleCondition {
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// These conditions will only evaluate to true if the comparison is ordered - i.e. neither operand is NaN.
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DoubleEqual = X86Assembler::ConditionE | DoubleConditionBitSpecial,
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DoubleNotEqual = X86Assembler::ConditionNE,
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DoubleGreaterThan = X86Assembler::ConditionA,
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DoubleGreaterThanOrEqual = X86Assembler::ConditionAE,
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DoubleLessThan = X86Assembler::ConditionA | DoubleConditionBitInvert,
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DoubleLessThanOrEqual = X86Assembler::ConditionAE | DoubleConditionBitInvert,
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// If either operand is NaN, these conditions always evaluate to true.
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DoubleEqualOrUnordered = X86Assembler::ConditionE,
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DoubleNotEqualOrUnordered = X86Assembler::ConditionNE | DoubleConditionBitSpecial,
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DoubleGreaterThanOrUnordered = X86Assembler::ConditionB | DoubleConditionBitInvert,
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DoubleGreaterThanOrEqualOrUnordered = X86Assembler::ConditionBE | DoubleConditionBitInvert,
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DoubleLessThanOrUnordered = X86Assembler::ConditionB,
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DoubleLessThanOrEqualOrUnordered = X86Assembler::ConditionBE
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static void staticAsserts() {
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!((X86Assembler::ConditionE | X86Assembler::ConditionNE | X86Assembler::ConditionA | X86Assembler::ConditionAE | X86Assembler::ConditionB | X86Assembler::ConditionBE) & DoubleConditionBits),
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DoubleConditionBits_should_not_interfere_with_X86Assembler_Condition_codes);
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static const RegisterID stackPointerRegister = X86Registers::esp;
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static inline bool CanUse8Bit(RegisterID reg) {
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return !!((1 << reg) & ~((1 << X86Registers::esp) |
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(1 << X86Registers::edi) |
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(1 << X86Registers::esi) |
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(1 << X86Registers::ebp)));
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// Integer arithmetic operations:
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// Operations are typically two operand - operation(source, srcDst)
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// For many operations the source may be an Imm32, the srcDst operand
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// may often be a memory location (explictly described using an Address
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void add32(RegisterID src, RegisterID dest)
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m_assembler.addl_rr(src, dest);
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void add32(TrustedImm32 imm, Address address)
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m_assembler.addl_im(imm.m_value, address.offset, address.base);
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void add32(TrustedImm32 imm, RegisterID dest)
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m_assembler.addl_ir(imm.m_value, dest);
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void add32(Address src, RegisterID dest)
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m_assembler.addl_mr(src.offset, src.base, dest);
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void add32(RegisterID src, Address dest)
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m_assembler.addl_rm(src, dest.offset, dest.base);
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void and32(RegisterID src, RegisterID dest)
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m_assembler.andl_rr(src, dest);
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void and32(Imm32 imm, RegisterID dest)
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m_assembler.andl_ir(imm.m_value, dest);
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void and32(RegisterID src, Address dest)
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m_assembler.andl_rm(src, dest.offset, dest.base);
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void and32(Address src, RegisterID dest)
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m_assembler.andl_mr(src.offset, src.base, dest);
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void and32(Imm32 imm, Address address)
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m_assembler.andl_im(imm.m_value, address.offset, address.base);
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void lshift32(Imm32 imm, RegisterID dest)
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m_assembler.shll_i8r(imm.m_value, dest);
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void lshift32(RegisterID shift_amount, RegisterID dest)
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// On x86 we can only shift by ecx; if asked to shift by another register we'll
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// need rejig the shift amount into ecx first, and restore the registers afterwards.
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if (shift_amount != X86Registers::ecx) {
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swap(shift_amount, X86Registers::ecx);
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// E.g. transform "shll %eax, %eax" -> "xchgl %eax, %ecx; shll %ecx, %ecx; xchgl %eax, %ecx"
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if (dest == shift_amount)
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m_assembler.shll_CLr(X86Registers::ecx);
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// E.g. transform "shll %eax, %ecx" -> "xchgl %eax, %ecx; shll %ecx, %eax; xchgl %eax, %ecx"
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else if (dest == X86Registers::ecx)
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m_assembler.shll_CLr(shift_amount);
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// E.g. transform "shll %eax, %ebx" -> "xchgl %eax, %ecx; shll %ecx, %ebx; xchgl %eax, %ecx"
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m_assembler.shll_CLr(dest);
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swap(shift_amount, X86Registers::ecx);
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m_assembler.shll_CLr(dest);
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void mul32(RegisterID src, RegisterID dest)
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m_assembler.imull_rr(src, dest);
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void mul32(Address src, RegisterID dest)
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m_assembler.imull_mr(src.offset, src.base, dest);
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void mul32(Imm32 imm, RegisterID src, RegisterID dest)
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m_assembler.imull_i32r(src, imm.m_value, dest);
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void idiv(RegisterID reg)
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m_assembler.idivl_r(reg);
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void neg32(RegisterID srcDest)
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m_assembler.negl_r(srcDest);
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void neg32(Address srcDest)
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m_assembler.negl_m(srcDest.offset, srcDest.base);
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void not32(RegisterID srcDest)
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m_assembler.notl_r(srcDest);
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void not32(Address srcDest)
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m_assembler.notl_m(srcDest.offset, srcDest.base);
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void or32(RegisterID src, RegisterID dest)
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m_assembler.orl_rr(src, dest);
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void or32(TrustedImm32 imm, RegisterID dest)
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m_assembler.orl_ir(imm.m_value, dest);
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void or32(RegisterID src, Address dest)
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m_assembler.orl_rm(src, dest.offset, dest.base);
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void or32(Address src, RegisterID dest)
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m_assembler.orl_mr(src.offset, src.base, dest);
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void or32(TrustedImm32 imm, Address address)
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m_assembler.orl_im(imm.m_value, address.offset, address.base);
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void rshift32(RegisterID shift_amount, RegisterID dest)
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// On x86 we can only shift by ecx; if asked to shift by another register we'll
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// need rejig the shift amount into ecx first, and restore the registers afterwards.
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if (shift_amount != X86Registers::ecx) {
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swap(shift_amount, X86Registers::ecx);
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// E.g. transform "shll %eax, %eax" -> "xchgl %eax, %ecx; shll %ecx, %ecx; xchgl %eax, %ecx"
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if (dest == shift_amount)
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m_assembler.sarl_CLr(X86Registers::ecx);
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// E.g. transform "shll %eax, %ecx" -> "xchgl %eax, %ecx; shll %ecx, %eax; xchgl %eax, %ecx"
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else if (dest == X86Registers::ecx)
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m_assembler.sarl_CLr(shift_amount);
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// E.g. transform "shll %eax, %ebx" -> "xchgl %eax, %ecx; shll %ecx, %ebx; xchgl %eax, %ecx"
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m_assembler.sarl_CLr(dest);
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swap(shift_amount, X86Registers::ecx);
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m_assembler.sarl_CLr(dest);
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void rshift32(Imm32 imm, RegisterID dest)
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m_assembler.sarl_i8r(imm.m_value, dest);
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void urshift32(RegisterID shift_amount, RegisterID dest)
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// On x86 we can only shift by ecx; if asked to shift by another register we'll
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// need rejig the shift amount into ecx first, and restore the registers afterwards.
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if (shift_amount != X86Registers::ecx) {
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swap(shift_amount, X86Registers::ecx);
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// E.g. transform "shrl %eax, %eax" -> "xchgl %eax, %ecx; shrl %ecx, %ecx; xchgl %eax, %ecx"
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if (dest == shift_amount)
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m_assembler.shrl_CLr(X86Registers::ecx);
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// E.g. transform "shrl %eax, %ecx" -> "xchgl %eax, %ecx; shrl %ecx, %eax; xchgl %eax, %ecx"
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else if (dest == X86Registers::ecx)
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m_assembler.shrl_CLr(shift_amount);
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// E.g. transform "shrl %eax, %ebx" -> "xchgl %eax, %ecx; shrl %ecx, %ebx; xchgl %eax, %ecx"
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m_assembler.shrl_CLr(dest);
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swap(shift_amount, X86Registers::ecx);
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m_assembler.shrl_CLr(dest);
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void urshift32(Imm32 imm, RegisterID dest)
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m_assembler.shrl_i8r(imm.m_value, dest);
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void sub32(RegisterID src, RegisterID dest)
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m_assembler.subl_rr(src, dest);
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void sub32(TrustedImm32 imm, RegisterID dest)
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m_assembler.subl_ir(imm.m_value, dest);
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void sub32(TrustedImm32 imm, Address address)
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m_assembler.subl_im(imm.m_value, address.offset, address.base);
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void sub32(Address src, RegisterID dest)
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m_assembler.subl_mr(src.offset, src.base, dest);
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void sub32(RegisterID src, Address dest)
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m_assembler.subl_rm(src, dest.offset, dest.base);
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void xor32(RegisterID src, RegisterID dest)
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m_assembler.xorl_rr(src, dest);
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void xor32(TrustedImm32 imm, Address dest)
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m_assembler.xorl_im(imm.m_value, dest.offset, dest.base);
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void xor32(TrustedImm32 imm, RegisterID dest)
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m_assembler.xorl_ir(imm.m_value, dest);
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void xor32(RegisterID src, Address dest)
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m_assembler.xorl_rm(src, dest.offset, dest.base);
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void xor32(Address src, RegisterID dest)
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m_assembler.xorl_mr(src.offset, src.base, dest);
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void sqrtDouble(FPRegisterID src, FPRegisterID dst)
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m_assembler.sqrtsd_rr(src, dst);
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// Memory access operations:
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// Loads are of the form load(address, destination) and stores of the form
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// store(source, address). The source for a store may be an Imm32. Address
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// operand objects to loads and store will be implicitly constructed if a
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// register is passed.
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void load32(ImplicitAddress address, RegisterID dest)
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m_assembler.movl_mr(address.offset, address.base, dest);
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void load32(BaseIndex address, RegisterID dest)
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m_assembler.movl_mr(address.offset, address.base, address.index, address.scale, dest);
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void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)
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load32(address, dest);
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DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
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m_assembler.movl_mr_disp32(address.offset, address.base, dest);
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return DataLabel32(this);
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void store8(RegisterID src, Address address)
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m_assembler.movb_rm(src, address.offset, address.base);
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void store8(RegisterID src, BaseIndex address)
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m_assembler.movb_rm(src, address.offset, address.base, address.index, address.scale);
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void store16(RegisterID src, Address address)
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m_assembler.movw_rm(src, address.offset, address.base);
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void store16(RegisterID src, BaseIndex address)
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m_assembler.movw_rm(src, address.offset, address.base, address.index, address.scale);
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void load8ZeroExtend(BaseIndex address, RegisterID dest)
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m_assembler.movzbl_mr(address.offset, address.base, address.index, address.scale, dest);
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void load8ZeroExtend(Address address, RegisterID dest)
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m_assembler.movzbl_mr(address.offset, address.base, dest);
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void load8SignExtend(BaseIndex address, RegisterID dest)
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m_assembler.movxbl_mr(address.offset, address.base, address.index, address.scale, dest);
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void load8SignExtend(Address address, RegisterID dest)
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m_assembler.movxbl_mr(address.offset, address.base, dest);
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void load16SignExtend(BaseIndex address, RegisterID dest)
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m_assembler.movxwl_mr(address.offset, address.base, address.index, address.scale, dest);
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void load16SignExtend(Address address, RegisterID dest)
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m_assembler.movxwl_mr(address.offset, address.base, dest);
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void load16(BaseIndex address, RegisterID dest)
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m_assembler.movzwl_mr(address.offset, address.base, address.index, address.scale, dest);
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void load16(Address address, RegisterID dest)
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m_assembler.movzwl_mr(address.offset, address.base, dest);
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DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
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m_assembler.movl_rm_disp32(src, address.offset, address.base);
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return DataLabel32(this);
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void store32(RegisterID src, ImplicitAddress address)
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m_assembler.movl_rm(src, address.offset, address.base);
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void store32(RegisterID src, BaseIndex address)
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m_assembler.movl_rm(src, address.offset, address.base, address.index, address.scale);
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void store32(TrustedImm32 imm, BaseIndex address)
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m_assembler.movl_i32m(imm.m_value, address.offset, address.base, address.index, address.scale);
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void store16(Imm32 imm, BaseIndex address)
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m_assembler.movw_i16m(imm.m_value, address.offset, address.base, address.index, address.scale);
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void store8(Imm32 imm, BaseIndex address)
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m_assembler.movb_i8m(imm.m_value, address.offset, address.base, address.index, address.scale);
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void store32(TrustedImm32 imm, ImplicitAddress address)
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m_assembler.movl_i32m(imm.m_value, address.offset, address.base);
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void store16(Imm32 imm, ImplicitAddress address)
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m_assembler.movw_i16m(imm.m_value, address.offset, address.base);
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void store8(Imm32 imm, ImplicitAddress address)
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m_assembler.movb_i8m(imm.m_value, address.offset, address.base);
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// Floating-point operation:
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// Presently only supports SSE, not x87 floating point.
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void moveDouble(FPRegisterID src, FPRegisterID dest)
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ASSERT(isSSE2Present());
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m_assembler.movsd_rr(src, dest);
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void loadFloat(ImplicitAddress address, FPRegisterID dest)
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ASSERT(isSSE2Present());
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m_assembler.movss_mr(address.offset, address.base, dest);
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m_assembler.cvtss2sd_rr(dest, dest);
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void loadFloat(BaseIndex address, FPRegisterID dest)
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ASSERT(isSSE2Present());
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m_assembler.movss_mr(address.offset, address.base, address.index, address.scale, dest);
525
m_assembler.cvtss2sd_rr(dest, dest);
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void convertDoubleToFloat(FPRegisterID src, FPRegisterID dest)
530
ASSERT(isSSE2Present());
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m_assembler.cvtsd2ss_rr(src, dest);
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void loadDouble(ImplicitAddress address, FPRegisterID dest)
536
ASSERT(isSSE2Present());
537
m_assembler.movsd_mr(address.offset, address.base, dest);
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void loadDouble(BaseIndex address, FPRegisterID dest)
542
ASSERT(isSSE2Present());
543
m_assembler.movsd_mr(address.offset, address.base, address.index, address.scale, dest);
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void storeFloat(ImmDouble imm, Address address)
553
store32(Imm32(u.u32), address);
556
void storeFloat(ImmDouble imm, BaseIndex address)
563
store32(Imm32(u.u32), address);
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void storeDouble(FPRegisterID src, ImplicitAddress address)
568
ASSERT(isSSE2Present());
569
m_assembler.movsd_rm(src, address.offset, address.base);
572
void storeFloat(FPRegisterID src, ImplicitAddress address)
574
ASSERT(isSSE2Present());
575
m_assembler.movss_rm(src, address.offset, address.base);
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void storeDouble(FPRegisterID src, BaseIndex address)
580
ASSERT(isSSE2Present());
581
m_assembler.movsd_rm(src, address.offset, address.base, address.index, address.scale);
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void storeFloat(FPRegisterID src, BaseIndex address)
586
ASSERT(isSSE2Present());
587
m_assembler.movss_rm(src, address.offset, address.base, address.index, address.scale);
590
void addDouble(FPRegisterID src, FPRegisterID dest)
592
ASSERT(isSSE2Present());
593
m_assembler.addsd_rr(src, dest);
596
void addDouble(Address src, FPRegisterID dest)
598
ASSERT(isSSE2Present());
599
m_assembler.addsd_mr(src.offset, src.base, dest);
602
void divDouble(FPRegisterID src, FPRegisterID dest)
604
ASSERT(isSSE2Present());
605
m_assembler.divsd_rr(src, dest);
608
void divDouble(Address src, FPRegisterID dest)
610
ASSERT(isSSE2Present());
611
m_assembler.divsd_mr(src.offset, src.base, dest);
614
void subDouble(FPRegisterID src, FPRegisterID dest)
616
ASSERT(isSSE2Present());
617
m_assembler.subsd_rr(src, dest);
620
void subDouble(Address src, FPRegisterID dest)
622
ASSERT(isSSE2Present());
623
m_assembler.subsd_mr(src.offset, src.base, dest);
626
void mulDouble(FPRegisterID src, FPRegisterID dest)
628
ASSERT(isSSE2Present());
629
m_assembler.mulsd_rr(src, dest);
632
void mulDouble(Address src, FPRegisterID dest)
634
ASSERT(isSSE2Present());
635
m_assembler.mulsd_mr(src.offset, src.base, dest);
638
void xorDouble(FPRegisterID src, FPRegisterID dest)
640
ASSERT(isSSE2Present());
641
m_assembler.xorpd_rr(src, dest);
644
void andDouble(FPRegisterID src, FPRegisterID dest)
646
ASSERT(isSSE2Present());
647
m_assembler.andpd_rr(src, dest);
650
void absDouble(FPRegisterID src, FPRegisterID dest)
652
ASSERT(isSSE2Present());
653
/* Compile abs(x) as x & -x. */
655
subDouble(src, dest);
656
andDouble(src, dest);
659
void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
661
ASSERT(isSSE2Present());
662
m_assembler.cvtsi2sd_rr(src, dest);
665
void convertInt32ToDouble(Address src, FPRegisterID dest)
667
ASSERT(isSSE2Present());
668
m_assembler.cvtsi2sd_mr(src.offset, src.base, dest);
671
Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
673
ASSERT(isSSE2Present());
675
if (cond & DoubleConditionBitInvert)
676
m_assembler.ucomisd_rr(left, right);
678
m_assembler.ucomisd_rr(right, left);
680
if (cond == DoubleEqual) {
681
Jump isUnordered(m_assembler.jp());
682
Jump result = Jump(m_assembler.je());
683
isUnordered.link(this);
685
} else if (cond == DoubleNotEqualOrUnordered) {
686
Jump isUnordered(m_assembler.jp());
687
Jump isEqual(m_assembler.je());
688
isUnordered.link(this);
689
Jump result = jump();
694
ASSERT(!(cond & DoubleConditionBitSpecial));
695
return Jump(m_assembler.jCC(static_cast<X86Assembler::Condition>(cond & ~DoubleConditionBits)));
698
// Truncates 'src' to an integer, and places the resulting 'dest'.
699
// If the result is not representable as a 32 bit value, branch.
700
// May also branch for some values that are representable in 32 bits
701
// (specifically, in this case, INT_MIN).
702
Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest)
704
ASSERT(isSSE2Present());
705
m_assembler.cvttsd2si_rr(src, dest);
706
return branch32(Equal, dest, Imm32(0x80000000));
709
// Convert 'src' to an integer, and places the resulting 'dest'.
710
// If the result is not representable as a 32 bit value, branch.
711
// May also branch for some values that are representable in 32 bits
712
// (specifically, in this case, 0).
713
void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp)
715
ASSERT(isSSE2Present());
716
ASSERT(src != fpTemp);
717
m_assembler.cvttsd2si_rr(src, dest);
719
// If the result is zero, it might have been -0.0, and the double comparison won't catch this!
720
failureCases.append(branchTest32(Zero, dest));
722
// Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.
723
convertInt32ToDouble(dest, fpTemp);
724
m_assembler.ucomisd_rr(fpTemp, src);
725
failureCases.append(m_assembler.jp());
726
failureCases.append(m_assembler.jne());
729
void zeroDouble(FPRegisterID srcDest)
731
ASSERT(isSSE2Present());
732
m_assembler.xorpd_rr(srcDest, srcDest);
736
// Stack manipulation operations:
738
// The ABI is assumed to provide a stack abstraction to memory,
739
// containing machine word sized units of data. Push and pop
740
// operations add and remove a single register sized unit of data
741
// to or from the stack. Peek and poke operations read or write
742
// values on the stack, without moving the current stack position.
744
void pop(RegisterID dest)
746
m_assembler.pop_r(dest);
749
void push(RegisterID src)
751
m_assembler.push_r(src);
754
void push(Address address)
756
m_assembler.push_m(address.offset, address.base);
761
m_assembler.push_i32(imm.m_value);
765
// Register move operations:
767
// Move values in registers.
769
void move(TrustedImm32 imm, RegisterID dest)
771
// Note: on 64-bit the Imm32 value is zero extended into the register, it
772
// may be useful to have a separate version that sign extends the value?
774
m_assembler.xorl_rr(dest, dest);
776
m_assembler.movl_i32r(imm.m_value, dest);
780
void move(RegisterID src, RegisterID dest)
782
// Note: on 64-bit this is is a full register move; perhaps it would be
783
// useful to have separate move32 & movePtr, with move32 zero extending?
785
m_assembler.movq_rr(src, dest);
788
void move(TrustedImmPtr imm, RegisterID dest)
790
m_assembler.movq_i64r(imm.asIntptr(), dest);
793
void swap(RegisterID reg1, RegisterID reg2)
795
// XCHG is extremely slow. Don't use XCHG.
797
m_assembler.movq_rr(reg1, scratchRegister);
798
m_assembler.movq_rr(reg2, reg1);
799
m_assembler.movq_rr(scratchRegister, reg2);
803
void signExtend32ToPtr(RegisterID src, RegisterID dest)
805
m_assembler.movsxd_rr(src, dest);
808
void zeroExtend32ToPtr(RegisterID src, RegisterID dest)
810
m_assembler.movl_rr(src, dest);
813
void move(RegisterID src, RegisterID dest)
816
m_assembler.movl_rr(src, dest);
819
void move(TrustedImmPtr imm, RegisterID dest)
821
m_assembler.movl_i32r(imm.asIntptr(), dest);
824
void swap(RegisterID reg1, RegisterID reg2)
827
m_assembler.xchgl_rr(reg1, reg2);
830
void signExtend32ToPtr(RegisterID src, RegisterID dest)
835
void zeroExtend32ToPtr(RegisterID src, RegisterID dest)
842
// Forwards / external control flow operations:
844
// This set of jump and conditional branch operations return a Jump
845
// object which may linked at a later point, allow forwards jump,
846
// or jumps that will require external linkage (after the code has been
849
// For branches, signed <, >, <= and >= are denoted as l, g, le, and ge
850
// respecitvely, for unsigned comparisons the names b, a, be, and ae are
851
// used (representing the names 'below' and 'above').
853
// Operands to the comparision are provided in the expected order, e.g.
854
// jle32(reg1, Imm32(5)) will branch if the value held in reg1, when
855
// treated as a signed 32bit value, is less than or equal to 5.
857
// jz and jnz test whether the first operand is equal to zero, and take
858
// an optional second operand of a mask under which to perform the test.
861
Jump branch8(Condition cond, Address left, Imm32 right)
863
m_assembler.cmpb_im(right.m_value, left.offset, left.base);
864
return Jump(m_assembler.jCC(x86Condition(cond)));
867
Jump branch32(Condition cond, RegisterID left, RegisterID right)
869
m_assembler.cmpl_rr(right, left);
870
return Jump(m_assembler.jCC(x86Condition(cond)));
873
Jump branch32(Condition cond, RegisterID left, TrustedImm32 right)
875
if (((cond == Equal) || (cond == NotEqual)) && !right.m_value)
876
m_assembler.testl_rr(left, left);
878
m_assembler.cmpl_ir(right.m_value, left);
879
return Jump(m_assembler.jCC(x86Condition(cond)));
882
// Branch based on a 32-bit comparison, forcing the size of the
883
// immediate operand to 32 bits in the native code stream to ensure that
884
// the length of code emitted by this instruction is consistent.
885
Jump branch32FixedLength(Condition cond, RegisterID left, TrustedImm32 right)
887
m_assembler.cmpl_ir_force32(right.m_value, left);
888
return Jump(m_assembler.jCC(x86Condition(cond)));
891
// Branch and record a label after the comparison.
892
Jump branch32WithPatch(Condition cond, RegisterID left, TrustedImm32 right, DataLabel32 &dataLabel)
894
// Always use cmpl, since the value is to be patched.
895
m_assembler.cmpl_ir_force32(right.m_value, left);
896
dataLabel = DataLabel32(this);
897
return Jump(m_assembler.jCC(x86Condition(cond)));
900
Jump branch32WithPatch(Condition cond, Address left, TrustedImm32 right, DataLabel32 &dataLabel)
902
m_assembler.cmpl_im_force32(right.m_value, left.offset, left.base);
903
dataLabel = DataLabel32(this);
904
return Jump(m_assembler.jCC(x86Condition(cond)));
907
Jump branch32(Condition cond, RegisterID left, Address right)
909
m_assembler.cmpl_mr(right.offset, right.base, left);
910
return Jump(m_assembler.jCC(x86Condition(cond)));
913
Jump branch32(Condition cond, Address left, RegisterID right)
915
m_assembler.cmpl_rm(right, left.offset, left.base);
916
return Jump(m_assembler.jCC(x86Condition(cond)));
919
Jump branch32(Condition cond, Address left, TrustedImm32 right)
921
m_assembler.cmpl_im(right.m_value, left.offset, left.base);
922
return Jump(m_assembler.jCC(x86Condition(cond)));
925
Jump branch32(Condition cond, BaseIndex left, TrustedImm32 right)
927
m_assembler.cmpl_im(right.m_value, left.offset, left.base, left.index, left.scale);
928
return Jump(m_assembler.jCC(x86Condition(cond)));
931
Jump branch32WithUnalignedHalfWords(Condition cond, BaseIndex left, TrustedImm32 right)
933
return branch32(cond, left, right);
936
Jump branch16(Condition cond, BaseIndex left, RegisterID right)
938
m_assembler.cmpw_rm(right, left.offset, left.base, left.index, left.scale);
939
return Jump(m_assembler.jCC(x86Condition(cond)));
942
Jump branch16(Condition cond, BaseIndex left, Imm32 right)
944
ASSERT(!(right.m_value & 0xFFFF0000));
946
m_assembler.cmpw_im(right.m_value, left.offset, left.base, left.index, left.scale);
947
return Jump(m_assembler.jCC(x86Condition(cond)));
950
Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask)
952
ASSERT((cond == Zero) || (cond == NonZero));
953
m_assembler.testl_rr(reg, mask);
954
return Jump(m_assembler.jCC(x86Condition(cond)));
957
Jump branchTest32(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1))
959
ASSERT((cond == Zero) || (cond == NonZero));
960
// if we are only interested in the low seven bits, this can be tested with a testb
961
if (mask.m_value == -1)
962
m_assembler.testl_rr(reg, reg);
963
else if (CanUse8Bit(reg) && (mask.m_value & ~0x7f) == 0)
964
m_assembler.testb_i8r(mask.m_value, reg);
966
m_assembler.testl_i32r(mask.m_value, reg);
967
return Jump(m_assembler.jCC(x86Condition(cond)));
970
Jump branchTest32(Condition cond, Address address, Imm32 mask = Imm32(-1))
972
ASSERT((cond == Zero) || (cond == NonZero));
973
if (mask.m_value == -1)
974
m_assembler.cmpl_im(0, address.offset, address.base);
976
m_assembler.testl_i32m(mask.m_value, address.offset, address.base);
977
return Jump(m_assembler.jCC(x86Condition(cond)));
980
Jump branchTest32(Condition cond, BaseIndex address, Imm32 mask = Imm32(-1))
982
ASSERT((cond == Zero) || (cond == NonZero));
983
if (mask.m_value == -1)
984
m_assembler.cmpl_im(0, address.offset, address.base, address.index, address.scale);
986
m_assembler.testl_i32m(mask.m_value, address.offset, address.base, address.index, address.scale);
987
return Jump(m_assembler.jCC(x86Condition(cond)));
990
Jump branchTest8(Condition cond, Address address, Imm32 mask = Imm32(-1))
992
ASSERT((cond == Zero) || (cond == NonZero));
993
if (mask.m_value == -1)
994
m_assembler.cmpb_im(0, address.offset, address.base);
996
m_assembler.testb_im(mask.m_value, address.offset, address.base);
997
return Jump(m_assembler.jCC(x86Condition(cond)));
1000
Jump branchTest8(Condition cond, BaseIndex address, Imm32 mask = Imm32(-1))
1002
ASSERT((cond == Zero) || (cond == NonZero));
1003
if (mask.m_value == -1)
1004
m_assembler.cmpb_im(0, address.offset, address.base, address.index, address.scale);
1006
m_assembler.testb_im(mask.m_value, address.offset, address.base, address.index, address.scale);
1007
return Jump(m_assembler.jCC(x86Condition(cond)));
1012
return Jump(m_assembler.jmp());
1015
void jump(RegisterID target)
1017
m_assembler.jmp_r(target);
1020
// Address is a memory location containing the address to jump to
1021
void jump(Address address)
1023
m_assembler.jmp_m(address.offset, address.base);
1026
void jump(BaseIndex address)
1028
m_assembler.jmp_m(address.offset, address.base, address.index, address.scale);
1031
// Arithmetic control flow operations:
1033
// This set of conditional branch operations branch based
1034
// on the result of an arithmetic operation. The operation
1035
// is performed as normal, storing the result.
1037
// * jz operations branch if the result is zero.
1038
// * jo operations branch if the (signed) arithmetic
1039
// operation caused an overflow to occur.
1041
Jump branchAdd32(Condition cond, RegisterID src, RegisterID dest)
1043
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
1045
return Jump(m_assembler.jCC(x86Condition(cond)));
1048
Jump branchAdd32(Condition cond, Imm32 imm, RegisterID dest)
1050
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
1052
return Jump(m_assembler.jCC(x86Condition(cond)));
1055
Jump branchAdd32(Condition cond, Imm32 src, Address dest)
1057
ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));
1059
return Jump(m_assembler.jCC(x86Condition(cond)));
1062
Jump branchAdd32(Condition cond, RegisterID src, Address dest)
1064
ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));
1066
return Jump(m_assembler.jCC(x86Condition(cond)));
1069
Jump branchAdd32(Condition cond, Address src, RegisterID dest)
1071
ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));
1073
return Jump(m_assembler.jCC(x86Condition(cond)));
1076
Jump branchMul32(Condition cond, RegisterID src, RegisterID dest)
1078
ASSERT(cond == Overflow);
1080
return Jump(m_assembler.jCC(x86Condition(cond)));
1083
Jump branchMul32(Condition cond, Address src, RegisterID dest)
1085
ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));
1087
return Jump(m_assembler.jCC(x86Condition(cond)));
1090
Jump branchMul32(Condition cond, Imm32 imm, RegisterID src, RegisterID dest)
1092
ASSERT(cond == Overflow);
1093
mul32(imm, src, dest);
1094
return Jump(m_assembler.jCC(x86Condition(cond)));
1097
Jump branchSub32(Condition cond, RegisterID src, RegisterID dest)
1099
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
1101
return Jump(m_assembler.jCC(x86Condition(cond)));
1104
Jump branchSub32(Condition cond, Imm32 imm, RegisterID dest)
1106
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
1108
return Jump(m_assembler.jCC(x86Condition(cond)));
1111
Jump branchSub32(Condition cond, Imm32 imm, Address dest)
1113
ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));
1115
return Jump(m_assembler.jCC(x86Condition(cond)));
1118
Jump branchSub32(Condition cond, RegisterID src, Address dest)
1120
ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));
1122
return Jump(m_assembler.jCC(x86Condition(cond)));
1125
Jump branchSub32(Condition cond, Address src, RegisterID dest)
1127
ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));
1129
return Jump(m_assembler.jCC(x86Condition(cond)));
1132
Jump branchNeg32(Condition cond, RegisterID srcDest)
1134
ASSERT((cond == Overflow) || (cond == Zero) || (cond == NonZero));
1136
return Jump(m_assembler.jCC(x86Condition(cond)));
1139
Jump branchOr32(Condition cond, RegisterID src, RegisterID dest)
1141
ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
1143
return Jump(m_assembler.jCC(x86Condition(cond)));
1147
// Miscellaneous operations:
1156
return Call(m_assembler.call(), Call::LinkableNear);
1159
Call call(RegisterID target)
1161
return Call(m_assembler.call(target), Call::None);
1164
void call(Address address)
1166
m_assembler.call_m(address.offset, address.base);
1174
void set8(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
1176
m_assembler.cmpl_rr(right, left);
1177
m_assembler.setCC_r(x86Condition(cond), dest);
1180
void set8(Condition cond, Address left, RegisterID right, RegisterID dest)
1182
m_assembler.cmpl_mr(left.offset, left.base, right);
1183
m_assembler.setCC_r(x86Condition(cond), dest);
1186
void set8(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
1188
if (((cond == Equal) || (cond == NotEqual)) && !right.m_value)
1189
m_assembler.testl_rr(left, left);
1191
m_assembler.cmpl_ir(right.m_value, left);
1192
m_assembler.setCC_r(x86Condition(cond), dest);
1195
void set32(Condition cond, Address left, RegisterID right, RegisterID dest)
1197
m_assembler.cmpl_rm(right, left.offset, left.base);
1198
m_assembler.setCC_r(x86Condition(cond), dest);
1199
m_assembler.movzbl_rr(dest, dest);
1202
void set32(Condition cond, RegisterID left, Address right, RegisterID dest)
1204
m_assembler.cmpl_mr(right.offset, right.base, left);
1205
m_assembler.setCC_r(x86Condition(cond), dest);
1206
m_assembler.movzbl_rr(dest, dest);
1209
void set32(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
1211
m_assembler.cmpl_rr(right, left);
1212
m_assembler.setCC_r(x86Condition(cond), dest);
1213
m_assembler.movzbl_rr(dest, dest);
1216
void set32(Condition cond, Address left, Imm32 right, RegisterID dest)
1218
m_assembler.cmpl_im(right.m_value, left.offset, left.base);
1219
m_assembler.setCC_r(x86Condition(cond), dest);
1220
m_assembler.movzbl_rr(dest, dest);
1223
void set32(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
1225
if (((cond == Equal) || (cond == NotEqual)) && !right.m_value)
1226
m_assembler.testl_rr(left, left);
1228
m_assembler.cmpl_ir(right.m_value, left);
1229
m_assembler.setCC_r(x86Condition(cond), dest);
1230
m_assembler.movzbl_rr(dest, dest);
1234
// The mask should be optional... paerhaps the argument order should be
1235
// dest-src, operations always have a dest? ... possibly not true, considering
1236
// asm ops like test, or pseudo ops like pop().
1238
void setTest8(Condition cond, Address address, Imm32 mask, RegisterID dest)
1240
if (mask.m_value == -1)
1241
m_assembler.cmpb_im(0, address.offset, address.base);
1243
m_assembler.testb_im(mask.m_value, address.offset, address.base);
1244
m_assembler.setCC_r(x86Condition(cond), dest);
1245
m_assembler.movzbl_rr(dest, dest);
1248
void setTest32(Condition cond, Address address, Imm32 mask, RegisterID dest)
1250
if (mask.m_value == -1)
1251
m_assembler.cmpl_im(0, address.offset, address.base);
1253
m_assembler.testl_i32m(mask.m_value, address.offset, address.base);
1254
m_assembler.setCC_r(x86Condition(cond), dest);
1255
m_assembler.movzbl_rr(dest, dest);
1258
// As the SSE's were introduced in order, the presence of a later SSE implies
1259
// the presence of an earlier SSE. For example, SSE4_2 support implies SSE2 support.
1260
enum SSECheckState {
1271
static SSECheckState getSSEState()
1273
if (s_sseCheckState == NotCheckedSSE) {
1274
MacroAssemblerX86Common::setSSECheckState();
1277
ASSERT(s_sseCheckState != NotCheckedSSE);
1279
return s_sseCheckState;
1283
X86Assembler::Condition x86Condition(Condition cond)
1285
return static_cast<X86Assembler::Condition>(cond);
1289
friend class MacroAssemblerX86;
1291
static SSECheckState s_sseCheckState;
1293
static void setSSECheckState()
1295
// Default the flags value to zero; if the compiler is
1296
// not MSVC or GCC we will read this as SSE2 not present.
1297
volatile int flags_edx = 0;
1298
volatile int flags_ecx = 0;
1299
#if WTF_COMPILER_MSVC
1303
__cpuid(cpuinfo, 1);
1304
flags_ecx = cpuinfo[2];
1305
flags_edx = cpuinfo[3];
1308
mov eax, 1 // cpuid function 1 gives us the standard feature set
1314
#elif WTF_COMPILER_GCC
1323
: "=g" (flags_ecx), "=g" (flags_edx)
1325
: "%eax", "%ecx", "%edx"
1335
: "=g" (flags_ecx), "=g" (flags_edx)
1337
: "%eax", "%ecx", "%edx"
1340
#elif WTF_COMPILER_SUNCC
1347
"movl %%ecx, (%rsi);"
1348
"movl %%edx, (%rdi);"
1350
: "S" (&flags_ecx), "D" (&flags_edx)
1351
: "%eax", "%ecx", "%edx"
1359
"movl %ecx, (%esi);"
1360
"movl %edx, (%edi);"
1362
: "S" (&flags_ecx), "D" (&flags_edx)
1363
: "%eax", "%ecx", "%edx"
1367
static const int SSEFeatureBit = 1 << 25;
1368
static const int SSE2FeatureBit = 1 << 26;
1369
static const int SSE3FeatureBit = 1 << 0;
1370
static const int SSSE3FeatureBit = 1 << 9;
1371
static const int SSE41FeatureBit = 1 << 19;
1372
static const int SSE42FeatureBit = 1 << 20;
1373
if (flags_ecx & SSE42FeatureBit)
1374
s_sseCheckState = HasSSE4_2;
1375
else if (flags_ecx & SSE41FeatureBit)
1376
s_sseCheckState = HasSSE4_1;
1377
else if (flags_ecx & SSSE3FeatureBit)
1378
s_sseCheckState = HasSSSE3;
1379
else if (flags_ecx & SSE3FeatureBit)
1380
s_sseCheckState = HasSSE3;
1381
else if (flags_edx & SSE2FeatureBit)
1382
s_sseCheckState = HasSSE2;
1383
else if (flags_edx & SSEFeatureBit)
1384
s_sseCheckState = HasSSE;
1386
s_sseCheckState = NoSSE;
1392
// All X86 Macs are guaranteed to support at least SSE2
1393
static bool isSSEPresent()
1398
static bool isSSE2Present()
1403
#else // OS(MAC_OS_X)
1405
static bool isSSEPresent()
1407
if (s_sseCheckState == NotCheckedSSE) {
1411
ASSERT(s_sseCheckState != NotCheckedSSE);
1413
return s_sseCheckState >= HasSSE;
1416
static bool isSSE2Present()
1418
if (s_sseCheckState == NotCheckedSSE) {
1422
ASSERT(s_sseCheckState != NotCheckedSSE);
1424
return s_sseCheckState >= HasSSE2;
1428
#endif // PLATFORM(MAC)
1429
#elif !defined(NDEBUG) // CPU(X86)
1431
// On x86-64 we should never be checking for SSE2 in a non-debug build,
1432
// but non debug add this method to keep the asserts above happy.
1433
static bool isSSE2Present()
1439
static bool isSSE3Present()
1441
if (s_sseCheckState == NotCheckedSSE) {
1445
ASSERT(s_sseCheckState != NotCheckedSSE);
1447
return s_sseCheckState >= HasSSE3;
1450
static bool isSSSE3Present()
1452
if (s_sseCheckState == NotCheckedSSE) {
1456
ASSERT(s_sseCheckState != NotCheckedSSE);
1458
return s_sseCheckState >= HasSSSE3;
1461
static bool isSSE41Present()
1463
if (s_sseCheckState == NotCheckedSSE) {
1467
ASSERT(s_sseCheckState != NotCheckedSSE);
1469
return s_sseCheckState >= HasSSE4_1;
1472
static bool isSSE42Present()
1474
if (s_sseCheckState == NotCheckedSSE) {
1478
ASSERT(s_sseCheckState != NotCheckedSSE);
1480
return s_sseCheckState >= HasSSE4_2;
1486
#endif // ENABLE(ASSEMBLER)
1488
#endif // MacroAssemblerX86Common_h